Communication control device for subscriber stations of a serial bus system and method for communication in a serial bus system

Abstract

A communication control device for a subscriber station of a serial bus system and a method for communicating in a serial bus system are provided. The communication control device is designed to control a communication of the subscriber station of the bus system with at least one other subscriber station and to generate a transmission signal for transmission onto a bus of the bus system and / or to receive a signal from the bus, wherein the communication control device is designed to generate the transmission signal in accordance with a frame and wherein the communication control device is designed to generate the transmission signal in such a way that in the transmission signal a bit time of at least one bit is adjusted in accordance with an edge height, which is provided between the at least one bit and a preceding bit in a signal in which the bit is transmitted via the bus.

Description

Technical Field

[0001] The present invention relates to a communication control device for a user station in a serial bus system and a method for communication in a serial bus system that operates at high data rates and high fault tolerance. Background Technology

[0002] Bus systems used for communication between sensors and controllers, such as in vehicles, should be designed to handle large data transfer volumes, depending on the number of technical devices or vehicle functions. Many applications require the ability to transmit data from the transmitter to the receiver at the highest possible data transfer rate.

[0003] In vehicles, the bus system is currently in the introduction phase. In this system, data is transmitted as messages (Nachrichts) according to the standard ISO 11898-1:2015, which specifies the CAN protocol with CAN FD. These messages are transmitted between bus users, such as sensors, controllers, and transmitters. For this purpose, messages are sent to the bus in frames, where transitions are made between two communication phases. In the first communication phase (arbitration), it is agreed which user station in the bus system should send its frame to the bus in the subsequent second communication phase (the data phase or transmission of valid data). CAN FD is used by most manufacturers in vehicles with an arbitration bit rate of 500 kbit / s and a data bit rate of 2 Mbit / s in the first step. Therefore, it is possible to switch between slow and fast operating modes when transmitting on the bus.

[0004] To achieve even higher data rates in the second communication phase, a successor bus system for CAN FD, called CAN XL, has been developed and is currently being standardized within the CAN Automation Association (CiA). In addition to pure data transmission via the CAN bus, CAN XL supports other functions such as functional safety, data security, and Quality of Service (QoS). These are fundamental attributes required in autonomous vehicles.

[0005] To increase the data rate that can be transmitted via the bus, the edge steepness of the signals coupled to the bus can be increased. The higher the edge steepness, the greater the electromagnetic radiation. However, this radiation should not exceed the limits related to the electromagnetic compatibility of the user station. Therefore, the edge steepness cannot be arbitrarily increased. If it is necessary to safely distinguish the voltage differences of the bus signals (which refer to different bits of the digital signal sent onto the bus), then it is advisable to choose the voltage difference as large as possible. However, the larger the voltage difference, the longer the transient effects between different voltage differences last. Therefore, a predetermined bit time or bit duration must be set for transmission on the bus so that the signal received by the bus can be correctly scanned by the receiver. The duration increases with the magnitude of the voltage difference between different bus states.

[0006] Furthermore, errors can occur when transmitting data in frames via the CAN Bus. These errors can be caused by external influences, particularly incident or reflected light at the bus ends, spoofed bits, or shifted edges between bits. Additionally, stage errors may occur in the user station due to a non-ideal clock source, where the user is not currently a message transmitter but only a message receiver (receiving node) in the communication on the bus.

[0007] These frame conditions help reduce the amount of data that can be effectively transmitted per unit of time, i.e., the net data rate. Summary of the Invention

[0008] Therefore, the objective of this invention is to provide a communication control device for a user station in a serial bus system and a method for communication in a serial bus system, which solve the aforementioned problems. In particular, it is intended to provide a user station for a serial bus system and a method for communication in a serial bus system, wherein high fault tolerance of communication can be achieved even at high data rates, and, if necessary, when the effective data volume per frame increases.

[0009] This task is solved by a communication control device for a user station in a serial bus system according to the invention. The communication control device is designed to control communication between the user station and at least one other user station in the bus system and to generate transmit signals for transmission onto the bus of the bus system and / or to receive signals from the bus. The communication control device is designed to generate transmit signals based on frames, and to generate transmit signals such that the bit timing of at least one bit in the transmit signal is adjusted according to an edge height set between the at least one bit in the signal and a previous bit, in which the bit is transmitted via the bus.

[0010] The term "bit" refers to a number in a base-2 system or a number system with a base of -3 or less, 3 or greater than 3. Through the design of the communication control device, more data can be transmitted per unit time via the bus than previously possible without reducing the fault tolerance of the bus system. Overall, the data rate can be increased by more than 2.5 times, particularly with user stations.

[0011] The use of communication control devices enables robust communication in serial bus systems, particularly in CAN, CAN FD, or CAN XL, even with further increases in data rates.

[0012] Here, what can be achieved in the bus system using a communication control device is that, in the first communication phase, the arbitration known by CAN is maintained, and the transmission rate is significantly improved again compared to CAN or CAN FD or CAN XL.

[0013] When there is at least one CAN user station and / or at least one CAN FD user station in the bus system that transmits messages according to the CAN protocol and / or CAN FD protocol, the method executed by the communication control device can also be used.

[0014] Advantageous alternative designs for the communication control device and user station are described in other parts of this disclosure.

[0015] The edge steepness of a signal transmitted via a bus can be essentially the same as the edge height, regardless of the edge steepness.

[0016] In addition, the communication control device may have: a conversion block for converting the logic value of at least two bits of the transmitted signal from a binary digital system into a logic value in a digital system based on numbers greater than 2, and for generating at least one bit for the transmitted signal; and a bit time adjustment block for adjusting the bit time of at least one bit of the transmitted signal according to the logic value of at least one bit of the transmitted signal.

[0017] In one design, the communication control device is designed to shorten at least one bit in a bit sequence of at least two bits having the same logic value compared to another bit in the bit sequence within the frame.

[0018] Each bit of the transmitted signal can be divided into four segments over a period of time without shortening, wherein a first scan point for scanning the signal after transmission via the bus is provided between the first and second segments, and a second scan point for scanning the signal after transmission via the bus is provided between the third and fourth segments.

[0019] According to one embodiment, the communication control device is designed to embed at least one predetermined bit into a transmitted signal, which indicates to a receiving node in the bus system that the signal currently being received by the bus has been at least partially modified such that at least one bit is adjusted according to the edge height. Here, the communication control device is also designed to embed at least one predetermined bit into the control field of a frame and / or the data field of a frame.

[0020] One consideration is that the communication control device has an error frame counting block for counting erroneous frames received by the bus, wherein the communication control device is designed to not adjust the bit time in the transmitted signal when the count value of the error frame counting block exceeds a predetermined number.

[0021] The communication control device can be designed to generate a transmission signal such that, for messages exchanged between user stations in the bus system, the bit timing of a signal transmitted on the bus in a first communication phase may differ from the bit timing of a signal transmitted in a second communication phase, wherein in the first communication phase it is agreed which user station in the bus system will obtain at least temporarily exclusive, conflict-free access to the bus in the subsequent second communication phase, and wherein the communication control device is designed to adjust at least one bit in the bit timing during the first and / or second communication phases.

[0022] The frames formed for this message can be constructed in a way that is compatible with CAN FD and / or CAN XL.

[0023] The previously described communication control device may be part of a user station, which also has a voltage distribution module for assigning a first voltage value or a second voltage value to a logic value of a bit of a signal to be transmitted via the bus. The voltage distribution module is designed to assign a logic value to at least one bit of the signal on the bus, where at least one bit of the signal on the bus has a minimum edge height at its beginning accompanied by the logic value.

[0024] In one design, a first voltage value is assigned to the first logic value of the first bit in the bit sequence of the transmitted signal, wherein a second voltage value is assigned to the second logic value of the second bit in the bit sequence, wherein the first logic value is less than the second logic value, and wherein the first voltage value is less than the second voltage value.

[0025] Furthermore, the user station described above may have a transmitting / receiving device for transmitting signals to the bus of the bus system, wherein the transmitting / receiving device is designed to transmit the entire frame to the bus in the first communication phase under the operation mode for transmitting and receiving frames.

[0026] The user station described above can be part of a bus system, which also includes a bus and at least two user stations interconnected via the bus, enabling the user stations to communicate serially with each other. Here, at least one of the at least two user stations is the user station described above.

[0027] Furthermore, the previously described task is also solved by a method according to the invention for communication in a serial bus system. This method is implemented using a user station of the bus system, the user station having a communication control device, wherein the method includes the steps of: controlling communication between one user station of the bus system and at least one other user station using the communication control device and for generating a transmit signal for transmission onto the bus of the bus system and / or for receiving a signal from the bus, wherein the communication control device generates the transmit signal according to a frame, wherein the communication control device generates the transmit signal such that the bit time of at least one bit in the transmit signal is adjusted according to an edge height, the edge height being set between at least one bit in a signal and a previous bit, in which bits are transmitted via the bus.

[0028] This method offers the same advantages as previously mentioned regarding communication control devices and user stations.

[0029] Other possible implementations of the invention also include combinations of features or implementation methods described above or below with respect to embodiments, not explicitly mentioned. Those skilled in the art can also add individual aspects as improvements or supplements to the corresponding basic form of the invention. Attached Figure Description

[0030] The invention will now be described in more detail with reference to the accompanying drawings and embodiments.

[0031] Figure 1 This is a simplified block diagram of the bus system according to the first embodiment; Figure 2 It is a simplified diagram used to illustrate the structure of a message that can be sent by a user station of the bus system according to the first embodiment; Figure 3 This is a simplified schematic block diagram of a user station in a bus system according to the first embodiment; Figure 4 The time variation curves of bus signals CAN-XL_H and CAN-XL_L in the user station according to the first embodiment; Figure 5 The curves showing the time variation of the differential voltage VDIFF of bus signals CAN-XL_H and CAN-XL_L in the user station according to the first embodiment are shown. Figure 6It is a time-varying curve of a portion of a signal that appears at the connector of the user station according to the first embodiment when the frame is transmitted; Figure 7 It is a time-varying curve of a portion of the signal that appears at the connector of the user station according to the second embodiment when the frame is transmitted; Figure 8 It is a time-varying curve of a portion of the signal that appears at the connector of the user station according to the third embodiment when the frame is transmitted; Figure 9 This is a simplified diagram illustrating the structure of a message that can be sent by a user station in a bus system according to the fourth embodiment; and Figure 10 This is a simplified diagram illustrating the structure of a message that can be sent by a user station in the bus system according to the fifth embodiment.

[0032] In the accompanying drawings, unless otherwise specified, the same reference numerals are used for the same or functionally equivalent elements. Detailed Implementation

[0033] Figure 1 Bus system 1 is shown as an example, which is designed in particular based on CAN bus system, CAN FD bus system, CAN XL bus system and / or modifications thereof, as will be explained below. Bus system 1 can be used in vehicles, especially motor vehicles, aircraft, etc., or in hospitals, etc.

[0034] exist Figure 1 In the bus system 1, there are multiple user stations 10, 20, and 30, which are respectively connected to a bus 40 with a first bus core line 41 and a second bus core line 42. Bus core lines 41 and 42 can also be referred to as CAN_H and CAN_L, or CAN-XL_H and CAN-XL_H, and are used for electrical signal transmission after coupling an input dominant level, generating a recessive level, or other levels for signals in the transmitting state. Messages 45 and 46 in signal form can be serially transmitted between the user stations 10, 20, and 30 via bus 40. If an error occurs on bus 40 during communication, such as through… Figure 1 As shown by the jagged black square arrow, error frame 47 (Error Flag) can optionally be sent. User stations 10, 20, and 30 are, for example, vehicle controllers, sensors, display devices, etc.

[0035] As in Figure 1As shown, user station 10 has a communication control device 11, a transmitting / receiving device 12, a bit time correction module 15, and a voltage distribution module 16. User station 20 has a communication control device 21, a transmitting / receiving device 22, and optionally a bit time correction module 25 and a voltage distribution module 26. User station 30 has a communication control device 31, a transmitting / receiving device 32, a bit time correction module 35, and a voltage distribution module 36. The transmitting / receiving devices 12, 22, and 32 of user stations 10, 20, and 30 are directly connected to bus 40, even if this is... Figure 1 It is not shown in the middle.

[0036] Communication control devices 11, 21, and 31 are respectively used to control the communication between the corresponding user stations 10, 20, and 30 and at least one other user station among the user stations 10, 20, and 30 connected to the bus 40 via the bus 40.

[0037] Communication control devices 11 and 31 compile and read a first message 45, which is, for example, a modified CAN message 45. Here, the modified CAN message 45 is constructed based on the CAN XL format, which is referenced from... Figure 2 To explain in more detail, the corresponding bit time correction modules 15 and 35 are used in this CAN XL format. The communication control devices 11 and 31 can also be designed to provide CAN XL messages 45 or CANFD messages 46 to the transmitting / receiving device 32, or to be received by this transmitting / receiving device, as needed. The corresponding bit time correction modules 15 and 35 can also be used here. The communication control devices 11 and 31 thus compile and read the first message 45 or the second message 46, wherein the difference between the first and second messages 45 and 46 lies in their data transmission standard, i.e., in this case CAN XL or CAN FD, which are further modified as will be explained below.

[0038] The communication control unit 21 can be designed as a conventional CAN controller according to ISO 11898-1:2015, that is, a conventional CAN controller or CAN FD controller with CAN FD fault tolerance. Optionally, a bit time correction module 25 is present, which has the same function as bit time correction modules 15 and 25. The communication control unit 21 compiles and reads a second message 46, such as a CAN FD message 46. The CAN FD message 46 can include 0 to 64 data bytes, which are transmitted at a significantly faster data rate than in conventional CAN messages. The communication control unit 21 is designed, in particular, like a conventional CAN FD controller.

[0039] The transmitting / receiving device 22 can be designed as a conventional CAN transceiver or CAN FD transceiver according to ISO 11898-1:2015. In addition, there is a voltage distribution module 26, which has the same function as voltage distribution modules 16 and 36.

[0040] The transmitting / receiving devices 12 and 32 can be designed to, as needed, provide or be received by the relevant communication control device 11 or 31 with messages 45 in CAN XL format or messages 46 in the current CAN FD format. In addition, voltage distribution modules 16 and 36 are also present.

[0041] Using two user stations 10 and 30, it is possible to form and transmit, as well as receive, messages 45 in CAN XL format. Message 45 can be further modified, as explained below.

[0042] Figure 2 Frame 450 is shown for message 45, which is in particular a CAN XL frame, provided by communication control unit 11 to transmitting / receiving unit 12 for transmission onto bus 40. Here, in the current embodiment, communication control unit 11 has frame 450 configured to be compatible with CAN FD. The same description applies to communication control unit 31 and transmitting / receiving unit 32 of user station 30.

[0043] according to Figure 2 The frame 450 used for CAN communication on bus 40 is divided into different communication phases 451 and 452, namely the arbitration phase 451 and the data phase 452. After the start bit SOF, frame 450 has an arbitration field 453, a control field 454, a data field 455, a checksum field 456, and a frame end field 457.

[0044] In arbitration phase 451, user stations 10, 20, and 30 agree bit-by-bit in arbitration domain 453, using identifiers (IDs) such as bits ID28 to ID18, which user station 10, 20, or 30 wants to send messages 45 and 46 with the highest priority and thus gain exclusive access to bus 40 in the subsequent data phase 452 after the transmission period. In arbitration phase 451, a physical layer, similar to that used in CAN and CAN FD, is used. The physical layer corresponds to the bit transport layer or layer 1 of the well-known OSI model (Open Systems Interconnection model).

[0045] An important point during phase 451 is the use of the known CSMA / CR method, which allows user stations 10, 20, and 30 to simultaneously access bus 40 without disrupting higher-priority messages 45 and 46. This makes it relatively easy to add other bus user stations 10, 20, and 30 to bus system 1, which is extremely advantageous.

[0046] The CSMA / CR method inevitably results in a so-called recessive state on bus 40, which can be rewritten by other user stations 10, 20, and 30 that have a dominant state on bus 40. In the recessive state, there is high impedance at each user station 10, 20, and 30, which, combined with parasitic bus wiring, causes a long time constant. This limits the maximum bit rate of the current CAN-FD physical layer to approximately 2 megabits per second in real-world vehicle applications.

[0047] In data phase 452, in addition to a portion of control field 454, valid data for the CAN-XL frame or message 45 from data field 455, as well as checksum field 456, are transmitted. Checksum field 456 may contain a checksum related to the data of data phase 452, along with padding bits, which is inserted by the transmitter of message 45 as reversed bits after each predetermined number of identical bits, specifically after 10 identical bits. At the end of data phase 452, the system returns to arbitration phase 451.

[0048] In the frame end phase 457, the end field may contain at least one acknowledgment bit. Additionally, there is a sequence of 11 identical bits that indicate the end of the CAN XL frame 450. At least one acknowledgment bit can be used to notify the receiver whether any errors were found in the received CAN XL frame 450 or message 45.

[0049] The transmitter of message 45 only begins to send bits of data stage 452 onto bus 40 when user station 10, as the transmitter, obtains arbitration and user station 10, as the transmitter, therefore has exclusive access to bus 40 of bus system 1 for transmission.

[0050] In bus systems with CAN XL, proven properties responsible for the robustness and user-friendliness of CAN and CAN FD are employed, particularly the frame structure with identifiers and arbitration according to the CSMA / CR method. Therefore, in the arbitration phase 451, which is the first communication phase, user station 10 uses a format known from CAN / CAN-FD according to ISO 11898-1:2015, specifically up to the FDF bit (inclusive). However, compared to CAN or CAN FD, the net data transfer rate can be improved in the data phase 452, which is the second communication phase, particularly increasing it to approximately 10 megabits per second. Furthermore, the size of the effective data per frame can be increased, particularly increasing it to approximately 2 kilobytes or any other value.

[0051] Figure 3 The basic structure of user station 10 is shown, which includes a communication control unit 11, a transmitting / receiving unit 12, a bit time correction module 15 (part of the communication control unit 11), and a voltage distribution module 16 (part of the transmitting / receiving unit 12). User station 20 is constructed in the same manner in terms of basic structure, except for the differences described above, as shown in... Figure 3 As shown in the diagram. User station 30 is constructed in a similar manner, as in... Figure 3 As shown, but the bit time correction module 35 is based on Figure 1 It is arranged separately from the communication control unit 31 and the transmitting / receiving unit 32. The same description applies to the voltage distribution module 36, therefore the user station 30 is not described separately.

[0052] according to Figure 3 In addition to the communication control unit 11 and the transmitting / receiving unit 12, user station 10 also includes: a microcontroller 13 to which the communication control unit 11 is associated; and a system ASIC 17 (ASIC = Application-Specific Integrated Circuit), which can be an alternative to a system base chip (SBC) on which the functions required by multiple electronic components of user station 10 are integrated. In addition to the transmitting / receiving unit 12, a power supply unit 18 is also installed in the system ASIC 17, which supplies power to the transmitting / receiving unit 12. The power supply unit 18 typically provides a 5V voltage for CAN_Supply. However, the power supply unit 18 can provide other voltages as needed. The power supply unit 18 is additionally or alternatively designed as a power source.

[0053] The bit time correction module 15 includes a conversion block 151 that, using conversion rule 1511, converts the transmitted signal TxD from a binary bit sequence to a bit sequence in which more than two voltage states are set for each bit. Furthermore, the bit time correction module 15 also includes a bit time adjustment block 152 for adjusting the bit length or bit time according to a predetermined bit time determination rule 1521, and optionally includes an error frame counting block 153. Blocks 151, 152, and 153 will be described in more detail below.

[0054] Furthermore, the transmitting / receiving device 12 has a transmitting module 121 and a receiving module 122. Even though the term "transmitting / receiving device 12" will continue to refer to the transmitting / receiving device 12, alternatively, the receiving module 122 can be housed in a separate device outside the transmitting module 121. The transmitting module 121 and the receiving module 122 can be constructed as in a conventional transmitting / receiving device 12. The transmitting module 121 may, in particular, have an operational amplifier and / or a transistor. The receiving module 122 may, in particular, have at least one operational amplifier and / or a transistor. Additionally, the voltage distribution module 16 is configured with a transmitting block 161 and a receiving block 162, as will be explained more precisely below.

[0055] The transmitting / receiving device is connected to bus 40, more precisely to its first bus line 41 for CAN_H or CAN-XL_H and its second bus line 42 for CAN_L or CAN-XL_L. A voltage supply to the power supply device 17, which supplies electrical energy, particularly voltage, to the first and second bus lines 41, 42 via at least one connector 43, is provided. Connection to ground or CAN_GND is achieved via connector 44. The first and second bus lines 41, 42 are terminated with terminating resistors 49.

[0056] The first and second bus cores 41 and 42 are connected in the transmitting / receiving device 12 not only to the transmitting module 121, also known as the transmitter, but also to the receiving module 122, also known as the receiver, even if this connection is in... Figure 3 For simplicity, these are not shown. Furthermore, the first and second bus cores 41 and 42 are connected in the transmitting / receiving device 12 to the voltage distribution module 16, particularly to the transmitting block 161 and the receiving block 162.

[0057] During the operation of bus system 1, the transmitting module 121 converts the transmitting signal TXD or TxD_TC from the communication control device 11 into corresponding signals CAN-XL_H and CAN-XL_L for bus core lines 41 and 42, and sends these signals CAN-XL_H and CAN-XL_L to the connectors for CAN_H and CAN_L on bus 40, such as in... Figure 4As shown in the diagram. At least in data phase 452, the transmit signal TXD or TxD_TC of the voltage distribution module 16, specifically with transmit block 161, is converted into signals for the first and second bus cores 41, 42 and sent to the connectors on bus 40 for CAN_H and CAN_L. For this purpose, transmit block 161 has at least one operational amplifier and / or transistor.

[0058] Receiver module 122 is based on Figure 4 The signals CAN-XL_H and CAN-XL_L received by bus 40 form a received signal RXD or RxD and this received signal is transmitted to the communication control device 11, as shown in... Figure 3 As shown in the diagram. At least in the data phase 452, the receiving block 162 of the voltage distribution module 16 forms a received signal RXD or RxD and transmits this received signal to the communication control device 11. For this purpose, the receiving block 162 has at least one operational amplifier and / or transistor. Except in an idle or ready state (idle or hibernating), the transmit / receive module 12 with the receiving module 122 and / or the receiving module 162 always stops the transmission of data or messages 45, 46 on the bus 40 during emergency operation, regardless of whether the transmit / receive module 12 is the transmitter of message 45.

[0059] according to Figure 4 For example, signals CAN-XL_H and CAN-XL_L have dominant and recessive bus levels 401 and 402, respectively, at least during arbitration phase 451, as is known from CAN. A differential signal VDIFF = CAN-XL_H - CAN-XL_L is formed on bus 40, which... Figure 5 The diagram shows the arbitration phase 451. The individual bits of the signal VDIFF with a bit time t_bt1 can be identified in arbitration phase 451 using, for example, a receive threshold T_a of 0.7 V. In data phase 452, the bits of signals CAN-XL_H and CAN-XL_L are transmitted faster than in arbitration phase 451, i.e., with a shorter bit time t_bt2. Therefore, signals CAN-XL_H and CAN-XL_L differ from the conventional signals CAN_H and CAN_L in data phase 452, at least in their faster bit rate.

[0060] Figure 4 The sequence of states 401 and 402 for signals CAN-XL_H and CAN-XL_L. Figure 5 The resulting voltage VDIFF variation curve is only used to illustrate the power supply of user station 10. The order of data states for bus states 401 and 402 can be selected as needed.

[0061] In other words, when the sending module is connected to the first operating mode B_451 (slow), the sending module 121 according to... Figure 4 A first data state is generated as bus state 402 with different bus levels for the two bus cores 41 and 42 of the bus line, and a second data state is generated as bus state 401 with the same level for the two bus cores 41 and 42 of the bus line of bus 40.

[0062] Furthermore, the transmitting module 121 or the transmitting module 162 transmits bits at a higher bit rate to the bus 40 based on the time variation curves of the signals CAN-XL_H and CAN-XL_L in the second operating mode B_452_TX (FAST_TX) including the data phase 452. The CAN-XL_H and CAN-XL_L signals can also be generated in the data phase 452 using a different physical layer than in CAN FD. The bit rate in the data phase 452 can thus be further increased compared to CAN FD. User stations that are not transmitters of frame 450 in the data phase 452 have a third operating mode B_452_RX (FAST_RX) configured in their transmitting / receiving devices.

[0063] When user station 10 operates as a transmitter and / or receiver of frame 450, Figure 3 The bit time correction module 15 is active. The bit time correction module 15, and in particular its conversion block 151, converts the bit sequence of frame 450 from a binary digital system to another digital system whose digital base is greater than 2, before the communication control device 11 transmits the TxD signal as the TxD_TC signal at the connector TXD to the transmitting / receiving device 12 for transmission on the bus 40.

[0064] Conversion block 151, for example, converts a 16-bit binary sequence... When using conversion rule 1511, convert to a number system with a base of 3, 4, or 5. Figure 6 In the example, the converted bit sequence has a logical value or a number in the quinary number system (base 5). And therefore it only has seven bits.

[0065] Furthermore, the bit time correction module 15, and particularly its bit time adjustment block 152, can adjust the bits of the TxD signal for the TxD_TC signal. The voltage distribution module 16, and particularly the transmitting block 161, provides the aforementioned bit sequence in the quinary digital system using distribution rule 1521. Each bit is assigned a predetermined voltage value. This is explained below using... Figure 6 To explain more accurately.

[0066] The method implemented by bit time correction module 15 and voltage distribution module 16 is particularly suitable for data phase 452, where one of user stations 10, 20, 30 has exclusive access to bus 40 to transmit one of messages 45, 46, specifically as frame 450. Modules 15, 16 may use this method at least partially, but alternatively or additionally, in arbitration phase 451.

[0067] Figure 6 An example for the differential signal VDIFF is shown within time t, which is constituted by the digital transmit signal TxD or TxD-TC on bus 40. The transmit signal TxD can be generated either according to frame 450 or according to the CANFD protocol.

[0068] The bit sequence shown initially has a bit 1 with a logic value of 0, followed by bits with logical values ​​or digits according to the base-5 number system. The seven digits B2 to B8.

[0069] Voltage distribution module 16 is the in-situ sequence in signal TxD_TC Each logic value or digital number in the sequence is assigned a predetermined voltage value for the signal VDIFF. The transmitting module 162 transmits the bit sequence... Correspondingly, it is sent to bus 40, thus forming a [system / mechanism] on bus 40. Figure 6 The signal is given. A voltage value of +2V corresponds to digital 0. Therefore, the transmitting module 162 may have a circuit with at least one operational amplifier and / or at least one transistor. A voltage value of +1V corresponds to digital 1. A voltage value of +1V corresponds to digital 2. A voltage value of -1V corresponds to digital 3. A voltage value of -2V corresponds to digital 4.

[0070] In the received signal RxD, the voltage distribution module 16, and especially its receiving module 162, will divide the corresponding bit sequence during error-free reception. The digital values ​​are assigned to the corresponding voltages of the differential signal VDIFF. For this purpose, the voltage distribution module 16, and particularly its receiving module 162, uses receiving thresholds U_TH1, U_TH2, U_TH3, and U_TH4. These receiving thresholds can be implemented in a circuit with at least one operational amplifier and / or at least one transistor.

[0071] Figure 6 Bits B1 to B8 are divided into multiple time quanta. At least one time quantum is assigned to one of the multiple segments SY, PP, P1, and P2. Figure 6 Each bit B1 to B8 in the array has at least segments SY, P1, and P2. Therefore Figure 6 Each bit B1 to B8 in the array has at least three segments.

[0072] A synchronization segment SY is provided at the beginning of bits B1 to B8, which has 1 to 4 time quanta TQ depending on the bit. This is followed by a propagation segment PP, which has multiple time quanta TQ. Between segments SY and PP is a first scan point TP for scanning bits. Following segment PP is a first stage P1 before the second scan point TP for scanning bits. Following the second scan point TP is a second stage P2. If a transition exists between two different logic values ​​in the transmitted signal TxD or the received signal RxD (i.e., between 1 and 0 or 0 and 1), the receiving node or receiver of frame 450 checks whether a transition exists at the expected time. If no transition exists at the expected time at the beginning of the bit, the receiver of frame 450 can calculate the time difference and adjust the duration of stage P1 or stage P2 as needed. The receiver can thus be continuously synchronized with the timing of the transmitting node or transmitter of frame 450. This reduces errors (physical layer effects) based on radiation on bus 40. The communication control device 11 is designed to scan bits B1 to B8 at a first scan point TP and a second scan point TP in the signal RxD received by the bus 40. The scan points are respectively arranged between two of the segments SY, PP, P1, and P2.

[0073] Figure 6 Bits B1 to B8 in the bus 40 have the same edge steepness but different edge heights. The edge steepness is generally substantially the same. The transmit-receive device 12 specifically drives the signal VDIFF of the edges with the same edge steepness onto the bus 40. The edge height between each bit corresponds to the difference VDIFF of the voltage values ​​of directly consecutive bits, which are arranged between the directly consecutive bits. The larger the edge height, the longer the duration of segments SY, PP, P1, and P2 is selected by the bit time adjustment module 152 during time t. Here, the bit time adjustment module 152 selects the duration of segments SY and PP based on the edge height. In contrast, the bit time adjustment module 152 selects the length of segments P1 and P2 independently of the edge height of the relevant bits. Segments P1 and P2 can be used for clock synchronization of the various user stations of the bus system 1.

[0074] Bit B1 has a logic value of 0 and a rising edge with a height of 4 volts, positioned between voltage values ​​of -2V and +2V. The segment SY of bit B1 thus extends for 4 time quanta TQ. The segment PP of bit B1 extends for 16 time quanta TQ. Bit B1 has a bit length or bit time T1.

[0075] Bit B2 has a logic value of 3 and a falling edge with a height of 3 volts, positioned between voltage values ​​of +2V and -1V. The segment SY of bit B2 thus extends over 3 time quanta TQ. The segment PP of bit B2 extends over 12 time quanta TQ. Bit B2 has a bit length or bit time T2.

[0076] Bit B3 has a logic value of 2 and a rising edge with a height of 2 volts, positioned between the voltage values ​​-1V and +1V. The segment SY of bit B3 thus extends over 2 time quanta TQ. The segment PP of bit B3 extends over 8 time quanta TQ. Bit B3 has a bit length or bit time T3.

[0077] Bit B4 has a logic value of 1 and a falling edge with a height of 1 volt, positioned between the voltage values ​​+1V and 0V. The segment SY of bit B4 thus extends over 1 time quantum TQ. The segment PP of bit B4 extends over 4 time quantum TQ. Bit B4 has a bit length or bit time T4.

[0078] Bit B5 has a logic value of 1 and therefore has an edge height of 0 volts due to the preceding bit B4 which has the same logic value. The segment SY of bit B5 thus extends over 1 time quantum TQ. Bit B5 also does not have a segment PP. Bit B5 has a bit length or bit time T5.

[0079] Bit B6 has a logic value of 4 and a falling edge with a height of 2 volts, positioned between voltage values ​​of 0V and -2V. The segment SY of bit B6 thus extends over 2 time quanta TQ. The segment PP of bit B6 extends over 8 time quanta TQ. Bit B6 has a bit length or bit time T3.

[0080] Bit B7 has a logic value of 4 and therefore has an edge height of 0 volts due to the preceding bit B6 which has the same logic value. The segment SY of bit B7 thus extends over 1 time quantum TQ. Bit B7 also does not have a segment PP. Bit B7 has a bit length or bit time T5.

[0081] Bit B8 has a logic value of 3 and a rising edge with a height of 1 volt, positioned between voltage values ​​of -2V and -1V. The segment SY of bit B8 thus extends over 1 time quantum TQ. The segment PP of bit B8 extends over 4 time quantum TQ. Bit B8 has a bit length or bit time T4.

[0082] Therefore, in the bit sequence of a base-5 number system, such as Figure 6As shown, different voltage states exist on bus 40. Voltage distribution module 16 therefore assigns five different voltage values, +2V, +1V, 0V, -1V, and -2V, to the corresponding voltage states on bus 40. Furthermore, bit time adjustment module 152 adapts the bits of the transmitted signal TxD_TC to five different bit lengths or bit times, i.e., bit times T1 to T5. Bit time adjustment module 152 determines this adjustment based on rule 1521, which takes into account the corresponding switching between digits 0 and 4. Bit time adjustment module 152 adjusts the bit length or bit time in such a way that signal VDIFF has a differential voltage whose duration depends on the height prior to the differential voltage change. Figure 6 In the example, the selected differential voltage VDIFF, ranging from +2V to -2V, has edge transitions from 0V to 4V depending on the bit sequence. This can result in longer bit times, such as bit time T1, or shorter bit times, such as bit time T5. However... Figure 6 Number sequence It has only 99 time quantum TQs.

[0083] In the current embodiment, the data rate can be significantly improved compared to the prior art. In particular, the data rate can be significantly improved by 21% compared to the prior art, for example, by using a maximum differential voltage of 1V, as in LVCAN and additional bit-time compression.

[0084] Bits B1 to B8 can, of course, shorten the time length beyond what has been described previously. In particular, they can shorten the time length of segment P1 or any other length between the lengths of segments PP and P1. At least one of bits B1 to B8 can alternatively shorten the time length of segment P1.

[0085] If user station 10 is the receiving user station of bus system 1, and it is not currently the transmitter of frame 450, but only receives frame 450 (reception phase), then user station 10 uses its bit time adjustment module 152 to identify the shortened bit length of the dominant bit B1 by scanning at the scan point TP of the received signal RxD. The communication control device scans the received signal RxD after each time quantum TQ. Therefore, the receiving node can correctly scan according to... Figure 6 The receiving node receives the signal VDIFF at its CAN_H and CAN_L connectors on bus 40. The bit timing module 152 can optionally extend the shortened bit B1 of the received signal RxD back to the normal length in the binary digital system. The communication control device 11 can optionally evaluate received signals RxD with different bit lengths.

[0086] With this design scheme of user stations 10, 20, and 30 in bus system 1, more bits can be transmitted through bus 40 in the same amount of time. Therefore, the data rate in bus system 1 is increased.

[0087] If user stations 10, 20, and 30 at bus 40 are not aware of bit time shortening, then when one of the bit time correction modules 15, 25, and 35 is active with respect to the transmitted signal TxD, these user stations 10, 20, and 30 will disrupt communication in bus system 1 via error frames 47. In this case, error frame counting block 153 counts the error frames 47 received by bus 40. From a certain number of error frames 47 onwards, bit time correction module 15 determines that the method is no longer used to shorten bits or bit sequences. Instead, communication control device 11 then only uses the conventional protocol, in which bit or bit sequence shortening is not used. Therefore, the relevant bit time correction modules 15, 25, and 35 of user stations 10, 20, and 30 are disabled.

[0088] This enables robust emergency operation of communication within Bus System 1. This is particularly advantageous when Bus System 1 is used in vehicles. Emergency operation is then guaranteed, for example, during vehicle operation.

[0089] The communication control device 11, particularly its bit time correction module 15, can reduce the count value of the error frame counter block 153 after successfully sending a message 45 with shortened bits or bit sequences. This is not an occasional error caused by incompatibility of the communication protocols of user stations 10, 20, and 30 at bus 40, and therefore will not lead to a reduction in the possible transmittable baud rate in bus system 1.

[0090] In contrast, when performing vehicle software updates in the workshop, it may be desirable to operate at the highest possible data rate. This may be the case when the various user stations at bus 40 are only interested in the data from the new software. In this situation, it is possible that workshop testers may intentionally use the previously described method of shortening bits or bit sequences when sending messages 45, 46 on bus 40 for an extended period until (multiple) incompatible user stations interrupt the transmission of error frame 47 and enter an error exception state. From this point onward, the communication control device 11 non-destructively uses the previously described method... Figure 6 This method is used to shorten the bits or bit sequence when sending messages 45 and 46. Therefore, software updates can be transmitted in a shorter time than traditional messages 45 and 46 with their normal bit length.

[0091] Figure 7A second embodiment regarding time t illustrates an example for a differential signal VDIFF, which is formed on bus 40 following a digital transmit signal TxD or TxD_TC. The transmit signal TxD can be generated either according to frame 450 or according to the CAN FD protocol.

[0092] The bit sequence shown has 10 bits, namely bits B1 to B10. In a ternary number system, each bit has a logical value or a numerical value. This sequence of numbers corresponds to the sequence of numbers in the binary number system. and according to the quinary number system Figure 6 A sequence of numbers or bit sequences .

[0093] Voltage distribution module 16-bit sequence Each logic value or digital assignment in the bit array corresponds to up to two predetermined voltage values ​​for the signal VDIFF on bus 40. The two voltage values ​​+2V and -1V are assigned to digital 2. The two voltage values ​​+1V and -2V are assigned to digital 1. The voltage value 0V is assigned to digital 0. This assignment is performed such that the smallest possible edge height is generated between each two consecutive bits.

[0094] In the received signal RxD, the voltage distribution module 16, and particularly its receiving module 162, divides the corresponding bit sequence The digital values ​​are assigned to the corresponding voltages of the differential signal VDIFF when received without errors. For this purpose, the voltage distribution module 16, and in particular its receiving module 162, uses receiving thresholds U_TH1, U_TH2, U_TH3, and U_TH4.

[0095] Therefore, only the digits 0, 1, and 2 can be included in the transmitted signal TxD-TC and transmitted via bus 40. The bit time adjustment module 152 can therefore adjust the duration of segments SY, PP, P1, and P2 during time t in such a way that... Figure 7 In the examples, there are only bits with shorter bit lengths or bit times T3 to T5.

[0096] Therefore, in the bit sequence of a ternary number system, such as in Figure 7 As shown, five different voltage states exist on bus 40. Voltage distribution module 16 therefore assigns five different voltage values, +2V, +1V, 0V, -1V, and -2V, to the corresponding voltage states on bus 40. However, bit time adjustment module 152 adapts the bits of the transmitted signal TxD_TC to only three different bit lengths or bit times, namely bit times T3 to T5. Bit time adjustment module 152 determines this adjustment according to rule 1521, which takes into account the corresponding switching between the digits 0 and 2.

[0097] exist Figure 7 In the example, the selected differential voltage VDIFF, ranging from +2V to -2V, has edge transitions from 0V to 2V depending on the bit sequence. The resulting shorter bit times T3 to T5 lead to... Figure 7 Number sequence or It only lasted for 88 time quantum times (TQ). Compared to this... Figure 6 The example saves time T_E for transmissions on bus 40.

[0098] Data rate compared to the current embodiment Figure 6 Examples can be further improved significantly. Data rates can be increased by up to 36% compared to existing technologies, for example, by using a maximum differential voltage of 1V, as in LVCAN and additional bit-time compression.

[0099] Figure 8 A third embodiment regarding time t illustrates an example for a differential signal VDIFF, which is formed on bus 40 following a digital transmit signal TxD or TxD_TC. The transmit signal TxD can be generated either according to frame 450 or according to the CAN FD protocol.

[0100] for Figure 8 Bit sequence allocation and in Figure 7 The same logical value. Bits B1 to B10 therefore have logical values ​​or numbers in the ternary number system. As explained earlier.

[0101] Voltage distribution module 16-bit sequence Each logic value or digital assignment in the code corresponds to up to two predetermined voltage values ​​for the signal VDIFF on bus 40. The two voltage values, +2V and -1V, are assigned to digital 2. The voltage value +1V is assigned to digital 1. The voltage value 0V is assigned to digital 0. Therefore, an additional differential voltage of -2V is not required.

[0102] In the received signal RxD, the voltage distribution module 16, and particularly its receiving module 162, divides the corresponding bit sequence The digital value is assigned to the corresponding voltage of the differential signal VDIFF when received without errors. For this purpose, the voltage distribution module 16, and in particular its receiving module 162, uses receiving thresholds U_TH1, U_TH2, and U_TH3. However, receiving threshold U_TH4 is not required.

[0103] Therefore, only the digits 0, 1, and 2 can be included in the transmitted signal TxD-TC and transmitted via bus 40. The bit time adjustment module 152 can therefore adjust the duration of segments SY, PP, P1, and P2 during time t in such a way that... Figure 8 In the examples, there are only bits with shorter bit lengths or bit times T3 to T5.

[0104] Therefore, in the bit sequence of a ternary number system, such as in Figure 8 As shown, only four different voltage states exist on bus 40. Voltage distribution module 16 therefore assigns four different voltage values, +2V, +1V, 0V, and -1V, to the corresponding voltage states on bus 40. However, bit time adjustment module 152 adapts the bits of the transmitted signal TxD_TC to only three different bit lengths or bit times, namely bit times T3 to T5. Bit time adjustment module 152 determines this adjustment based on rule 1521, which takes into account the corresponding switching between digits 0 and 2.

[0105] exist Figure 7 In the example, the selected differential voltage VDIFF, ranging from +2V to -2V, has edge transitions from 0V to 2V depending on the bit sequence. The resulting shorter bit times T3 to T5 lead to... Figure 8 Number sequence or More precisely, having and in Figure 7 The same duration as in the example, namely 88 time quanta TQ.

[0106] However, in messages 45 and 46, lower digits, especially 0, appeared statistically more frequently than higher digits, such as 2. Therefore, in Figure 8 In this implementation, lower absolute differential voltages are assigned to lower digits, such as 0 and 1. For example, a voltage of 0V is therefore assigned to the digit 0. Figure 8 The signal can be transmitted via bus 40 in a particularly energy-efficient manner.

[0107] Therefore, the data rate is compared to the current embodiment. Figure 7 Examples can be improved in a more energy-efficient way.

[0108] Figure 9 A frame 450A according to a fourth embodiment is shown. Frame 450A can be used by the communication control device 11 to formulate the transmitted signal TxD and / or evaluate the received signal RxD, as previously described.

[0109] In frame 450A, control field 454 contains at least one bit B_V. The fewer bits B_V are included, the less the net data rate that can be transmitted in bus system 1 decreases.

[0110] At least one bit B_V indicates whether the bit or bit sequence has been shortened in the receive signal RxD currently being received by bus 40.

[0111] Therefore, the transmitting node can notify the receiving node at bus 40, which has at least one bit B_V, how to evaluate the currently received received signal RxD. The receiving node can thus correctly take into account predetermined rules 1521 and 1511 when evaluating the currently received received signal RxD.

[0112] In other words, according to Figure 6 or Figure 7 or Figure 8 The shortened bit or bit sequence used in the previously described method can be notified by the bits reserved in the header of message 45.

[0113] This ensures backward compatibility with known communication protocols, especially CAN-based protocols.

[0114] At least one bit B_V alternative is included in data field 455.

[0115] Figure 9 A frame 450B according to a third embodiment is shown. Frame 450B can be used by the communication control device 11 to formulate the transmit signal TxD and / or evaluate the receive signal RxD, as previously described.

[0116] In frame 450B, at least one bit B_V is included in the data field 455. This at least one bit B_V indicates that in the message 45 immediately transmitted via bus 40, bits or bit sequences are sent after being shortened. Therefore, the receiving node knows that bits or bit sequences are shortened in the subsequent received signal RxD, as in... Figure 7 As shown in the diagram.

[0117] If more than one bit B_V is involved, it can be indicated which of the following messages 45 and 46 is modified at bus 40 to shorten the bits or bit sequence. For example, a special identifier for this message 45 or 46 can be encoded in a bit sequence of at least two bits B_V.

[0118] Therefore, the transmitting node can notify the receiving node with bit B_V how to evaluate the receive signal RxD of the next message 45 or 46 to be received by bus 40. The receiving node can thus correctly take into account the predetermined rules 1521 and 1511 when evaluating this receive signal RxD.

[0119] In other words, the previously described method of shortening bits or bit sequences is used, as in... Figure 6 or Figure 7 or Figure 8 As shown, notification can be made in previous messages for the current received signal RxD.

[0120] It is possible that at least partially shortened bits or bit sequences are also used in messages compiled based on Frame 450B.

[0121] This ensures backward compatibility with known communication protocols, especially CAN-based protocols.

[0122] All previously described design options for user stations 10, 20, and 30, bus system 1, and the methods implemented in bus system 1 can be used individually or in all possible combinations. Features of the previously described embodiments and / or modifications thereof can be combined arbitrarily, in particular. The following modifications can be considered additionally or alternatively.

[0123] At least one of user stations 10, 20, and 30 may, of course, have an alternative design to generate the bus signal VDIFF, as previously described. At least one of modules 15, 25, and 35 is arranged, for example, at least partially, in the associated transmitting / receiving devices 12, 22, and 32.

[0124] Even though the present invention has been described using a CAN bus system as an example, the present invention can be used in every communication network and / or communication method that uses two different communication phases, in which the bus states generated for the different communication phases are different.

[0125] According to this embodiment, bus system 1 can in particular be a communication network in which data can be transmitted serially at two different bit rates. Advantageously, but not mandatory, is that, in bus system 1, exclusive, conflict-free access to a common channel by user stations 10, 20, and 30 is ensured, at least for a specific time period.

[0126] The number and arrangement of user stations 10, 20, and 30 in the bus system 1 of the embodiment are arbitrary. In particular, user station 20 in bus system 1 can be omitted. It is possible that one or more of user stations 10 or 30 exist in bus system 1. It is conceivable that all user stations in bus system 1 are designed to be identical, i.e., only user station 10 or only user station 30 exist.

Claims

1. A communication control device (11; 21; 31) for user stations (10; 20; 30) of a serial bus system (1). in, The communication control unit (11; 21; 31) is designed to control communication between user stations (10; 20; 30) of the bus system (1) and at least one other user station (10; 20; 30) and to generate transmit signals for transmission to the bus (40) of the bus system (1) and / or to receive signals VDIFF from the bus (40). The communication control unit (11; 21; 31) is designed to generate a transmission signal based on the frame (450; 450A; 450B), and The communication control device (11; 21; 31) is designed to generate a transmission signal such that the bit time (T1 to T5) of at least one bit is adjusted according to the edge height in the transmission signal, the edge height being set between at least one bit in the signal VDIFF and a previous bit, the bit being transmitted in the signal via a bus (40), wherein the communication control device (11; 21; 31) is designed to embed at least one predetermined bit B_V into the transmission signal, the at least one predetermined bit indicating to the receiving node in the bus system (1) that the signal VDIFF currently received by the bus (40) is at least partially modified such that the at least one bit is adjusted according to the edge height.

2. The communication control device (11; 21; 31) according to claim 1, wherein, The edge steepness of the signal VDIFF transmitted through the bus (40) is the same as the edge height.

3. The communication control device (11; 21; 31) according to claim 1 further comprises: A conversion block (151) is used to convert at least two bits of the transmitted signal from a binary digital system into logical values ​​in a digital system based on numbers greater than 2, and to generate at least one bit for the transmitted signal; and Bit time adjustment block (152) is used to adjust the bit time of at least one bit of the transmitted signal according to the logic value of at least one bit of the transmitted signal.

4. The communication control device (11; 21; 31) according to any one of claims 1 to 3, wherein, The communication control device (11; 21; 31) is designed to shorten by at least one bit compared to another bit in the frame (450; 450A; 450B), the at least one bit being arranged in a bit sequence of at least two bits having the same logic value.

5. The communication control device (11; 21; 31) according to any one of claims 1 to 3. in, Each bit of the transmitted signal is divided into four segments (SY, PP, P1, P2) within time (t) without shortening. A first scan point (TP) is provided between the first and second segments (SY, PP) for scanning signals after transmission via the bus (40), and A second scan point (TP) is provided between the third and fourth segments (P1, P2) for transmitting the scan signal after transmission via the bus (40).

6. The communication control device (11; 21; 31) according to claim 1, wherein, The communication control device (11; 21; 31) is designed to embed at least one predetermined bit B_V into the control field (454) of the frame (450A; 450B) and / or the data field (455) of the frame (450A; 450B).

7. The communication control device (11; 21; 31) according to any one of claims 1 to 3, wherein the communication control device (11; 21; 31) has an error frame counting block (153) for counting error frames (47) received by the bus (40), and in, The communication control device (11; 21; 31) is designed to not adjust the bit time in the transmitted signal when the count value of the error frame counting block (154) exceeds a predetermined number.

8. The communication control device (11; 21; 31) according to any one of claims 1 to 3, wherein, The communication control device (11; 21; 31) is designed to generate the transmission signal such that, for the message (45) exchanged between user stations (10, 20, 30) of the bus system (1), the bit time (t_bt1) of the signal transmitted on the bus (40) in the first communication phase (451) may be different from the bit time (T1 to T5) of the signal transmitted in the second communication phase (452), and In the first communication phase (451), it is agreed which of the user stations (10, 20, 30) of the bus system (1) will obtain at least temporary exclusive, conflict-free access to the bus (40) in the subsequent second communication phase (452), and The communication control device (11; 21; 31) is designed to adjust at least one bit during the first and / or second communication phase (451, 452) in the time in place (T1 to T5).

9. User stations (10; 20; 30), with The communication control device (11; 21; 31) according to any one of claims 1 to 8, and A voltage distribution module (16; 26; 36) is used to distribute a first voltage value or a second voltage value to the logic value of the bit of the signal VDIFF to be transmitted via the bus (40) of the transmitting signal. in, The voltage distribution modules (16; 26; 36) are designed to assign a logic value to at least one bit of the signal VDIFF on the bus (40), the at least one bit having a minimum edge height at the beginning of the signal VDIFF on the bus (40) along with the logic value.

10. The user station (10; 20; 30) according to claim 9. in, The first voltage value is assigned to the first logic value of the first bit in the bit sequence of the transmitted signal. Specifically, the second voltage value is assigned to the second logic value of the second bit of the bit sequence. Wherein, the first logic value is less than the second logic value, and The first voltage value is less than the second voltage value.

11. The user station (10; 20; 30) according to claim 9, wherein, The frame (450) formed for the message (45) is constructed to be compatible with CAN FD and / or CAN XL.

12. The user station (10; 20; 30) according to any one of claims 9 to 11. In addition, it also includes a transmitting / receiving device (22) on the bus (40) of the bus system (1) for transmitting the transmitted signal or the modified transmitted signal to the bus system (1). in, The transmitting / receiving device (22) is designed to transmit the entire frame (450) onto the bus (40) in an operating mode (B_452_TX) for transmitting and receiving the frame (450) in the first communication phase (451).

13. Bus system (1), with: Bus (40), and At least two user stations (10; 20; 30) are interconnected via a bus (40) such that they can communicate serially with each other, and at least one of the at least two user stations (10; 20; 30) is a user station (10; 20; 30) according to any one of claims 9 to 12.

14. A method for communication in a serial bus system (1), wherein, The method is implemented using a user station (10; 20; 30) of a bus system (1), the user station having a communication control device (11; 21; 31) according to any one of claims 1 to 8, wherein the method comprises the steps of: The communication control device (11; 21; 31) controls the communication between the user stations (10; 20; 30) of the bus system (1) and at least one other user station (10; 20; 30) and generates a transmit signal for transmission to the bus (40) of the bus system (1) and / or a receive signal VDIFF for transmission to the bus (40). Among them, the communication control device (11; 21; 31) generates a transmission signal according to the frame (450; 450A; 450B), and The communication control device (11; 21; 31) generates a transmission signal such that the bit time (T1 to T5) of at least one bit is adjusted according to the edge height in the transmission signal, the edge height being set between at least one bit in the signal VDIFF and the previous bit, in which the bit is transmitted via the bus (40).

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