A processor and method for reducing power consumption

Abstract

A processor and a method for reducing power consumption are used to solve the problem of performance deterioration of a processor core in a high power consumption scenario. The processor includes a processor core configured to determine whether the processor core is in a high power consumption scenario; and execute a first response strategy when the processor core is in the high power consumption scenario. The first response strategy is configured to reduce power consumption of the processor core in a current frequency period, and the high power consumption scenario is configured to indicate that the processor core executes a high power consumption instruction, and the frequency period is configured to indicate a period in which the processor core works based on a frequency.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a processor and a method for reducing power consumption. Background Technology

[0002] In a processor chip, the types of instructions executed by the processor core are diverse. For certain types of instructions, the processor core may utilize more processor components (such as memory units and arithmetic units) to achieve higher execution efficiency, resulting in excessively high processor power consumption, i.e., operating in a high-power scenario. For example, these instructions could be Advanced Vector Extensions (AVX) instructions under the x86 architecture or Scalable Vector Extensions (SVE) instructions under the Advanced Reduced Instruction Set Machine (RISC) machine (ARM) architecture.

[0003] When the processor core is in a high-power scenario, it may cause the processor's instantaneous power consumption to increase sharply, and the required current may exceed the system's design limit for power supply current, which may lead to processor timing disorder or even power-down operation.

[0004] Therefore, existing processor chips suffer from performance degradation under high power consumption scenarios. Summary of the Invention

[0005] This application provides a processor and a method for reducing power consumption, in order to solve the problem of performance degradation of processor chips in high power consumption scenarios.

[0006] In a first aspect, embodiments of this application provide a processor, including: a processor core, configured to determine whether the processor core is in a high-power scenario; when the processor core is in a high-power scenario, executing a first response strategy, the first response strategy being configured to reduce the power consumption of the processor core within the current frequency cycle, the high-power scenario being configured to instruct the processor core to execute a high-power instruction, and the frequency cycle being configured to instruct the processor core to operate based on a frequency for a certain period of time.

[0007] For example, high-power instructions can be AVX instructions under the x86 architecture, SVE instructions under the ARM architecture, or single instruction multiple data (SIMD) instructions.

[0008] Using the processor core provided in the first aspect, when it is determined that the processor core is in a high-power scenario, the processor core executes a first response strategy to reduce the power consumption of the processor core in the current frequency cycle and make an immediate response to the high-power scenario.

[0009] In one possible design, the processor provided in the first aspect further includes a frequency controller, the processor core being further configured to: send a first system control signal to the frequency controller, the first system control signal being configured to instruct the frequency controller to execute a second response strategy, the second response strategy being configured to reduce the power consumption of the processor core in the next frequency cycle of the current frequency cycle. The frequency controller is configured to receive the first system control signal and execute the second response strategy.

[0010] Using the above scheme, the processor core also sends a first system control signal to the frequency controller to instruct the frequency controller to execute a second response strategy, thereby reducing the power consumption of the processor core in the next frequency cycle, so that the frequency controller can respond to high power consumption scenarios in the next frequency cycle, thereby adjusting the system for high power consumption scenarios.

[0011] In addition, the frequency controller is also used to: after executing the second response strategy, send a second system control signal to the processor core, the second system control signal being used to indicate that the second response strategy is in effect; and after receiving the second system response signal, the processor core stops executing the first response strategy.

[0012] Using the above scheme, the execution of the first response strategy can be stopped after the second response strategy executed by the frequency controller takes effect, and the system adjustment can replace the immediate strategy.

[0013] In one possible design, when determining whether a processor core is in a high-power scenario, the processor core specifically does so by: determining whether the processor core is in a high-power scenario based on the density of high-power instructions in the instruction pipeline.

[0014] Specifically, the processor core includes: an instruction comparison circuit for identifying high-power instructions in the instruction pipeline; a counter for counting the high-power instructions identified by the instruction comparison circuit to obtain a first count value; and determining that the processor core is in a high-power scenario when the first count value exceeds a first threshold within a unit time.

[0015] The above approach determines whether a processor core is in a high-power scenario based on the density of high-power instructions in the instruction pipeline, rather than immediately determining that the processor core is in a high-power scenario after a high-power instruction appears. This improves the accuracy of the method for determining high-power scenarios and avoids frequently adopting response strategies to reduce the power consumption of the processor core.

[0016] In one possible design, when determining whether the processor core is in a high-power scenario, the processor core specifically uses the density of the characteristic signal of the high-power event to determine whether the processor core is in a high-power scenario.

[0017] Specifically, the processor core includes: an accumulator for accumulating the number of occurrences of the characteristic signal of the high-power event to obtain a second count value; and a comparator for determining that the processor core is in a high-power scenario when the second count value exceeds a second threshold within a unit time.

[0018] The above scheme determines whether the processor core is in a high-power scenario based on the density of the characteristic signal of the high-power event, rather than immediately determining that the processor core is in a high-power scenario after a high-power instruction occurs. Therefore, it can improve the accuracy of the method of determining the high-power scenario and avoid frequently taking response strategies to reduce the power consumption of the processor core.

[0019] In one possible design, when the processor core executes the first response strategy, it specifically reduces the issue width of the instruction pipeline within the current frequency cycle.

[0020] By adopting the above approach, reducing the issue width of the instruction pipeline can reduce the processing load of the processor core, thereby reducing the power consumption of the processor core.

[0021] Specifically, when reducing the issue width of the instruction pipeline, the processor core can shut down at least one issue channel in the instruction pipeline.

[0022] In other words, the first response strategy can be implemented by reducing the issue width from the issue stage to the execution stage in the instruction pipeline. Closing some issue channels can reduce the switching of subsequent execution unit circuits, thereby reducing the power consumption of the processor core.

[0023] In addition, the processor core may also include a phase-locked loop (PLL) circuit for outputting a clock signal. When executing the first response strategy, the processor core specifically performs the following: divides the clock signal output by the PLL circuit to obtain a divided clock signal; outputs the divided clock signal within the current frequency period, and the divided clock signal drives the processor core. The frequency of the divided clock signal is less than the frequency of the clock signal output by the PLL circuit.

[0024] By adopting the above solution, the power consumption of the processor core can be reduced by lowering the clock signal frequency of the processor core.

[0025] In one possible design, the frequency controller, when executing the second response strategy, specifically adjusts the frequency sent to the processor core in the next frequency cycle of the current frequency cycle.

[0026] By using the above scheme, the frequency controller can adjust the frequency of the processor core, thereby adjusting the power consumption of the processor core.

[0027] In the first implementation, the frequency controller is specifically used to: issue a frequency modulation frequency to the processor core, the effective time of the frequency modulation frequency is the start of the next frequency cycle of the current frequency cycle, and the frequency modulation frequency is less than the preset frequency modulation frequency of the next frequency cycle of the current frequency cycle.

[0028] In the second implementation, the frequency controller is specifically used to: issue a power budget and a maximum frequency to the processor core. The power budget and the maximum frequency take effect at the start of the next frequency cycle of the current frequency cycle. The maximum frequency is used to indicate the maximum frequency at which the processor core operates. The power budget is the same as the preset power budget of the next frequency cycle of the current frequency cycle, and the maximum frequency is less than the preset maximum frequency of the next frequency cycle of the current frequency cycle.

[0029] By employing the two implementation methods described above, when the frequency controller sends the frequency to the processor core in different ways, the sent frequency or the maximum sent frequency can be adjusted respectively, thereby reducing the power consumption of the processor core.

[0030] In one possible design, the frequency controller is also used to: after executing the second response strategy, query (e.g., periodically) whether the first system control signal from the processor core has been received again; if the first system control signal from the processor core has not been received within a preset time period, then stop executing the second response strategy.

[0031] High-power instructions, once compiled, may be repeatedly compiled. Therefore, if the second response strategy has a short effective time (e.g., one frequency cycle), the frequency controller may frequently perform frequency ramping operations on the processor core. To avoid this, the above-mentioned solution allows the frequency controller to stop executing the second response strategy only after the first system control signal indicating a high-power scenario has cooled down.

[0032] Secondly, embodiments of this application provide a method for reducing power consumption, comprising: a processor core determining whether the processor core is in a high-power scenario; when the processor core is in a high-power scenario, the processor core executes a first response strategy, the first response strategy being used to reduce the power consumption of the processor core within the current frequency cycle, the high-power scenario being used to instruct the processor core to execute a high-power instruction, and the frequency cycle being used to instruct the processor core to operate based on a frequency.

[0033] In one possible design, the method further includes: the processor core sending a first system control signal to the frequency controller, the first system control signal being used to instruct the frequency controller to execute a second response strategy; the frequency controller receiving the first system control signal; and the frequency controller executing the second response strategy, the second response strategy being used to reduce the power consumption of the processor core in the next frequency cycle of the current frequency cycle.

[0034] In addition, after the frequency controller executes the second response strategy, the frequency controller can also send a second system control signal to the processor core, which is used to indicate that the second response strategy is in effect.

[0035] Furthermore, after the processor core sends the first system control signal, the processor core receives the second system control signal; then, the processor core stops executing the first response strategy.

[0036] In one possible implementation, the processor core determines whether it is in a high-power scenario by: the processor core determining whether it is in a high-power scenario based on the density of high-power instructions in the instruction pipeline.

[0037] Specifically, the processor core determines whether it is in a high-power scenario based on the density of high-power instructions in the instruction pipeline. This can be achieved in the following way: the processor core identifies high-power instructions in the instruction pipeline; the processor core counts the identified high-power instructions to obtain a first count value; if the first count value exceeds a first threshold, the processor core determines that it is in a high-power scenario.

[0038] In another possible implementation, the processor core determines whether it is in a high-power scenario by: the processor core determining whether it is in a high-power scenario based on the density of the characteristic signal of the high-power event, wherein the characteristic signal of the high-power event is the signal that appears in the control unit, arithmetic unit or memory unit of the processor core when the processor core executes a high-power instruction.

[0039] Specifically, the processor core determines whether it is in a high-power scenario based on the density of the characteristic signals of high-power events. This can be achieved as follows: the processor core accumulates the number of occurrences of the characteristic signals of high-power events to obtain a second count value; if the second count value exceeds a second threshold, the processor core determines that it is in a high-power scenario.

[0040] In one possible implementation, the processor core executes a first response strategy, which includes reducing the issue width of the instruction pipeline within the current frequency cycle.

[0041] Specifically, the processor core can reduce the issue width of the instruction pipeline by shutting down at least one issue channel in the instruction pipeline.

[0042] In another possible implementation, the processor core executes a first response strategy, which includes: the processor core divides the clock signal output by the phase-locked loop circuit to obtain a divided clock signal; the processor core outputs the divided clock signal within the current frequency period, and the divided clock signal is used to drive the processor core.

[0043] In one possible design, the frequency controller executes a second response strategy, which includes adjusting the frequency sent to the processor core in the next frequency cycle of the current frequency cycle.

[0044] For example, the frequency controller can adjust the frequency sent to the processor core in the next frequency cycle of the current frequency cycle by the following method: the frequency controller sends a frequency modulation frequency to the processor core, the effective time of the frequency modulation frequency is the beginning of the next frequency cycle of the current frequency cycle, and the frequency modulation frequency is less than the preset frequency modulation frequency of the next frequency cycle of the current frequency cycle.

[0045] For example, the frequency controller can adjust the frequency sent to the processor core in the next frequency cycle of the current frequency cycle by the following method: the frequency controller sends a power budget and a maximum frequency to the processor core. The power budget and the maximum frequency take effect at the beginning of the next frequency cycle of the current frequency cycle. The maximum frequency is used to indicate the maximum frequency at which the processor core operates. The power budget is the same as the preset power budget of the next frequency cycle of the current frequency cycle, and the maximum frequency is less than the preset maximum frequency of the next frequency cycle of the current frequency cycle.

[0046] In addition, after the frequency controller executes the second response strategy, the method further includes: the frequency controller querying whether it has received the first system control signal from the processor core again; if the frequency controller does not receive the first system control signal from the processor core within a preset time period, it stops executing the second response strategy.

[0047] It should be noted that the power reduction method provided in the second aspect can be regarded as the method executed by the processor provided in the first aspect. The specific implementation method and corresponding technical effects of the power reduction method provided in the second aspect can be found in the relevant description in the first aspect, and will not be repeated here.

[0048] Thirdly, embodiments of this application provide an apparatus for reducing power consumption, comprising: a processor and a power supply, the processor including a plurality of processor cores, the power supply for providing power to the plurality of processor cores, wherein each processor core is used for:

[0049] Determine whether the processor core is in a high-power scenario; when the processor core is in a high-power scenario, execute the first response strategy. The first response strategy is used to reduce the power consumption of the processor core within the current frequency cycle. The high-power scenario is used to instruct the processor core to execute high-power instructions. The frequency cycle is used to indicate the cycle in which the processor core operates based on a frequency.

[0050] It should be noted that the functions of each of the processor cores mentioned above are the same as those of the processor cores in the first aspect or various implementations of the first aspect, and will not be repeated here; the processor mentioned above may also include a frequency controller, the functions of which are the same as those of the frequency controllers in various implementations of the first aspect, and will not be repeated here. Attached Figure Description

[0051] Figure 1 This is a schematic diagram of the structure of an integrated chip provided in an embodiment of this application;

[0052] Figure 2 A flowchart illustrating a frequency controller's decision to exit a second response strategy, provided as an embodiment of this application;

[0053] Figure 3 A schematic diagram illustrating the response time of a first response strategy and a second response strategy provided in an embodiment of this application;

[0054] Figure 4 A flowchart illustrating a processor core provided in an embodiment of this application;

[0055] Figure 5 A flowchart illustrating a frequency controller provided in an embodiment of this application;

[0056] Figure 6 A schematic diagram illustrating a frequency controller distributing frequencies, provided as an embodiment of this application;

[0057] Figure 7 An interaction flowchart of a processor core and a frequency controller provided for an embodiment of this application;

[0058] Figure 8 This is a schematic diagram of another integrated chip structure provided in an embodiment of this application;

[0059] Figure 9 This is a schematic diagram illustrating a method for determining a processor core in a high-power scenario, as provided in an embodiment of this application.

[0060] Figure 10 This is a schematic diagram illustrating another method for determining that a processor core is in a high-power scenario, provided in an embodiment of this application.

[0061] Figure 11 This is a schematic diagram of a phase-locked loop frequency divider circuit provided in an embodiment of this application;

[0062] Figure 12 This is a flowchart illustrating a method for reducing power consumption provided in an embodiment of this application. Detailed Implementation

[0063] The application scenarios of the embodiments of this application will be introduced below.

[0064] The embodiments of this application can be applied to Figure 1 The processor 100 shown, by way of example, can be a system-on-a-chip (SoC). Figure 1 As shown, the processor 100 includes at least one processor core 101 and a frequency controller 102. If the processor 100 includes one processor core 101, then the processor 100 is a single-core processor; if the processor includes multiple processor cores 101, then the processor 100 is a multi-core processor.

[0065] The frequency controller 102 is coupled to all processor cores 101 and is used to control the operating frequency of the processor cores 101; the processor cores 101 are used to execute instructions.

[0066] Generally, the frequency controller can be implemented by a general-purpose processor (a processor different from processor 100).

[0067] In the prior art, when controlling the operating frequency of the processor core 101, the frequency controller 102 can determine the operating frequency of each processor core 101 based on frequency adjustment instructions from the system or hardware. Furthermore, in this embodiment, the frequency controller 102 also determines the operating frequency of each processor core 101 based on system control signals from each processor core 101. For example, if a system control signal sent by a processor core 101 indicates that the processor core 101 is in a high-power scenario, the frequency controller 102 will consider this situation when determining the operating frequency of that processor core 101 and perform power-saving operations such as frequency reduction.

[0068] The concept of high-power instructions can be understood as follows: an instruction is considered high-power if the number of arithmetic or memory units called by the processor core during execution exceeds a preset value. For example, if an instruction calls more than four or six arithmetic logic units (ALUs), it can be considered a high-power instruction. Exemplarily, high-power instructions can be AVX instructions in the x86 architecture, SVE instructions in the ARM architecture, or SIMD instructions.

[0069] The high-power scenario can be understood as follows: When processor core 101 executes certain high-power instructions, it may call up more processor components to achieve higher execution efficiency, resulting in excessive power consumption of processor core 101. This scenario can be called a high-power scenario. In practical applications, a power consumption threshold can be preset. When the power consumption of processor core 101 exceeds the preset threshold, it is considered that processor core 101 is in a high-power scenario.

[0070] Specifically, when controlling the operating frequency of the processor core 101, the frequency controller 102 performs periodic control based on the system frequency modulation cycle. This frequency cycle is used to indicate the cycle in which the processor core 101 operates based on a certain frequency. That is, before each frequency cycle arrives, the frequency controller 102 issues the operating frequency of the processor core 101 for the next frequency cycle to each processor core 101; then, in the next frequency cycle, the processor core 101 operates at the frequency indicated by the frequency controller 102.

[0071] It is important to note that the frequency cycle is different from the clock cycle in which processor core 101 operates; a frequency cycle typically comprises multiple clock cycles. Furthermore, the operating frequency of processor core 101 may differ within different frequency cycles.

[0072] When the frequency controller 102 sends a frequency to the processor core 101, there are two implementation methods. First, the frequency controller 102 can directly send the operating frequency of the processor core 101, in which case the processor core 101 will operate at that frequency in the next frequency cycle. Second, the frequency controller 102 sends a power budget and the maximum operating frequency of the processor core 101 to the processor core 101, in which case the processor core 101 can operate at any frequency lower than the maximum frequency in the next frequency cycle, as long as the power consumption does not exceed the power budget.

[0073] In a specific implementation, each processor core 101 is equipped with a clock generation circuit to generate a clock signal that drives the processor core 101 to operate. For example, the clock generation circuit can be a phase-locked loop (PLL). Before each frequency cycle arrives, the processor core 101 can adjust the PLL so that the processor core operates at the frequency indicated by the frequency controller 102.

[0074] Specifically, in this embodiment, the processor 100 may include a processor core 101, which is used to determine whether it is in a high-power scenario; when it is in a high-power scenario, it executes a first response strategy. The first response strategy is used to reduce the power consumption of the processor core 101 within the current frequency cycle; the high-power scenario indicates that the processor core 101 is executing a high-power instruction; and the frequency cycle indicates the cycle in which the processor core 101 operates based on a frequency.

[0075] In processor 100, when processor core 101 is determined to be in a high-power scenario, processor core 101 executes a first response strategy, thereby reducing the power consumption of processor core 101 within the current frequency cycle. In other words, processor 100 can achieve immediate response in high-power scenarios by reducing processor power consumption within the current frequency cycle through processor core 101.

[0076] In addition, the processor 100 may also include a frequency controller 102, and the processor core 101 is also used to send a first system control signal to the frequency controller 102, the first system control signal being used to instruct the frequency controller 101 to execute a second response strategy; the frequency controller 102 is used to receive the first system control signal and execute the second response strategy, the second response strategy being used to reduce the power consumption of the processor core 101 in the next frequency cycle of the current frequency cycle.

[0077] In other words, the processor core 101 can also send a first system control signal to the frequency controller 102 to instruct the frequency controller 102 to execute a second response strategy. In this scheme, the frequency controller 102 can also reduce the processor power consumption in the next frequency cycle to achieve system response in high power consumption scenarios.

[0078] The processor 100 provided in this application embodiment can reduce processor power consumption and response time within the current frequency cycle. Furthermore, the frequency controller 102 can respond to high-power scenarios in the next frequency cycle, thereby adjusting the system for high-power scenarios. Combining these two adjustment methods allows for both immediate response to high-power scenarios and system-level adjustment, achieving a two-layer response mechanism.

[0079] Furthermore, in the processor 100, after executing the second response strategy, the frequency controller 102 can also send a second system control signal to the processor core 101. The second system control signal is used to indicate that the second response strategy is in effect. Then, upon receiving the second system control signal, the processor core 101 can stop executing the first response strategy.

[0080] In this embodiment of the application, the system control signal can be called a Flag signal. For example, the first system control signal can be called Flag signal 1, and the second system control signal can be called Flag signal 2.

[0081] It is easy to see that the first and second response strategies are implemented in a time-sharing manner. After determining that processor core 101 is in a high-power scenario, processor core 101 can execute the first response strategy in the current frequency cycle, thereby reducing the power consumption of processor core 101 in a short period of time. At the same time, it sends a first system control signal to the frequency controller 102 to instruct the frequency controller 102 to execute the second response strategy. At the beginning of the next frequency cycle, the second response strategy executed by the frequency controller 102 takes effect. The frequency controller 102 can send a second system control signal to processor core 101 to instruct processor core 101 to exit the first response strategy. At this time, only the frequency controller 102 needs to perform system adjustment of processor power consumption. By adjusting the power consumption of processor core 101 at different times by processor core 101 and frequency controller 102, real-time response and system adjustment in high-power scenarios can be achieved.

[0082] Furthermore, after the frequency controller 102 executes the second response strategy, the frequency controller 102 can also query (e.g., periodically) whether it has received the first system control signal from the processor core 101 again; if the frequency controller 102 does not receive the first system control signal from the processor core 101 within a preset time period, it stops executing the second response strategy.

[0083] It is easy to see that, in this embodiment, the effective duration of the second response strategy is configurable. That is, the frequency controller 102 can start timing after receiving the first system control signal. If no first system control signal is received from the same processor core 101 within a preset duration (the specific duration is configurable), the execution of the second response strategy can be stopped. If a first system control signal from the same processor core 101 is received again within the preset duration, timing restarts.

[0084] The above-mentioned scheme for determining when to stop executing the second response strategy can be called the cooling-off mechanism of the second response strategy. In specific implementation, this cooling-off mechanism can be implemented through a timer or counter in the frequency controller 102.

[0085] For example, after receiving the first system control signal sent by the processor core 101, the frequency controller 102 can start a timer for the processor core 101. When the timer reaches a preset duration and the frequency controller 102 does not receive the first system control signal sent by the processor core 101 again within the preset duration, it can stop executing the second response strategy for the processor core 101.

[0086] For example, after receiving the first system control signal sent by the processor core 101, the frequency controller 102 can start a counter for the processor core 101. The counter has a counting threshold. After each frequency cycle, the counter decrements the counting threshold by one. When the counting threshold is zero, the frequency controller 102 stops executing the second response strategy.

[0087] It should be understood that if the processor 100 includes multiple processor cores, processor core 101 can be regarded as any one of the processor cores in the processor 100, and the frequency controller 102 can set a timer or counter for each processor core, thereby implementing an appropriate frequency adjustment strategy for each processor core.

[0088] In a specific example, when the frequency controller 102 determines whether to stop executing the second response strategy, the decision-making process can be as follows: Figure 2 As shown. The frequency controller 102 receives and stores the first system control signal. Corresponding to the stored signal, there is a counting device (timer or scoreboard). Each time the frequency controller 102 receives a first system control signal from the processor core 101, the corresponding timer or scoreboard is cleared. The frequency controller 102 repeatedly queries whether it has received another first system control signal from the processor core 101 at a certain period (e.g., a clock cycle or a frequency cycle). Once a first system control signal from the processor core 101 is found during a query, the corresponding counting device is cleared; otherwise, the value of the counting device is incremented. Each time the value of the counting device increases, it is compared with a preset threshold. If the threshold is reached or exceeded, the corresponding stored signal is cleared and the execution of the second response strategy stops. Otherwise, monitoring and counting continue.

[0089] In the above example, the method of increasing the count by the counting device is used as an example for illustration. In practical applications, a preset threshold can also be set in the counting device. Each time the first system control signal is received, the counting device is set to the threshold. If the first system control signal is not received within a cycle, the count value of the counting device is decremented by one until the count value is zero, and the second response strategy is stopped.

[0090] It should be understood that the reason for adopting the above-mentioned cooling exit mechanism is that high-power instructions, once called and compiled, may be repeatedly called and compiled. Therefore, if the effective time of the second response strategy is short (e.g., one frequency cycle), then after the second response strategy stops executing, if the high-power instructions are repeatedly called and compiled, the frequency controller 102 will frequently perform frequency ramping and boosting operations on the processor core 101. To avoid this phenomenon, the frequency controller 102 can adopt the above-mentioned cooling exit mechanism, stopping the execution of the second response strategy only after the first system control signal indicating the high-power scenario has cooled down (e.g., the count value is 0).

[0091] Furthermore, the above examples illustrate the cooling exit mechanism being executed by the frequency controller 102. In practical applications, the processor core 101 can also determine the exit timing (i.e., the time to stop execution) of the second response strategy, and then notify the frequency controller 102 to stop executing the second response strategy.

[0092] Based on the above description, Figure 3 The diagram illustrates the response times of the first and second response strategies, where the X-axis represents the system's time axis. From... Figure 3 It can be seen that at some point within the (N-1)th frequency cycle of the system frequency adjustment, processor core 101 experienced a high-power scenario, and the first response strategy took effect. At the beginning of the Nth frequency cycle, the second response strategy took effect, and processor core 101 stopped executing the first response strategy. A counter is set in the frequency controller 102. Starting from the Nth frequency cycle, in each frequency cycle, if the frequency controller 102 does not receive the first system control signal sent by processor core 101, the counter value is incremented by one. In the subsequent M-1 frequency cycles, the counter for processor core 101 in the frequency controller 102 never reaches the threshold, so the second response strategy remains in effect during these M-1 frequency cycles. At some point within the N+Mth frequency cycle, the counter reaches the threshold, so at the beginning of the N+M+1th frequency cycle, the frequency controller 102 stops executing the second response strategy.

[0093] Specifically, in this embodiment, the specific process of the operation performed by the processor core 101 can be as follows: Figure 4 As shown. Figure 4As shown, after determining that a high-power scenario has occurred, processor core 101 sends a first system control signal to frequency controller 102. Then, processor core 101 determines whether the second response strategy executed by frequency controller 102 is effective. If it is effective, the process ends; if it is not effective, the first response strategy is executed. After the first response strategy takes effect, processor core 101 determines whether the second response strategy executed by frequency controller 102 is effective. Once the second response strategy takes effect or the high-power scenario ends, the execution of the first response strategy is stopped, and the process ends.

[0094] Specifically, in this embodiment of the application, the specific process of the operation performed by the frequency controller 102 within one frequency cycle can be as follows: Figure 5 As shown. Figure 5 As shown, the frequency controller 102 executes a frequency adjustment process according to a frequency period (e.g., 1ms). Specifically, at the beginning of a frequency period, the frequency controller 102 receives a first system control signal sent by the processor core 101. After receiving and saving this signal, the frequency controller 102 activates a second response strategy and sends a second system control signal to the processor core 101 to indicate that the second response strategy has taken effect. Then, the frequency adjustment for the current frequency period ends.

[0095] Assuming processor 100 includes N processor cores, at the beginning of a frequency cycle, frequency controller 102 receives a first system control signal from M of the N processor cores. Then, frequency controller 102 executes the following for each of the M processor cores: Figure 5 The process is shown below.

[0096] In this context, when the frequency controller 102 executes the second response strategy for the M processor cores, it typically reduces power consumption by lowering the frequency. When controlling the operating frequency of the processor cores, the frequency controller 102 can determine the operating frequency of each processor core based on frequency adjustment instructions from the system or hardware and whether it receives a first system control signal from the processor core. Therefore, for the M processor cores, the frequency controller 102 can reduce the frequency indicated by the frequency adjustment instruction and then issue it to the M processor cores. For the NM processor cores (excluding the M cores), it directly issues the frequency indicated by the frequency adjustment instruction, such as... Figure 6 As shown. In addition, the frequency controller 102 can also send a second system control signal to the M processor cores to indicate that the second response strategy is in effect.

[0097] Combination Figure 4 and Figure 5 The interaction flowchart between processor core 101 and frequency controller 102 can be shown as follows: Figure 7 As shown. From Figure 7 It can be seen that after detecting a high-power scenario, the processor core 101 sends a first system control signal to the frequency controller 102. After the second response strategy takes effect, the frequency controller 102 sends a second system control signal to the processor core 101. The processor core 101 determines whether the second response strategy is effective based on the second system control signal, thereby determining whether to continue executing the first response strategy or stop executing the first response strategy.

[0098] It is not difficult to see that in this embodiment, the processor core 101 has the functions of high power consumption scenario judgment, frequency adjustment, and frequency selection. Therefore, the processor core 101 can be composed of a high power consumption scenario judgment module, a frequency adjustment circuit, and a frequency selection circuit. Taking the processor 100 as an example, which includes four processor cores 101, a possible structural schematic diagram of the processor 100 can be shown as follows. Figure 8 As shown. In Figure 8 In the processor shown, each processor core includes a high-power scenario determination module, a frequency adjustment circuit, and a frequency selection circuit. The high-power scenario determination module is used to determine that the processor core is in a high-power scenario; the frequency adjustment circuit is used to adjust the frequency of the processor core 101; and the frequency selection circuit is used to select the output frequency of the processor core 101 based on the determination of the high-power scenario determination module. The frequency selection circuit and the frequency adjustment circuit can be collectively referred to as the in-core control circuit.

[0099] The above describes the timing of the execution of response strategies by the processor core 101 and the frequency controller 102 in the processor 100, as well as their interaction process. The following section describes the specific internal processes and implementation methods of the processor core 101 and the frequency controller 102 in the processor 100.

[0100] I. Determining the Implementation Method of Processor Core 101 in High-Power Scenarios

[0101] In this embodiment, the high-power scenario is used to indicate that processor core 101 is executing high-power instructions. However, it does not mean that processor core 101 is necessarily in a high-power scenario just because it is executing high-power instructions. Processor core 101 can determine that it is in a high-power scenario in various ways.

[0102] For example, processor core 101 can determine that it is in a high-power scenario based on the density of high-power instructions in the instruction pipeline.

[0103] by Figure 9The following is an example of a six-decode, six-issue, five-stage (fetch, decode, execute, memory access, write-back) out-of-order issue pipeline microarchitecture. In the instruction fetch (IF) stage, the instructions executed by processor core 101 are fetched from the instruction cache. After decoding, they are stored in a queue, awaiting selection and execution in the execute (EX) stage. Depending on the instruction type, some instructions may also access memory (such as main memory) in the memory access (MEM) stage. Finally, the result of instruction execution is written back to a register in the write-back (WB) stage and stored again in a queue, completing the final confirmation sequentially.

[0104] As shown above, instructions exist in different forms in various stages of the instruction pipeline at different levels of the microarchitecture. Therefore, processor core 101 can determine whether it is in a high-power scenario based on the density of high-power instructions at a certain point in the pipeline (such as after decoding). When the density reaches or exceeds a certain preset threshold, processor core 101 is determined to be in a high-power scenario.

[0105] In a specific example, after the instruction is decoded, it is identified by the instruction comparison circuit. Once it is determined to be a high-power instruction, the counter value increases. Within a certain period, once the counter value exceeds a preset threshold, it is determined that processor core 101 is in a high-power scenario.

[0106] For example, processor core 101 can determine whether it is in a high-power scenario based on the density of the characteristic signals of high-power events. These characteristic signals are those appearing in the control unit, arithmetic unit, or memory unit of processor core 101 when it executes high-power instructions. For instance, when processor core 101 executes a high-power instruction, certain characteristic signals will appear in the load store unit (LSU), floating-point SIMD unit (FSU), or ALU. The density of these characteristic signals can determine whether processor core 101 is in a high-power scenario.

[0107] In practical implementation, counters can be set in different execution units within processor core 101. By calculating the number of times the characteristic signal of a high-power event occurs per unit time, it can be determined whether processor core 101 is in a high-power scenario. Alternatively, a scoreboard can be used to determine whether it is in a high-power scenario. For example, a fixed score can be assigned to each characteristic signal of a high-power event. When a characteristic signal of a high-power event occurs, the corresponding score is added to the scoreboard. When the score recorded on the scoreboard reaches a preset value, it is determined that processor core 101 is in a high-power scenario.

[0108] In a specific example, such as Figure 10 As shown, four high-power event characterization signals can be selected from both the LSU and FSU. The occurrence of these characterization signals is counted by an accumulator and then compared with a preset threshold by a comparator. When the count of the accumulator exceeds the preset threshold within a preset period, it is determined that the processor core 101 is in a high-power scenario (outputting a high-power scenario indication signal).

[0109] II. Implementation of the First Response Strategy by Processor Core 101

[0110] In this embodiment of the application, the processor core 101 can execute the first response strategy in a variety of ways.

[0111] In the first implementation, processor core 101 can reduce the issue width of the instruction pipeline within the current frequency cycle. That is, processor core 101 can execute the first response strategy by reducing the issue width from any stage in the instruction pipeline to the next stage. For example, for Figure 9 The instruction pipeline shown allows processor core 101 to execute a first response strategy by reducing the issue width from the fetch stage to the decode stage; alternatively, processor core 101 can also execute a first response strategy by reducing the issue width from the execution stage to the memory access stage.

[0112] In a specific example, processor core 101 may shut down at least one issue channel in the instruction pipeline when executing the first response strategy.

[0113] It's easy to understand that in the first implementation, the first-response strategy is executed by blocking the execution frequency of high-power instructions. For example, in... Figure 9 In the instruction pipeline shown, the maximum number of instructions issued within the same clock cycle is six (i.e., six instructions can be issued to the execution unit simultaneously within the same clock cycle). Therefore, when executing the first response strategy, the maximum number of instructions issued within the same clock cycle can be limited to less than six, i.e., some issue channels are closed. Closing some issue channels can reduce the switching of subsequent execution unit circuits, thereby reducing the power consumption of processor core 101.

[0114] In the second implementation, the processor core 101 includes a PLL circuit for outputting a clock signal. When executing the first response strategy, the processor core 101 can divide the clock signal output by the phase-locked loop circuit to obtain a divided clock signal. Then, it outputs the divided clock signal within the current frequency period, which drives the processor core 101. The frequency of the divided clock signal is less than the frequency of the clock signal output by the phase-locked loop circuit.

[0115] It is not difficult to understand that in the second implementation, the power consumption is reduced by lowering the operating frequency of processor core 101.

[0116] In a specific example, such as Figure 11 As shown, processor core 101 includes a PLL circuit for outputting the aforementioned clock signal. Processor core 101 can divide the clock signal using a frequency divider circuit, and then switch the clock signal using a clock switching circuit. Specifically, it selects to output the clock signal in high-power scenarios and selects to output the divided clock signal in non-high-power scenarios. The PLL can be considered as... Figure 8 The frequency regulation circuit in the processor shown is part of the frequency divider circuit and the selection circuit, which can be considered as part of the frequency regulation circuit. Figure 8 This is a portion of the frequency selection circuitry in the processor shown.

[0117] Of course, in addition to the above-mentioned method of executing the first response strategy through PLL and frequency divider circuit, processor core 101 can also execute the first response strategy by reducing the clock signal frequency or changing the clock signal phase shift. This application embodiment does not specifically limit this.

[0118] Furthermore, in the embodiments of this application, the first implementation method can be combined with the second implementation method to achieve the first response strategy. For example, when the density of the characteristic signal of a high-power instruction or high-power event exceeds 20%, a partial transmission channel can be shut down; when the density of the characteristic signal of a high-power instruction or high-power event exceeds 40%, a PLL frequency divider can be used to output a divided clock signal (i.e., the clock frequency after division is 1 / 2 of the clock frequency output by the PLL); when the density of the characteristic signal of a high-power instruction or high-power event exceeds 80%, a PLL frequency divider can be used to output a divided clock signal (i.e., the clock frequency after division is 1 / 3 of the clock frequency output by the PLL), as shown in Table 1.

[0119] Table 1

[0120] Density of the characterizing signal for high-power commands or high-power events Corresponding first response strategy

[0121] 40％ PLL frequency divider 80％ PLL three-way frequency conversion

[0122] III. Implementation of the Second Response Strategy by Frequency Controller 102

[0123] In this embodiment, when the frequency controller 102 executes the second response strategy, it can adjust the frequency sent to the processor core 101 in the next frequency cycle to reduce the power consumption of the processor core 101. Specifically, various implementation methods can be used to adjust the frequency sent to the processor core 101.

[0124] For example, the frequency controller 102 can directly send the frequency modulation frequency to the processor core 101. The effective time of the frequency modulation frequency is the beginning of the next frequency cycle of the current frequency cycle, and the frequency modulation frequency is less than the preset frequency modulation frequency of the next frequency cycle of the current frequency cycle.

[0125] like Figure 6 As can be seen from the signal flow of the frequency controller 102, when the frequency controller 102 sends the frequency to each processor core in the processor 100, it does so according to the frequency adjustment command. That is, when the first system control signal sent by the processor core 101 is not received, the frequency controller 102 can determine the operating frequency of the processor core 101 in the next frequency cycle according to the frequency adjustment command. For ease of understanding, this operating frequency is called frequency 1 (i.e., the aforementioned preset frequency adjustment frequency). When the first system control signal is received, the frequency controller 102 can add an offset to the frequency 1 to obtain frequency 2 (i.e., the aforementioned frequency adjustment frequency) and send it to the processor core 101. The frequency value of frequency 2 is less than the frequency value of frequency 1.

[0126] For example, the frequency controller 102 calculates that the frequency of Core M in the next frequency cycle is 3GHz according to the frequency adjustment command. When the frequency controller 102 receives the first system control signal sent by Core M, the frequency finally sent to Core M is 2.5GHz, that is, the offset added by the frequency controller 102 to the preset frequency modulation is -0.5GHz.

[0127] Furthermore, in this embodiment, the intensity of the high-power scenario can be indicated by the first system control signal. When the frequency controller 102 adds an offset to the preset frequency modulation, it can select different offsets based on the varying intensity of the high-power scenario. For example, the first system control signal is a 2-bit indicator signal. When the high power consumption is most severe, the indicator signal is "11"; when it is slightly less severe, the indicator signal is "10"; when it is even less severe, the indicator signal is "01"; and when there is no high power consumption, the indicator signal is "00". Correspondingly, the absolute value of the frequency offset set by the frequency controller 102 for the processor core 101 can gradually increase as the severity of the high-power scenario intensifies.

[0128] For example, the frequency controller 102 can send a power budget and a maximum frequency to the processor core 101. The power budget and the maximum frequency take effect at the beginning of the next frequency cycle of the current frequency cycle. The maximum frequency is used to indicate the maximum frequency at which the processor core 101 works. The power budget is the same as the preset power budget of the next frequency cycle, and the maximum frequency is less than the preset maximum frequency of the next frequency cycle.

[0129] In this implementation, when the frequency controller 102 issues a frequency to each processor core, it issues the frequency in the form of maximum frequency plus power budget. After receiving the maximum frequency plus power budget, the processor core 101 performs power control through a local proportional-integral-differential (PID) control system, so that the operating frequency of the processor core 101 is less than the maximum frequency and the power consumption of the processor core 101 is less than the power budget.

[0130] Therefore, if the first system control signal sent by the processor core 101 is not received, the frequency controller 102 can determine the preset maximum frequency and preset power budget of the processor core 101 in the next frequency cycle according to the frequency adjustment instruction; if the first system control signal is received, the maximum frequency sent by the frequency controller 102 to the processor core 101 is less than the preset maximum frequency, and the power budget sent to the processor core 101 is the same as the preset power budget. Thus, under the condition that the power budget is the same, the operating frequency of the processor core 101 is reduced, thereby achieving the purpose of reducing the power consumption of the processor core 101.

[0131] Using the processor 100 provided in this application embodiment, when it is determined that the processor core 101 is in a high-power scenario, the processor core 101 executes a first response strategy to reduce the power consumption of the processor core 101 in the current frequency cycle, thereby realizing an immediate response strategy for high-power scenarios. Furthermore, the processor core 101 can also send a first system control signal to the frequency controller 102 to instruct the frequency controller 102 to execute a second response strategy, thereby reducing the power consumption of the processor core in the next frequency cycle. In other words, in the processor 100, both the processor core can reduce processor power consumption in the current frequency cycle to achieve an immediate response to high-power scenarios, and the frequency controller 102 can reduce processor power consumption in the next frequency cycle to achieve a system response to high-power scenarios.

[0132] The processor 100 provided in this application embodiment can reduce the power consumption of the processor core 101 and decrease the response time within the current frequency cycle. Furthermore, the frequency controller 102 can respond to high-power scenarios in the next frequency cycle, thereby adjusting the system for high-power scenarios. Combining these two adjustment methods allows for both immediate response to high-power scenarios and system-level adjustment, achieving a two-layer response mechanism.

[0133] This application provides an apparatus for reducing power consumption, comprising: a processor and a power supply. The processor includes multiple processor cores, and the power supply provides power to the multiple processor cores. Each processor core is used for:

[0134] Determine if the processor core is in a high-power scenario;

[0135] When the processor core is in a high-power scenario, a first response strategy is executed. The first response strategy is used to reduce the power consumption of the processor core within the current frequency cycle. The high-power scenario is used to instruct the processor core to execute high-power instructions. The frequency cycle is used to instruct the processor core to operate based on a frequency.

[0136] It should be noted that the function of each processor core is the same as that of the processor core in the previous embodiment, and will not be repeated here; the processor may also include a frequency controller, the function of which is the same as that of the frequency controller in the previous embodiment, and will not be repeated here.

[0137] Based on the same inventive concept, embodiments of this application provide a method for reducing power consumption, see [link to relevant documentation]. Figure 12 The method includes the following steps.

[0138] S1201: The processor core determines whether it is in a high-power scenario.

[0139] S1202: When the processor core is in a high-power scenario, it executes the first response strategy.

[0140] The first response strategy is used to reduce the power consumption of the processor core within the current frequency cycle, the high power scenario is used to indicate that the processor core is executing high power instructions, and the frequency cycle is used to indicate the cycle in which the processor core operates based on a frequency.

[0141] Optionally, the method further includes: the processor core sending a first system control signal to the frequency controller, the first system control signal being used to instruct the frequency controller to execute a second response strategy; the frequency controller receiving the first system control signal; and the frequency controller executing the second response strategy, the second response strategy being used to reduce the power consumption of the processor core in the next frequency cycle of the current frequency cycle.

[0142] In addition, after the frequency controller executes the second response strategy, the frequency controller can also send a second system control signal to the processor core, which is used to indicate that the second response strategy is in effect.

[0143] Furthermore, after the processor core sends the first system control signal, the processor core receives the second system control signal; then, the processor core stops executing the first response strategy.

[0144] In addition, after the frequency controller executes the second response strategy, the method further includes: the frequency controller querying whether it has received the first system control signal from the processor core again; if the frequency controller does not receive the first system control signal from the processor core within a preset time period, it stops executing the second response strategy.

[0145] It should be noted that, Figure 12 The power consumption reduction method shown is the method executed by the processor core 101 and the frequency controller 102 in the processor 100. Figure 12 The implementation methods and their technical effects not described in detail in the illustrated method can be found in the relevant description in the processor 100, and will not be repeated here.

[0146] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the scope of the embodiments of this application. Therefore, if these modifications and variations to the embodiments of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

Claims

1. A processor, characterized in that, include: Processor core, used to determine whether the processor core is in a high-power scenario; The processor core includes a phase-locked loop circuit for outputting a clock signal; When the processor core is in the high-power scenario, a first response strategy is executed. The first response strategy is used to reduce the power consumption of the processor core within the current frequency cycle. The high-power scenario is used to instruct the processor core to execute high-power instructions. The frequency cycle is used to indicate the cycle in which the processor core operates based on a frequency. When executing the first response strategy, the processor core is specifically used for: The clock signal output by the phase-locked loop circuit is divided to obtain a frequency-divided clock signal. The frequency-divided clock signal is output within the current frequency period. The frequency-divided clock signal is used to drive the processor core. The frequency of the frequency-divided clock signal is less than the frequency of the clock signal output by the phase-locked loop circuit. The processor further includes a frequency controller; the processor core is also configured to: send a first system control signal to the frequency controller, the first system control signal being used to instruct the frequency controller to execute a second response strategy; The frequency controller is configured to receive the first system control signal and execute the second response strategy, which is configured to reduce the power consumption of the processor core in the next frequency cycle of the current frequency cycle.

2. The processor as described in claim 1, characterized in that, The frequency controller is also used for: After executing the second response strategy, a second system control signal is sent to the processor core, the second system control signal being used to indicate that the second response strategy is in effect.

3. The processor as described in claim 2, characterized in that, The processor core is also used for: After sending the first system control signal, the second system control signal is received; Stop executing the first response strategy.

4. The processor according to any one of claims 1 to 3, characterized in that, When the processor core determines whether it is in a high-power scenario, it is specifically used for: The processor core is determined to be in a high-power scenario based on the density of high-power instructions in the instruction pipeline.

5. The processor as described in claim 4, characterized in that, The processor core includes: An instruction comparison circuit is used to identify the high-power instructions in the instruction pipeline; A counter is used to count the high-power instructions identified by the instruction comparison circuit to obtain a first count value; if the first count value exceeds a first threshold, it is determined that the processor core is in a high-power scenario.

6. The processor according to any one of claims 1 to 3, characterized in that, When determining whether the processor core is in a high-power scenario, the processor core is specifically used for: The density of the characteristic signal of the high power event determines whether the processor core is in a high power scenario. The characteristic signal of the high power event is the signal that appears in the control unit, arithmetic unit or storage unit of the processor core when the processor core executes a high power instruction.

7. The processor as described in claim 6, characterized in that, The processor core includes: An accumulator is used to accumulate the number of occurrences of the characteristic signal of the high-power event to obtain a second count value; A comparator is used to determine that the processor core is in a high-power scenario when the second count value exceeds a second threshold.

8. The processor as claimed in claim 1, characterized in that, When reducing the issue width of the instruction pipeline, the processor core is specifically used for: Shut down at least one transmit channel in the command pipeline.

9. The processor according to any one of claims 1 to 3, characterized in that, When the frequency controller executes the second response strategy, it is specifically used for: The frequency sent to the processor core is adjusted in the next frequency cycle of the current frequency cycle.

10. The processor as claimed in claim 9, characterized in that, When the frequency controller adjusts the frequency sent to the processor core in the next frequency cycle of the current frequency cycle, it is specifically used for: A frequency modulation frequency is issued to the processor core. The effective time of the frequency modulation frequency is the start time of the next frequency cycle of the current frequency cycle. The frequency modulation frequency is less than the preset frequency modulation frequency of the next frequency cycle of the current frequency cycle.

11. The processor as claimed in claim 10, characterized in that, When the frequency controller adjusts the frequency sent to the processor core in the next frequency cycle of the current frequency cycle, it is specifically used for: A power budget and a maximum frequency are issued to the processor core. The power budget and the maximum frequency take effect at the start of the next frequency cycle of the current frequency cycle. The maximum frequency is used to indicate the maximum frequency at which the processor core operates. The power budget is the same as the preset power budget of the next frequency cycle of the current frequency cycle, and the maximum frequency is less than the preset maximum frequency of the next frequency cycle of the current frequency cycle.

12. The processor according to any one of claims 1 to 3, characterized in that, The frequency controller is also used for: After executing the second response strategy, query whether the first system control signal from the processor core has been received again; If no first system control signal is received from the processor core within a preset time period, the execution of the second response strategy will be stopped.

13. A method for reducing power consumption, characterized in that, include: The processor core determines whether it is in a high-power scenario. The processor core includes a phase-locked loop circuit for outputting a clock signal, and the processor also includes a frequency controller. When the processor core is in the high-power scenario, the processor core executes a first response strategy. The first response strategy is used to reduce the power consumption of the processor core within the current frequency cycle. The high-power scenario is used to instruct the processor core to execute high-power instructions. The frequency cycle is used to indicate the cycle in which the processor core operates based on a frequency. When executing the first response strategy, the processor core is specifically used for: The clock signal output by the phase-locked loop circuit is divided to obtain a frequency-divided clock signal. The frequency-divided clock signal is output within the current frequency period. The frequency-divided clock signal is used to drive the processor core. The frequency of the frequency-divided clock signal is less than the frequency of the clock signal output by the phase-locked loop circuit. The method further includes: the processor core sending a first system control signal to the frequency controller, the first system control signal being used to instruct the frequency controller to execute a second response strategy; The frequency controller receives the first system control signal; The frequency controller executes the second response strategy, which is used to reduce the power consumption of the processor core in the next frequency cycle of the current frequency cycle.

14. The method as described in claim 13, characterized in that, After the frequency controller executes the second response strategy, the following is also included: The frequency controller sends a second system control signal to the processor core, the second system control signal being used to indicate that the second response strategy is in effect.

15. The method as described in claim 14, characterized in that, After the processor core sends the first system control signal, the system further includes: The processor core receives the second system control signal; The processor core stops executing the first response strategy.

16. The method according to any one of claims 13 to 15, characterized in that, After the frequency controller executes the second response strategy, the following is also included: The frequency controller queries whether it has received the first system control signal from the processor core again; If the frequency controller does not receive a first system control signal from the processor core within a preset time period, it stops executing the second response strategy.

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