Semiconductor die assembly including bonded through- stack via structures and methods of manufacturing the same

Abstract

This invention discloses a bonding assembly comprising: a first three-dimensional memory die including a first alternating stack of a first insulating layer and a first conductive layer, and a first memory structure located within the first alternating stack; and a second three-dimensional memory die bonded to the first three-dimensional memory die, including a second alternating stack of a second insulating layer and a second conductive layer, and a second memory structure located within the second alternating stack. The first conductive layers have different lateral extents along a first horizontal direction, which decrease with a corresponding vertical distance from driver circuitry devices, and the second conductive layers have different lateral extents along the first horizontal direction, which increase with a corresponding vertical distance from the driver circuitry devices.

Description

[0001] Related applications

[0002] This application claims the benefit of priority to U.S. non-provisional application No. 16 / 936,047, filed July 22, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates in general to the field of semiconductor devices, and more particularly to semiconductor die assemblies including connections through a stacked via structure and methods for forming the same. Background Technology

[0004] Three-dimensional semiconductor devices, including three-dimensional vertical NAND strings with one bit per cell, are disclosed in T. Endoh et al.’s article entitled “Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEDM Proc. (2001) 33-36. Summary of the Invention

[0005] According to embodiments of this disclosure, the bonding assembly includes: a first three-dimensional memory die including a first alternating stack of a first insulating layer and a first conductive layer, a first memory structure located in the first alternating stack, and a first stepped dielectric material portion contacting a stepped surface of the first alternating stack; a second three-dimensional memory die bonded to the first three-dimensional memory die, wherein the second three-dimensional memory die includes a second alternating stack of a second insulating layer and a second conductive layer, a second memory structure located in the second alternating stack, and a second stepped dielectric material portion contacting a stepped surface of the second alternating stack; and driver circuitry. The first conductive layers have different lateral extents along a first horizontal direction, which decrease with a corresponding vertical distance from the driver circuitry, and the second conductive layers have different lateral extents along the first horizontal direction, which increase with a corresponding vertical distance from the driver circuitry.

[0006] According to another embodiment of this disclosure, a method of forming a bonding assembly includes: providing a first three-dimensional memory die, the first three-dimensional memory die including a first alternating stack of a first insulating layer and a first conductive layer, a first memory structure located in the first alternating stack, and a first stepped dielectric material portion contacting a stepped surface of the first alternating stack; and bonding a second three-dimensional memory die to the first three-dimensional memory die, wherein the second three-dimensional memory die includes a second alternating stack of a second insulating layer and a second conductive layer, a second memory structure located in the second alternating stack, and a second stepped dielectric material portion contacting a stepped surface of the second alternating stack. The first three-dimensional memory die is located between driver circuit devices and the second three-dimensional memory die, the first conductive layers having different lateral extents along a first horizontal direction, the lateral extents decreasing with a corresponding vertical distance from the driver circuit devices, and the second conductive layers having different lateral extents along the first horizontal direction, the lateral extents increasing with a corresponding vertical distance from the driver circuit devices. Attached Figure Description

[0007] Figure 1 This is a vertical cross-sectional view of a first exemplary structure following the laterally isolated through-substrate via structure and substrate insulating spacer formed during the formation process in a first substrate according to a first embodiment of the present disclosure.

[0008] Figure 2 This is a vertical cross-sectional view of a first exemplary structure after a first alternating stack of a first insulating layer and a first sacrificial material layer has been formed, according to a first embodiment of the present disclosure.

[0009] Figure 3 This is a vertical cross-sectional view of a first exemplary structure following the patterning of a first stepped dielectric material portion and a first non-stepped dielectric material portion, according to a first embodiment of the present disclosure.

[0010] Figure 4 This is a schematic vertical cross-sectional view of a first exemplary structure after the formation of the memory opening and the connection via opening, according to a first embodiment of the present disclosure.

[0011] Figure 5 This is a vertical cross-sectional view of a first exemplary structure after the formation of a sacrificial connection through-hole opening filling structure according to a first embodiment of the present disclosure.

[0012] Figures 6A to 6H A sequential vertical cross-sectional view of the memory openings during the formation of the memory opening filling structure, according to a first embodiment of the present disclosure, is shown.

[0013] Figure 7This is a vertical cross-sectional view of a first exemplary structure after the formation of a memory opening-filling structure, according to a first embodiment of the present disclosure.

[0014] Figure 8 This is a vertical cross-sectional view of a first exemplary structure after the formation of the back side groove, according to a first embodiment of the present disclosure.

[0015] Figure 9 This is a vertical cross-sectional view of a first exemplary structure after the formation of the back recess according to a first embodiment of the present disclosure.

[0016] Figure 10 This is a vertical cross-sectional view of a first exemplary structure after the formation of a conductive layer, according to a first embodiment of the present disclosure.

[0017] Figure 11 This is a vertical cross-sectional view of a first exemplary structure after removing the sacrificial connecting through-hole opening filler structure from the connecting through-hole opening, according to a first embodiment of the present disclosure.

[0018] Figure 12 This is a vertical cross-sectional view of a first exemplary structure after the formation of a back-side trench insulating spacer and a through-stack insulating spacer, according to a first embodiment of the present disclosure.

[0019] Figure 13 This is a vertical cross-sectional view of a first exemplary structure after forming a back-side contact through-hole structure in a back-side trench and forming a first laterally isolated through-stacked through-hole structure according to a first embodiment of the present disclosure.

[0020] Figure 14 This is a vertical cross-sectional view of a first exemplary structure after the formation of a contact-level dielectric layer and various contact via cavities, according to a first embodiment of the present disclosure.

[0021] Figure 15 This is a vertical cross-sectional view of a first exemplary structure after forming a through-hole structure, a layer contact via structure, a drain contact via structure, and a connection via structure, according to a first embodiment of the present disclosure.

[0022] Figure 16 This is a vertical cross-sectional view of a first exemplary structure after the formation of a first metal interconnect structure and a first interconnect side bonding pad embedded in a first dielectric material layer, according to a first embodiment of the present disclosure.

[0023] Figure 17 This is a vertical cross-sectional view of a first exemplary structure after attaching the handle substrate to the interconnect side of a first three-dimensional memory die, according to a first embodiment of the present disclosure.

[0024] Figure 18This is a vertical cross-sectional view of a first exemplary structure according to a first embodiment of the present disclosure after thinning the first substrate from the back side and forming a first substrate-side bonding pad embedded in the first back-side insulating layer.

[0025] Figure 19 It is a vertical cross-sectional view of a logical die according to the first embodiment of this disclosure.

[0026] Figure 20 This is a vertical cross-sectional view of a first exemplary structure after attaching a logic die to the substrate side of a first three-dimensional memory die, according to a first embodiment of the present disclosure.

[0027] Figure 21 This is a vertical cross-sectional view of the first exemplary structure after the handle substrate has been removed.

[0028] Figure 22 This is a vertical cross-sectional view of a first exemplary structure after attaching a second three-dimensional memory die, according to a first embodiment of the present disclosure.

[0029] Figure 23 This is a vertical cross-sectional view of a first exemplary structure after thinning the back side of the second three-dimensional memory device and forming a second substrate-side bonding pad, according to a first embodiment of the present disclosure.

[0030] Figure 24 This is a vertical cross-sectional view of a first exemplary structure after attaching a third three-dimensional memory device to a second three-dimensional memory device, according to a first embodiment of the present disclosure.

[0031] Figure 25 This is a vertical cross-sectional view of a first exemplary structure after attaching a fourth three-dimensional memory device to a third three-dimensional memory device, according to a first embodiment of the present disclosure.

[0032] Figure 26 This is a vertical cross-sectional view of a first exemplary structure after thinning the substrate of the logic die and forming the back-side bonding pad of the logic die, according to a first embodiment of the present disclosure.

[0033] Figure 27 This is a vertical cross-sectional view of an alternative embodiment of the first exemplary structure according to the first embodiment of the present disclosure.

[0034] Figure 28 This is a vertical cross-sectional view of a second exemplary structure according to a second embodiment of the present disclosure.

[0035] Figure 29 This is a vertical cross-sectional view of an alternative embodiment of the second exemplary structure according to the second embodiment of the present disclosure.

[0036] Figure 30This is a vertical cross-sectional view of a third exemplary structure according to a third embodiment of the present disclosure.

[0037] Figure 31 , Figure 32 and Figure 33 This is a vertical cross-sectional view of the steps of manufacturing a fourth exemplary structure according to a fourth embodiment of the present disclosure. Detailed Implementation

[0038] The performance of a memory package can be enhanced by bonding at least one three-dimensional memory die to a logic die, the logic die including peripheral circuitry for operating a three-dimensional memory array within the at least one three-dimensional memory die. As discussed above, embodiments of this disclosure relate to semiconductor die assemblies including bonding through-hole structures and methods of forming thereof, various aspects of which are described in detail herein.

[0039] The accompanying drawings are not to scale. Where a single instance of an element is shown, multiple instances of the element may be repeated unless explicitly described or otherwise clearly indicated that no repetition of an element exists. Numbers such as “first,” “second,” and “third” are used only to identify similar elements and may be used differently throughout the specification and claims of this disclosure. The term “at least one” element refers to all possibilities, including the possibility of a single element and the possibility of multiple elements.

[0040] The same reference numerals denote the same or similar elements. Unless otherwise stated, elements with the same reference numerals are assumed to have the same composition and the same function. Unless otherwise specified, “contact” between elements means direct contact between elements that provide a shared edge or surface. If two or more elements are not in direct contact with each other, the two elements are “separated” from each other. As used herein, a first element positioned “on” a second element may be positioned on the outer side of the surface of the second element or on the inner side of the second element. As used herein, if there is physical contact between the surfaces of the first element and the second element, the first element is positioned “directly” on the second element. As used herein, if there is a conductive path made of at least one conductive material between the first element and the second element, the first element is “electrically connected” to the second element. As used herein, a “prototype” structure or a “process” structure refers to a transient structure in which the shape or composition of at least one of its components is subsequently modified.

[0041] As used herein, the first and second surfaces are “vertically coincident” if the second surface is above or below the first surface and if there is a vertical or substantially vertical plane that includes both the first and second surfaces. A substantially vertical plane is a plane that extends in a straight line along an angle less than 5 degrees from the vertical direction. The vertical or substantially vertical plane is straight along the vertical or substantially vertical direction and may or may not include curvature along a direction perpendicular to the vertical or substantially vertical direction.

[0042] As used herein, a “memory level” or “memory array level” refers to a level corresponding to the general area between a first horizontal plane (i.e., a plane parallel to the top surface of the substrate) that includes the topmost surface of the memory element array and a second horizontal plane that includes the bottommost surface of the memory element array. As used herein, a “through-stack” element refers to an element that extends vertically through the memory level.

[0043] As used in this article, "semiconductor material" refers to a material with a conductivity of 1.0 × 10⁻⁶ m / s. -5 S / m to 1.0×10 5 Materials exhibiting electrical conductivity in the range of S / m. As used herein, "semiconductor material" refers to a material having a conductivity in the absence of electrical dopants in the presence of 1.0 × 10⁻⁶ S / m. -5 Materials with electrical conductivity ranging from 1.0 S / m to 1.0 S / m can be produced by appropriate doping with electrodopersive agents, resulting in materials with conductivity ranging from 1.0 S / m to 1.0 × 10⁻⁶ S / m. 5 Doped materials with electrical conductivity in the range of S / m. As used herein, “electrical dopant” refers to a p-type dopant that adds holes to the valence band of the band structure, or an n-type dopant that adds electrons to the conduction band of the band structure. As used herein, “conductive material” refers to a material with conductivity greater than 1.0 × 10⁻⁶ S / m. 5 Materials with a conductivity of S / m. As used herein, "insulating material" or "dielectric material" refers to a material with a conductivity of less than 1.0 × 10⁻⁶ S / m. -5 Materials with an electrical conductivity of S / m. As used herein, "heavily doped semiconductor material" refers to a material doped with an electrically conductive agent at a sufficiently high atomic concentration to become a conductive material when formed into a crystalline material or when converted into a crystalline material by an annealing process (e.g., from an initial amorphous state). 5 Semiconductor materials with a conductivity of S / m. "Doped semiconductor materials" can be heavily doped semiconductor materials, or can include those exhibiting a conductivity of 1.0 × 10⁻⁶ S / m. -5 S / m to 1.0×10 5Semiconductor materials with electrical dopant concentrations (i.e., p-type and / or n-type dopant) in the range of S / m. "Intrinsic semiconductor material" refers to a semiconductor material undoped with electrical dopants. Therefore, a semiconductor material can be semiconductor or conductive, and can be intrinsic or doped. Doped semiconductor materials can be semiconductor or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, "metallic material" refers to a conductive material comprising at least one metallic element. All conductivity measurements were performed under standard conditions.

[0044] A monolithic three-dimensional memory array is a memory array in which multiple memory levels are formed over a single substrate, such as a semiconductor wafer, without an intervening substrate. The term "monolithic" refers to the fact that the layers of each level of the array are deposited directly on the layers of each lower level of the array. In contrast, two-dimensional arrays can be formed separately and then packaged together to form a non-monolithic memory device. For example, as described in U.S. Patent 5,915,167 entitled "Three-dimensional Structure Memory," a non-monolithic stacked memory is constructed by forming memory levels on separate substrates and vertically stacking the memory levels. The substrate may be thinned or removed from the memory level prior to bonding, but since the memory levels are initially formed over separate substrates, such a memory is not a true monolithic three-dimensional memory array. The substrate may include integrated circuits, such as drive circuitry for the memory device, fabricated thereon.

[0045] The various three-dimensional memory devices disclosed herein include three-dimensional NAND string memory devices and can be fabricated using the various embodiments described herein. The three-dimensional NAND string may be located in a single three-dimensional NAND string array. Driver circuitry may be formed on the same substrate as the NAND string, or on a different substrate, and then the driver circuitry is bonded to the NAND string. At least one memory cell in a first device layer of the three-dimensional NAND string array is located above another memory cell in a second device layer of the three-dimensional NAND string array.

[0046] Generally speaking, a semiconductor package (or "package") refers to a unit semiconductor device that can be attached to a circuit board via a set of pins or solder balls. A semiconductor package may include one or more semiconductor chips (or "chips") that are joined through each other, for example, by flip-chip bonding or another chip-to-chip bonding method. A package or chip may include a single semiconductor die (or "die") or multiple semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Typically, a package or chip with multiple dies can execute as many external commands simultaneously as the total number of dies therein. Each die includes one or more planes. The same concurrent operation can be performed in each plane within the same die, but there may be some limitations. When the die is a memory die (i.e., a die that includes memory elements), concurrent read operations, concurrent write operations, or concurrent erase operations can be performed in each plane within the same memory die. In a memory die, each plane contains multiple memory blocks (or "blocks") that are the smallest units that can be erased by a single erase operation. Each memory block contains multiple pages that are the smallest units that can be selected for programming. A page is also the smallest unit that can be selected for read operations.

[0047] refer to Figure 1 The illustration shows a first exemplary structure according to a first embodiment of the present disclosure, which can be used, for example, to manufacture a three-dimensional memory die comprising an array of three-dimensional memory elements, such as a three-dimensional NAND memory element array or a three-dimensional NOR memory element array. Although the present disclosure is described in terms of a one-dimensional NAND memory element array, embodiments of the present disclosure can be used to form a three-dimensional NOR memory element array or other types of three-dimensional memory elements.

[0048] The first exemplary structure includes a substrate 910, which includes a semiconductor material layer 912 at least in its upper portion. In one embodiment, the substrate 910 may be a monolithic semiconductor substrate (such as a commercially available silicon wafer with a diameter ranging from 150 mm to 450 mm and a thickness ranging from 600 micrometers to 1 mm), or it may be a semiconductor-on-insulator (e.g., silicon-on-insulator, SOI) substrate, which includes a semiconductor material layer as a top semiconductor layer covering a buried oxide layer. Optionally, deep trenches may be formed through the upper portion of the substrate 910, and a combination of substrate insulating spacers 932 and transversely isolated through-substrate via structures 934 may be formed within each deep trench. The depth of each deep trench may range from 1 micrometer to 20 micrometers, such as 2 micrometers to 10 micrometers, and the maximum lateral dimension of each deep trench may range from 1 micrometer to 20 micrometers, such as 2 micrometers to 10 micrometers, but smaller and larger depths and maximum lateral dimensions may be used for the deep trenches. Each deep trench can have the following horizontal profile shapes: circular, elliptical, rectangular, rounded rectangle, or generally curved two-dimensional closed shape. A conformal insulating material layer comprising an insulating material (such as silicon oxide, silicon nitride, silicon oxynitride, and / or dielectric metal oxide) can be deposited in the deep trench using a conformal deposition process. At least one conductive filling material, such as at least one metallic material and / or a heavily doped semiconductor material, can be deposited in the remaining volume of the deep trench after the formation of the conformal insulating material layer. Excess portions of the conformal insulating material layer and the at least one metallic material can be removed from a horizontal plane including the top surface of the substrate 910 using a planarization process such as a chemical mechanical planarization process. Each remaining portion of the conformal insulating material layer constitutes a substrate insulating spacer 932, and each remaining portion of the at least one conductive material constitutes a laterally isolated through-substrate via structure 934'. Each successive combination of the substrate insulating spacer 932 and the laterally isolated through-substrate via structure 934' constitutes a through-substrate connection structure 930'. Alternatively, the through-substrate connection structure 930' can be omitted at this stage of the process, and the connection structure can be formed during subsequent process steps.

[0049] refer to Figure 2An alternating stack of insulating layer 32 and sacrificial material layer 42 is formed above the top surface of substrate 910. In one embodiment, the alternating stack (32, 42) may include an insulating layer 32 made of a first material and a sacrificial material layer 42 made of a second material, which is different from the first material and can subsequently be selectively removed from the first material. Insulating materials that can be used for insulating layer 32 include, but are not limited to, silicon oxide (including doped or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicon glass (OSG), spin-coated dielectric materials, dielectric metal oxides (e.g., alumina, hafnium oxide, etc.) and their silicates, dielectric metal oxynitrides and their silicates, and organic insulating materials, which are commonly referred to as high dielectric constant (high k) dielectric oxides. In one embodiment, the first material of insulating layer 32 may be silicon oxide.

[0050] The second material of the sacrificial material layer 42 is a sacrificial material that can be selectively removed from the first material of the insulating layer 32. As used herein, the removal of the first material is "selective" for the second material if the removal process removes the first material at a rate at least twice the removal rate of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material. The sacrificial material layer 42 may comprise an insulating material, a semiconductor material, or a conductive material. The second material of the sacrificial material layer 42 may subsequently be replaced with a conductive electrode, which may be used as, for example, a control gate electrode for a vertical NAND device. Non-limiting examples of the second material include silicon nitride, amorphous semiconductor materials (such as amorphous silicon), and polycrystalline semiconductor materials (such as polycrystalline silicon). In one embodiment, the sacrificial material layer 42 may be a spacer material layer comprising silicon nitride or a semiconductor material, the semiconductor material comprising at least one of silicon and germanium.

[0051] In one embodiment, insulating layer 32 may comprise silicon oxide, and sacrificial material layer 42 may comprise silicon nitride. The first material of insulating layer 32 may be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is used for insulating layer 32, tetraethyl orthosilicate (TEOS) may be used as a precursor material for the CVD process. The second material of sacrificial material layer 42 may be formed, for example by CVD or atomic layer deposition (ALD). The thickness of insulating layer 32 and sacrificial material layer 42 may range from 20 nm to 50 nm, but smaller and larger thicknesses may be used for each insulating layer 32 and each sacrificial material layer 42. The number of repetitions of pairs of insulating layer 32 and sacrificial material layer (e.g., control gate electrode or sacrificial material layer) 42 may range from 2 to 1,024, and is typically in the range of 8 to 256, but more repetitions may also be used.

[0052] Although this disclosure describes an embodiment in which the spacer material layer is a sacrificial material layer 42 that is subsequently replaced by a conductive layer, embodiments in which the sacrificial material layer 42 is formed in place of the conductive layer are explicitly contemplated. In this case, the process step of replacing the sacrificial material layer 42 with a conductive layer can be omitted.

[0053] refer to Figure 3 The alternating stacks (32, 42) can be patterned to form a stepped surface on at least one side. As used herein, a “stepped surface” refers to a set of surfaces including at least two horizontal surfaces and at least two vertical surfaces, such that each horizontal surface abuts the bottom edge of a corresponding vertical surface, and the top edge of each vertical surface abuts the edge of a corresponding horizontal surface. A stepped cavity is formed within the volume by removing portions of the alternating stacks (32, 42) from the volume by forming the stepped surface. A “stepped cavity” refers to a cavity having a stepped surface. Optionally, a non-stepped cavity can be formed on opposite sides of the stepped cavity. As used herein, a non-stepped cavity refers to a cavity without a stepped surface. Thus, a non-stepped cavity may include a straight sidewall extending vertically from the bottom surface of the alternating stacks (32, 42) to the top surface of the alternating stacks (32, 42).

[0054] The stepped cavity can have various stepped surfaces, such that the horizontal profile shape of the stepped cavity gradually changes according to the vertical distance from the top surface of the substrate 910. In one embodiment, the stepped cavity can be formed by repeatedly performing a set of processing steps. This set of processing steps may include, for example, a first type of etching process and a second type of etching process, the first type of etching process vertically increasing the cavity depth by one or more levels, and the second type of etching process laterally extending the area to be vertically etched in subsequent etching processes of the first type of etching process. As used herein, a “level” comprising alternating multiple structures is defined as the relative position of a pair of first and second material layers within the structure.

[0055] In the platform region 300, each sacrificial material layer 42 within the alternating stacks (32, 42), except for the topmost sacrificial material layer 42, extends laterally further than any overlying sacrificial material layer 42 within the alternating stacks (32, 42). The platform region 300 includes stepped surfaces of the alternating stacks (32, 42) that extend continuously from the bottommost layer within the alternating stacks (32, 42) to the topmost layer within the alternating stacks (32, 42). Each sacrificial material layer 42 has a corresponding lateral extent. The sacrificial material layers 42 may have different lateral extents along the horizontal direction hd1. In one embodiment, the lateral extent of the sacrificial material layers 42 may increase with a corresponding vertical distance from the top surface of the substrate 910. Each insulating layer 32 has a corresponding lateral extent. The insulating layers 32 may have different lateral extents along the horizontal direction hd1 (e.g., word line direction). In one embodiment, the lateral extent of the insulating layer 32 may increase with a corresponding vertical distance from the top surface of the substrate 910. The second horizontal direction (e.g., the bit line direction) may be defined as a horizontal direction perpendicular to the horizontal direction hd1.

[0056] A stepped dielectric portion 65 can be formed in the stepped cavity by depositing a dielectric material within the cavity. For example, a dielectric material such as silicon oxide can be deposited in the stepped cavity. Excess portions of the deposited dielectric material can be removed from the top surfaces of the alternating stacks (32, 42), for example, by chemical mechanical planarization (CMP). The remaining portion of the deposited dielectric material filling the stepped cavity constitutes the stepped dielectric portion 65. If silicon oxide is used for the stepped dielectric portion 65, the silicon oxide of the stepped dielectric portion 65 may or may not be doped with dopants such as B, P, and / or F. A non-stepped dielectric portion 165 can be formed in the non-stepped cavity simultaneously with the formation of the stepped dielectric portion 65.

[0057] refer to Figure 4 A photolithographic material stack (not shown), including at least a photoresist layer, can be formed over the alternating stacks (32, 42) and the stepped dielectric material portion 65, and can be photolithographically patterned to form openings therein. The openings include a first set of openings formed over the memory array region 100 and a second set of openings formed over the connection region 200 adjacent to the stepped surface. The memory array region 100 and the connection region 200 are located within the regions where each layer of the alternating stacks (32, 42) exists. The memory array region 100 can be laterally spaced from the plateau region 300 by the connection region 200. In other words, the connection region 200 can be located between the memory array region 100 and the plateau region 300.

[0058] The pattern in the photolithographic material stack can be transferred through at least one anisotropic etching using a patterned photolithographic material stack as an etching mask through the alternating stacks (32, 42) or stepped dielectric material portions 65, and through the alternating stacks (32, 42). The portions of the alternating stacks (32, 42) below the openings in the patterned photolithographic material stack are etched to form memory openings 49 and connection via openings 29. As used herein, a “memory opening” refers to a structure in which memory elements, such as memory stack structures, are subsequently formed. As used herein, a “connection via opening” refers to a structure in which connection via structures are subsequently formed. The memory opening 49 is formed through each layer of the alternating stacks (32, 42) in the memory array region 100. The connection via opening 29 is formed through each layer of the alternating stacks (32, 42) in the connection region 200. The top surface of the laterally isolated through-substrate via structure 934' (if present) can be physically exposed at the bottom of each connection via opening 29 during the process. Alternatively, the connection via opening 29 may be formed during subsequent steps of the process. Optionally, in addition to the memory opening 49 and the connection via opening 29, support openings (not shown) may be formed. In this case, a support pillar structure (not shown) comprising dielectric material or the same group of materials may subsequently be formed within each support opening as a memory opening filling structure.

[0059] The chemicals used in the anisotropic etching process for etching materials through the alternating stacks (32, 42) can be alternated to optimize the etching of the first and second materials in the alternating stacks (32, 42). Anisotropic etching can be, for example, a series of reactive ion etchings. The sidewalls of the memory opening 49 and the via opening 29 can be substantially vertical or tapered. The patterned photolithographic material stack can then be removed, for example, by ashing. The memory opening 49 and the via opening 29 can extend from the top surface of the alternating stacks (32, 42) at least to a horizontal plane including the topmost surface of the semiconductor material layer 912. The photolithographic mask stack can then be removed, for example, by ashing.

[0060] Each of the memory opening 49 and the connection via opening 29 may include a sidewall (or multiple sidewalls) extending substantially perpendicular to the topmost surface of the substrate 910. A two-dimensional array of memory openings 49 may be formed in the memory array region 100. A two-dimensional array of connection via openings 29 may be formed in the connection region 200.

[0061] refer to Figure 5Sacrificial filler material can be deposited in the memory opening 49 and the via opening 29. The sacrificial filler material differs from the materials of the semiconductor material layer 912, the insulating layer 32, and the sacrificial material layer 42. For example, if the insulating layer 32 comprises silicon oxide and if the sacrificial material layer 42 comprises silicon nitride, the sacrificial filler material can comprise amorphous carbon, amorphous silicon, silicon-germanium alloy, silicon-based polymer, organosilicon glass, or another material that can be selectively removed from the materials of the semiconductor material layer 912, the insulating layer 32, and the sacrificial material layer 42. Excess portions of the sacrificial filler material layer can be removed from a horizontal plane comprising the top surface of the alternating stack (32, 42) by a planarization process such as chemical mechanical planarization. Furthermore, a photoresist layer (not shown) can be applied over the alternating stack (32, 42) and can be photolithographically patterned to cover the connection region 200 but not the memory array region 100. Portions of the sacrificial filler material filling the memory opening 49 can be removed by an etching process, which can be an isotropic etching process or an anisotropic etching process. The photoresist layer can then be removed, for example, by ashing. Each remaining portion of the sacrificial filler material filling the via opening 29 constitutes a sacrificial via opening filling structure 28. Each sacrificial via opening filling structure 28 may have a cylindrical shape having at least one straight sidewall extending vertically from the bottom surface of the alternating stacks (32, 42) to the top surface of the alternating stacks (32, 42). Each sacrificial via opening filling structure 28 may have a maximum lateral dimension in the range of 200 nm to 2,000 nm, such as 400 nm to 1,000 nm, but smaller and larger maximum lateral dimensions may be used for the sacrificial via opening filling structure 28. Each sacrificial via opening filling structure 28 may have the following horizontal profile shapes: circular, elliptical, rectangular, rounded rectangle, or generally curved two-dimensional closed shape. Alternatively, if the via opening 29 is formed during subsequent process steps, it may be omitted. Figure 4 and Figure 5 The steps shown are as well as the sacrificial connection through-hole opening filling structure 28.

[0062] Figures 6A to 6H The structural change in memory opening 49 is shown, which is Figure 5 A memory opening in memory opening 49 of the first exemplary structure. (Refer to...) Figure 6A , showed Figure 5The exemplary device structure includes memory openings 49. Memory openings 49 extend through the alternating stack (32, 42) and optionally extend into the upper portion of the semiconductor material layer 912. The recess depth of the bottom surface of each memory opening 49 relative to the top surface of the semiconductor material layer 912 can range from 0 nm to 30 nm, but larger recess depths are also possible. Optionally, the sacrificial material layer 42 can be partially laterally recessed, for example, by isotropic etching to form lateral recesses (not shown).

[0063] refer to Figure 6B Optional pedestal channel portions (e.g., epitaxial pedestals) 11 may be formed, for example, by selective epitaxy at the bottom of each memory opening 49. If the semiconductor material layer 912 is single-crystal, each pedestal channel portion 11 may include single-crystal semiconductor material epitaxially aligned with the single-crystal semiconductor material of the semiconductor material layer 912. In one embodiment, the pedestal channel portion 11 may be doped with an electrical dopant of the same conductivity type as the semiconductor material layer 912.

[0064] refer to Figure 6C A stack of layers, including a barrier dielectric layer 52, a charge storage layer 54, a tunneling dielectric layer 56, and an optional semiconductor channel layer 601, can be sequentially deposited in the memory opening 49.

[0065] refer to Figure 6D The optional semiconductor channel layer 601, tunneling dielectric layer 56, charge storage layer 54, and barrier dielectric layer 52 are sequentially and anisotropically etched using at least one anisotropic etching process. Portions of the semiconductor channel layer 601, tunneling dielectric layer 56, charge storage layer 54, and barrier dielectric layer 52 located above the top surface of the alternating stack (32, 42) can be removed using at least one anisotropic etching process. Furthermore, horizontal portions of the semiconductor channel layer 601, tunneling dielectric layer 56, charge storage layer 54, and barrier dielectric layer 52 at the bottom of each memory cavity 49' can be removed to form openings in their remaining portions. Each of the semiconductor channel layer 601, tunneling dielectric layer 56, charge storage layer 54, and barrier dielectric layer 52 can be etched using a corresponding anisotropic etching process employing a corresponding etching chemical that can be the same or different for various material layers.

[0066] Each remaining portion of the semiconductor channel layer 601 may have a tubular configuration. The charge storage layer 54 may include a charge trapping material or a floating gate material. In one embodiment, each charge storage layer 54 may include a vertically stacked charge storage regions that store charge during programming. In one embodiment, the charge storage layer 54 may be a charge storage layer in which each portion adjacent to the sacrificial material layer 42 constitutes a charge storage region.

[0067] The surface of the base channel portion 11 (or the surface of the semiconductor material layer 912 in the absence of the base channel portion 11) may be physically exposed beneath the opening through the semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, and the barrier dielectric layer 52. Optionally, the physically exposed semiconductor surface at the bottom of each memory cavity 49' may be vertically recessed such that the recessed semiconductor surface beneath the memory cavity 49' is vertically offset by a recess distance from the topmost surface of the base channel portion 11 (or the semiconductor material layer 912 in the absence of the base channel portion 11). The tunneling dielectric layer 56 is positioned above the charge storage layer 54. The assembly of the barrier dielectric layer 52, the charge storage layer 54, and the tunneling dielectric layer 56 in the memory opening 49 constitutes a memory film 50, which includes a plurality of charge storage regions (e.g., portions of the charge storage layer 54) insulated from the surrounding material by the barrier dielectric layer 52 and the tunneling dielectric layer 56. In one embodiment, the semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, and the barrier dielectric layer 52 may have vertically overlapping sidewalls.

[0068] refer to Figure 6E The second semiconductor channel layer 602 may be deposited directly on the semiconductor surface of the base channel portion 11 or on the semiconductor material layer 912 (if the base channel portion 11 is omitted), and directly on the semiconductor channel layer 601. The second semiconductor channel layer 602 may partially fill the memory cavity 49' in each memory opening, or may completely fill the cavity in each memory opening. The materials of the semiconductor channel layer 601 and the second semiconductor channel layer 602 are collectively referred to as the semiconductor channel material. In other words, the semiconductor channel material is the collection of all semiconductor materials in the semiconductor channel layer 601 and the second semiconductor channel layer 602.

[0069] refer to Figure 6F If the memory cavity 49' in each memory opening is not completely filled by the second semiconductor channel layer 602, a dielectric core layer 62L can be deposited in the memory cavity 49' to fill any remaining portion of the memory cavity 49' in each memory opening. The dielectric core layer 62L comprises a dielectric material such as silicon oxide or organosilicon glass. The dielectric core layer 62L can be deposited by conformal deposition methods such as low-pressure chemical vapor deposition (LPCVD) or by self-planarization deposition processes such as spin coating.

[0070] refer to Figure 6GThe horizontal portion of the dielectric core layer 62L can be removed, for example, by recess etching from above the top surface of the alternating stack (32, 42). Each remaining portion of the dielectric core layer 62L constitutes the dielectric core 62. Furthermore, the horizontal portion of the second semiconductor channel layer 602 located above the top surface of the alternating stack (32, 42) can be removed by a planarization process employing recess etching or chemical mechanical planarization (CMP). Each remaining portion of the second semiconductor channel layer 602 can be entirely positioned within the memory opening 49 or entirely positioned within the via opening 29.

[0071] Each adjacent pair of semiconductor channel layer 601 and second semiconductor channel layer 602 can collectively form a vertical semiconductor channel 60 through which current can flow when a vertical NAND device including the vertical semiconductor channel 60 is turned on. A tunneling dielectric layer 56 is surrounded by a charge storage layer 54 and laterally surrounds a portion of the vertical semiconductor channel 60. Each pair of adjacent barrier dielectric layers 52, charge storage layers 54, and tunneling dielectric layers 56 collectively constitute a memory film 50, which can store charge for a macroscopic retention time. In some embodiments, the barrier dielectric layer 52 may be absent in the memory film 50 at this step, and the barrier dielectric layer may be formed subsequently after the formation of the backside recess. As used herein, macroscopic retention time refers to a retention time suitable for operation of a memory device as a permanent memory device, such as a retention time exceeding 24 hours.

[0072] refer to Figure 6H The top surface of each dielectric core 62 can be further recessed into each memory opening, for example by recess etching to a depth between the top and bottom surfaces of the alternating stack (32, 42). A drain region 63 can be formed by depositing doped semiconductor material within each recessed region above the dielectric core 62. The drain region 63 can have a second conductivity type doped to the opposite of the conductivity type. For example, if the conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration of the drain region 63 can be 5.0 × 10⁻⁶. 19 / cm 3 Up to 2.0 × 10 21 / cm 3 Within the range, although smaller and larger dopant concentrations can also be used. The doped semiconductor material can be, for example, doped polysilicon. Excess portions of the deposited semiconductor material can be removed from the top surface of the alternating stack (32,42), for example, by chemical mechanical planarization (CMP) or recess etching, to form the drain region 63.

[0073] Each combination of the memory film 50 within the memory opening 49 and the vertical semiconductor channel 60 constitutes a memory stack structure 55. The memory stack structure 55 is a combination of a semiconductor channel, a tunneling dielectric layer 56, a charge storage layer 54, and an optional barrier dielectric layer 52. Each combination of the base channel portion 11 (if present), the memory stack structure 55, the dielectric core 62, and the drain region 63 within the memory opening 49 is referred to herein as a memory opening-filled structure 58.

[0074] refer to Figure 7 This illustrates a first exemplary structure after a memory opening filling structure 58 is formed within the memory opening 49. It can be... Figure 5 An example of a memory opening-filling structure 58 is formed within each memory opening 49 of the structure. Each memory stack structure 55 includes a vertical semiconductor channel 60 and a memory film 50, the vertical semiconductor channel including multiple semiconductor channel layers (601, 602) or a single semiconductor channel layer 602. The memory film 50 may include a tunneling dielectric layer 56 laterally surrounding the vertical semiconductor channel 60, a charge storage region (e.g., including a portion of a charge storage layer 54) laterally surrounding the tunneling dielectric layer 56, and optionally a barrier dielectric layer 52. Although this disclosure is described using the illustrated configuration for a memory stack structure, the methods of this disclosure can be applied to alternative memory stack structures including different layer stacks or structures for the memory film 50 and / or for the vertical semiconductor channel 60.

[0075] Generally, the memory opening 49 extends vertically through each of the alternately stacked layers (32, 42). A memory opening filling structure 58 is located within the memory opening 49. Each memory opening filling structure 58 includes a corresponding vertical semiconductor channel 60 and a corresponding memory film 50. A three-dimensional memory element array is provided, including portions of the memory film 50. For example, the three-dimensional memory element array may include a portion of a charge storage layer 54 located at a level of the sacrificial material layer 42. In one embodiment, each memory element may include a cylindrical portion of the corresponding charge storage layer 54 contacting the corresponding sacrificial material layer 42. The substrate 910 may include a semiconductor material layer 912 in electrical contact with the bottom end of each vertical semiconductor channel 60.

[0076] refer to Figure 8A photoresist layer (not shown) can be applied over the alternating stacks (32, 42), the stepped dielectric portion 65, and the non-stepped dielectric portion 165, and photolithographically patterned to form openings in the region between the clusters of memory aperture-filled structures 58. The pattern in the photoresist layer can be anisotropically etched across the alternating stacks (32, 42) and the stepped dielectric portion 65 to form a back-side trench 79 that extends at least vertically from the top surface of the alternating stacks (32, 42) to the top surface of the substrate 910. In one embodiment, the back-side trench 79 can extend laterally in the horizontal direction.

[0077] refer to Figure 9 An etchant can be introduced into the back trench 79, for example, using an etching process, which selectively etches the second material of the sacrificial material layer 42 relative to the first material of the insulating layer 32. A back recess 43 is formed in the volume from which the sacrificial material layer 42 is removed. The second material of the sacrificial material layer 42 can be selectively removed from the first material of the insulating layer 32, the materials of the stepped dielectric portion 65 and the non-stepped dielectric portion 165, the semiconductor material of the semiconductor material layer 912, and the material of the outermost layer of the memory film 50. In one embodiment, the sacrificial material layer 42 may comprise silicon nitride, and the materials of the insulating layer 32, the stepped dielectric portion 65, and the non-stepped dielectric portion 165 may be selected from silicon oxide and dielectric metal oxides.

[0078] The etching process that selectively removes the second material from the outermost layer of the first material and memory film 50 can be a wet etching process using a wet etching solution, or a vapor-phase (dry) etching process that introduces the etchant in a vapor phase into the back-side trench 79. For example, if the sacrificial material layer 42 comprises silicon nitride, the etching process can be a wet etching process that immerses the first exemplary structure in a wet etching bath comprising phosphoric acid, which selectively etches the silicon nitride in a manner selective to silicon oxide, silicon, and various other materials employed in the art. When the back-side recess 43 is present within the volume previously occupied by the sacrificial material layer 42, the stepped dielectric portion 65 and the memory opening filling structure 58 provide structural support.

[0079] Each back-side recess 43 may be a laterally extending cavity, the lateral dimension of which is greater than the vertical extent of the cavity. In other words, the lateral dimension of each back-side recess 43 may be greater than the height of the back-side recess 43. Multiple back-side recesses 43 may be formed in a volume of a second material from which the sacrificial material layer 42 is removed. The memory openings forming the memory stack structure 55 are referred to herein as front openings or front cavities, in contrast to the back-side recesses 43. In one embodiment, the memory array region 100 includes a single three-dimensional NAND string array having multiple device levels disposed above the substrate 910. In this case, each back-side recess 43 may define space for receiving a corresponding word line of the single three-dimensional NAND string array.

[0080] Each of the plurality of back-side recesses 43 may extend substantially parallel to the top surface of the substrate 910. The back-side recesses 43 may be defined perpendicularly by the top surface of the underlying insulating layer 32 and the bottom surface covering the insulating layer 32. In one embodiment, each back-side recess 43 may always have a uniform height. The optional substrate channel portion 11 and physically exposed surface portions of the semiconductor material layer 912 may be converted into dielectric material portions by thermal and / or plasma conversion from semiconductor material to dielectric material. For example, thermal and / or plasma conversion may be used to convert the surface portions of each substrate channel portion 11 into tubular dielectric spacers and each physically exposed surface portion of the semiconductor material layer 912 into planar dielectric portions.

[0081] refer to Figure 10 Optionally, a back-side barrier dielectric layer (not shown) may be formed. At least one metallic material may be deposited in the back-side recess 43 using at least one conformal deposition process. For example, a combination of a metal barrier layer and a metal filler material may be deposited in the back-side recess 43. The metal barrier layer comprises a conductive metallic material, which may serve as a diffusion barrier layer and / or adhesion promoter layer for the metal filler material. The metal barrier layer may comprise conductive metal nitride materials such as TiN, TaN, WN, or stacks thereof, or may comprise conductive metal carbide materials such as TiC, TaC, WC, or stacks thereof. The metal filler material is deposited in the remaining volume of the back-side recess 43, on the sidewalls of at least one back-side trench 79, and above the top surface of the topmost insulating layer 32. The metal filler material may be deposited using a conformal deposition method, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. In one embodiment, the metal filler material layer may consist substantially of at least one elemental metal. At least one elemental metal in the metal filler layer can be selected from, for example, tungsten, cobalt, ruthenium, titanium, and tantalum.

[0082] The portion of the at least one conductive material deposited in the peripheral region of the back trench 79 or above the topmost insulating layer 32 can be removed by an isotropic etch-back process. Each remaining portion of the deposited metallic material in the back recess 43 constitutes a conductive layer 46. Each conductive layer 46 can be a conductive line structure. Therefore, the sacrificial material layer 42 is replaced by the conductive layer 46, and an alternating stack of insulating layer 32 and conductive layer 46 is formed.

[0083] Each conductive layer 46 can serve as a combination of multiple control gate electrodes located at the same level and word lines electrically interconnected (i.e., electrically short-circuited) with the multiple control gate electrodes located at the same level. The multiple control gate electrodes within each conductive layer 46 are control gate electrodes for vertical memory devices including the memory stack structure 55. In other words, each conductive layer 46 can serve as a word line serving as a common control gate electrode for multiple vertical memory devices.

[0084] refer to Figure 11 The via cavity 71 can be formed by selectively removing the sacrificial via opening fill structure 28 (if present) for the alternating stacks (32, 46) of insulating layer 32 and conductive layer 46. An isotropic etching process can be performed to selectively etch the sacrificial fill material of the sacrificial via opening fill structure 28 for the alternating stacks (32, 46) of insulating layer 32 and conductive layer 46.

[0085] refer to Figure 12 A conformal insulating layer, including an insulating material, can be deposited in the back trench 79 and the connecting via cavity 71, and can be anisotropically etched to form insulating spacers (74, 81). The insulating spacers (74, 81) include back trench insulating spacers 74 and through-stacking insulating spacers 81, the back trench insulating spacers being formed at the peripheral portions of the back trench 79 and the through-stacking insulating spacers being formed at the peripheral portions of the corresponding connecting via cavities in the connecting via cavity 71. The insulating spacers (74, 81) include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or dielectric metal oxide. The back trench insulating spacers 74 and the through-stacking insulating spacers 81 can have the same lateral thickness, which can range from 10 nm to 100 nm, such as 20 nm to 50 nm, but smaller and larger lateral thicknesses are also possible. By implanting a dopant of a second conductivity type, a source region (not shown) can be formed at the bottom of each back-side trench 79. This second conductivity type is the opposite of the first conductivity type. For example, if the first conductivity type is p-type, then the second conductivity type is n-type, and vice versa.

[0086] refer to Figure 13At least one conductive material can be deposited in the remaining volume of the backside trench 79 and the connecting via cavity 71. The at least one conductive material can include, for example, a combination of a metal barrier layer and a metal filler material. The metal barrier layer comprises a conductive metal material, which can serve as a diffusion barrier layer and / or adhesion promoter layer for the metal filler material. The metal barrier layer can include conductive metal nitride materials such as TiN, TaN, WN, or stacks thereof, or can include conductive metal carbide materials such as TiC, TaC, WC, or stacks thereof. The metal filler material can be deposited using a conformal deposition method, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. In one embodiment, the metal filler material layer can consist substantially of at least one elemental metal. The at least one elemental metal of the metal filler material layer can be selected from, for example, tungsten, cobalt, ruthenium, titanium, and tantalum. Excess portions of the at least one conductive material can be removed from above a horizontal plane comprising the alternating stacks (32, 46) by a planarization process such as chemical mechanical planarization. Each remaining portion of the at least one conductive material filling the back-side trench 79 constitutes a back-side contact via structure 76, which can contact the top surface of a corresponding source region embedded in the semiconductor material layer 912. Each remaining portion of the at least one conductive material filling the corresponding connecting via cavity 71 constitutes a laterally isolated through-stack via structure 82. Each laterally isolated through-stack via structure 82 can contact the top surface of the laterally isolated through-substrate via structure 934' during the process. Each laterally isolated through-stack via structure 82 is laterally surrounded by a corresponding through-stack insulating spacer 81. In one embodiment, each through-stack insulating spacer 81 may have a tubular configuration and can contact the top surface of the laterally isolated through-substrate via structure 934' and / or the top surface of the substrate insulating spacer 932 during the process.

[0087] In an alternative implementation scheme, it is possible to Figure 7 and Figure 8 Between the steps shown, a connection via opening 29 (i.e., a connection via cavity 71) is formed. In other words, the connection via opening 29 (i.e., the connection via cavity 71) can be formed after the memory opening filling structure 58 is formed and before the back trench 79 is formed. Then, before the back trench 79 is formed and before the back trench insulating spacer 74 and the back contact via structure 76 are formed in the back trench 79, each laterally isolated through-stack via structure 82 and the corresponding through-stack insulating spacer 81 are individually formed in each corresponding connection via opening 29 (i.e., the connection via cavity 71).

[0088] refer to Figure 14A contact-level dielectric layer 70 may be deposited over alternating stacks (32, 46), stepped dielectric material portions 65, and non-stepped dielectric material portions 165. The contact-level dielectric layer 70 comprises a dielectric material, such as silicon oxide. The thickness of the contact-level dielectric layer 70 may range from 100 nm to 600 nm, but smaller and larger thicknesses are also possible. A photoresist layer (not shown) may be applied over the contact-level dielectric layer 70 and may be photolithographically patterned to form openings therein. The pattern of the openings in the photoresist layer may be transferred through the contact-level dielectric layer 70 using an anisotropic etching process to form various contact via cavities (83, 85, 187, 181). Contact via cavities (83, 85, 187, 181) may include through-dielectric via cavities 83 that extend vertically through one of the contact-level dielectric layer 70 and the stepped dielectric portion 65 and the non-stepped dielectric portion 165, and extend to the top surface of the corresponding process-isolated through-substrate via structure 934'. Contact via cavities (83, 85, 187, 181) may include layer contact via cavities 85 that extend vertically through the contact-level dielectric layer 70 and the stepped dielectric portion 65, and extend downward to the top surface of the corresponding conductive layer in the conductive layer 46. Furthermore, the contact via cavities (83, 85, 187, 181) may include drain contact via cavities 187 that extend vertically through the contact-level dielectric layer 70 and downward to the top surface of the memory opening-fill structure 58. The top surface of the drain region 63 may be physically exposed at the bottom of each drain contact via cavity 187. Additionally, the contact via cavities (83, 85, 187, 181) may include contact-level connection cavities 181 that extend vertically through the contact-level dielectric layer 70 and downward to the top surface of a corresponding laterally isolated through-throw via structure 82.

[0089] refer to Figure 15 At least one conductive material can be deposited in the contact via cavities (83, 85, 187, 181). The at least one conductive material may include, for example, a combination of a metal barrier layer and a metal filler material. Excess portions of the at least one conductive material can be removed from above a horizontal plane including the top surface of the contact-level dielectric layer 70. The remaining portion of the at least one conductive material filling the contact via cavities (83, 85, 187, 181) constitutes the contact via structure (84, 86, 88, 184).

[0090] The contact via structures (84, 86, 88, 184) include: a through-dielectric via structure 84 filling a corresponding through-dielectric via cavity in a through-dielectric via cavity 83; a layer contact via structure 86 filling a corresponding layer contact via cavity in a layer contact via cavity 85; a drain contact via structure 88 filling a corresponding drain contact via cavity in a drain contact via cavity 187; and a connection via structure 184 filling a corresponding contact-level connection cavity in a contact-level connection cavity 181. Each through-dielectric via structure 84 may contact the top surface of a corresponding process-interlocked through-substrate via structure 934' (if present), and the straight sidewall of one of the stepped dielectric portion 65 and the non-stepped dielectric portion 165. Each layer contact via structure 86 contacts the horizontal surface of a corresponding conductive layer in the conductive layer 46 and the straight sidewall of the stepped dielectric portion 65. Each drain contact via structure 88 contacts the corresponding drain region in drain region 63. Each connection via structure 184 contacts the horizontal surface of the corresponding laterally isolated through-stack via structure 82.

[0091] refer to Figure 16 A dielectric material layer 90 may be formed above the contact-level dielectric layer 70. A metal interconnect structure 92 is formed in the dielectric material layer 90. Metal bonding pads formed in the dielectric material layer 90 are referred to herein as interconnect-side bonding pads 98.

[0092] In one embodiment, each laterally isolated through-throw via structure 82 is electrically connected to a corresponding layer contact via structure 86 via a corresponding conductive path (184, 92), the conductive path including at least one metal wire embedded in a dielectric material layer 90 located on alternating stacks (32, 46). Each conductive path (184, 92) includes at least one metal wire and a connecting via structure 184, the at least one metal wire being a component of the metal interconnect structure 92. In one embodiment, at least one conductive path (184, 92) may include two or more metal wires and two or more metal via structures within the metal interconnect structure 92. In one embodiment, a laterally isolated through-hole structure 82 can be electrically connected to a layer contact via structure 86 via a conductive path, the conductive path consisting of a metal wire contacting the top surface of the first layer contact via structure 82, and a connecting via structure 184 contacting the bottom surface of the metal wire and the top surface of the laterally isolated through-hole structure 86.

[0093] The first exemplary structure includes a three-dimensional memory die. In order to... Figure 16 The three-dimensional memory die in the first exemplary structure is distinguished from the additional three-dimensional memory dies that will be used subsequently. Figure 16 The three-dimensional memory die in the first exemplary structure is referred to herein as a first three-dimensional memory die 901. Each component of the first three-dimensional memory die is referred to herein as a corresponding first component. For example, the alternating stacking of insulating layer 32 and conductive layer 46 in the first three-dimensional memory die 901 is referred herein as a first alternating stacking of first insulating layer 32 and first conductive layer 46. The through-hole dielectric via structure 84 in the first three-dimensional memory die 901 is referred herein as a first through-hole dielectric via structure 84. The layer contact via structure 86 in the first three-dimensional memory die 901 is referred herein as a first layer contact via structure 86. The drain contact via structure 88 in the first three-dimensional memory die 901 is referred herein as a first drain contact via structure 88. The connection via structure 184 in the first three-dimensional memory die 901 is referred herein as a first contact via structure 184. The stepped dielectric material portion 65 in the first three-dimensional memory die 901 is referred herein as a first stepped dielectric material portion 65. The non-stepped dielectric material portion 165 in the first three-dimensional memory die 901 is referred to herein as the first non-stepped dielectric material portion 165. The dielectric material layer 90 in the first three-dimensional memory die 901 is referred herein as the first dielectric material layer 90. The metal interconnect structure 92 in the first dielectric material layer 90 is referred herein as the first metal interconnect structure 92. The interconnect side bonding pad 98 located in the first dielectric material layer 90 is referred herein as the first interconnect side bonding pad 98, and so on.

[0094] refer to Figure 17 The handle substrate 600 can be attached to one side of the 3D memory die 901, including the first interconnect side bonding pad 98. The handle substrate 600 comprises a material, such as metal, plastic, semiconductor, ceramic, or glass, capable of providing sufficient mechanical support to the 3D memory die including the substrate 910. The thickness of the handle substrate 600 can range from 200 micrometers to 2 mm, but smaller and larger thicknesses are also possible. Optionally, an adhesive layer (such as a thermally degradable adhesive material layer or an ultraviolet-deactivated adhesive material layer) can be used to attach the handle substrate 600 to the first 3D memory die 901.

[0095] refer to Figure 18The back side of the first substrate 910 (which may include the back side of the first semiconductor material layer 912) can be thinned, for example, by grinding, polishing, isotropic etching processes (such as wet etching processes), and / or anisotropic etching processes (such as reactive ion etching processes). The first substrate 910 can continue to be thinned until the surface of the laterally isolated through-substrate via structures 934' (if present) is physically exposed during the process. After the first substrate 910 is thinned, the laterally isolated through-substrate via structures 934' extend vertically through the entire thickness of the first substrate 910 during the process, and are referred to herein as laterally isolated through-substrate via structures 934. Each laterally isolated through-substrate via structure 934 may be laterally surrounded by a corresponding substrate insulating spacer 932. Each successive combination of substrate insulating spacers 932 and laterally isolated through-substrate via structures 934 constitutes a through-substrate connection structure 930.

[0096] In an alternative implementation scheme, it is possible to Figure 18 Following the thinning step of the first substrate 910, a through-substrate connection structure 930 is formed. Specifically, a deep trench can be formed through the remaining portion of the thinned first substrate 910 until the corresponding via structures (82, 84) are exposed in the deep trench. The deep trench is then filled with a combination of substrate insulating spacers 932 and laterally isolated through-substrate via structures 934 that contact the corresponding via structures (82, 84).

[0097] A first back-side insulating layer 990 may be deposited on the back-side surface of a first substrate 910, such as by a thinning process. The first back-side insulating layer 990 comprises an insulating material such as silicon oxide and may have a thickness in the range of 500 nm to 5 micrometers. First substrate-side bonding pads 99 may be formed in the first back-side insulating layer 990 such that each first substrate-side bonding pad 99 contacts the horizontal surface of a corresponding laterally isolated through-substrate via structure 934. Therefore, each first substrate-side bonding pad 99 is located on the back side of the first substrate 910 and is electrically connected to a corresponding first laterally isolated through-substrate via structure 934.

[0098] A first three-dimensional memory die 901 is provided, comprising a first insulating layer 32 and a first conductive layer 46 on the front side of a first substrate 910 in a first alternating stack. The first three-dimensional memory die 901 includes: a first memory structure (e.g., a first memory stack structure 55, part of a first memory opening-fill structure 58), the first memory structure being located within the first alternating stack (32, 46); a first stepped dielectric portion 65 contacting a stepped surface of the first alternating stack (32, 46); a first layer contact via structure 86 extending vertically through the first stepped dielectric portion 65 and contacting a corresponding first conductive layer in the first conductive layer 46; and a first laterally isolated through-stack via structure 82 extending vertically through a region of the first alternating stack (32, 46), in which the first alternating stack (32, 46)... 46) Each layer exists and is electrically connected to a corresponding first-layer contact via structure in the first-layer contact via structure 86; a first laterally isolated through-substrate via structure 934 electrically connected to a corresponding first laterally isolated through-stacked via structure in the first laterally isolated through-stacked via structure 82; and a first substrate-side bonding pad 99 embedded in a first back-side insulating layer 990 located on the back side of the first substrate 910 and electrically connected to a corresponding first laterally isolated through-substrate via structure 934. In one embodiment, the first substrate 910 includes a semiconductor material layer 912 electrically contacting the bottom end of each vertical semiconductor channel 60 in the first memory opening-fill structure 58, and each first laterally isolated through-substrate via structure 934 may be laterally surrounded by a corresponding substrate insulating spacer 932 contacting the sidewall of the semiconductor material layer 912.

[0099] refer to Figure 19The image illustrates a logic die 700 according to an embodiment of the present disclosure. In this embodiment, the logic die 700 is formed on a substrate different from that of the memory die 901. In an alternative embodiment described below, the logic die 700 may be formed on the same substrate as the first memory die 901. The logic die 700 includes driver circuitry devices, such as complementary metal-oxide-semiconductor (CMOS) transistors 720 located on a logic substrate including a logic die semiconductor material layer 712. The logic substrate may include a silicon wafer or a silicon-on-insulator wafer, and the logic die semiconductor material layer 712 may include doped wells in a top portion of the logic substrate and / or epitaxial semiconductor layers located on the logic substrate. In one embodiment, an optional logic die through-substrate interconnect structure 730 may be formed in an upper portion of the logic substrate. Each logic die through-substrate interconnect structure 730 may include a logic die laterally isolated through-substrate via structure 734 and a logic die substrate insulating spacer 732 surrounding the logic die laterally isolated through-substrate via structure 734. A logic die dielectric layer 760 may be formed above the CMOS transistor 720, and a logic die metal interconnect structure 780 may be embedded in the logic die dielectric layer 760. A logic die bonding pad 788 may be embedded in the topmost layer of the logic die dielectric layer 780. The logic die bonding pad 788 is electrically connected to a corresponding node (e.g., source, drain, or gate) of the CMOS transistor 720. The pattern of the logic die bonding pad 788 may be a mirror pattern of the pattern of the first substrate-side bonding pad 99 of the first three-dimensional memory die 901 or a pattern of the first interconnect-side bonding pad 98 of the first three-dimensional memory die 901.

[0100] refer to Figure 20 The logic die 700 can be bonded to the first 3D memory die 901. In one embodiment, the pattern of the logic die bonding pad 788 can be a mirror image of the pattern of the first substrate-side bonding pad 99 of the first 3D memory die 901, and the logic die 700 can be attached to the substrate side of the first 3D memory die 901 by bonding the logic die bonding pad 788 to the first substrate-side bonding pad 99 of the first 3D memory die 901. Metal-to-metal bonding (such as copper-to-copper bonding) or hybrid bonding (such as metal-to-metal and dielectric-to-dielectric bonding) can be used to bond the logic die bonding pad 788 to the first substrate-side bonding pad 99 of the first 3D memory die 901. The first 3D memory die 901 can be directly attached to the logic die 700.

[0101] refer to Figure 21 The handle substrate 600 can be separated from the bonding assembly of the logic die 700 and the first three-dimensional memory die 901.

[0102] refer to Figure 22 A second three-dimensional memory die 902 is provided, which can be formed using the same set of processing steps as the first three-dimensional memory die 901 (wherein the photolithographic pattern is appropriately modified during the manufacturing steps). Components of the second three-dimensional memory die 902 are referred to herein as second components. In one embodiment, the pattern of the second interconnect side bonding pad 98 in the second three-dimensional memory die 902 may be a mirror pattern of the first interconnect side bonding pad 98 in the first three-dimensional memory die 901. In one embodiment, the formation of the connection via opening 29, the connection via opening filling structure 28, the through-stack insulating spacer 81, the laterally isolated through-stack via structure 82, and the connection via structure 184 may be omitted during the manufacturing of the second three-dimensional memory die 902. In this case, each second conductive layer 46 can be electrically connected to the corresponding second interconnect side bonding pad in the second interconnect side bonding pad 98 via a corresponding second layer contact via structure 86 and a corresponding subset of the second metal interconnect structure 92 embedded in the second dielectric material layer 90 of the second three-dimensional memory die 902.

[0103] In one embodiment, the first conductive layer 46 in the first three-dimensional memory die 901 may have different lateral extents along a first horizontal direction hd1 (e.g., word line direction), these lateral extents decreasing with a corresponding vertical distance from the logic die 700, and the second conductive layer 46 in the second three-dimensional memory die 902 may have different lateral extents along the first horizontal direction hd1, these lateral extents increasing with a corresponding vertical distance from the logic die 700. Furthermore, the second plateau region 300 of the second three-dimensional memory die 902 may be laterally offset from the first plateau region 300 of the first three-dimensional memory die 901 along the first horizontal direction hd1. For example, all the second conductive layers 46 in the second plateau region 300 of the second three-dimensional memory die 902 may extend along the first horizontal direction hd1 past the bottom (e.g., longest) first conductive layer 46 in the first plateau region 300 of the first three-dimensional memory device 901.

[0104] refer to Figure 23 It can be implemented through any appropriate changes. Figure 18The processing steps involve thinning the back side of the second substrate 910 and forming a second back-side insulating layer 990 embedded with second substrate-side bonding pads 99, which contact corresponding second through-substrate interconnect structures 930. Each second through-substrate interconnect structure 930 includes a corresponding successive combination of second substrate insulating spacers 932 and second laterally isolated through-substrate via structures 934. Each second laterally isolated through-substrate via structure 934 may contact a corresponding through-dielectric via structure 84. The horizontal surface within the stepped surface of the first platform region 300 of the first three-dimensional memory die 901 may face away from the logic die 700, and the horizontal surface within the stepped surface of the second platform region 300 of the second three-dimensional memory die 902 may face the logic die 700.

[0105] refer to Figure 24 An optional third 3D memory die 903 may be provided, which may be formed using the same set of processing steps as the first 3D memory die 901 (wherein appropriate modifications are made to the photolithographic pattern during the manufacturing steps). Components of the third 3D memory die 903 are referred to herein as third components. In one embodiment, the pattern of the third substrate-side bonding pad 99 in the third 3D memory die 903 may be a mirror image of the pattern of the second substrate-side bonding pad 99 in the second 3D memory die 902. In one embodiment, the third 3D memory die 903 may include a third through-stack insulating spacer 81, a third laterally isolated through-stack via structure 82, and a third connection via structure 184. In this case, each third conductive layer 46 may be electrically connected to the corresponding third connection via structure 184 via a corresponding third layer contact via structure 86, a corresponding subset of the third metal interconnect structure 92 embedded in the third dielectric material layer 90, and the corresponding third connection via structure 184. Furthermore, each third connection via structure 184 can be electrically connected to a corresponding third substrate side bonding pad in the third substrate side bonding pad 99 via a corresponding laterally isolated through substrate via structure 934.

[0106] Typically, the third 3D memory die 903 includes a third insulating layer 32 and a third conductive layer 46 arranged in a third alternating stack on the front side of a third substrate 910. The third conductive layer 46 in the third 3D memory die 903 has a different lateral extent along a first horizontal direction hd1, which increases or decreases with a corresponding vertical distance from the logic die 700. In one embodiment, the lateral extent of the third conductive layer 46 in the third 3D memory die 903 decreases with a corresponding vertical distance from the logic die 700. The third 3D memory die 903 includes a third memory structure (e.g., memory stack structure 55) located in the third alternating stack (32, 46).

[0107] Furthermore, the second plateau region 300 of the third 3D memory die 903 may be laterally offset from the first and second plateau regions 300 of the first and second 3D memory dies (901, 902) along the first horizontal direction hd1. For example, all the second conductive layers 46 in the third plateau region 300 of the third 3D memory die 903 may extend along the first horizontal direction hd1 past the top (e.g., longest) second conductive layer 46 in the second plateau region 300 of the second 3D memory device 902.

[0108] The third 3D memory die 903 includes third-layer contact via structures 86 that contact a corresponding third conductive layer in the third conductive layer 46 and are electrically connected to a corresponding third bonding pad (such as a corresponding third substrate-side bonding pad 99) that is bonded to a corresponding second bonding pad (such as a corresponding second substrate-side bonding pad 99) within the second 3D memory die 902.

[0109] refer to Figure 25 An optional fourth 3D memory die 904 is provided, which can be formed using the same set of processing steps as the second 3D memory die 902 (wherein appropriate modifications are made to the photolithographic pattern during the manufacturing steps). Components of the fourth 3D memory die 904 are referred to herein as fourth components. In one embodiment, the pattern of the fourth interconnect side bonding pad 98 in the fourth 3D memory die 904 may be a mirror image of the pattern of the third interconnect side bonding pad 98 in the third 3D memory die 903. In one embodiment, the formation of the connection via opening 29, the connection via opening filling structure 28, the through-stack insulating spacer 81, the laterally isolated through-stack via structure 82, and the connection via structure 184 may be omitted during the manufacture of the fourth 3D memory die 904. In this case, each fourth conductive layer 46 can be electrically connected to the corresponding fourth interconnect side bonding pad in the fourth interconnect side bonding pad 98 via the corresponding fourth layer contact via structure 86 and the corresponding subset of the fourth metal interconnect structure 92 embedded in the fourth dielectric material layer 90 of the fourth 3D memory die 904.

[0110] The fourth conductive layer 46 in the fourth 3D memory die 904 has a different lateral extent along the first horizontal direction hd1, and these lateral extents increase or decrease with a corresponding vertical distance from the logic die 700. In one embodiment, the third conductive layer 46 in the third 3D memory die 903 decreases with a corresponding vertical distance from the logic die 700, and the fourth conductive layer 46 in the fourth 3D memory die 904 increases with a corresponding vertical distance from the logic die 700. The horizontal surface within the stepped surface of the third 3D memory die 903 may face away from the logic die 700, and the horizontal surface within the stepped surface of the fourth 3D memory die 904 may face the logic die 700.

[0111] refer to Figure 26 The back side of the logic die substrate, such as the back side of the logic die semiconductor material layer 712, can be thinned by grinding, polishing, isotropic etching, or anisotropic etching processes. The back side of the logic die semiconductor material layer 712 can be thinned until the surface of the laterally isolated through-substrate via structure 734 is physically exposed. The logic die through-substrate connection structure 730 can extend vertically through the logic die substrate, which may include the logic die semiconductor material layer 712, as thinned by a thinning process. Each logic die through-substrate connection structure 730 may include the laterally isolated through-substrate via structure 734 and the logic die substrate insulating spacer 732. Alternatively, the logic die through-substrate connection structure 730 may be formed after the logic die semiconductor material layer 712 has been thinned.

[0112] A logic die back-side insulating layer 790 can be formed on the back side of the logic die substrate, and logic die back-side bonding pads 798 can be formed within the logic die back-side insulating layer 790. Each logic die back-side bonding pad 798 can be formed directly on a corresponding logic die laterally isolated through-substrate via structure 734. The logic die back-side bonding pads 798 can then be used to mount bonding assemblies including logic die 700 and 3D memory dies (901, 902, 903, 904) to a printed circuit board, another semiconductor die, an interposer, or a package substrate. For example, the logic die back-side bonding pads 798 can be used to provide wire bonding or C4 bonding.

[0113] refer to Figure 27A first alternative embodiment of the first exemplary structure according to the present disclosure can be obtained from the first exemplary structure by attaching a fourth three-dimensional memory die 904 without any lateral isolation through-thrust via structure 82 to a second three-dimensional memory die 902, and subsequently attaching a third three-dimensional memory die 903 to the fourth three-dimensional memory die 904. The third three-dimensional memory die 903 includes a third through-thrust insulating spacer 81, a third laterally isolated through-thrust via structure 82, and a third connection via structure 184.

[0114] The fourth conductive layer 46 in the fourth three-dimensional memory die 904 has a different lateral extent along the first horizontal direction hd1, and these lateral extents increase or decrease with a corresponding vertical distance from the logic die 700. In one embodiment, the fourth conductive layer 46 in the fourth three-dimensional memory die 904 increases with a corresponding vertical distance from the logic die 700, and the third conductive layer 46 in the third three-dimensional memory die 903 decreases with a corresponding vertical distance from the logic die 700.

[0115] It should be understood that the ordinal numbers "third" and "fourth" in the third three-dimensional memory die 903 and the fourth three-dimensional memory die 904 can be interchanged by counting the three-dimensional memory dies from bottom to top. For example, if the third three-dimensional memory die, as counted from one side of the logic die 700, is considered the "third" three-dimensional memory die, then such a "third" three-dimensional memory die corresponds to... Figure 27 The fourth 3D memory die 904 is shown. (Comparison) Figure 26 and Figure 27 In the configuration shown, the "third" three-dimensional memory die directly attached to the second three-dimensional memory die 902 can be a third three-dimensional memory die 903 (where the lateral extent of the conductive layer 46 decreases with the corresponding vertical distance from the logic die 700, such as...). Figure 26 (as shown), or it could be a fourth three-dimensional memory die 904 (where the lateral extent of the conductive layer 46 increases with the corresponding vertical distance from the logic die 700, such as...). Figure 27 (As shown).

[0116] The horizontal surface within the stepped surface of the first three-dimensional memory die 901 can face away from the logic die 700, and the horizontal surface within the stepped surface of the second three-dimensional memory die 902 can face the logic die 700. The horizontal surface within the stepped surface of the third three-dimensional memory die 903 can face away from the logic die 700, and the horizontal surface within the stepped surface of the fourth three-dimensional memory die 904 can face the logic die 700.

[0117] refer to Figure 28A second exemplary structure according to the second embodiment of the present disclosure can be obtained from the first exemplary structure by directly bonding a second three-dimensional memory die 902, excluding the through-stacking insulating spacer 81, the laterally isolated through-stacking via structure 82, or the connecting via structure 184, to the logic die 700. Subsequently, the first three-dimensional memory die 901, including the first through-stacking insulating spacer 81, the first laterally isolated through-stacking via structure 82, and the first connecting via structure 184, can be bonded to the second three-dimensional memory die 902. The aforementioned handle substrate can be used to support the top of the first three-dimensional memory die 901 during the thinning of the first substrate 910 of the die 901 and during the bonding of the substrate 910 side of the die 901 to the substrate 910 side of the die 902. In this case, the first three-dimensional memory die 901 is indirectly attached to the logic die 700 via an intermediary die, which is the second three-dimensional memory die 902. The first substrate-side bonding pad 99 can be electrically connected to the logic die bonding pad 788 via a conductive path located within the intermediary die (i.e., the second three-dimensional memory die 902).

[0118] In one embodiment, the second three-dimensional memory die 902 may include a second alternating stack of a second insulating layer 32 and a second conductive layer 46 on the front side of a second substrate 910, a second memory structure (e.g., a second memory stack structure 55) on the second alternating stack (32, 46), and second substrate-side bonding pads 99 embedded in a second back-side insulating layer 990 on the back side of the second substrate 910 and bonded to corresponding first substrate-side bonding pads in the first substrate-side bonding pads 99.

[0119] In one embodiment, the first conductive layer 46 may have different lateral extents along the first horizontal direction hd1, these lateral extents decreasing with a corresponding vertical distance from the logic die 700, and the second conductive layer 46 may have different lateral extents along the first horizontal direction hd1, these lateral extents increasing with a vertical distance from the logic die 700. The horizontal surfaces within the stepped surface of the first three-dimensional memory die 901 may face away from the logic die 700, and the horizontal surfaces within the stepped surface of the second three-dimensional memory die 902 may face the logic die 700.

[0120] In one embodiment, a fourth 3D memory die 904 may be bonded to a first 3D memory die 901, and subsequently, a 3D memory die 903 may be bonded to the fourth 3D memory die 904. In one embodiment, a third conductive layer 46 in the third 3D memory die 903 may have different lateral extents along a first horizontal direction hd1, these lateral extents decreasing with a corresponding vertical distance from the logic die 700, and a fourth conductive layer 46 may have different lateral extents along the first horizontal direction hd1, these lateral extents increasing with a vertical distance from the logic die 700. The horizontal surfaces within the stepped surface of the third 3D memory die 903 may face away from the logic die 700, and the horizontal surfaces within the stepped surface of the fourth 3D memory die 904 may face the logic die 700.

[0121] In the second embodiment, the first three-dimensional memory die 901 may be curved or twisted with its edges pointing downwards before bonding, while the second three-dimensional memory die 902 may also be curved or twisted with its edges pointing downwards until bonding. Figure 28 As shown, after the second three-dimensional memory die 902 is bonded to the first three-dimensional memory die 901, the curvature or twist of the bonded dies cancels each other out, resulting in a flatter bonded assembly.

[0122] refer to Figure 29 You can get from the following methods Figure 29 The second exemplary structure is obtained by an alternative embodiment of the second exemplary structure according to the second embodiment of the present disclosure: attaching a third three-dimensional memory die 903 to a first three-dimensional memory die 901, and then attaching a fourth three-dimensional memory die 904 to the third three-dimensional memory die 903.

[0123] refer to Figure 30A third exemplary structure according to a third embodiment of the present disclosure can be derived from a first exemplary structure by depositing a layer of a first three-dimensional memory die 901 over a layer of a logic die 700 configured under a CMOS array. In this embodiment, driver circuitry devices (such as CMOS transistors 720) are formed on or on a logic substrate including a logic die semiconductor material layer 712. A logic die dielectric material layer 760 is then formed over the driver circuitry devices (such as CMOS transistors 720). A horizontal semiconductor channel layer 922 (such as a polysilicon layer) is then deposited over the logic die dielectric material layer 760. Alternating stacks (32, 46) and memory structures (e.g., a memory stack structure 55 of a memory aperture-filled structure 58) are then deposited over the logic die dielectric material layer 760. Thus, the first substrate 910 and bonding pads located between the logic die 700 and the first three-dimensional memory die 901 are omitted, and in this third embodiment, dies 700 and 901 comprise monolithic structures and are not bonded to each other.

[0124] In the third embodiment, the single-unit combinational logic die 700 and the first three-dimensional memory die 901 may be curved or twisted with their edges pointing upwards before bonding, while the second three-dimensional memory die 902 may be curved or twisted with its edges pointing downwards before bonding. Figure 30 As shown, after the second three-dimensional memory die 902 is bonded to the first three-dimensional memory die 901, the curvature or twist of the bonded dies cancels each other out, resulting in a flatter bonded assembly.

[0125] While various embodiments of this disclosure are illustrated using an embodiment attaching four three-dimensional memory dies (901, 902, 903, 904) to logic die 700, embodiments attaching one, two, three, five, six, seven, or more three-dimensional memory dies to logic die 700 are explicitly contemplated herein. Furthermore, a portion of the driver circuitry (such as a sense amplifier switching device) may be located in each of the memory dies (901, 902, 903, 904). The sense amplifier switching device in each of the memory dies (901, 902, 903, 904) may be electrically connected to the remaining driver circuitry, such as a CMOS transistor 720 in logic die 700, using laterally isolated through-thrust via structures 82 and / or corresponding through-dielectric via structures 84.

[0126] refer to Figure 31 It can be achieved by omitting the passage. Figure 1 The formation of the through-substrate interconnect structure 930 of the semiconductor material layer 912 shown is from... Figure 17The first exemplary structure shown yields a fourth exemplary structure according to a fourth embodiment of this disclosure. Furthermore, in Figure 31 In the fourth exemplary structure, the entire substrate 910, including the entire semiconductor material layer 912, is removed, rather than simply thinning the substrate 910, leaving, as Figure 17 A portion of the semiconductor material layer 912 is shown. After removing the semiconductor material layer 912, the exposed bottom portion of the memory film 50 is selectively etched to expose the bottom portion of the vertical semiconductor channel 60, as described in U.S. Patent No. 10,629,616 B1, which is incorporated herein by reference in its entirety.

[0127] like Figure 32 As shown, a doped semiconductor layer is formed on the exposed portion of the vertical semiconductor channel 60. The doped semiconductor layer may include a polycrystalline semiconductor layer such as polysilicon, having a dopant with a conductivity type opposite to that of the vertical semiconductor channel 60. The doped semiconductor layer is patterned by photolithography and etching to form a source layer 952 located in the memory array region 100 containing the vertical semiconductor channel 60. The source layer 952 serves as a common source region and / or source line for the vertical NAND strings containing the vertical semiconductor channel 60.

[0128] A first back-side insulating layer 990 is then formed above the source layer 952, and this first back-side insulating layer fills the exposed space above the connection region 200 and the plateau region 300 that is laterally adjacent to the source layer 952. Via openings are then formed by photolithography and etching through the first back-side insulating layer 990. Connection structures 930 (which are not "through-substrate" in this embodiment, as they extend through the insulating layer rather than through the substrate) and first substrate-side bonding pads 99 are then formed in the via openings in the first back-side insulating layer 990, as... Figure 32 As shown. In this fourth embodiment, the connection structure 930 may include only the corresponding laterally isolated through-hole structure 934 (which is not "through the substrate" in this embodiment), while the substrate insulating spacer 932 may be omitted. Alternatively, the insulating spacer 932 (which is not "substrate" insulating spacer in this embodiment) may be present in the connection structure 930.

[0129] Then you can Figure 32 The fourth exemplary structure is incorporated into any joining component of the first, second, or third embodiment. For example, as... Figure 33 As shown, Figure 32 The fourth exemplary structure is incorporated into the joining component, replacing Figure 28 The second exemplary structure of the second embodiment shown.

[0130] Referring to all the accompanying drawings and according to various embodiments of the present disclosure, the bonding assembly includes: a first three-dimensional memory die 901, the first three-dimensional memory die including a first alternating stack of a first insulating layer 32 and a first conductive layer 46, a first memory structure 55 located in the first alternating stack, and a first stepped dielectric material portion 65 contacting the stepped surface of the first alternating stack; a second three-dimensional memory die 902 bonded to the first three-dimensional memory die 901, wherein the second three-dimensional memory die includes a second alternating stack of a second insulating layer 32 and a second conductive layer 46, a second memory structure 55 located in the second alternating stack, and a second stepped dielectric material portion 65 contacting the stepped surface of the second alternating stack; and a driver circuit device 720. The first conductive layer 46 has a different lateral extent along a first horizontal direction hd1, which decreases with a corresponding vertical distance from the driver circuit device 720, and the second conductive layer 46 has a different lateral extent along the first horizontal direction hd1, which increases with a corresponding vertical distance from the driver circuit device 720.

[0131] In one embodiment, the stepped surface of the second alternating stack (32, 46) in the first platform region 300 of the second three-dimensional memory die 902 is laterally offset from the stepped surface of the first alternating stack (32, 46) in the first platform region 300 of the first three-dimensional memory die 901 along the first horizontal direction hd1.

[0132] In one embodiment, the first three-dimensional memory die 901 further includes a memory opening 49 extending vertically through each layer within the first alternating stack (32, 46), wherein a first memory structure 55 is located in the memory opening 49 and includes a corresponding vertical semiconductor channel 60 and a corresponding memory film 50. The die 901 also includes: a first-layer contact via structure 86 extending vertically through a first stepped dielectric portion 65 and contacting a corresponding first conductive layer in the first conductive layer 46; and a first laterally isolated through-stack via structure 82 extending vertically through a region of the first alternating stack (32, 46) in which each layer of the first alternating stack is present and electrically connected to a corresponding first-layer contact via structure in the first-layer contact via structure 86.

[0133] exist Figures 26 to 29 and Figure 33In the first, second, and fourth embodiments shown, the bonding assembly further includes a logic die 700 bonded to a first 3D memory die 901, wherein a driver circuit device 720 includes a complementary metal-oxide-semiconductor (CMOS) transistor located in the logic die. In one embodiment, the first 3D memory die 901 further includes: a first substrate 910, wherein a first alternating stack (32, 46) is located on the front side of the first substrate 910; a first laterally isolated via structure 934 electrically connected to a corresponding first laterally isolated through-stacked via structure 82 in the first laterally isolated through-stacked via structure; and a first substrate-side bonding pad 99 embedded in a first back-side insulating layer 990 located on the back side of the first substrate 910 and electrically connected to a corresponding first laterally isolated via structure 934 in the first laterally isolated via structure.

[0134] In one embodiment, the logic die 700 further includes a logic die bonding pad 788 embedded in the logic die dielectric layer 760 and electrically connected to a corresponding node of the CMOS transistor 720. A first substrate-side bonding pad 99 is bonded to the logic die bonding pad 788, or electrically connected to the logic die bonding pad via conductive paths (98, 934, 84, 92, 99) located in an intermediary die between the logic die and the first three-dimensional memory die.

[0135] exist Figure 30 In another embodiment shown, the driver circuit device 720 includes a complementary metal-oxide-semiconductor (CMOS) transistor located above a logic substrate 712, and a second alternating stack (32, 46) of a second insulating layer and a second conductive layer is integrally formed above the driver circuit device 720 without having any bonding pads located between the driver circuit device and the second alternating stack.

[0136] exist Figure 26 and Figure 30In the first and third embodiments shown, a first 3D memory die 901 is located between a driver circuit device 720 and a second 3D memory die 902. In both embodiments, the first 3D memory die 901 includes first dielectric layers 90 with embedded first metal interconnect structures 92 and first interconnect-side bonding pads 98, the first metal interconnect structures and first interconnect-side bonding pads being located further from the driver circuit device 720 than the distance of the first alternating stack (32, 46) from the driver circuit device 720. The second 3D memory die 902 includes second dielectric layers 90 with embedded second metal interconnect structures 92 and second interconnect-side bonding pads 98, the second interconnect structures and second interconnect-side bonding pads being located closer to the driver circuit device 720 than the distance of the second alternating stack (32, 46) from the driver circuit device 720. The first interconnect-side bonding pads 98 are bonded to the second interconnect-side bonding pads 98. The second three-dimensional memory die 902 may further include a second layer of contact via structure 86 that extends vertically through the second stepped dielectric portion 65 and contacts a corresponding second conductive layer in the second conductive layer 46. Each second layer of contact via structure 86 is electrically connected to a corresponding second interconnect side bonding pad in the second interconnect side bonding pad 98 via a corresponding sub-collector of the second metal interconnect structure 92.

[0137] like Figure 26 and Figure 30 As shown, a third 3D memory die 903 is bonded to a second 3D memory die 902. The third 3D memory die 903 includes: a third alternating stack of a third insulating layer 32 and a third conductive layer 46, wherein the third conductive layer 46 has a different lateral extent along a first horizontal direction hd1, and these lateral extents decrease with a corresponding vertical distance from the driver circuit device 720; a third memory structure 55 located in the third alternating stack; a third stepped dielectric material portion 65 contacting the stepped surface of the third alternating stack; and a third-layer contact via structure 86 contacting a corresponding third conductive layer in the third conductive layer 46.

[0138] exist Figure 28In the second embodiment shown, a second three-dimensional memory die 902 is located between the driver circuit device 720 and the first three-dimensional memory die 901. A third three-dimensional memory die 904 is bonded to the first three-dimensional die 901. The third three-dimensional memory die 904 includes: a third alternating stack of a third insulating layer 32 and a third conductive layer 46, wherein the third conductive layer 46 has different lateral extents along a first horizontal direction, and these lateral extents increase with a corresponding vertical distance from the driver circuit device 720; a third memory structure 55 located in the third alternating stack; a third stepped dielectric material portion 65 contacting the stepped surface of the third alternating stack; and a third-layer contact via structure 86 contacting a corresponding third conductive layer in the third conductive layer 46.

[0139] Various embodiments of this disclosure can provide a compact vertical interconnect structure within at least one three-dimensional memory die (901, 902, 903, 904). The compact vertical interconnect structure may include laterally isolated through-throw via structures 82, through-throw insulating spacers 81, and connection via structures 184 that can be formed in three-dimensional memory dies such as a first three-dimensional memory die 901 and a third three-dimensional memory die 903. Each laterally isolated through-throw via structure 82 may be formed within a connection region 200 comprising each layer within an alternating stack of insulating layers 32 and conductive layers 46. Each laterally isolated through-throw via structure 82 may be electrically connected to only one conductive layer in the conductive layers 46 via a corresponding layer contact via structure 86, and is electrically isolated from all other conductive layers 46 via a corresponding through-throw insulating spacer 81. By electrically connecting alternating stacked sections (32, 46) that do not overlap with any portion of the dielectric material portions (65, 165), it is ensured that the laterally isolated through-thrust via structure 82 does not overlap with any through-dielectric via structure 84 or any layer contact via structure 86 in any region. The laterally isolated through-thrust via structure 82 can be used to reliably electrically connect the conductive layer 46, used as word lines for corresponding three-dimensional memory element arrays, to the logic die. Furthermore, memory dies twisted in opposite directions can be joined together in such a way that the corresponding twists are offset to form a flatter bonding assembly.

[0140] Although specific embodiments have been mentioned for the foregoing, it should be understood that this disclosure is not limited thereto. Those skilled in the art will appreciate that various modifications can be made to the disclosed embodiments, and such modifications are intended to fall within the scope of this disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words “comprising” or “including” contemplate that the words “substantially constitute…” or “consist of…” replace all embodiments in which the words “comprising” or “including” are used. While embodiments using specific structures and / or configurations are shown in this disclosure, it should be understood that this disclosure can be practiced with any other functionally equivalent compatible structures and / or configurations, provided that such substitutions are not expressly prohibited or otherwise considered impossible by those skilled in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A joining assembly, comprising: The first three-dimensional memory die includes: a first alternating stack of a first insulating layer and a first conductive layer, a first memory structure located in the first alternating stack, and a first stepped dielectric material portion contacting the stepped surface of the first alternating stack. A second three-dimensional memory die, the second three-dimensional memory die being bonded to a first three-dimensional memory die, wherein the second three-dimensional memory die includes: a second alternating stack of a second insulating layer and a second conductive layer, a second memory structure located within the second alternating stack, and a second stepped dielectric material portion contacting the stepped surface of the second alternating stack; and Driver circuit devices; in: The first conductive layer has a different lateral extent along a first horizontal direction, and the lateral extent decreases with a corresponding vertical distance from the driver circuit device; and The second conductive layer has a different lateral extent along the first horizontal direction, and the lateral extent increases with a corresponding vertical distance from the driver circuit device; and The first three-dimensional memory die further includes: A memory opening that extends vertically through each layer within the first alternating stack, wherein the first memory structure is located in the memory opening and includes a corresponding vertical semiconductor channel and a corresponding memory film; A first-layer contact via structure extends vertically through the first stepped dielectric material portion and contacts a corresponding first conductive layer in the first conductive layer; and A first laterally isolated through-throw via structure, the first laterally isolated through-throw via structure extending vertically through the first alternating stack region, in which each layer of the first alternating stack is present and electrically connected to a corresponding first-layer contact via structure in the first-layer contact via structure; and Each laterally isolated through-thrust via structure is electrically connected to a corresponding layer contact via structure in the layer contact via structure via a corresponding conductive path. The conductive path includes at least one metal wire embedded in a dielectric material layer located on the first alternating stack. Each conductive path includes at least one metal wire and a connecting via structure. The at least one metal wire is a component of a metal interconnect structure.

2. The bonding assembly of claim 1, wherein the second alternating stacked stepped surfaces are laterally offset from the first alternating stacked stepped surfaces along the first horizontal direction.

3. The bonding assembly of claim 1 further includes a logic die bonded to the first three-dimensional memory die, wherein the driver circuitry includes a complementary metal-oxide-semiconductor (CMOS) transistor located in the logic die.

4. The bonding assembly of claim 3, wherein the first three-dimensional memory die further comprises: A first substrate, wherein the first alternating stack is located on the front side of the first substrate; A first laterally isolated through-hole structure, the first laterally isolated through-hole structure being electrically connected to a corresponding first laterally isolated through-stacked through-hole structure in the first laterally isolated through-stacked through-hole structure. and A first substrate-side bonding pad is embedded in a first back-side insulating layer located on the back side of the first substrate and electrically connected to a corresponding first laterally isolated via structure in the first laterally isolated via structure.

5. The joining assembly according to claim 4, wherein: The logic die also includes logic die bonding pads, which are embedded in the logic die dielectric layer and electrically connected to the corresponding nodes of the CMOS transistor; and The first substrate-side bonding pad is bonded to the logic die bonding pad, or electrically connected to the logic die bonding pad via a conductive path within an intermediary die located between the logic die and the first 3D memory die.

6. The joining assembly according to claim 1, wherein: The driver circuitry includes complementary metal-oxide-semiconductor (CMOS) transistors located above a logic substrate; and The second alternating stack of the second insulating layer and the second conductive layer is integrally formed on the driver circuit device without having any bonding pads located between the driver circuit device and the second alternating stack.

7. The bonding assembly of claim 1, wherein the first three-dimensional memory die is located between the driver circuit device and the second three-dimensional memory die.

8. The joining assembly according to claim 7, wherein: The first three-dimensional memory die includes a first dielectric material layer, in which a first metal interconnect structure and a first interconnect side bonding pad are embedded. The distance between the first metal interconnect structure and the first interconnect side bonding pad and the driver circuit device is greater than the distance between the first alternating stack and the driver circuit device. The second three-dimensional memory die includes a second dielectric layer, in which a second metal interconnect structure and a second interconnect side bonding pad are embedded. The second metal interconnect structure and the second interconnect side bonding pad are located closer to the driver circuit device than the second alternating stack is located to the driver circuit device. The first interconnect side bonding pad is bonded to the second interconnect side bonding pad.

9. The joining assembly according to claim 8, wherein: The second three-dimensional memory die also includes a second layer of contact via structure, which extends vertically through the second stepped dielectric material portion and contacts a corresponding second conductive layer in the second conductive layer; and Each second-layer contact via structure in the second-layer contact via structure is electrically connected to a corresponding second-interconnect side bonding pad in the second interconnect side bonding pad via a corresponding sub-collector of the second metal interconnect structure.

10. The bonding assembly of claim 7 further includes a third three-dimensional memory die bonded to the second three-dimensional memory die.

11. The bonding assembly of claim 10, wherein the third three-dimensional memory die comprises: A third alternating stack of a third insulating layer and a third conductive layer, wherein the third conductive layer has a different lateral extent along the first horizontal direction, the lateral extent decreasing with a corresponding vertical distance from the driver circuit device; A third memory structure, which is located in the third alternating stack; The third step dielectric material portion contacts the third alternating stacked step surface; and The third contact via structure contacts the corresponding third conductive layer in the third conductive layer.

12. The bonding assembly of claim 1, wherein the second three-dimensional memory die is located between the driver circuit device and the first three-dimensional memory die.

13. The bonding assembly of claim 12, further comprising a third three-dimensional memory die bonded to the first three-dimensional memory die.

14. The bonding assembly of claim 13, wherein the third three-dimensional memory die comprises: A third alternating stack of a third insulating layer and a third conductive layer, wherein the third conductive layer has a different lateral extent along the first horizontal direction, the lateral extent increasing with a corresponding vertical distance from the driver circuit device; A third memory structure, which is located in the third alternating stack; The third step dielectric material portion contacts the third alternating stacked step surface; and The third contact via structure contacts the corresponding third conductive layer in the third conductive layer.

15. A method of forming a mating assembly, the method comprising: A first three-dimensional memory die is provided, the first three-dimensional memory die comprising: a first alternating stack of a first insulating layer and a first conductive layer, a first memory structure located in the first alternating stack, and a first stepped dielectric material portion contacting a stepped surface of the first alternating stack; and A second three-dimensional memory die is bonded to a first three-dimensional memory die, wherein the second three-dimensional memory die includes: a second alternating stack of a second insulating layer and a second conductive layer, a second memory structure located in the second alternating stack, and a second stepped dielectric material portion contacting the stepped surface of the second alternating stack; in: The first three-dimensional memory die is located between the driver circuit device and the second three-dimensional memory die; The first conductive layer has a different lateral extent along a first horizontal direction, and the lateral extent decreases with a corresponding vertical distance from the driver circuit device; and The second conductive layer has a different lateral extent along the first horizontal direction, and the lateral extent increases with a corresponding vertical distance from the driver circuit device; and The first three-dimensional memory die further includes: A memory opening that extends vertically through each layer within the first alternating stack, wherein the first memory structure is located in the memory opening and includes a corresponding vertical semiconductor channel and a corresponding memory film; A first-layer contact via structure extends vertically through the first stepped dielectric material portion and contacts a corresponding first conductive layer in the first conductive layer; and A first laterally isolated through-throw via structure, the first laterally isolated through-throw via structure extending vertically through the first alternating stack region, in which each layer of the first alternating stack is present and electrically connected to a corresponding first-layer contact via structure in the first-layer contact via structure; and Each laterally isolated through-thrust via structure is electrically connected to a corresponding layer contact via structure in the layer contact via structure via a corresponding conductive path. The conductive path includes at least one metal wire embedded in a dielectric material layer located on the first alternating stack. Each conductive path includes at least one metal wire and a connecting via structure. The at least one metal wire is a component of a metal interconnect structure.

16. The method of claim 15, further comprising bonding a logic die to the first three-dimensional memory die, wherein the driver circuitry includes a complementary metal-oxide-semiconductor (CMOS) transistor located in the logic die.

17. The method of claim 15, wherein: The driver circuitry includes complementary metal-oxide-semiconductor (CMOS) transistors located above a logic substrate; and The second alternating stack of the second insulating layer and the second conductive layer is integrally formed on the driver circuit device without having any bonding pads located between the driver circuit device and the second alternating stack.

18. The method of claim 15, further comprising bonding a third three-dimensional memory die to the first three-dimensional memory die or the second three-dimensional memory die, wherein the third three-dimensional memory die comprises: A third alternating stack of a third insulating layer and a third conductive layer, wherein the third conductive layer has a different lateral extent along the first horizontal direction, the lateral extent increasing or decreasing with a corresponding vertical distance from the driver circuit device; A third memory structure, which is located in the third alternating stack; The third step dielectric material portion contacts the third alternating stacked step surface; and The third contact via structure contacts the corresponding third conductive layer in the third conductive layer.

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