Refresh counter in a memory system

Abstract

This application relates to refresh counters in memory systems. In some instances, a memory device may include two or more counters configured to increment a corresponding count based on a refresh operation performed on a memory array. Comparisons may be made between two or more of the corresponding counts, which may include determining a difference between the corresponding counts or a difference in the increment rate. The memory device may send an indication to a host device based on the determined difference between the counters, and the memory device, the host device, or both may perform various operations or enter various operating modes based on the determined difference.

Description

[0001] Cross-references

[0002] This patent application is the national phase application of International Patent Application No. PCT / US2020 / 059876, filed November 10, 2020, entitled "Refresh Counters in a Memory System" by Schaefer et al., which claims priority to U.S. Patent Application No. 17 / 090,630, filed November 5, 2020, entitled "Refresh Counters in a Memory System" by Schaefer et al., and U.S. Provisional Patent Application No. 62 / 941,630, filed November 27, 2019, entitled "Refresh Counters in a Memory System" by Schaefer et al., each of which is assigned to the assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to refresh counters in memory systems. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into different states. For example, a binary memory cell can be programmed to support one of two states, typically indicated by logic 1 or logic 0. In some instances, a single memory cell can support more than two states, any one of which can be stored. To access the stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write to or program the states in the memory device.

[0005] Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), auto-select memory, and chalcogenide memory technology. Memory cells can be volatile or non-volatile. For example, non-volatile FeRAM can maintain its stored logic state for a long time even without external power. Volatile DRAM devices, on the other hand, may lose their stored state when disconnected from external power.

[0006] Some memory devices, such as memory devices containing volatile memory cells, can perform refresh operations to periodically refresh the logical state stored in the memory cells. Summary of the Invention

[0007] Describe a method. The method may include: determining at a first counter a first count based at least partially on refresh operations performed on a memory array of a memory device; determining at a second counter a second count based at least partially on the refresh operations performed on the memory array of the memory device; comparing the first count and the second count at the memory device; determining, at least partially based on the comparison, that the first count based at least partially on the refresh operations is different from the second count based at least partially on the refresh operations; and sending an indication to a host device based at least partially on the determination that the first count is different from the second count.

[0008] Describe an apparatus. The apparatus may include: a memory array; a first counter configured to increment a first count at least partially based on a refresh operation performed on the memory array; a second counter configured to increment a second count at least partially based on the refresh operation performed on the memory array; a comparator configured to determine a difference between the first count and the second count; and a transmitter configured to transmit an indication at least partially based on the difference between the first count and the second count.

[0009] Describe a method. The method may include: sending a command to a memory device to perform a refresh operation on a memory array of the memory device; receiving at a host device an indication that a first count of a first refresh counter of the memory device is different from a second count of a second refresh counter of the memory device; and at the host device determining an operating state of the memory device at least in part based on receiving the indication. Attached Figure Description

[0010] Figure 1 This describes an example of a system that supports a refresh counter in a memory system, as illustrated in the examples disclosed herein.

[0011] Figure 2 This describes an example of a memory die supporting a refresh counter in a memory system, as disclosed in this document.

[0012] Figure 3 This describes an example of a counter comparison layout for a refresh counter in a memory system, based on examples disclosed herein.

[0013] Figure 4 A block diagram of a memory device supporting a refresh counter in a memory system, based on examples disclosed herein.

[0014] Figure 5 A block diagram of a host device supporting a refresh counter in a memory system, based on examples disclosed herein.

[0015] Figures 6 to 8 The flowchart illustrates one or more methods for supporting refresh counters in a memory system, based on examples disclosed herein. Detailed Implementation

[0016] The memory system according to the examples disclosed herein may include a memory device and a host device coupled to the memory device. The reliability of the memory device in this system may be based on the statistical probability of failure at the memory device, which may be referred to as the failure rate (FIT) or other terms. Some applications, such as vehicle safety systems, autonomous vehicle systems, or other safety-critical systems, may have particularly high reliability requirements or may require a particularly low failure probability.

[0017] In some memory systems, reliability can be improved by identifying, detecting, or otherwise handling faults. For example, if a memory device experiences one hundred faults over a given period (e.g., a FIT of 100), but all errors are handled without operational failures (e.g., all errors are handled by an error correction algorithm), then the memory device can be associated with zero FIT (e.g., zero "safe FIT") or other metrics of relatively high reliability. In other words, a memory device that employs techniques to reduce the uncertainty associated with faults can have advantageous reliability even in the event of such faults, compared to a memory device that does not employ such techniques to reduce uncertainty or has relatively high uncertainty associated with faults.

[0018] In memory devices, such as those containing memory cells with a degree of volatility, the memory device may perform refresh operations to periodically refresh the logical state stored by the corresponding memory cells. Some memory devices may include counters, which may be called refresh counters, that increment a count based on the refresh operations performed on the memory array. For example, such counters increment a count whenever a row of the memory array is refreshed, or whenever a page of the memory array is refreshed, or whenever a segment of the memory array is refreshed, and other instances. Such counters can be used to evaluate whether the refresh operation is being performed properly on the memory device, and for other purposes. Although a single counter can be evaluated to identify whether the operation is being performed successfully, faults in the counter itself (e.g., stall bits, count skipping or omitting, incorrect addresses, or other erroneous counting operations) can introduce errors or uncertainties associated with the operation of the memory device or the memory system containing the memory device. Therefore, without further verification of the operation of the refresh counter, it may be necessary to assume some FIT loss or other reliability uncertainty of the refresh counter, because the operation of the refresh counter is uncertain when the memory device is in operation.

[0019] The techniques described herein can improve the reliability or reliability level of a memory system by implementing multiple refresh counters at the memory device and evaluating the differences between the counts of such refresh counters to identify whether the memory device is experiencing errors or other operational anomalies. For example, the memory device can send an indication to a host device based on determining the difference between the refresh counters, and the memory device, host device, or both can perform various operations or enter various operating modes based on the determined difference. Therefore, the memory device, host device, or both can support the reduction of operational uncertainty, which might not be supported by another memory device with a single refresh counter or this determined memory device that does not perform the difference between counters. For example, real-time confirmation or evaluation supported by multiple refresh counters can remove specific uncertainties regarding refresh or other operations, which can improve safety fit-in (FIT) or other reliability metrics that take into account the removal or mitigation of such failure uncertainties and other benefits.

[0020] First, as referenced Figure 1 and 2 The features of this disclosure are described in the context of the memory system and the die. (See references...) Figure 3 The features of this disclosure are described in the context of the counter comparison layout. These and other features of this disclosure are derived from references to [reference needed]. Figures 4 to 8 The device diagram and flowchart of the refresh counter in the described memory system are further illustrated and described with reference to the device diagram and flowchart.

[0021] Figure 1This describes an example of a system 100 that supports refresh counters in a memory system, as disclosed herein. System 100 may include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 to the memory device 110. System 100 may include one or more memory devices 110, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0022] System 100 may include portions of electronic devices, such as computing devices, mobile computing devices, wireless devices, graphics processing devices, vehicles, or other systems. For example, system 100 may describe aspects of computers, laptop computers, tablet computers, smartphones, cellular phones, wearable devices, internet-connected devices, vehicle controllers, etc. Memory device 110 may be a component of the system used to store data for one or more other components of system 100.

[0023] At least a portion of system 100 may be an instance of host device 105. Host device 105 may be an instance of a processor or other circuitry within a device that uses memory to execute processes (e.g., a computing device, mobile computing device, wireless device, graphics processing device, computer, notebook computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, or other fixed or portable electronic device), and other examples. In some instances, host device 105 may refer to the hardware, firmware, software, or a combination thereof that implements the functions of external memory controller 120. In some instances, external memory controller 120 may be referred to as a host or host device 105.

[0024] Memory device 110 may be a standalone device or a component that can be used to provide physical memory address / space available for use or reference by system 100. In some instances, memory device 110 may be configured to work with one or more different types of host devices. Signaling between host device 105 and memory device 110 may be used to support one or more of the following: modulation schemes for modulating signals, various pin configurations for conveying signals, various form factors for the physical packages of host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other factors.

[0025] Memory device 110 may be used to store data of components of host device 105. In some instances, memory device 110 may act as a slave device to host device 105 (e.g., responding to and executing commands provided by host device 105 via external memory controller 120). Such commands may include one or more of the following: write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands.

[0026] The host device 105 may include an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or one or more other components such as one or more peripheral components or one or more input / output controllers. The components of the host device may be coupled to each other via bus 135.

[0027] Processor 125 may be used to provide control or other functionality for at least a portion of system 100 or at least a portion of host device 105. Processor 125 may be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. In such instances, processor 125 may be an instance of a central processing unit (CPU), graphics processing unit (GPU), general-purpose GPU (GPGPU), or system-on-a-chip (SoC), as well as other instances. In some instances, external memory controller 120 may be implemented by processor 125 or be part of said processor.

[0028] BIOS component 130 may be a software component containing a BIOS operating as firmware, which can initialize and run various hardware components of system 100 or host device 105. BIOS component 130 may also manage data flow between processor 125 and various components of system 100 or host device 105. BIOS component 130 may contain programs or software stored in one or more read-only memory (ROM), flash memory, or any other non-volatile memory.

[0029] Memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). Memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more banks, one or more tiles, one or more segments), wherein each memory cell can be used to store at least one bit of data. Memory device 110 containing two or more memory dies may be referred to as a multi-die memory or multi-die package, or a multi-chip memory or multi-chip package.

[0030] The device memory controller 155 may include circuitry, logic, or components for controlling the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations, and may be used to receive, send, or execute commands, data, or control information related to components of the memory device 110. The device memory controller 155 may be used to communicate with one or more of an external memory controller 120, one or more memory dies 160, or processor 125. In some instances, the device memory controller 155 may be used in conjunction with a local memory controller 165 of the memory die 160 to control the operation of the memory device 110 described herein.

[0031] In some instances, memory device 110 may receive data or commands, or both, from host device 105. For example, memory device 110 may receive a write command instructing memory device 110 to store data from host device 105, or a read command instructing memory device 110 to provide data stored in memory die 160 to host device 105, or a refresh command instructing memory device 110 to refresh the logical state stored at memory device 110.

[0032] A local memory controller 165 (e.g., local to memory die 160) can be used to control the operation of memory die 160. In some instances, the local memory controller 165 can be used to communicate with device memory controller 155 (e.g., to receive or send data or commands, or both). In some instances, memory device 110 may not include device memory controller 155, and either the local memory controller 165 or the external memory controller 120 can perform the various functions described herein. Thus, the local memory controller 165 can be used to communicate with device memory controller 155, with other local memory controllers 165, or directly with external memory controller 120 or processor 125, or combinations thereof. Examples of components that may be included in device memory controller 155 or local memory controller 165 or both may include a receiver for receiving signals (e.g., from external memory controller 120), a transmitter for sending signals (e.g., to external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be sent, or various other circuitry or controllers that may be used to support the described operation of device memory controller 155 or local memory controller 165 or both.

[0033] External memory controller 120 may be used to enable the communication of one or more information, data, or commands between components of system 100 or host device 105 (e.g., processor 125) and memory device 110. External memory controller 120 may translate or interpret communications exchanged between components of host device 105 and memory device 110. In some instances, external memory controller 120, or other components of system 100 or host device 105, or their functionality as described herein, may be implemented by processor 125. For example, external memory controller 120 may be hardware, firmware, or software, or a combination thereof, implemented by processor 125 or other components of system 100 or host device 105. Although external memory controller 120 is depicted as external to memory device 110, in some instances, external memory controller 120, or its functionality as described herein, may be implemented by one or more components of memory device 110 (e.g., device memory controller 155, local memory controller 165), or vice versa.

[0034] Components of host device 105 may exchange information with memory device 110 using one or more channels 115. Channels 115 may be used to support communication between external memory controller 120 and memory device 110. Each channel 115 may be an example of a transmission medium carrying information between host device 105 and memory device. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. Signal paths may be examples of conductive paths that can be used to carry signals. For example, channel 115 may include a first terminal comprising one or more pins or pads at host device 105 and one or more pins or pads at memory device 110. Pins may be examples of conductive input or output points of devices of system 100, and pins may be used to serve as part of a channel.

[0035] Channel 115 (and associated signal paths and terminals) may be dedicated to conveying one or more types of information. For example, channel 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or combinations thereof. In some instances, single data rate (SDR) signaling or double data rate (DDR) signaling may be used to convey signaling via channel 115. In SDR signaling, one modulation symbol (e.g., signal level) of the signal may be registered for each clock cycle (e.g., on the rising or falling edge of the clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of the signal may be registered for each clock cycle (e.g., on both the rising and falling edges of the clock signal).

[0036] In some instances, the memory array 170 of memory device 110 may include memory cells with a certain degree of volatility, and memory device 110 may perform refresh operations to periodically refresh the logical state stored by the corresponding memory cells. In some instances, refresh operations may be performed at memory device 110 based on configured periodic or other triggering events of components of memory device 110 (e.g., determined at device memory controller 155 or local memory controller 165). An example of this configuration may be referred to as a "self-refresh" mode, in which memory device 110 may enter a standby mode and perform refresh operations based on an internal oscillator (e.g., of the device memory controller or local memory controller 165).

[0037] Alternatively, a refresh operation may be performed at the memory device 110 based on periodicity or other triggering events of the host device 105 (e.g., signaling or commanding via channel 115). An example of this configuration may be referred to as "automatic refresh" mode, in which a refresh command is initiated by the host device 105, such as a command to refresh all rows of the memory array 170. The periodicity of such commands may be determined at the host device and may depend on temperature, among other parameters.

[0038] According to the examples disclosed herein, memory device 110 may include two or more refresh counters configured to increment a count value based on the same refresh operation, and the corresponding count values ​​of such refresh counters may be compared or otherwise evaluated to determine whether memory device 110 is operating normally. For example, each of a set of refresh counters may be configured to increment a count (e.g., simultaneously, in parallel) based on a row of memory cells in refresh memory array 170, a page of memory cells in refresh memory array 170, or a segment of memory cells in refresh memory array 170. In other words, multiple refresh counters, which may be referred to as redundant refresh counters or supplementary refresh counters, may be provided at memory device 110 to provide normal or generally redundant count values ​​(e.g., count values ​​that increment at the same rate under normal operation).

[0039] The difference between the count values ​​of the redundant refresh counters of memory device 110 can indicate errors or abnormal operations at memory device 110, which can be used to support various operations or operating modes of memory device 110 or host device 105. Therefore, memory device 110, host device 105, or both can support reduced operational uncertainty, whereas a memory device with a single refresh counter or that does not perform the difference between counters may not support reduced operational uncertainty. In some instances, a set of two or more redundant or supplementary refresh counters may be provided at the device memory controller 155 of memory device 110, or a corresponding plurality of sets of two or more redundant or supplementary refresh counters may be provided at each of a set of local memory controllers 165 of memory device 110, which can support error identification or handling at various granularities (e.g., error identification or handling of memory device 110 as a whole, error identification or handling of a specific memory die 160 of memory device 110).

[0040] Figure 2 This describes an example of a memory die 200 supporting a refresh counter in a memory system, as disclosed herein. The memory die 200 may be a reference. Figure 1Examples of the described memory die 160. In some instances, the memory die 200 may be referred to as a memory chip, memory device, or electronic memory device. The memory die 200 may include one or more memory cells 205, each of which can be programmed to store different logical states (e.g., one of a set of two or more possible states programmed). For example, memory cell 205 may be used to store one bit of information at a time (e.g., logic 0 or logic 1). In some instances, memory cell 205 (e.g., a multi-level memory cell) may be used to store more than one bit of information at a time (e.g., logic 00, logic 01, logic 10, logic 11).

[0041] Memory cell 205 can store charge representing a programmable state in a capacitor. A DRAM architecture may include a capacitor containing a dielectric material to store charge representing a programmable state. In other memory architectures, other memory devices and components are possible. For example, a nonlinear dielectric material may be used. Memory cell 205 may include logic storage components, such as capacitor 230 and switching component 235. Capacitor 230 may be an example of a dielectric capacitor or a ferroelectric capacitor. Nodes of capacitor 230 may be coupled to a voltage source 240, which may be a cell board reference voltage, such as Vpl, or may be ground, such as Vss.

[0042] The memory die 200 may include one or more access lines (e.g., one or more word lines 210 and one or more digital lines 215) arranged in a pattern such as a grid pattern. The access lines may be conductive lines coupled to memory cells 205 and used to perform access operations on memory cells 205. In some instances, word lines 210 may be referred to as row lines. In some instances, digital lines 215 may be referred to as column lines or bit lines. References to access lines, row lines, column lines, word lines, digital lines, or bit lines, or the like, may be interchanged without affecting understanding or operation. Memory cells 205 may be located at the intersection of word lines 210 and digital lines 215.

[0043] Operations such as reading and writing can be performed on memory cell 205 by activating or selecting one or more access lines, such as word line 210 or digital line 215. A single memory cell 205 at its intersection can be accessed by applying a bias voltage to word line 210 and digital line 215 (e.g., applying a voltage to word line 210 or digital line 215). The intersection point of word line 210 and digital line 215 in a two-dimensional or three-dimensional configuration can be referred to as the address of memory cell 205.

[0044] The access memory unit 205 can be controlled via either row decoder 220 or column decoder 225. For example, row decoder 220 can receive a row address from local memory controller 260 and activate word line 210 based on the received row address. Column decoder 225 can receive a column address from local memory controller 260 and activate digital line 215 based on the received column address.

[0045] The selection or deselection of memory cell 205 can be achieved by activating or deactivating the activation switch assembly 235 using word line 210. Capacitor 230 can be coupled to digital line 215 using the switch assembly 235. For example, when the activation switch assembly 235 is deactivated, capacitor 230 can be isolated from digital line 215, and when the switch assembly 235 is activated, capacitor 230 can be coupled to digital line 215.

[0046] Word line 210 may be a conductive line electrically connected to the memory cell 205 for performing access operations on the memory cell 205. In some architectures, word line 210 may be coupled to the gate of a switching component 235 of the memory cell 205 and may be used to control the switching component 235 of the memory cell. In some architectures, word line 210 may be coupled to a node of a capacitor in the memory cell 205, and the memory cell 205 may not include a switching component.

[0047] Digital line 215 may be a conductive line connecting memory cell 205 to sensing component 245. In some architectures, memory cell 205 may be selectively coupled to digital line 215 during a portion of an access operation. For example, word line 210 and switching component 235 of memory cell 205 may be used to couple and / or isolate capacitor 230 of memory cell 205 and digital line 215. In some architectures, memory cell 205 may be coupled to digital line 215.

[0048] Sensing component 245 can be used to detect the state (e.g., charge) stored on capacitor 230 of memory cell 205 and determine the logic state of memory cell 205 based on the stored state. Sensing component 245 may include one or more sensing amplifiers to amplify or otherwise convert the signal generated by accessing memory cell 205. Sensing component 245 can compare the signal detected from memory cell 205 with reference 250 (e.g., reference voltage). The detected logic state of memory cell 205 can be provided as an output of sensing component 245 (e.g., to input / output 255) and can indicate the detected logic state to another component of the memory device including memory die 200.

[0049] The local memory controller 260 can control access to the memory cell 205 through various components (e.g., row decoder 220, column decoder 225, sensing component 245). The local memory controller 260 can be a reference. Figure 1 Examples of the described local memory controller 165. In some instances, one or more of the row decoder 220, column decoder 225, and sensing components 245 may be co-located with the local memory controller 260. The local memory controller 260 may be used to receive one or more commands or data from one or more different memory controllers (e.g., an external memory controller 120 associated with host device 105, another controller associated with memory die 200), translate the commands or data (or both) into information usable by memory die 200, perform one or more operations on memory die 200, and transmit data from memory die 200 to host device 105 based on the performance of said one or more operations. The local memory controller 260 may generate row signals and column address signals to activate target word line 210 and target digital line 215. The local memory controller 260 may also generate and control various voltages or currents used during operation of memory die 200. Generally, the amplitude, shape, or duration of the applied voltage or current discussed herein may vary and may differ for the various operations discussed when operating the memory die 200.

[0050] The local memory controller 260 can be used to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations may include write operations, read operations, refresh operations, precharge operations, or activation operations, etc. The local memory controller 260 can also be used to perform other access operations not listed herein or other operations related to the operation of the memory die 200 but not directly related to accessing the memory cells 205.

[0051] The local memory controller 260 can be used to perform write operations (e.g., programming operations) on one or more memory cells 205 of the memory die 200. During a write operation, the memory cells 205 of the memory die 200 can be programmed to store a desired logical state. The local memory controller 260 can identify the target memory cell 205 to which a write operation will be performed. The local memory controller 260 can identify a target word line 210 and a target digital line 215 coupled to the target memory cell 205 (e.g., the address of the target memory cell 205). The local memory controller 260 can activate the target word line 210 and the target digital line 215 (e.g., apply a voltage to the word line 210 or the digital line 215) to access the target memory cell 205. During a write operation, the local memory controller 260 can apply a specific signal (e.g., a write pulse) to the digital line 215 to store a specific state (e.g., charge) in the capacitor 230 of the memory cell 205. The pulse used as part of the write operation may contain one or more voltage levels over a duration.

[0052] The local memory controller 260 can be used to perform read operations (e.g., sensing operations) on one or more memory cells 205 of the memory die 200. During the read operation, the logical state stored in the memory cells 205 of the memory die 200 can be determined. The local memory controller 260 can identify the target memory cell 205 to which the read operation will be performed. The local memory controller 260 can identify the target word line 210 and the target digital line 215 coupled to the target memory cell 205 (e.g., the address of the target memory cell 205). The local memory controller 260 can activate the target word line 210 and the target digital line 215 (e.g., apply a voltage to the word line 210 or the digital line 215) to access the target memory cell 205. The target memory cell 205 can transmit a signal to the sensing component 245 in response to applying a bias voltage to the access line. The sensing component 245 can amplify the signal. The local memory controller 260 can activate the sensing component 245 (e.g., a latching sensing component), and thereby compare the signal received from the memory cell 205 with the reference 250. Based on the comparison, the sensing component 245 can determine the logic state stored in the memory cell 205.

[0053] The local memory controller 260 can be used to perform refresh operations on one or more memory cells 205 of the memory die 200. During a refresh operation, the logical state stored in the memory cell 205 of the memory die 200 can be first determined (e.g., according to aspects of the read operation described above), and then the memory cell 205 can be reprogrammed according to the determined logical state (e.g., according to aspects of the write operation described above). This refresh operation can be performed to restore or enhance the charge state associated with the corresponding logical state, or to restore or expand the read margin within an acceptable range, which can overcome aspects of volatility or other logical state degradation in the memory cell 205 of the memory die 200. In various instances, the refresh operation can be initiated by a component of the memory die 200 (e.g., initiated by the local memory controller 260), or by a host device communicating with the memory die 200 (e.g., performed in response to signaling received from the host device, such as at the local memory controller 260), or both.

[0054] According to the examples disclosed herein, memory die 200 (e.g., local memory controller 260) may include a first refresh counter 270-a and a second refresh counter 270-b, each configured to increment a corresponding count value based on a refresh operation performed on memory cell 205. The corresponding count values ​​of the first refresh counter 270-a and the second refresh counter 270-b may be compared or otherwise evaluated to determine whether memory die 200 is operating correctly. For example, the difference between the count value of the first refresh counter 270-b and the count value of the second refresh counter 270-b, or a difference that meets a threshold, may indicate an error or abnormal operation at memory die 200. For example, the difference between the count values ​​of the first refresh counter 270-b and the second refresh counter 270-b may indicate that one of the refresh counters 270 has failed or has otherwise operated abnormally (e.g., with a stall bit, skipped increments, or skipped increments).

[0055] In some instances, the indication of the count difference between refresh counters 270 can be used to support various operating or operational modes of the memory die 200, the memory device 110 containing the memory die 200, or the host device 105 communicating with the memory die 200 (or any combination thereof) to reduce uncertainties that may be associated with various failures or problems (e.g., the first refresh counter 270-a, the second refresh counter 270-b of another component of the memory die 200). Therefore, including both the first refresh counter 270-a and the second refresh counter 270-b can support reduced operational uncertainty, while a memory die with a single refresh counter or one that does not perform an evaluation of the difference between counters may not support reduced operational uncertainty. This can improve FIT or other reliability metrics associated with the memory die 200.

[0056] Figure 3 This describes an example of a counter comparison layout 300 for a refresh counter in a memory system, as disclosed herein. The counter comparison layout 300 can be described as shown in the references. Figure 1 and 2 The memory device 110 or memory die 200 is described in various aspects. In various examples, the counter comparison layout can be illustrated as shown in the references. Figure 1 The described device memory controller or local memory controller 165 components, or as referenced Figure 2 The local memory controller 260, or a combination thereof, as described.

[0057] The counter comparison layout 300 may include one or more components configured or usable for signaling with the host device 105. For example, the counter comparison layout 300 may include control logic 310, a command and address decoder 320, and a mode register 330, which may be configured to exchange information or other signaling with the host device 105. The counter comparison layout 300 may also include various components configured to support operations on the memory die 160 or the memory array 170. For example, the counter comparison layout 300 may include a row address multiplexer (MUX) 340 and bank group (BG) and bank address (BA) control logic 350, which may be configured to support access operations to specific portions of the memory array 170.

[0058] The counter comparison layout 300 may also include a master refresh counter 360 configured to increment a count based on refresh operations performed on the associated memory array 170. The master refresh counter 360 may be configured to increment a count each time a row of the memory array 170 is refreshed, and the count may toggle to zero after exceeding the digital capacity or other limits of the master refresh counter 360. Alternatively, the count of the master refresh counter 360 may be reset to a default value (e.g., zero) periodically or after all rows of the memory array 170 have been refreshed. Alternatively, the count of the master refresh counter 360 may be reset after a verification operation is completed (e.g., after a different count value is detected and normal operation is resumed) or after other issues are resolved. In some instances, the master refresh counter 360 may be configured to output the count value or other status signaling to one or both of the row address MUX 340 or the BG and BA control logic 350.

[0059] The counter comparison layout 300 may also include an auxiliary refresh counter 370 (e.g., a redundant refresh counter, an acknowledged refresh counter), which is also configured to increment the count based on refresh operations performed on the associated memory array 170. The auxiliary refresh counter 370 may be configured to increment the count in the same manner as the primary refresh counter 360. Therefore, under normal operating conditions (e.g., normal operation of the primary refresh counter 360 and the auxiliary refresh counter 370), the count accumulated by the auxiliary refresh counter 370 may be the same as the count accumulated by the primary refresh counter 360, or the increment rate of the auxiliary refresh counter 370 may be the same as the increment rate of the primary refresh counter 360. When the count of the primary refresh counter 360 differs from the count of the auxiliary refresh counter 370 or increments at different rates, one or both of the primary refresh counter 360 or the auxiliary refresh counter 370 may operate abnormally.

[0060] By including the auxiliary refresh counter 370, the counter comparison layout 300 can support various techniques for reducing operational uncertainty of the memory device 110 or a system including the memory device 110. For example, the memory device 110 or the host device 105 communicating with the memory device 110 can enter an operating mode (e.g., a secure state, an evaluation state) that supports: identifying or confirming whether the memory device 110 is operating properly in other ways, such as identifying or confirming that the refresh operation itself is being performed normally, whether address decoding is being performed normally, whether abnormal operation of the main refresh counter 360 or the auxiliary refresh counter 370 is temporary, whether data exchange with the memory device 110 (e.g., read or write operations) is supported, etc. In some instances, the memory device 110 can increase the rate at which refresh operations are performed (e.g., double the rate of refresh operations), which may be associated with a temporary state (e.g., during the evaluation of a secure state) or with an increasing refresh rate that continues whenever the count or increment rate between the main refresh counter and the auxiliary refresh counter differs or otherwise meets a threshold.

[0061] Alternatively, the signaling supported by the auxiliary refresh counter 370 may support informing the host device 105 of the operating state of the memory device 110 or modifying the operating state of the memory device 110 (e.g., modifying it to a safe state). This allows the host device 105 to enter an operating mode in which it verifies the functional operation of the memory device 110, performs access operations using different memory devices 110, indicates possible error states (e.g., to the user, to the system containing the host device 105 and the memory device 110), and performs other functions. In another example, if the memory device 110 indicates to the host device 105 that a counter mismatch condition exists, the host device 105 may increase the rate of command refresh operations.

[0062] Therefore, including the auxiliary refresh counter 370 can help reduce uncertainty about the operational state, which may include reducing uncertainty about conditions that could indicate or suggest possible erroneous states of the memory device 110. This reduction in uncertainty can be beneficial in applications such as vehicle control systems, safety systems, and autonomous vehicles, where operational determinism is required to ensure continuous system operation. For example, although the operation of the memory device 110 can continue normally even in cases where the counts of the main refresh counter 360 and the auxiliary refresh counter differ or have a difference greater than a threshold, such conditions can provide an early indication of abnormal conditions that can be evaluated by the memory system, supporting confirmation of operation and reducing uncertainty about the operational state of the system 100.

[0063] To support the evaluation of counting or incrementing between the primary refresh counter 360 and the secondary refresh counter 370, the counter comparison layout 300 also includes a comparator 380 to compare counts as indicated by the primary refresh counter 360 and the secondary refresh counter 370. The comparator 380 can be configured to support various signaling when the counts of the primary refresh counter 360 and the secondary refresh counter 370 are equal or different, or when the increment rates of the primary refresh counter 360 and the secondary refresh counter 370 are the same or different. Although the comparator 380 is described as comparing signaling received from two refresh counters, the comparator 380 can be configured to compare three or more refresh counters in a comparison set. Furthermore, in some instances, the comparator 380 can be configured to select or compute a specific count value to be output (e.g., to line address MUX 340, to BG and BA control logic 350), such as selecting the output from a preferred refresh counter, or one of its average values. Therefore, comparator 380 can be configured in various ways and can support various functionalities based on the count values ​​received from the main refresh counter 360 or the auxiliary refresh counter 370 or both.

[0064] In one example, comparator 380 can be configured in an XOR configuration with binary output via a "refresh counter status" pin or signal path. In this configuration, comparator 380 can output logic 0 when the counts indicated by the main refresh counter 360 and the auxiliary refresh counter are the same, or output logic 1 when the counts indicated by the main refresh counter 360 and the auxiliary refresh counter 370 are different. In another example, comparator 380 can be configured to signal logic 0 when the counts or rate of increase of the main refresh counter 360 and the auxiliary refresh counter 370 meet a threshold (e.g., within a threshold count, within a threshold rate of increase), or signal logic 1 when the counts or rate of increase of the main refresh counter 360 and the auxiliary refresh counter 370 do not meet the threshold. However, other logic and signaling configurations are possible according to the examples described herein. In some examples, comparator 380 may also include a switching detector for one or more of the associated counters, which can support the detection of stuck counters.

[0065] In some instances, the result of comparator 380 can be indicated to mode register 330, and the result of comparator 380 can be stored in mode register 330. For example, any mismatch in the count or increment rate between the main refresh counter 360 and the auxiliary refresh counter 370 can be registered as an error in mode register 330 (e.g., in the MRx5[op4] field). The value of mode register 330 can be signaled to host device 105 in various situations, including during periodic or triggered state exchanges (e.g., via control channels or signal paths, via sideband channels or signal paths). For example, signaling associated with refresh counter comparisons can be contained on sideband signals separate from other signaling, such as enhanced state signaling channels or signal paths (e.g., real-time state channels, DSF channels, DSF+ channels, alarm pins, parallel pins). In some instances, the DSF channel can refer to a dedicated function enable input. In some instances, an error value in mode register 330 can be indicated by a data burst (e.g., via a data channel between memory device 110 and host device 105). In other instances of the counter comparison layout 300, an indication can be provided to the host device 105 without first storing the value in the mode register 330.

[0066] In some instances, host device 105 may poll or query memory device 110, which contains counter comparison layout 300, to obtain information from mode register 330. This may include, or otherwise refer to, host device 105 reading mode register 330 from memory device 110, or memory device 110 sending signaling indicating the value or flag of mode register 330 to host device 105. The rate of such polling or querying can be configured for various applications, such as a relatively high polling rate for safety-critical systems, or a relatively low polling rate for systems where latency in status signaling to host device 105 is more permissible. In other words, signaling related to the difference between primary refresh counter 360 and secondary refresh counter 370 may not be immediate. In other instances, signaling may be immediate, for example, signaling initiated once the difference between primary refresh counter 360 and secondary refresh counter 370 is detected or identified.

[0067] In some instances, the rate or initialization criterion evaluated by comparator 380 can be configured for various applications. This rate or initialization criterion may be a periodic rate or initialization criterion set at comparator 380 itself, or a periodic rate or initialization criterion set at another component (e.g., counter comparison layout 300, memory device 110, host device 105). For example, comparisons performed by comparator 380 may be initiated by a component external to comparator 380, or the results of comparisons performed by comparator 380 may be requested or polled externally to comparator 380.

[0068] In some instances, the described techniques for refresh counter verification (e.g., row refresh counter verification) can be enabled based on the value of mode register 330, which may be a value set during the manufacture of memory device 110, a value configured before the memory device 110 is mounted with host device 105, or a value configured by or using host device 105. In one instance, such functionality can be enabled by setting a mode register (e.g., MRx3[OP6]) to a value of 1. Host device 105 may instruct polling of memory device 110 to obtain such mode register indications and perform operations (e.g., refresh operation, evaluation operation, recovery operation) at least in part based on whether the value indicates that memory device 110 is enabled to perform refresh counter verification.

[0069] The host device 105 can use signaling from the memory device 110 regarding refresh counter verification in various ways. For example, the host device 105, receiving an indication of the difference between refresh counters from the memory device 110, can determine the operating state of the memory device 110 (e.g., the memory device 110 is operating in a safe state or an evaluation state) and then perform one or more actions or operations. In some instances, upon receiving this signaling, the host device 105 can determine that a different memory device 110 is being accessed, and if this signaling is not present (e.g., after the initial signaling of the difference in the refresh counters), the host device 105 may or may not return to accessing the memory device 110. In some instances, the host device 105 can assess the duration of the presence of this signaling, and after a threshold duration has elapsed, the host device 105 can identify an error state of the memory device 110 (e.g., the memory device 110 has a persistent error, or the memory device 110 has failed). Under such conditions, host device 105 may (e.g., to a user, to a system containing host device 105) send an error indication, which may include a warning indication, an error display, an indication that host device 105 or memory device 110 is operating in a degraded manner, an indication that memory device 110 should be replaced, or other indications.

[0070] Figure 4 A block diagram 400 illustrates a memory device 405 supporting a refresh counter in a memory system according to an example disclosed herein. The memory device 405 may be as described in the references... Figures 1 to 3 Examples of various aspects of the described memory device. Memory device 405 may include a first counter component 410, a second counter component 415, a counter comparison component 420, a counter status indication component 425, an operation status manager 430, a control signaling receiver 435, a mode register component 440, and a refresh operation manager 445. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0071] The first counter component 410 can determine a first count based on a refresh operation performed on the memory array of the memory device at a first counter.

[0072] The second counter component 415 can determine a second count at the second counter based on refresh operations performed on the memory array of the memory device.

[0073] The counter comparison component 420 can compare the first count with the second count at the memory device.

[0074] In some instances, the counter comparison component 420 may determine, based on the comparison, that a first count based on a refresh operation differs from a second count based on a refresh operation. In some instances, the counter comparison component 420 may determine that the difference between the first count and the second count meets a threshold, wherein sending an indication to the host device is based on determining that the difference between the first count and the second count meets the threshold. In some instances, the counter comparison component 420 may compare the first count and the second count based on a periodic duration.

[0075] The counter status indication component 425 can send an indication to the host device based on determining that a first count differs from a second count. In some instances, the counter status indication component 425 can send the indication to the host device via a data burst. In some instances, the counter status indication component 425 can send the indication to the host device via sideband transmission.

[0076] In some cases, the transmission indication may be based on determining that the difference between a first count and a second count meets a threshold. In some cases, the indication may be configured to indicate to the host device that the memory device has modified its operating state to a safe state. In some cases, the transmission indication may be based on the value of a field in a mode register.

[0077] The operation state manager 430 can modify the operation state of the memory device based on the determination that a first count based on a refresh operation is different from a second count based on a refresh operation.

[0078] The control signaling receiver 435 can receive signals from the host device and can initiate a comparison between the first count and the second count based on the signals received from the host device.

[0079] The mode register component 440 can set a field of the mode register to a value based on determining that the first count and the second count are different.

[0080] The refresh operation manager 445 can perform refresh operations on the volatile memory cells of the memory array at the memory device.

[0081] Figure 5A block diagram 500 illustrates a host device 505 supporting a refresh counter in a memory system according to an example disclosed herein. The host device 505 may be as described in the references... Figures 1 to 3 Examples of various aspects of the described host device. Host device 505 may include a refresh operation manager 510, a counter status indication receiver 515, an operation status manager 520, a memory device manager 525, an access operation manager 530, an error status determination component 535, an error status indication component 540, and a control signaling transmitter 545. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0082] The refresh operation manager 510 can send commands to the memory device to perform refresh operations on the memory array of the memory device.

[0083] The counter status indication receiver 515 can receive at the host device an indication that the first count of the first refresh counter of the memory device is different from the second count of the second refresh counter of the memory device.

[0084] The operation status manager 520 can determine the operation status of the memory device at the host device based on received instructions.

[0085] In some instances, the operation state manager 520 can determine that the duration associated with the operation state of the memory device meets a threshold.

[0086] The memory device manager 525 can determine access to a second memory device based on the determined operating state of the memory device.

[0087] The access operation manager 530 can perform an access operation on the second memory device based on determining that access to the second memory device is required.

[0088] Error state determination component 535 can determine the error state of the memory device based on determining that the duration associated with the operating state of the memory device meets a threshold.

[0089] Error status indication component 540 can send an error indication based on the error status of the memory device.

[0090] The control signaling transmitter 545 can send an instruction (e.g., a second instruction) to the memory device, wherein receiving an instruction from the memory device is based on (e.g., in response to) sending the instruction.

[0091] Figure 6The flowchart illustrates one or more methods 600 for supporting refresh counters in a memory system according to examples disclosed herein. Operation of method 600 can be implemented by a memory device or its components as described herein. For example, operation of method 600 can be performed as described in the references... Figure 4 The described memory device performs the function. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described function. Alternatively, the memory device may use dedicated hardware to perform aspects of the described function.

[0092] At 605, the memory device may determine a first count based on refresh operations performed on the memory array of the memory device at a first counter. The operation of 605 may be performed according to the method described herein. In some instances, aspects of the operation of 605 may be determined by reference to... Figure 4 The first counter component described is executed.

[0093] At 610, the memory device may determine a second count based on refresh operations performed on the memory array of the memory device at a second counter. The operation of 610 may be performed according to the method described herein. In some instances, aspects of the operation of 610 may be determined by reference to... Figure 4 The described second counter component is executed.

[0094] At 615, the memory device can compare a first count with a second count. The operation of 615 can be performed according to the method described herein. In some instances, aspects of the operation of 615 can be derived from, as referenced... Figure 4 The described counter comparison component is executed.

[0095] At 620, the memory device can determine, based on the comparison, that the first count based on the refresh operation differs from the second count based on the refresh operation. The operation of 620 can be performed according to the method described herein. In some instances, aspects of the operation of 620 can be determined by reference to... Figure 4 The described counter comparison component is executed.

[0096] At 625, the memory device may send an indication to the host device based on determining that the first count differs from the second count. The operation of 625 may be performed according to the method described herein. In some instances, aspects of the operation of 625 may be provided as referenced. Figure 4 The described counter status indicates component execution.

[0097] In some instances, the device as described herein may perform one or more methods, such as method 600. The device may include features, circuitry, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following operations: determining at a first counter a first count based on refresh operations performed on a memory array of a memory device; determining at a second counter a second count based on refresh operations performed on a memory array of a memory device; comparing the first count with the second count; determining based on the comparison that the first count based on the refresh operations differs from the second count based on the refresh operations; and sending an indication to a host device based on the determination that the first count differs from the second count.

[0098] Method 600 and some examples of the devices described herein may further include operations, features, circuit systems, components, or instructions for modifying the operating state of the memory device based on determining that a first count based on a refresh operation differs from a second count based on a refresh operation.

[0099] In some instances of method 600 and the devices described herein, the indication may be configured to indicate to the host device that the memory device may have modified its operating state to a safe state.

[0100] Method 600 and some examples of the devices described herein may further include operations, features, circuitry, components, or instructions for performing the following: determining that the difference between a first count and a second count satisfies a threshold, and sending an indication to a host device may be based on determining that the difference between the first count and the second count satisfies the threshold.

[0101] In some instances of method 600 and the device described herein, comparing the first count with the second count may include operations, features, circuitry, components, or instructions for comparing the first count with the second count based on a periodic duration.

[0102] Method 600 and some examples of the devices described herein may further include operations, features, circuit systems, components, or instructions for receiving signals from a host device and initiating a comparison of a first count with a second count based on the signals received from the host device.

[0103] Method 600 and some instances of the devices described herein may further include operations, features, circuitry, components, or instructions for setting a field of a mode register to a value based on determining that a first count differs from a second count. In some instances, a transmission instruction may include sending an instruction based on the value of a field in the mode register to a host device.

[0104] In some instances of method 600 and the devices described herein, the transmission indication may include operations, features, circuitry, components, or instructions for transmitting the indication to the host device in a data burst.

[0105] In some instances of method 600 and the devices described herein, the transmission indication may include operations, features, circuitry, components, or instructions for transmitting the indication to the host device via sidebands.

[0106] Method 600 and some examples of the devices described herein may further include operations, features, circuitry, components, or instructions for performing refresh operations on volatile memory cells of a memory array at a memory device.

[0107] Figure 7 The flowchart illustrates one or more methods 700 for supporting refresh counters in a memory system according to examples disclosed herein. Operation of method 700 may be implemented by a memory device or its components as described herein. For example, operation of method 700 may be performed as described in the references... Figure 4 The described memory device performs the function. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described function. Alternatively, the memory device may use dedicated hardware to perform aspects of the described function.

[0108] At 705, the memory device may determine a first count based on refresh operations performed on the memory array of the memory device at a first counter. The operation of 705 may be performed according to the methods described herein. In some instances, aspects of the operation of 705 may be determined by reference to... Figure 4 The first counter component described is executed.

[0109] At 710, the memory device may determine a second count based on refresh operations performed on the memory array of the memory device at a second counter. The operation of 710 may be performed according to the method described herein. In some instances, aspects of the operation of 710 may be determined by reference to... Figure 4 The described second counter component is executed.

[0110] At 715, the memory device can compare a first count with a second count. The operation of 715 can be performed according to the method described herein. In some instances, aspects of the operation of 715 can be derived from, as referenced... Figure 4 The described counter comparison component is executed.

[0111] At 720, the memory device can determine, based on the comparison, that a first count based on a refresh operation differs from a second count based on a refresh operation. The operation of 720 can be performed according to the methods described herein. In some instances, aspects of the operation of 720 can be determined by reference to... Figure 4 The described counter comparison component is executed.

[0112] At 725, the memory device can modify its operating state based on determining that a first count based on a refresh operation differs from a second count based on a refresh operation. The operation of 725 can be performed according to the method described herein. In some instances, aspects of the operation of 725 can be determined as described in reference... Figure 4 The described operation state manager is executed.

[0113] At 730, the memory device may send an indication to the host device based on determining that the first count differs from the second count. The operation of 730 may be performed according to the methods described herein. In some instances, the indication may be configured to indicate to the host device that the memory device has modified its operating state to a safe state. In some instances, aspects of the operation of 730 may be determined by reference to [reference needed]. Figure 4 The described counter status indicates component execution.

[0114] Figure 8 The flowchart illustrates one or more methods 800 for supporting refresh counters in a memory system according to examples disclosed herein. Operation of method 800 may be implemented by a host device or its components as described herein. For example, operation of method 800 may be performed by, as referenced... Figure 5 The described host device performs the function. In some instances, the host device may execute a set of instructions to control the functional elements of the host device to perform the described function. Alternatively, the host device may use dedicated hardware to perform aspects of the described function.

[0115] At point 805, the host device may send a command to the memory device to perform a refresh operation on the memory array of the memory device. The operation of point 805 may be performed according to the methods described herein. In some instances, aspects of the operation of point 805 may be derived from, as referenced... Figure 5 The refresh operation manager is executed as described.

[0116] At 810, the host device may receive from the memory device an indication that a first count of a first refresh counter of the memory device differs from a second count of a second refresh counter of the memory device. The operation of 810 may be performed according to the method described herein. In some instances, aspects of the operation of 810 may be determined by reference to [reference needed]. Figure 5 The described counter status indicates the receiver's action.

[0117] At 815, the host device can determine the operating state of the memory device based on a received instruction. The operation of 815 can be performed according to the methods described herein. In some instances, aspects of the operation of 815 can be determined as described in reference [reference needed]. Figure 5 The described operation state manager is executed.

[0118] In some instances, the device as described herein may perform one or more methods, such as method 800. The device may include features, circuitry, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following operations: sending a command to a memory device to perform a refresh operation on the memory array of the memory device; receiving from the memory device an indication that a first count of a first refresh counter of the memory device differs from a second count of a second refresh counter of the memory device; and determining an operational state of the memory device based on the received indication.

[0119] Method 800 and some examples of the devices described herein may further include operations, features, circuit systems, components, or instructions for performing the following: determining access to a second memory device based on a determined operating state of the memory device; and performing an access operation on the second memory device based on the determination to access the second memory device.

[0120] Method 800 and some instances of the device described herein may further include operations, features, circuitry, components, or instructions for performing the following: determining that a duration associated with an operating state of the memory device satisfies a threshold; determining an error state of the memory device based on the determination that the duration associated with the operating state of the memory device satisfies the threshold; and sending an error indication based on the error state of the memory device.

[0121] Method 800 and some examples of the devices described herein may further include operations, features, circuit systems, components or instructions for sending an indication (e.g., a second indication) to a memory device, wherein receiving an indication from the memory device may be based on (e.g., in response to) sending the indication.

[0122] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, parts from two or more methods can be combined.

[0123] An apparatus is described. The apparatus may include: a memory array; a first counter configured to increment a first count based on a refresh operation performed on the memory array; a second counter configured to increment a second count based on a refresh operation performed on the memory array; a comparator configured to determine a difference between the first count and the second count; and a transmitter configured to transmit an indication based on the difference between the first count and the second count.

[0124] Some instances of the device may include a state controller configured to modify the operating state of the device based on the difference between a first count and a second count.

[0125] In some instances, the indication sent by the transmitter can be configured to indicate that the state controller has entered a safe state.

[0126] In some instances, the comparator may be configured to determine that the difference between the first count and the second count satisfies a threshold, and the transmitter may be configured to send an indication based on the determination that the difference between the first count and the second count satisfies the threshold.

[0127] In some instances, the comparator can be configured to initiate the determination of the difference between a first count and a second count based on the periodic duration.

[0128] Some instances of the device may include a receiver configured to receive signals from a host device, and a comparator may be configured to determine the difference between a first count and a second count based on signals received from the host device by the receiver.

[0129] In some instances, the indication sent by the transmitter may include the device’s line decoding status.

[0130] Some instances of the device may include a mode register configured to store operation indicators for the device, and the mode register may be configured to set the value of a field based on determining the difference between a first count and a second count. In some instances, in order to send an indication, a transmitter may be configured to send an indication of the value of a field.

[0131] In some instances, the transmitter can be configured to send data in bursts.

[0132] In some instances, the transmitter can be configured to send indications via one or more signaling paths dedicated to status signaling between the device and the host device.

[0133] In some instances, the memory array contains a set of volatile memory cells.

[0134] The information and signals described herein can be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, those skilled in the art will understand that the signal may represent a signal bus, wherein the bus may have multiple bit widths.

[0135] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" refer to a relationship between components that supports the flow of signals between them. Components are considered electronically connected (or electrically contacting, connected, or coupled) to each other if any conductive path exists between them that supports the flow of signals at any given time. At any given time, the conductive path between electronically connected (or electrically contacting, connected, or coupled) components can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, the signal flow between connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0136] The term "coupling" refers to the condition that moves from an open-circuit relationship between components to a closed-circuit relationship, in which a signal is currently unable to travel between the components via a conductive path, and in which a signal can travel between the components via the conductive path. When a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between the other components via conductive paths that were previously not permitted.

[0137] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. If there is an open circuit between components, then the components are isolated from each other. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. When a controller isolates two components, it prevents signals from flowing between the components using previously permitted conductive paths.

[0138] The devices containing memory arrays discussed herein can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by using doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0139] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, drain, and gate. Terminals may be connected to other electronic components via a conductive material, such as a metal. The source and drain may be conductive and may include heavily doped semiconductor regions, such as degenerate semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., most carriers are signals), then the FET may be called an n-type FET. If the channel is p-type (i.e., most carriers are holes), then the FET may be called a p-type FET. The channel may be end-capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, makes the channel conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0140] The descriptions herein, illustrated with reference to the accompanying drawings, depict exemplary configurations and do not represent all possible implementations or all instances within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior to" other instances. The detailed description includes specific details that provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0141] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a dash followed by a second reference numeral to differentiate similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0142] The information and signals described herein can be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof.

[0143] The various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device designed to perform the functions described herein, discrete gate or transistor logic, discrete hardware components or any combination thereof. The general-purpose processor may be a microprocessor; however, alternatively, the processor may be any processor, controller, microcontroller or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0144] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distributed implementations such that portions of the functions are implemented in different physical locations. And, as used herein, the word “or” used in the list of items included in the claims (e.g., a list of items beginning with phrases such as “at least one of” or “one or more of”) indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). And, as used herein, the phrase “based on” should not be construed as referring to a set of closing conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0145] The description herein is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for memory operations, comprising: A first count is determined at the first counter, based at least in part on refresh operations performed on the memory array of the memory device; A second count is determined at the second counter, based at least in part on the same refresh operation performed on the same memory array of the same memory device; The first count is compared with the second count at the memory device; The first count, which is at least partially based on the refresh operation, is determined to be different from the second count, which is at least partially based on the same refresh operation, based at least in part on the comparison. The indication is sent to the host device based at least in part on the determination that the first count is different from the second count; as well as The operating state of the memory device is modified at least in part based on the determination that the first count is different from the second count.

2. The method of claim 1, wherein the indication is configured to indicate to the host device that the memory device has modified the operating state to a secure state.

3. The method according to claim 1, further comprising: Determining that the difference between the first count and the second count satisfies a threshold, wherein the indication is sent to the host device at least in part based on determining that the difference between the first count and the second count satisfies the threshold.

4. The method of claim 1, wherein comparing the first count with the second count comprises: The first count is compared with the second count based on the periodic duration.

5. The method of claim 1, further comprising: The signal is received from the host device, wherein the comparison of the first count with the second count is initiated based at least in part on the signal received from the host device.

6. The method of claim 1, further comprising: Setting a field in the mode register to a value based at least in part on determining that the first count is different from the second count, wherein sending the indication includes: The indication, which is at least partially based on the value of the field of the mode register, is sent to the host device.

7. The method of claim 1, wherein transmitting the indication comprises: The instruction is sent to the host device via a data burst.

8. The method of claim 1, wherein transmitting the indication comprises: The instruction is sent to the host device via a sideband.

9. The method of claim 1, further comprising: The refresh operation is performed on the volatile memory cells of the memory array at the memory device.

10. A memory device comprising: Memory array; A first counter is configured to increment a first count based at least in part on refresh operations performed on the memory array; A second counter is configured to increment a second count based at least in part on the same refresh operation performed on the memory array; A comparator is configured to determine the difference between the first count and the second count; A transmitter configured to transmit an indication based at least in part on the difference between the first count and the second count; as well as A state controller is configured to modify the operating state of the memory device at least in part based on the difference between the first count and the second count.

11. The memory device of claim 10, wherein the indication sent by the transmitter is configured to indicate that the state controller has entered a safe state.

12. The memory device according to claim 10, wherein: The comparator is configured to determine that the difference between the first count and the second count satisfies a threshold; and The transmitter is configured to send the indication at least in part based on the difference between the first count and the second count satisfying the threshold.

13. The memory device of claim 10, wherein the comparator is configured to: The difference between the first count and the second count is determined based on the periodic duration.

14. The memory device of claim 10, further comprising: A receiver configured to receive a signal from a host device, wherein the comparator is configured to determine the difference between the first count and the second count based at least in part on the signal received from the host device.

15. The memory device of claim 10, wherein the indication transmitted by the transmitter includes the row decoding state of the memory device.

16. The memory device of claim 10, further comprising: A mode register, configured to store an operation indicator for the memory device, wherein the mode register is configured to set the value of a field at least in part based on determining the difference between the first count and the second count, and wherein, in order to send the indicator, the transmitter is configured to send an indication of the value of the field.

17. The memory device of claim 10, wherein the transmitter is configured to transmit the indication in data bursts.

18. The memory device of claim 10, wherein the transmitter is configured to transmit the indication via one or more signal paths dedicated to status signaling between the memory device and a host device.

19. The memory device of claim 10, wherein the memory array comprises a plurality of volatile memory cells.

20. A method for memory operations, comprising: Send a command to the memory device to perform a refresh operation on the memory array of the memory device; The host device receives an indication that the first count of the refresh operation of the first refresh counter of the memory device is different from the second count of the same refresh operation of the second refresh counter of the memory device. The operating state of the memory device is determined at the host device at least in part based on receiving the instruction; as well as The operating state of the host device is modified, at least in part, based on determining the operating state of the memory device.

21. The method of claim 20, further comprising: Access to the second memory device is determined at least in part based on the determination of the operating state of the memory device; as well as An access operation is performed on the second memory device at least in part based on the determination to access the second memory device.

22. The method of claim 20, further comprising: Determine that the duration associated with the operating state of the memory device satisfies a threshold. The error state of the memory device is determined at least in part based on the determination that the duration associated with the operating state of the memory device satisfies the threshold; as well as An error indication is sent, at least in part, based on the error state of the memory device.

23. The method of claim 20, further comprising: A second instruction is sent to the memory device, wherein receiving the instruction from the memory device is at least in part based on sending the second instruction.

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