A data storage system and method

Abstract

A data storage system and method. The data storage system comprises a memory (20), a controller (10) and a temperature detection circuit (30); the controller (10) is configured to set a temperature detection period of the memory (20); the temperature detection circuit (30) is configured to detect the temperature of the memory (20) according to the temperature detection period, and send detection information corresponding to the temperature to the controller (10); the controller (10) is further configured to determine a refresh frequency of the memory (20) according to the detection information; and the memory (20) is configured to be refreshed according to the refresh frequency to maintain the data stored in the memory (20).

Description

Technical Field

[0001] This application relates to the field of memory technology, and in particular to a data storage system and method. Background Technology

[0002] Memory typically stores data based on voltage levels. However, in Dynamic Random Access Memory (DRAM), the charge stored in capacitors disappears after a relatively short period, causing data corruption. Therefore, to prevent data loss, the DRAM must be refreshed periodically—that is, the data is repeatedly read out and then recharged to its initial charge level. The maximum allowable time between refresh operations is determined by the charge storage capacity of the capacitors that make up the DRAM cell array.

[0003] Currently, the DRAM refresh rate is adjusted based on the DRAM temperature. Typically, a temperature detection circuit is built into the DRAM. The desired refresh rate is adjusted based on the temperature detection results from this circuit module; generally, the higher the temperature, the higher the desired refresh rate. Specifically, the controller reads the mode register inside the DRAM to obtain the current DRAM temperature detection result and determine the corresponding desired refresh rate. For example, in High Bandwidth Memory (HBM) applications, the DRAM outputs a 3-bit result in real time to indicate the desired refresh rate.

[0004] However, the controller needs to periodically or in real-time read the mode register inside the DRAM; with more reads, the data bus is occupied more often, increasing overhead and affecting the effective memory access bandwidth of the DRAM; furthermore, the detection cycle of the temperature detection circuit cannot be flexibly adjusted. In existing HBM applications, the DRAM not only outputs the temperature detection results in real time, but the detection temperature range corresponding to the 3-bit output result cannot be adjusted; when the temperature fluctuates at the critical point of different temperature ranges (such as the critical point of 25℃ between 16℃-25℃ and 25℃-40℃), there are false sampling results, leading to multiple adjustments of the refresh frequency; and real-time output of temperature detection results will cause certain power consumption.

[0005] Therefore, how to reasonably adjust the temperature refresh frequency of the memory according to the temperature is an urgent problem to be solved. Summary of the Invention

[0006] This application provides a data storage system and method that can configure the temperature detection cycle of the memory and effectively and reasonably adjust the refresh frequency of the memory based on the acquired temperature detection results.

[0007] In a first aspect, embodiments of this application provide a data storage system, including:

[0008] The system includes a memory, a controller, and a temperature detection circuit; the controller is connected to the temperature detection circuit; and the memory is connected to the controller.

[0009] The controller is used to set the temperature detection cycle of the memory;

[0010] The temperature detection circuit is used for:

[0011] The temperature of the memory is detected according to the stated temperature detection cycle;

[0012] Send the detection information corresponding to the temperature to the controller;

[0013] The controller is also configured to set the refresh frequency of the memory based on the detection information;

[0014] The memory is used to refresh according to the refresh frequency.

[0015] This application embodiment primarily configures the temperature detection cycle of the memory through a controller, enabling the controller to acquire the memory's temperature status (e.g., the temperature range of the memory at a certain moment) at a certain period. Based on the memory's temperature status, the controller adjusts the refresh frequency of the memory. Specifically, the controller sets the temperature detection cycle of the memory; when the count value reaches the temperature detection cycle (e.g., when the cycle is 50µs, and the count value reaches the corresponding 50µs after resetting the detection cycle), the temperature detection circuit detects the current temperature of the memory and sends target detection information corresponding to the current temperature to the controller; after receiving the target detection information, the controller determines the corresponding refresh frequency to instruct the memory to refresh and maintain the stored data. In the prior art, the temperature detection cycle cannot be changed by the controller, and is usually a fixed value or real-time temperature detection, making it difficult to reasonably acquire memory temperature information; moreover, acquiring temperature information requires occupying the data bus, resulting in increased overhead. By implementing this application embodiment, not only can different temperature detection cycles be configured according to system requirements, but the energy consumption generated by real-time monitoring can also be reduced. Furthermore, by adjusting the memory refresh frequency in a timely manner based on temperature information and acquiring temperature detection results without occupying the data bus, memory access efficiency is effectively improved.

[0016] In one possible implementation, the system further includes: a counter connected to the controller; the controller is further configured to send the temperature detection cycle to the counter; the counter is configured to: cyclically count until the count value reaches the temperature detection cycle; when the count value reaches the temperature detection cycle, send a detection command to the temperature detection circuit; the temperature detection circuit is specifically configured to: when receiving the detection command, detect the temperature of the memory, and send detection information corresponding to the temperature to the controller. In this embodiment, the controller sends the set temperature detection cycle to the counter; after receiving the temperature detection cycle, the counter starts counting from an initial value (e.g., 0) until the count value (corresponding time) reaches the detection cycle value, at which point the counter triggers the temperature detection circuit to perform temperature detection. Accurately calculating the relationship between time and the set cycle through the counter's counting is beneficial for the temperature detection circuit to accurately detect the temperature according to the cycle.

[0017] In one possible implementation, the controller is further configured to send a detection command to the temperature detection circuit according to the temperature detection cycle; specifically, the temperature detection circuit is configured to detect the temperature of the memory when receiving the detection command, and send the detection information corresponding to the temperature to the controller. In this embodiment, the controller sends a detection command to the temperature detection circuit according to the temperature detection cycle. The controller integrates a cycle counting function, sending a detection command at a certain time to enable the temperature detection circuit.

[0018] In one possible implementation, the temperature detection circuit is specifically used to: determine the target temperature range of the memory, where the target temperature range is one of multiple temperature ranges managed by the temperature detection circuit; and send detection information corresponding to the target temperature range to the controller. In this embodiment, after detecting the temperature through the temperature detection circuit, and combining it with multiple preset temperature ranges, the temperature range is determined to be one of the multiple temperature ranges (e.g., a temperature range of -40 to -10℃); the target detection information corresponding to this temperature range (e.g., 000 in 3-bit temperature data) is sent to the controller. In this embodiment, by sending multiple temperature ranges as the basis for adjusting the refresh frequency, on the one hand, it conforms to the correspondence between the memory temperature and the refresh frequency (i.e., the refresh frequency is consistent within a certain temperature range of the memory, for example, the same refresh frequency applies within 20-30℃); on the other hand, since the memory lacks a sufficient number of input / output ports (i.e., I / O ports) to output specific temperature values, using output temperature ranges can reduce I / O usage and allow for adjustments to the temperature range (e.g., the number of bits corresponding to the output) to increase or decrease the use of I / O ports, adapting to specific memory configurations.

[0019] In one possible implementation, the system further includes: a register connected to the controller; the register is also connected to the temperature detection circuit; the register is used to: store a plurality of first temperature ranges corresponding to each of one or more detection information, the one or more detection information including the target detection information; the controller is further used to: determine a second temperature range matching each detection information from the plurality of first temperature ranges; the register is further used to: send the second temperature range matching each detection information to the temperature detection circuit. In this embodiment, the controller selects the second temperature range matching each detection information from the plurality of first temperature ranges stored in the register; for example, the detection information is 000 in 3-bit data, and the register stores four temperature ranges corresponding to 000 (such as -40~-10℃, -40~-15℃, -40~-5℃, and -40~0℃); the default temperature range corresponding to 000 is -40~-10℃. The temperature range corresponding to 000 can be changed through the controller, that is, the temperature range corresponding to the detection information can be configured. The temperature range can be configured for 8 types of detection information to meet the refresh requirements of different memories or different conditions of the same memory.

[0020] In one possible implementation, the detection information includes information indicating a target temperature range within which the memory's temperature falls. Specifically, the controller is configured to: determine the target temperature range based on the detection information; and determine the refresh frequency of the memory based on the target temperature range. In this embodiment, the controller obtains target detection information from a temperature detection circuit; determines the temperature range corresponding to the detection information; and determines the refresh frequency corresponding to the temperature range. This allows for the determination of different refresh frequencies to adapt to temperature changes in the memory, based on detection information within different temperature ranges.

[0021] In one possible implementation, the temperature detection circuit is specifically used to send the target detection information to the controller via a pin. In this embodiment, the target detection information is directly sent to the controller via the pin of the temperature detection circuit, avoiding bus occupancy caused by the controller reading the target temperature from the register.

[0022] In one possible implementation, the controller is further configured to send a refresh instruction to the memory according to the refresh frequency; the memory is specifically configured to: receive the refresh instruction and automatically refresh according to the refresh instruction to maintain the data stored in the memory. In this embodiment, the controller sends a refresh instruction to the memory at a determined refresh frequency to instruct the memory to refresh in a timely manner to prevent data loss.

[0023] In one possible implementation, the temperature detection cycle is 64 clock cycles, 128 clock cycles, 256 clock cycles, 512 clock cycles, 1024 clock cycles, 2048 clock cycles, or 4096 clock cycles. This application provides various cycle configurations to meet different energy consumption requirements. For example, configuring a temperature detection cycle to 4096 clock cycles, with an enable time of 8 clock cycles per detection, reduces energy consumption by 1 / 512 compared to real-time detection.

[0024] In one possible implementation, the controller is further configured to shorten the temperature detection cycle when the change in the detection information within the temperature detection cycle exceeds a preset change threshold. In this embodiment, the temperature detection cycle is adjusted to adapt to the current operating conditions of the memory based on temperature changes in the memory or system requirements.

[0025] In one possible implementation, the controller is further configured to: send one or more temperature configuration parameters to the register, the one or more temperature configuration parameters being used to determine a first temperature range matching each of the one or more detection information stored in the register. In this embodiment, the temperature configuration parameters sent by the controller to the register accurately adjust and configure the temperature range corresponding to the detection information.

[0026] Secondly, embodiments of this application provide a data storage device applied to a dynamic random access memory, comprising: a memory and a controller connected to the memory, the memory including a temperature detection circuit; the controller being configured to set a temperature detection period for the memory; the temperature detection circuit being configured to: detect the temperature of the memory when the count value reaches the temperature detection period; and send target detection information corresponding to the temperature to the controller; the controller being further configured to: determine the refresh frequency of the memory based on the target detection information; and the memory being configured to refresh according to the refresh frequency to maintain the data stored in the memory.

[0027] In one possible implementation, the memory further includes a counter connected to the temperature detection circuit; the controller is further configured to send the temperature detection cycle to the counter; the counter is configured to: cyclically count until the count value reaches the temperature detection cycle; when the count value reaches the temperature detection cycle, send a detection command to the temperature detection circuit; the temperature detection circuit is specifically configured to: when receiving the detection command, detect the temperature of the memory, and send the target detection information corresponding to the temperature to the controller.

[0028] In one possible implementation, the temperature detection circuit is specifically configured to: determine a target temperature range from one or more first temperature ranges; determine target detection information matching the target temperature range; and send the target detection information to the controller.

[0029] In one possible implementation, the memory further includes a register connected to the temperature detection circuit, configured to: store a plurality of first temperature ranges corresponding to each of one or more detection information, the one or more detection information including the target detection information; the controller is further configured to: determine a second temperature range matching each of the plurality of first temperature ranges; the register is further configured to: send the second temperature range matching each of the detection information to the temperature detection circuit.

[0030] In one possible implementation, the controller is specifically configured to: determine the target temperature range based on the detection information; and determine the refresh frequency of the memory based on the target temperature range.

[0031] In one possible implementation, the temperature detection circuit is specifically used to send the detection information to the controller via a pin.

[0032] In one possible implementation, the controller is further configured to send a refresh instruction to the memory according to the refresh frequency; the memory is specifically configured to: receive the refresh instruction and refresh the memory according to the refresh instruction to maintain the data stored in the memory.

[0033] In one possible implementation, the temperature detection cycle is 64 clock cycles, 128 clock cycles, 256 clock cycles, 512 clock cycles, 1024 clock cycles, 2048 clock cycles, or 4096 clock cycles.

[0034] In one possible implementation, the controller is further configured to shorten the temperature detection cycle when the degree of change of the detection information within the temperature detection cycle exceeds a preset change threshold.

[0035] Thirdly, embodiments of this application provide a data storage method, including: setting a temperature detection cycle for a memory, wherein the temperature detection cycle is the cycle during which a temperature detection circuit detects the temperature of the memory and sends detection information corresponding to the temperature;

[0036] The detection information is received from the temperature detection circuit according to the temperature detection cycle.

[0037] The refresh frequency of the memory is set based on the detection information.

[0038] In one possible implementation, the method further includes:

[0039] Send the temperature detection cycle to the counter;

[0040] The counter counts cyclically until the count value reaches the temperature detection cycle.

[0041] When the count value reaches the temperature detection cycle, a detection command is sent to the temperature detection circuit through the counter. The detection command is used to instruct the temperature detection circuit to detect the temperature of the memory and send the detection information corresponding to the temperature.

[0042] In one possible implementation, the method further includes:

[0043] The temperature detection circuit is instructed to send a detection command according to the temperature detection cycle; the detection command is used to instruct the temperature detection circuit to detect the temperature of the memory and send the detection information corresponding to the temperature.

[0044] In one possible implementation, the detection information includes information indicating the target temperature range of the memory, and setting the refresh frequency of the memory based on the detection information includes:

[0045] The target temperature range is determined based on the detection information;

[0046] The refresh frequency of the memory is set according to the target temperature range.

[0047] In one possible implementation, the method further includes:

[0048] A refresh instruction is sent to the memory according to the refresh frequency; the refresh instruction is used to instruct the memory to refresh.

[0049] In one possible implementation, the temperature detection cycle is 64 clock cycles, 128 clock cycles, 256 clock cycles, 512 clock cycles, 1024 clock cycles, 2048 clock cycles, or 4096 clock cycles.

[0050] In one possible implementation, the method further includes:

[0051] When the change in the detection information within the temperature detection cycle exceeds a preset change threshold, the temperature detection cycle is shortened.

[0052] In one possible implementation, receiving the detection information from the temperature detection circuit includes:

[0053] The detection information is received from the temperature detection circuit via a pin.

[0054] Fourthly, embodiments of this application provide a chip system that performs the method described in any one of the third aspects.

[0055] Fifthly, embodiments of this application provide an electronic device that may include: a data storage device as described in the first or second aspect above, and discrete devices coupled to the outside of the data storage device.

[0056] Sixthly, embodiments of this application provide a terminal including a processor configured to support the terminal in performing corresponding functions of a data storage method provided in the third aspect. The terminal may also include a memory coupled to the processor, which stores necessary program instructions and data for the terminal. The terminal may further include a communication interface for communicating with other devices or communication networks. Attached Figure Description

[0057] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below.

[0058] Figure 1 This is a schematic diagram of a data storage system architecture provided in an embodiment of this application;

[0059] Figure 2 This is a schematic diagram of another data storage system architecture provided in an embodiment of this application;

[0060] Figure 3 This application provides a method related to... Figure 2 Corresponding data storage function diagram;

[0061] Figure 4 This is a partial structural schematic diagram of a data storage device provided in an embodiment of this application;

[0062] Figure 5 This is a partial structural schematic diagram of another data storage device provided in an embodiment of this application;

[0063] Figure 6 This is a schematic diagram of the periodic detection process of a temperature detection circuit provided in an embodiment of this application;

[0064] Figure 7 This is a partial structural schematic diagram of another data storage device provided in the embodiments of this application;

[0065] Figure 8 This is a flowchart illustrating a data storage method provided in an embodiment of this application;

[0066] Figure 9 This is a schematic diagram of the structure of a device provided in an embodiment of this application. Detailed Implementation

[0067] The embodiments of this application will now be described with reference to the accompanying drawings.

[0068] The terms "first," "second," "third," and "fourth," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order; and the objects described by the terms "first," "second," "third," and "fourth," etc., may also be the same object, or may contain or otherwise relate to each other. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0069] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0070] As used in this specification, the terms "component," "module," "system," etc., are used to refer to computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. As illustrated, applications running on computing devices and computing devices can both be components. One or more components may reside in a process and / or an execution thread, and components may be located on a single computer and / or distributed among two or more computers. Furthermore, these components can be executed from various computer-readable media on which various data structures are stored. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).

[0071] It should be noted that, in the embodiments of this application, a module can be understood as a coupling of circuits or devices; the embodiments of this application do not limit this.

[0072] First, some of the terms used in this application will be explained to facilitate understanding by those skilled in the art.

[0073] (1) Dynamic Random Access Memory (DRAM) is a type of semiconductor memory. Its main operating principle is to use the amount of charge stored in a capacitor to represent whether a binary bit is 1 or 0. Due to the leakage current phenomenon of transistors, the amount of charge stored in the capacitor is insufficient to correctly identify the data, resulting in data corruption. Therefore, DRAM needs to be periodically charged to ensure that the data is stored properly.

[0074] (2) Enable can be an input pin of a chip or an input port of a circuit. Only when this pin is activated, for example, when it is set to a high level, can the entire module work normally. Enable is not just about control; it is a demand response that requires certain conditions to be met. For example, when the enable pin is low, the circuit performs the function of a NAND gate; when it is high, the circuit is in a high-impedance state. Enable has a wide range of applications. For example, digital flip-flops and counters all have an enable pin to control their operation or the operation of other components.

[0075] (3) Clock cycle, also known as oscillation cycle, is defined as the reciprocal of the clock frequency. The clock cycle is the most basic and smallest unit of time in a computer. Within one clock cycle, the CPU completes only one basic action. The clock cycle is a quantity of time. The clock cycle can represent the highest frequency that memory (such as synchronous dynamic random access memory) can operate at. A smaller clock cycle means a higher operating frequency.

[0076] (4) A bit is the smallest unit of information. It is the amount of information contained in one binary digit or the amount of information required to specifically specify one of two options. Generally speaking, n bits of information can represent 2 to the power of n choices. For example, if a computer has a word length of 16 bits, that is, 16 binary bits, then the numerical information it represents is 0-65535.

[0077] (5) Decoding is the reverse process of encoding, and it removes noise mixed in during the transmission of the bit stream. The process of using a decoding table to translate text into a series of digital codes or using a decoding table to translate a series of signals representing a certain piece of information into text is called decoding.

[0078] (6) Refreshing refers to the process of periodically charging high-potential capacitors to maintain their stability, as the capacitors used to record DRAM logic values ​​inevitably have significant leakage (discharge phenomenon) due to various technical difficulties.

[0079] (7) Registers are small storage areas used to temporarily store data and the results of calculations. They are a common type of sequential logic circuit, but such sequential logic circuits only contain storage circuits. The storage circuit of a register is composed of latches or flip-flops. Since one latch or flip-flop can store one bit of binary data, N latches or flip-flops can form an N-bit register. Registers are a component of the central processing unit. Registers are high-speed storage components with limited storage capacity; they can be used to temporarily store instructions, data, and addresses.

[0080] The following describes a system architecture upon which the embodiments of this application are based. Please refer to [link to relevant documentation]. Figure 1 , Figure 1 This is a schematic diagram of a data storage system architecture provided in an embodiment of this application; as shown... Figure 1 As shown, the system architecture includes a controller 10, a memory 20, and a temperature detection circuit 30. Optionally, the controller 10, memory 20, and temperature detection circuit 30 can be three independent logic circuits or devices; alternatively, the memory 20 can include the temperature detection circuit 30 and the controller 10; or, the memory 20 can include the temperature detection circuit 30, and the controller 10 can be an independent device separate from the memory 20; this embodiment does not limit the specific implementation.

[0081] The controller 10 is used to set the temperature detection cycle for the memory 20. Before the controller 10 configures the temperature detection cycle, the temperature detection circuit 30 can detect the temperature of the memory 20 in real time and feed back the detection information to the controller 10, or perform detection and feedback according to a preset fixed cycle. When the controller 10 sets the temperature detection cycle and the cycle is reached, it triggers the temperature detection circuit 30 (or the temperature detection circuit) to detect the temperature of the memory and feed back the corresponding detection information to the controller 10. The controller 10 adjusts the refresh frequency of the memory 20 according to the target detection information.

[0082] The memory 20 is used to store data and is automatically refreshed according to the refresh frequency set by the controller 10 (i.e., the memory performs self-refresh) to maintain the data stored in the memory.

[0083] The temperature detection circuit 30 is used to detect the temperature of the memory 20 according to the temperature detection cycle set by the controller 10, and to feed back target detection information corresponding to the detected temperature to the controller 10. The controller 10 can analyze the target detection information to obtain the corresponding temperature range, and then determine the refresh frequency based on the temperature range. Alternatively, the controller 10 can directly determine the refresh frequency based on the target detection information.

[0084] Understandable, Figure 1The system architecture described above is merely an exemplary implementation in the embodiments of this application. The system architecture in the embodiments of this application includes, but is not limited to, the above system architecture.

[0085] The following is another system architecture involved in the embodiments of this application. Please refer to... Figure 2 and Figure 3 , Figure 2 This is a schematic diagram of another data storage system architecture provided in an embodiment of this application; Figure 3 This application provides a method related to... Figure 2 Corresponding data storage function diagram; such as Figure 2 and Figure 3 As shown, the system architecture includes a memory 20 (taking DRAM as an example) and a controller 10; wherein,

[0086] The memory 20 includes a register 201, a temperature detection circuit 30, and a counter 202. The register 201 is connected to the temperature detection circuit 30; the counter 202 is also connected to the temperature detection circuit 30. Specifically, the register 201 can send multiple detection information entries and their corresponding temperature ranges to the temperature detection circuit 30 to configure the temperature detection range. When the temperature detection circuit 30 detects the current temperature of the memory 20, it determines which of the multiple temperature ranges the current temperature falls within based on the received temperature ranges. The counter 202 receives the temperature detection cycle configured by the controller. When the count value reaches the temperature detection cycle, it triggers the temperature detection circuit to perform temperature detection and feeds back the temperature result to the controller 10.

[0087] The controller 10 includes a first circuit 101, a second circuit 102, and a third circuit 103. The first circuit 101 is used to set the temperature range that matches each detection information from multiple temperature ranges stored in the register. The second circuit 102 is used to receive target detection information and determine the refresh frequency according to the target detection information. It also sends a refresh command to the temperature detection circuit according to the refresh frequency. The third circuit 103 is used to set the temperature detection cycle and send the temperature detection cycle to the counter.

[0088] Understandable, Figure 2 The system architecture described above is merely an exemplary implementation method in this application embodiment. The application scenarios in this application embodiment include, but are not limited to, the above application scenarios.

[0089] The following is in conjunction with the above. Figure 2 The system architecture shown provides a detailed analysis and solution to the technical problems raised in this application.

[0090] Please see Figure 4 , Figure 4This is a partial structural diagram of a data storage device provided in an embodiment of this application; the data storage device can be applied to data storage system architectures (including those described above). Figure 2 The system architecture shown is as follows. The data storage device includes a DRAM 20 (i.e., memory 20) and a controller 10; the controller 10 is connected to the DRAM 20. Specifically, the DRAM includes a built-in temperature detection circuit 30 and a refresh command decoding module 203; the controller 10 includes a temperature structure receiving module 104 and a refresh operation management module (i.e., the second circuit) 102.

[0091] The controller 10 is used to set the temperature detection period of the memory (i.e., the timing period shown in the figure). Specifically, the controller can adjust the temperature detection period of the memory through built-in circuitry (such as a counting circuit or a counting module). Before setting a new temperature detection period through the controller, the temperature detection period is either a preset default temperature detection period or a temperature detection period prior to the setting. Optionally, after setting a new temperature detection period through the controller, the controller can output a detection command (e.g., an enable signal) according to the temperature detection period, instructing the temperature detection circuit to perform temperature detection on the memory. For example, after receiving the detection command, the temperature detection circuit ends its sleep state and begins to detect the temperature of the memory at a preset detection frequency.

[0092] like Figure 4 As shown, the temperature detection circuit 20 outputs a 3-bit temperature result and directly sends the corresponding 3-bit interface signal to the controller via the corresponding interface. Optionally, the 3-bit interface information can be data encoded based on the 3-bit temperature result. After receiving the 3-bit interface signal sent by the DRAM through the interface or pin, the controller 10 receives and parses the interface signal through the built-in temperature result receiving module. The controller obtains the corresponding 3-bit temperature result after parsing, determines the current temperature range of the memory based on the 3-bit temperature result, and then adjusts the timing cycle according to the temperature range. The adjusted timing cycle data is sent to the refresh operation management module 102 (i.e., Figure 2 The second circuit 102 shown in the diagram sends a cycle change command containing new timing cycle data to the DRAM via the memory control interface in the controller through the refresh operation management module. When the DRAM receives the cycle change command containing the new timing cycle data, it decodes the command through the command decoding module 203. Under the new timing cycle, the built-in temperature detection circuit is controlled to detect its own temperature.

[0093] Optionally, the controller 10 is specifically configured to determine the target temperature range based on the detection information; and to determine the refresh frequency of the memory based on the target temperature range. For example, if the temperature range corresponding to the target detection information is 6–40°C, a suitable refresh frequency for the memory is determined based on this temperature range. The detection information may correspond to the specific temperature of the memory or the temperature range within which the specific temperature of the memory falls. For example, when the detection information corresponds to the specific temperature of the memory, the controller can obtain the specific temperature of the memory at a certain moment or within a certain time period through the detection information. As another example, when the detection information corresponds to the temperature range within which the memory temperature falls, the controller can determine the temperature range of the memory through the detection information, and then match it with multiple preset temperature ranges to determine the refresh frequency of the memory.

[0094] Optionally, the controller 10 is further configured to send a refresh instruction to the memory according to the refresh frequency; the memory is specifically configured to receive the refresh instruction and automatically refresh it according to the refresh instruction to maintain the data stored in the memory. For example, if a refresh frequency suitable for the current temperature is determined based on target detection information (e.g., refreshing the data stored in the memory every 5 seconds), then the data in the memory is refreshed every 5 seconds to ensure that the data is not lost.

[0095] In one possible implementation, the controller is further configured to: shorten the temperature detection cycle when the change in the target detection information within a preset number of temperature detection cycles exceeds a preset change threshold. The controller adjusts the temperature detection cycle for the memory based on system requirements or the historical temperature change trend of the DRAM. For example, in summer or high-temperature environments, shortening the temperature detection cycle ensures accurate temperature information of the memory (such as DRAM) to prevent data loss. In low-temperature environments or where memory temperature changes slowly, the temperature detection cycle can be extended (e.g., from 128 clock cycles to 512 clock cycles) to reduce device power consumption without data loss.

[0096] In one possible implementation, the device further includes a counter connected to the controller; the counter is also connected to the temperature detection circuit; the controller sends the temperature detection cycle to the counter; the counter is used to count cyclically until the count value reaches the temperature detection cycle; when the count value reaches the temperature detection cycle, a detection command is sent to the temperature detection circuit; the temperature detection circuit is specifically used to: detect the temperature of the memory when receiving the detection command, and send target detection information corresponding to the temperature to the controller. The temperature detection circuit is also used to detect the temperature of the memory when the count value reaches the temperature detection cycle; send the target detection information corresponding to the temperature to the controller; the controller is further used to determine the refresh frequency of the memory based on the target detection information; the memory is used to refresh according to the refresh frequency.

[0097] Please see Figure 5 , Figure 5 This is a partial structural schematic diagram of another data storage device provided in an embodiment of this application; as shown... Figure 5 As shown, this data storage device can be applied to data storage system architectures (including those mentioned above). Figure 1 (System architecture shown). Specifically, the controller 10 includes a counter 202, a temperature detection cycle configuration register (i.e., the third circuit) 103, and an enable control module 105; wherein, the enable control module 105 is used to control the enable of DRAM memory temperature reading; for example, the enable control module 105 updates the memory temperature enable command, instructing the memory to stop or start temperature detection. The counter 202 is built into the controller 10 and is used to time or count according to the configured time period. Optionally, the counter 202, the temperature detection cycle configuration register 103, and the enable control module 105 can be devices independent of the controller 10. The controller 10 can be connected to the DRAM through a preset memory control interface.

[0098] Alternatively, the counter 202 may be integrated into the memory or otherwise connected to the controller.

[0099] The DRAM 20 includes a temperature detection circuit 30, a temperature detection enable module 204, and a command decoding module 203. The command decoding module 203 is also used to decode commands received by the memory, thereby controlling the operation of the temperature detection enable module. Optionally, the DRAM can also decode commands through other command decoding modules; this embodiment does not limit this.

[0100] Optionally, the operating enable cycle of the DRAM temperature detection circuit is configurable; a longer detection cycle results in greater power savings. For example, the temperature detection cycle can be 64 clock cycles, 128 clock cycles, 256 clock cycles, 512 clock cycles, 1024 clock cycles, 2048 clock cycles, or 4096 clock cycles. For instance, if the controller sends cycle configuration parameter 000 to the counter (using 3-bit data as an example in this embodiment), the counter monitors the memory temperature in real time; if the controller sends cycle configuration parameter 001 to the counter, the counter checks the temperature every 64 clock cycles. Other specific cycle configuration parameters are shown in Table 1 below.

[0101] Table 1

[0102] Periodic configuration Meaning of periodic configuration 000 Real-time monitoring of DRAM temperature 001 64 clock cycles 010 128 clock cycles 011 256 clock cycles 100 512 clock cycles 101 1024 clock cycles 110 2048 * clock cycles 111 4096 * clock cycles

[0103] As shown in Table 1, if the temperature detection is configured to occur every 4096 clock cycles, and assuming the enable time for one temperature detection cycle is 8 cycles, then the power consumption introduced by temperature detection will be reduced to 1 / 512 compared to the case of real-time detection. It should be noted that the embodiments of this application do not limit the form of the cycle configuration parameters. Table 1 shows only an exemplary parameter form and meaning.

[0104] The controller configures the temperature detection period, and determines whether the configured period has been reached based on the counter's count. Upon reaching the period, the counter triggers the temperature detection circuit to perform temperature detection. Optionally, the counter sends a high-level signal (i.e., a detection command) to the temperature detection circuit, which then performs temperature detection upon receiving the high-level signal. It should be understood that the high-level signal is merely an exemplary detection command; this application does not limit the specific enabling method.

[0105] The temperature detection circuit is specifically used to determine the target temperature range of the temperature from one or more first temperature ranges; determine the target detection information matching the target temperature range; and send the target detection information (in this embodiment, the detection information is 3-bit data) to the controller. Specifically, after being enabled, the temperature detection circuit begins to detect the current temperature of the DRAM. This embodiment does not limit the specific circuit design within the temperature detection circuit or the method of temperature detection. For example, the temperature detection circuit can be composed of a comparator, a resistor divider circuit, a counter, etc. After the temperature detection circuit obtains the current temperature of the DRAM, it determines the temperature range in which the temperature falls. When only one temperature range is set, the current temperature can only correspond to that preset temperature range. When multiple temperature ranges are set, the temperature value can be used to determine which temperature range the current temperature falls within. For example, if the current DRAM temperature is detected to be 10°C, and the preset temperature range is 1–25°C, then the current temperature can be determined to be within the temperature range of 1–25°C. Optionally, the temperature detection circuit detects the DRAM temperature by detecting voltage changes in the detection circuit. This embodiment does not limit the specific method of temperature detection.

[0106] Please see Figure 6 , Figure 6 This is a schematic diagram of the periodic detection process of a temperature detection circuit provided in an embodiment of this application; as shown... Figure 6 As shown, after the controller sets the temperature detection cycle, the counter starts counting from the number of cycles received for the temperature detection cycle, until the count value reaches the corresponding number of cycles; the counter triggers the temperature detection circuit to detect the temperature; the temperature detection circuit detects the temperature and outputs the detection information (i.e., the temperature detection result) to the controller, and then disables the temperature detection circuit. Optionally, after configuring the temperature detection cycle, the counter can set an initial counting value, start counting from this initial value, and compare it with the preset number of cycles after each count to determine whether to adjust the counting cycle.

[0107] Optionally, after determining the temperature range corresponding to the current DRAM temperature, the temperature detection circuit outputs detection information matching that temperature range to the controller. For example, the detection information corresponding to 1–25°C is 001, and detection information 001 is sent to the controller. Optionally, the detection information can be 4 bits or other bit numbers of data. When the detection information is 3 bits of data, eight corresponding temperature ranges can be set. The number of bits in the detection information is set according to the actual temperature detection requirements and temperature range requirements.

[0108] It should be noted that the output result of the temperature detection circuit in this embodiment is based on the temperature range; however, this application does not limit the actual output result, that is, the temperature detection circuit can output the actual temperature value of the memory or the temperature range in which the memory temperature is located.

[0109] This application embodiment primarily configures the temperature detection cycle of the memory through a controller, enabling the controller to acquire the memory's temperature status (e.g., the temperature range of the memory at a certain moment) at a certain period. Based on the memory's temperature status, the controller adjusts the refresh frequency of the memory. Specifically, the controller sets the temperature detection cycle of the memory; when the count value reaches the temperature detection cycle (e.g., when the cycle is 50µs, and the count value reaches the corresponding 50µs after resetting the detection cycle), the temperature detection circuit detects the current temperature of the memory and sends target detection information corresponding to the current temperature to the controller; after receiving the target detection information, the controller determines the corresponding refresh frequency to instruct the memory to refresh the stored data. In the prior art, the temperature detection cycle cannot be changed by the controller, and is usually a fixed value or real-time temperature detection, making it difficult to reasonably acquire memory temperature information; moreover, acquiring temperature information requires occupying the data bus, resulting in increased overhead. By implementing this application embodiment, not only can different temperature detection cycles be configured according to system requirements, but the energy consumption generated by real-time monitoring can also be reduced. Furthermore, by adjusting the memory refresh frequency in a timely manner based on temperature information and acquiring temperature detection results without occupying the data bus, memory access efficiency is effectively improved.

[0110] In one possible implementation, the device further includes a register connected to the controller; the register is also connected to the temperature detection circuit; the register is used to store a plurality of first temperature ranges corresponding to each of one or more detection information, the one or more detection information including the target detection information; the controller is further used to determine a first temperature range matching each detection information from the plurality of first temperature ranges; the register is further used to send the first temperature range matching each detection information to the temperature detection circuit.

[0111] Please see Figure 7 , Figure 7 This is a partial structural schematic diagram of another data storage device provided in the embodiments of this application; as shown... Figure 7 As shown, this data storage device can be applied to data storage system architectures (including those mentioned above). Figure 1 or Figure 2 (The system architecture shown). Specifically,

[0112] The controller 10 includes a temperature detection configuration management module (first circuit) 101. Optionally, the controller connects the temperature range configuration management module 101 and the temperature adjustment register 201 via a configured interface. When the total detected temperature range is -40 to 125°C, the temperature adjustment register can send seven temperature parameters to the temperature detection circuit 30, such as temperature adjustment G1, temperature adjustment G2, ..., temperature adjustment G1. This embodiment takes the output of a 3-bit temperature value and the use of 2-bit temperature adjustment parameters as an example. For example, temperature adjustment G7 is 2-bit data and can include four adjustment values: 00, 01, 10, and 11. Under the aforementioned assumptions, the 2-bit temperature adjustment parameters output seven parameters for a 3-bit temperature range (i.e., including eight adjustable temperature ranges such as 000-111). This embodiment does not limit the number of bits or temperature ranges. It should be noted that the upper and lower limits of the total temperature range generally cannot be adjusted. This embodiment does not limit the upper or lower limit of the adjustable temperature range corresponding to the temperature adjustment parameters.

[0113] DRAM 20 includes a temperature adjustment register 201 and a temperature detection circuit 30. The temperature detection circuit 30 is used to output a 3-bit temperature value after temperature detection, send a 3-bit interface signal to the corresponding interface of the controller 10, or directly send the 3-bit temperature value to the controller 10. It can be understood that the controller 10 can parse the current temperature range of the DRAM based on the 3-bit interface signal, which will not be elaborated here.

[0114] Combination Figure 7 As shown in Table 2, the temperature adjustment register 201 describes the temperature range adjustment of the temperature detection circuit. The register stores eight detection information entries (000 to 111), and each entry (the output of the temperature detection circuit) corresponds to one of four alternative temperature ranges. For example, the alternative temperature ranges for 000 are -40 to -10℃, -40 to -15℃, -40 to -5℃, and -40 to 0℃. The first column represents the default temperature range, which is the temperature range matched by the detection information output by the temperature detection circuit when no temperature range is selected. For example, the default temperature range matched by 000 is -40 to -10℃. After the controller selects one of the four alternative temperature ranges for 000 (e.g., -40 to 0℃), the temperature detection circuit outputs 000 to the controller when the detected DRAM temperature falls within the -40 to 0℃ range. The controller uses the temperature configuration parameters and 000 to determine the current DRAM temperature range as -40 to 0℃, thus determining the temperature refresh frequency within this range.

[0115] It should be understood that the temperature detection circuit output results, alternative temperature ranges, and 3-bit data (e.g., 000) and 2-bit data (e.g., 01) shown in Table 2 of this application embodiment are exemplary descriptions; this application embodiment does not limit them. For example, 5-bit data corresponds to 32 types of configuration selections, which can be the configuration of temperature range, the configuration of detection period, or the configuration of detection information.

[0116] Table 2

[0117]

[0118]

[0119] In one possible implementation, the controller adjusts the temperature range corresponding to the detected information using temperature configuration parameters. As shown in Table 2, 00-11 is a part of the 2-bit temperature configuration parameters, used to select the temperature range matching the corresponding detected information. For example, the controller sends 5 bits of data (such as 00011) to the register. The first 3 bits are used to determine that the detected information is 000 among the 8 types of detected information stored in the register; the last 2 bits (i.e., 11) are used to determine that the temperature range corresponding to the detected information 000 is -40 to 0℃.

[0120] In one possible implementation, the temperature detection circuit is specifically used to send the target detection information to the controller via a pin. For example, the pin responsible for outputting the detection information of the temperature detection circuit is directly connected to the input pin of the controller, and after the temperature detection circuit obtains the detection information, it outputs the detection information to the controller directly via the pin instead of through a bus.

[0121] In the aforementioned system and apparatus, this application embodiment uses DRAM as an example for data storage device. The DRAM includes: a memory (i.e., a memory array), and a controller connected to the memory. The memory includes a temperature detection circuit. The controller is configured to set a temperature detection cycle for the memory. The temperature detection circuit is configured to: detect the temperature of the memory when the count value reaches the temperature detection cycle; and send target detection information corresponding to the temperature to the controller. The controller is further configured to: determine the refresh frequency of the memory based on the target detection information. The memory is configured to refresh according to the refresh frequency to maintain the data stored in the memory.

[0122] In one possible implementation, the memory further includes a counter connected to the temperature detection circuit; the controller is further configured to send the temperature detection cycle to the counter; the counter is configured to: cyclically count until the count value reaches the temperature detection cycle; when the count value reaches the temperature detection cycle, send a detection command to the temperature detection circuit; the temperature detection circuit is specifically configured to: when receiving the detection command, detect the temperature of the memory, and send the target detection information corresponding to the temperature to the controller.

[0123] In one possible implementation, the temperature detection circuit is specifically configured to: determine a target temperature range from one or more first temperature ranges; determine target detection information matching the target temperature range; and send the target detection information to the controller.

[0124] In one possible implementation, the memory further includes a register connected to the temperature detection circuit, configured to: store a plurality of first temperature ranges corresponding to each of one or more detection information, the one or more detection information including the target detection information; the controller is further configured to: determine a first temperature range matching each detection information from the plurality of first temperature ranges; the register is further configured to: send the first temperature range matching each detection information to the temperature detection circuit.

[0125] In one possible implementation, the controller is specifically configured to: determine the target temperature range based on the target detection information; and determine the refresh frequency of the memory based on the target temperature range.

[0126] In one possible implementation, the temperature detection circuit is specifically used to send the target detection information to the controller via a pin.

[0127] In one possible implementation, the controller is further configured to send a refresh instruction to the memory according to the refresh frequency; the memory is specifically configured to: receive the refresh instruction and refresh the memory according to the refresh instruction to maintain the data stored in the memory.

[0128] In one possible implementation, the temperature detection cycle is 64 clock cycles, 128 clock cycles, 256 clock cycles, 512 clock cycles, 1024 clock cycles, 2048 clock cycles, or 4096 clock cycles.

[0129] In one possible implementation, the controller is further configured to: shorten the temperature detection cycle when the change in the target detection information within a preset number of temperature detection cycles exceeds a preset change threshold.

[0130] The specific data storage devices and application scenarios have been described above. The method embodiments involved in this application are described below.

[0131] Please see Figure 8 , Figure 8 This is a schematic flowchart illustrating a data storage method provided in an embodiment of this application; the data storage method is applied to a data storage system (including the system architecture described above). The data storage system includes a controller, a memory, and a temperature detection circuit, which will be discussed below in conjunction with the attached diagram. Figure 8 Described from the perspective of the controller alone, the method may include the following steps S801-S803.

[0132] Step S801: Set the temperature detection cycle for the memory.

[0133] Specifically, the controller sets a temperature detection cycle for detecting the memory temperature by sending instructions to the memory. The temperature detection cycle is the period during which the temperature detection circuit detects the memory temperature and sends the corresponding target detection information.

[0134] In one possible implementation, setting the temperature detection cycle for the memory includes: sending the temperature detection cycle to a counter; counting cyclically with the counter until the count value reaches the temperature detection cycle; and sending a detection command to the temperature detection circuit through the counter, the detection command being used to instruct the temperature detection circuit to send the target detection information.

[0135] Step S802: When the count value reaches the temperature detection cycle, the target detection information is received from the temperature detection circuit.

[0136] Specifically, when the corresponding temperature detection cycle is reached, the controller receives target detection information (or temperature detection result information) from the temperature detection circuit. This application embodiment does not limit this.

[0137] Step S803: Determine the refresh frequency of the memory based on the target detection information.

[0138] Specifically, the controller parses the received target detection information and determines, based on the target detection information, that the current temperature range of the memory belongs to a certain range within a preset temperature range; and determines the refresh frequency of the memory based on this temperature range; wherein, the refresh frequency is the frequency at which the memory is refreshed.

[0139] In one possible implementation, the method further includes: determining a first temperature range that matches each detection information from a plurality of first temperature ranges stored in a register; and sending the first temperature range that matches each detection information to the temperature detection circuit through the register.

[0140] In one possible implementation, determining the refresh frequency of the memory based on the target detection information includes: determining the target temperature range based on the target detection information; and determining the refresh frequency of the memory based on the target temperature range.

[0141] In one possible implementation, receiving the target detection information from the temperature detection circuit includes: receiving the target detection information from the temperature detection circuit via a pin.

[0142] In one possible implementation, the method further includes: sending a refresh instruction to the memory according to the refresh frequency; the refresh instruction is used to instruct the memory to refresh in order to maintain the stored data.

[0143] In one possible implementation, the temperature detection cycle is 64 clock cycles, 128 clock cycles, 256 clock cycles, 512 clock cycles, 1024 clock cycles, 2048 clock cycles, or 4096 clock cycles.

[0144] In one possible implementation, the method further includes: shortening the temperature detection cycle when the change in the target detection information within a preset number of temperature detection cycles exceeds a preset change threshold.

[0145] This application embodiment primarily configures the temperature detection cycle of the memory through a controller, enabling the controller to acquire the memory's temperature status (e.g., the temperature range of the memory at a certain moment) at a certain period. Based on the memory's temperature status, the controller adjusts the refresh frequency of the memory. Specifically, the controller sets the temperature detection cycle of the memory; when the count value reaches the temperature detection cycle (e.g., when the cycle is 50µs, and the count value reaches the corresponding 50µs after resetting the detection cycle), the temperature detection circuit detects the current temperature of the memory and sends target detection information corresponding to the current temperature to the controller; after receiving the target detection information, the controller determines the corresponding refresh frequency to instruct the memory to refresh and maintain the stored data. In the prior art, the temperature detection cycle cannot be changed by the controller, and is usually a fixed value or real-time temperature detection, making it difficult to reasonably acquire memory temperature information; moreover, acquiring temperature information requires occupying the data bus, resulting in increased overhead. By implementing this application embodiment, not only can different temperature detection cycles be configured according to system requirements, but the energy consumption generated by real-time monitoring can also be reduced. Furthermore, by adjusting the memory refresh frequency in a timely manner based on temperature information and acquiring temperature detection results without occupying the data bus, memory access efficiency is effectively improved.

[0146] It should be noted that the data storage method described in the embodiments of this application can be found in the above-mentioned... Figures 4-6 The description of the data storage device in the device embodiments described herein will not be repeated here.

[0147] like Figure 9 As shown, Figure 9 This is a schematic diagram of the structure of a device provided in an embodiment of this application. The data storage device can be... Figure 9 The device 90 is implemented using the structure described above, and includes at least one processor 901 and at least one memory 902. In addition, the device may also include general-purpose components such as a power supply, which will not be detailed here.

[0148] Processor 901 may be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits used to control the execution of programs in the above scheme.

[0149] The memory 902 may be a read-only memory (ROM) or other type of static storage device capable of storing static information and instructions, random access memory (RAM) or other type of dynamic storage device capable of storing information and instructions, or electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited thereto. The memory may exist independently and be connected to the processor via a bus. The memory may also be integrated with the processor.

[0150] The memory 902 stores the application code for executing the above scheme, and its execution is controlled by the processor 901. The processor 901 executes the application code stored in the memory 902.

[0151] Figure 9 When the device shown is a data storage device (such as DRAM), the code stored in memory 902 can execute the above. Figure 8 The provided data storage method, for example, involves setting a temperature detection cycle for the memory, whereby the temperature detection circuit detects the temperature of the memory and sends target detection information corresponding to that temperature. When a count value reaches the temperature detection cycle, the target detection information is received from the temperature detection circuit. Based on the target detection information, the refresh frequency of the memory is determined, whereby the refresh frequency is the frequency at which the memory refreshes data. In this embodiment, the hardware parsing circuit built into the memory can analyze relevant instructions sent by the controller. The controller inputs instructions into the memory, and the memory parses the instructions through a corresponding hardware parsing circuit (i.e., a command parsing circuit), thereby completing the refresh operation and the temperature detection operation. This embodiment does not limit the specific connection relationship between the device 90, the controller 901, and the memory 902.

[0152] It should be noted that the functions of the device 90 described in this embodiment are the same as those described above. Figures 4-6 The relevant descriptions in the device embodiments described herein will not be repeated here.

[0153] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0154] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0155] In the several embodiments provided in this application, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical or other forms.

[0156] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0157] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0158] If the integrated units described above are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which can be a personal computer, server, or network device, specifically a processor in the computer device) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium may include various media capable of storing program code, such as a USB flash drive, portable hard drive, magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM).

[0159] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A data storage system, characterized in that, include: The system includes a memory, a controller, and a temperature detection circuit, wherein the memory is a dynamic random access memory (DRAM). The controller is used to set the temperature detection cycle of the memory based on the requirements of the storage system; The temperature detection circuit is used for: The temperature of the memory is detected according to the stated temperature detection cycle; The detection information corresponding to the temperature is sent to the controller via a pin; The controller is further configured to set the refresh frequency of the memory based on the detection information; and send a refresh command to the memory based on the refresh frequency. The memory is used to receive the refresh instruction and refresh the memory according to the refresh instruction.

2. The system according to claim 1, characterized in that, The system also includes a counter; The controller is also used for: The temperature detection cycle is sent to the counter; The counter is used for: The counting continues until the count value reaches the stated temperature detection cycle; When the count value reaches the temperature detection cycle, a detection command is sent to the temperature detection circuit; The temperature detection circuit is specifically used for: When the detection command is received, the temperature of the memory is detected, and the detection information corresponding to the temperature is sent to the controller.

3. The system according to claim 1, characterized in that, The controller is also used for: Send a detection command to the temperature detection circuit according to the temperature detection cycle; The temperature detection circuit is specifically used for: When the detection command is received, the temperature of the memory is detected, and the detection information corresponding to the temperature is sent to the controller.

4. The system according to any one of claims 1-3, characterized in that, The temperature detection circuit is specifically used for: Determine the target temperature range in which the temperature of the memory is located, wherein the target temperature range is one of multiple temperature ranges managed by the temperature detection circuit; Send the detection information corresponding to the target temperature range to the controller.

5. The system according to any one of claims 1-3, characterized in that, The detection information includes information indicating the target temperature range within which the memory's temperature falls; the controller is specifically configured to: The target temperature range is determined based on the detection information; The refresh frequency of the memory is determined based on the target temperature range.

6. The system according to any one of claims 1-3, characterized in that, The temperature detection cycle is 64 clock cycles, 128 clock cycles, 256 clock cycles, 512 clock cycles, 1024 clock cycles, 2048 clock cycles, or 4096 clock cycles.

7. The system according to any one of claims 1-3, characterized in that, The controller is also used for: When the change in the detection information within the temperature detection cycle exceeds a preset change threshold, the temperature detection cycle is shortened.

8. A data storage method, characterized in that, The system is applied to a data storage system, which includes a memory and a temperature detection circuit, wherein the memory is a dynamic random access memory (DRAM). The method includes: Based on the requirements of the storage system, the temperature detection cycle of the memory is set. The temperature detection cycle is the cycle in which the temperature detection circuit detects the temperature of the memory and sends the detection information corresponding to the temperature. According to the temperature detection cycle, the detection information is received from the temperature detection circuit via a pin; The refresh frequency of the memory is set according to the detection information, and a refresh command is sent to the memory according to the refresh frequency; the refresh command is used to instruct the memory to refresh.

9. The method according to claim 8, characterized in that, The method further includes: Send the temperature detection cycle to the counter; The counter counts cyclically until the count value reaches the temperature detection cycle. When the count value reaches the temperature detection cycle, a detection command is sent to the temperature detection circuit through the counter. The detection command is used to instruct the temperature detection circuit to detect the temperature of the memory and send the detection information corresponding to the temperature.

10. The method according to claim 8, characterized in that, The method further includes: The temperature detection circuit is instructed to send a detection command according to the temperature detection cycle; the detection command is used to instruct the temperature detection circuit to detect the temperature of the memory and send the detection information corresponding to the temperature.

11. The method according to any one of claims 8-10, characterized in that, The detection information includes information indicating the target temperature range of the memory, and setting the refresh frequency of the memory based on the detection information includes: The target temperature range is determined based on the detection information; The refresh frequency of the memory is set according to the target temperature range.

12. The method according to any one of claims 8-10, characterized in that, The temperature detection cycle is 64 clock cycles, 128 clock cycles, 256 clock cycles, 512 clock cycles, 1024 clock cycles, 2048 clock cycles, or 4096 clock cycles.

13. The method according to any one of claims 8-10, characterized in that, The method further includes: When the change in the detection information within the temperature detection cycle exceeds a preset change threshold, the temperature detection cycle is shortened.

14. A chip system, characterized in that, The chip system performs the method as described in any one of claims 8-13.

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