Semiconductor device and method of manufacturing the same

Abstract

The embodiment of the present disclosure provides a semiconductor device, comprising: a substrate; a stack layer arranged above the substrate and alternately stacked by insulating layers and gate layers, the stack layer being divided into a transition channel pillar region and a virtual channel pillar region beside the transition channel pillar region along a first lateral direction parallel to the substrate; a transition channel pillar array and a virtual channel pillar array formed in the stack layer and respectively located in the transition channel pillar region and the virtual channel pillar region, the transition channel pillar array and the virtual channel pillar array respectively comprising a plurality of transition channel pillars and a plurality of virtual channel pillars arranged in an array in a first lateral direction and a second lateral direction perpendicular to the first lateral direction; and a gate slot formed in the stack layer and extending along the second lateral direction and arranged between the transition channel pillar array and the virtual channel pillar array.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] Memory is a storage device used in modern information technology to store information. As the demand for integration and data storage density in various electronic devices continues to increase, ordinary two-dimensional storage devices are increasingly unable to meet the requirements. Under these circumstances, three-dimensional (3D) memory has emerged.

[0003] In the fabrication of three-dimensional memory, a stacked structure is mainly formed on a substrate, and the stacked structure is divided into a core region and a stair-step region in the plane of the substrate. Several channel holes (CH) are set in the core region and the stair-step region, and the corresponding materials are filled to realize the storage function and the support function.

[0004] In current technology, to reduce manufacturing complexity, the channel vias for the memory region are fabricated first, followed by the channel vias for the step region. However, since the channel vias for the memory region are etched and filled first, charge is stored within them. When the channel vias for the step region are etched, the charge in the memory region channel vias exerts an attractive force on the step region channel vias, causing deformation of the step region channel vias. This deformation can lead to leakage current in the semiconductor device, affecting its performance. Summary of the Invention

[0005] To address the aforementioned problems, this disclosure provides a semiconductor device, the semiconductor device comprising:

[0006] Substrate;

[0007] A stacked layer is disposed above the substrate and is formed by alternating layers of insulating layer and gate layer. The stacked layer is divided into a transition channel pillar region and a virtual channel pillar region located next to the transition channel pillar region along a first lateral direction parallel to the substrate.

[0008] A transition channel pillar array is formed in the stacked layer and located in the transition channel pillar region, and includes a plurality of transition channel pillars arranged in an array in the first transverse direction and in the second transverse direction parallel to the substrate and perpendicular to the first transverse direction.

[0009] A virtual channel column array is formed in the stacked layer and located in the virtual channel column region, and includes a plurality of virtual channel columns arranged in an array in the first transverse and the second transverse directions;

[0010] A gate spacer is formed in the stacked layer and extends along the second lateral direction, and is disposed between the transition channel pillar array and the virtual channel pillar array.

[0011] In some embodiments, the virtual channel pillars are disposed in the stepped area formed by the stacked layers.

[0012] In some embodiments, the gate spacers include a plurality of gates arranged along the first lateral spacing, and the arrangement density gradually decreases from the transition channel pillar array toward the virtual channel pillar array.

[0013] In some embodiments, the gate spacers include a plurality of them and are arranged along the second lateral spacing in a dashed shape.

[0014] In some embodiments, the semiconductor device further includes a gate line slit that extends through the stacked layer in a longitudinal direction perpendicular to the substrate and extends along the first lateral direction.

[0015] In some embodiments, the gate spacer is made of the same material as the gate wire slit.

[0016] In some embodiments, the cross-sectional shape of the gate spacer in the first lateral direction includes at least one of a rectangle, a trapezoid, and a semicircle, and the side of the gate spacer facing the virtual channel pillar array is a plane.

[0017] In some embodiments, the arrangement density of the transition channel columns in the transition channel column array gradually decreases along the first transverse direction towards the virtual channel column region.

[0018] In some embodiments, the transition channel posts have a critical dimension, which is the distance from the center of the transition channel post to the edge of the transition channel post, and the critical dimension of the plurality of transition channel posts gradually increases along the first lateral direction toward the virtual channel post region.

[0019] On the other hand, this disclosure also provides a method for fabricating a semiconductor device, the method comprising:

[0020] Provide substrate;

[0021] A stacked layer is provided, which is disposed above the substrate and is formed by alternating layers of insulating layer and gate layer. The stacked layer is divided into a transition channel pillar region and a virtual channel pillar region located next to the transition channel pillar region along a first lateral direction parallel to the substrate.

[0022] A transition channel pillar array is provided, the transition channel pillar array being formed in the stacked layer and located in the transition channel pillar region, and including a plurality of transition channel pillars arranged in an array in a first lateral direction and in a second lateral direction parallel to the substrate and perpendicular to the first lateral direction;

[0023] A virtual channel column array is provided, the virtual channel column array being formed in the stacked layer and located in the virtual channel column region, and including a plurality of virtual channel columns arranged in an array in the first transverse and the second transverse directions;

[0024] A gate spacer is provided, which is formed in the stacked layer and extends along the second lateral direction, and is disposed between the transition channel pillar array and the virtual channel pillar array.

[0025] The beneficial effects of this disclosure are as follows: This disclosure provides a semiconductor device, including: a substrate; a stacked layer disposed above the substrate and formed by alternating layers of insulating layer and gate layer; the stacked layer is divided into a transition channel pillar region and a virtual channel pillar region located next to the transition channel pillar region along a first transverse direction parallel to the substrate; a transition channel pillar array and a virtual channel pillar array formed in the stacked layer and respectively located in the transition channel pillar region and the virtual channel pillar region; the transition channel pillar array and the virtual channel pillar array respectively include a plurality of transition channel pillars and a plurality of virtual channel pillars arranged in an array in the first transverse direction and in a second transverse direction perpendicular to the first transverse direction; and a gate spacer formed in the stacked layer and extending along the second transverse direction and disposed between the transition channel pillar array and the virtual channel pillar array. The semiconductor device provided by this disclosure, by providing a gate spacer between the transition channel pillar array and the virtual channel pillar array, effectively avoids the problem of deformation of the virtual channel pillars due to the attraction of the charge in the transition channel pillars to the virtual channel pillars, resulting in leakage current in the semiconductor device and affecting the performance of the semiconductor device. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the description of the various embodiments based on the embodiments of this disclosure will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a top view of a semiconductor device provided in the first embodiment according to the present disclosure.

[0028] Figure 2 This is a front view structural schematic diagram of a semiconductor device provided according to the first embodiment of the present disclosure.

[0029] Figure 3 This is a schematic flowchart of a method for fabricating a semiconductor device according to a first embodiment of the present disclosure.

[0030] Figure 4 This is a top view of a semiconductor device provided in a second embodiment based on the present disclosure.

[0031] Figure 5 This is a front view structural schematic diagram of a semiconductor device provided according to a second embodiment of the present disclosure. Detailed Implementation

[0032] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of the embodiments of this disclosure.

[0033] In the description of the embodiments of this disclosure, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing the embodiments of this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the embodiments of this disclosure. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of the embodiments of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.

[0034] In the description of the embodiments of this disclosure, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows for mutual communication; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this disclosure according to the specific circumstances.

[0035] In embodiments of this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0036] The following disclosure provides many different implementations or examples for carrying out different structures of the embodiments of this disclosure. To simplify the disclosure of the embodiments of this disclosure, components and arrangements of specific examples are described below. Of course, these are merely examples and are not intended to limit the embodiments of this disclosure. Furthermore, reference numerals and / or reference letters may be repeated in different examples of the embodiments of this disclosure; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in the embodiments of this disclosure, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0037] This disclosure addresses the problem that existing semiconductor devices suffer from leakage current due to the deformation of the stepped channel pillars caused by the attraction of the channel pillars in the memory region, which affects the performance of the semiconductor device. The embodiments of this disclosure are used to solve this problem.

[0038] Please see Figure 1 as well as Figure 2 , Figure 1 This is a top view of the semiconductor device 100 provided in the first embodiment according to the present disclosure. Figure 2 This is a front view of a semiconductor device 100 provided in the first embodiment according to the present disclosure. The front view is as follows: Figure 1 The top view of the structure shown is a cross-sectional view along aa'. From the figure, the components of the embodiment made according to the present disclosure and the relative positional relationship of the components can be seen very intuitively.

[0039] like Figure 1 as well as Figure 2 As shown, the semiconductor device 100 includes a substrate 110, a stacked layer 120, a channel pillar array 130, a virtual channel pillar array 140, a gate spacer 150, and a dielectric layer 170 disposed above the stacked layer 120, wherein:

[0040] The substrate 110 may be a semiconductor substrate, specifically including at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art;

[0041] A stacked layer 120 is disposed above a substrate 110 and is formed by alternating layers of an insulating layer 121 and a gate layer 122. The insulating layer 121 is made of an insulating material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. The gate layer 122 is made of a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped silicon, silicide, or combinations thereof. In some embodiments, the stacked layer 120 is divided along a first transverse direction X1 parallel to the substrate 110 into a channel pillar region A1 and a virtual channel pillar region A2 located next to the channel pillar region A1.

[0042] The channel pillar array 130 is formed in the stacked layer 120 and located in the channel pillar region A1, and includes a plurality of transition channel pillars 131 and storage channel pillars 132 arranged in an array on a first transverse X1 and a second transverse X2 parallel to the substrate 110 and perpendicular to the first transverse X1.

[0043] In some embodiments, a functional layer and a channel layer are sequentially formed on the inner walls of the transition channel post 131 and the storage channel post 132. However, the transition channel post 131 only serves a supporting function and does not perform a storage function, while the storage channel post 132 performs a storage function. For example, the storage channel post 132 is connected to an external circuit to receive control signals from the external circuit to realize the storage function. The functional layer includes a stacked tunneling dielectric layer, a charge storage layer, and a gate dielectric layer. Exemplary materials for the gate dielectric layer and the tunneling dielectric layer are silicon oxide, silicon nitride, an insulating material with a high insulating constant, or a combination of the above materials. Exemplary materials for the charge storage layer are silicon nitride, silicon oxynitride, silicon, or a combination of the above materials.

[0044] This application does not limit the material filled in the transition channel post 131. In some embodiments, the material filled in the transition channel post 131 may be filled together with the functional layer and channel layer filled in the storage channel post 132. For example, the functional layer filled in the transition channel post 131 and the functional layer filled in the storage channel post 132 may be completed in the same or multiple process steps, and the channel layer filled in the transition channel post 131 and the channel layer filled in the storage channel post 132 may also be completed in the same or multiple process steps. In other embodiments, the material filled in the transition channel post 131 may be different from the material filled in the storage channel post 132. For example, the material filled in the transition channel post 131 may be silicon dioxide or other insulating materials, while the material filled in the storage channel post 132 may be the functional layer and channel layer.

[0045] In some other embodiments of this application, the channel post region A1 may include a storage channel post 132, which may be adjacent to the gate partition 150.

[0046] In some embodiments, the transition channel post 131 is located between the storage channel post 132 and the virtual channel post 141, and the critical dimension of the transition channel post 131 is larger than the critical dimension of the storage channel post 132. The critical dimension of the transition channel post 131 can be the distance from its center to its edge, and the critical dimension of the storage channel post 132 can be the distance from its center to its edge. The larger critical dimension of the transition channel post 131 provides a larger support area, thereby improving support for the semiconductor device.

[0047] A virtual channel pillar array 140 is formed in the stacked layer 120 and located in the virtual channel pillar region A2, and includes a plurality of virtual channel pillars 141 arranged in an array on the first horizontal direction X1 and the second horizontal direction X2. Specifically, the plurality of virtual channel pillars 141 are disposed in the stepped region formed by the stacked layer 120. In some embodiments, the virtual channel pillars 141 serve a supporting function, and specifically, the material filled in the virtual channel pillars 141 may be silicon dioxide or other insulating materials.

[0048] Gate partition 150 is formed in stacked layer 120 and extends along second lateral X2, and is disposed between channel pillar array 130 and virtual channel pillar array 140. Specifically, gate partition 150 is located in virtual channel pillar region A2.

[0049] In some embodiments, such as Figure 2 As shown, the gate spacer 150 includes a plurality of gates and is arranged at intervals along the first transverse direction X1, and the arrangement density gradually decreases from the channel pillar array 130 to the virtual channel pillar array 140.

[0050] In some embodiments, the cross-sectional shape of the gate spacer 150 in the first transverse direction X1 includes at least one of a rectangle, a trapezoid, and a semicircle, and the cross-sectional shape is close to the channel pillar region A1, and the side of the gate spacer 150 facing the virtual channel pillar array 140 is a plane. In this embodiment, as shown... Figure 1 As shown, the gate spacer 150 has a rectangular cross-sectional shape on the first horizontal direction X1.

[0051] In some embodiments, please continue reading Figure 1 ,like Figure 1 As shown, the semiconductor device 100 also includes a gate line slit 160, which extends through the stacked layer 120 along a longitudinal direction perpendicular to the substrate 110 and extends along a first transverse direction X1. The gate spacer 150 is made of the same material as the gate line slit 160. Exemplary materials for the gate spacer 150 and the gate line slit 160 are polysilicon and tungsten.

[0052] In this embodiment, because the gate spacer 150 separates the channel pillar array 130 from the virtual channel pillar array 140, and the two sides facing the channel pillar array 130 and the virtual channel pillar array 140 are complete planes, this design can better resist the attraction of the charge in the functional layer of the transition channel pillar 131 on the gate spacer 150 and the virtual channel pillar 141, thereby avoiding the deformation of the gate spacer 150 and the virtual channel pillar 141, preventing leakage current from the semiconductor device 100, and improving the performance of the semiconductor device 100.

[0053] In some embodiments, in order to prevent abrupt changes in the attraction of charges in the functional layer of the transition channel pillar 131, in this embodiment, the arrangement density of the transition channel pillars 131 in the channel pillar array 130 gradually decreases along the first transverse direction X1 towards the virtual channel pillar region A2, and the transition channel pillar 131 has a critical dimension CD, which is the distance from the center of the transition channel pillar 131 to the edge of the transition channel pillar 131, and the critical dimension CD of the multiple transition channel pillars 131 gradually increases along the first transverse direction X1 towards the virtual channel pillar region A2.

[0054] Please see Figure 3 , Figure 3 This is a schematic flowchart of a method for fabricating a semiconductor device 100 according to a first embodiment of the present disclosure.

[0055] like Figure 3 As shown, and please refer to Figure 1 as well as Figure 2 The labeling of each component constituting the semiconductor device 100 is provided in the text. The fabrication method specifically includes:

[0056] Substrate provision step S101: Provide substrate 110;

[0057] Step S102: Provide a stacked layer 120. The stacked layer 120 is disposed above the substrate 110 and is formed by alternating layers of insulating layer 121 and gate layer 122. The stacked layer 120 is divided into a transition channel pillar region A1 and a virtual channel pillar region A2 located next to the transition channel pillar region A1 along a first transverse direction X1 parallel to the substrate 110.

[0058] Step S103: A transition channel pillar array 130 is provided, which is formed in the stacked layer 120 and located in the transition channel pillar region A1, and includes a plurality of transition channel pillars 131 arranged in an array on a first transverse X1 and a second transverse X2 that is parallel to the substrate 110 and perpendicular to the first transverse X1.

[0059] Step S104: Provide a virtual channel pillar array 140, which is formed in the stack layer 120 and located in the virtual channel pillar region A2, and includes a plurality of virtual channel pillars 141 arranged in an array on the first horizontal X1 and the second horizontal X2.

[0060] Gate partition provision step S105: Provide gate partition 150, which is formed in stacked layer 120 and extends along the second transverse X2, and is disposed between transition channel pillar array 130 and virtual channel pillar array 140.

[0061] Unlike existing technologies, this disclosure provides a semiconductor device 100, including: a substrate 110; a stacked layer 120 disposed above the substrate 110 and formed by alternating layers of an insulating layer 121 and a gate layer 122; the stacked layer 120 is divided along a first horizontal direction X1 parallel to the substrate 110 into a channel pillar region A1 and a virtual channel pillar region A2 located next to the channel pillar region A1; a channel pillar array 130 and a virtual channel pillar array 140 formed in the stacked layer 120 and respectively located in the channel pillar region A1 and the virtual channel pillar region A2; and the channel pillar array 130 and the virtual channel pillar array 140 are respectively included in the first horizontal direction X1 and in a direction perpendicular to the first horizontal direction X1. The semiconductor device 100 provided in this embodiment of the present disclosure has a plurality of transition channel pillars 131 and a plurality of virtual channel pillars 141 arranged in an array on the second horizontal X2, and a gate spacer 150 formed in the stacked layer 120 and extending along the second horizontal X2 and disposed between the channel pillar array 130 and the virtual channel pillar array 140. By providing a gate spacer 150 between the channel pillar array 130 and the virtual channel pillar array 140, the semiconductor device 100 effectively avoids the problem of leakage current caused by the attraction of the charge in the transition channel pillars 131 to the virtual channel pillars 141, which would deform the virtual channel pillars 141 and affect the performance of the semiconductor device 100.

[0062] Please see Figure 4 as well as Figure 5 , Figure 4 This is a top view of the semiconductor device 200 provided in the second embodiment according to the present disclosure. Figure 5 This is a front view schematic diagram of a semiconductor device provided according to a second embodiment of the present disclosure. The front view schematic diagram is as follows: Figure 4 The top view of the structure shown is a cross-sectional view along bb'. From the figure, the components of the embodiment made according to the present disclosure and the relative positional relationship of the components can be seen very intuitively.

[0063] like Figure 4As shown, the second embodiment has a structure that is largely the same as the first embodiment. Specifically, the substrate 210 in the second embodiment has the same function and location as the substrate 110 in the first embodiment; the stacked layer 220 in the second embodiment (including alternately stacked insulating layers 221 and gate layers 222) has the same function and location as the stacked layer 120 in the first embodiment (including alternately stacked insulating layers 121 and gate layers 122); and the channel pillar array 230 in the second embodiment (including multiple transition channel pillars 231 and multiple memory channel pillars 232) has the same function and location as the channel pillar array 230 in the first embodiment. The channel pillar array 130 (including multiple transition channel pillars 131 and multiple memory channel pillars 132) has the same function and location as the first embodiment; the virtual channel pillar array 240 (including multiple virtual channel pillars 241) in the second embodiment has the same function and location as the virtual channel pillar array 140 (including multiple virtual channel pillars 141) in the first embodiment; the gate line slot 260 in the second embodiment has the same function and location as the gate line slot 160 in the first embodiment; the dielectric layer 270 in the second embodiment has the same function and location as the dielectric layer 170 in the first embodiment. The difference lies in the arrangement of the gate spacer 250 in this embodiment, which differs from the arrangement of the gate spacer 150 in the first embodiment. In this embodiment, as shown... Figure 4 As shown, the gate spacer 250 includes a plurality of spaces and is arranged at intervals along the second transverse direction X2 in a dashed shape.

[0064] Unlike existing technologies, this disclosure provides a semiconductor device 200, including: a substrate 210; a stacked layer 220 disposed above the substrate 210 and formed by alternating layers of an insulating layer 221 and a gate layer 222; the stacked layer 220 is divided along a first horizontal direction X1 parallel to the substrate 210 into a channel pillar region B1 and a virtual channel pillar region B2 located next to the channel pillar region B1; a channel pillar array 230 and a virtual channel pillar array 240 formed in the stacked layer 220 and respectively located in the channel pillar region B1 and the virtual channel pillar region B2; and the channel pillar array 230 and the virtual channel pillar array 240 are respectively included in the first horizontal direction X1 and in a direction perpendicular to the first horizontal direction X1. The semiconductor device 200 provided in this embodiment of the present disclosure has a plurality of transition channel pillars 231 and a plurality of virtual channel pillars 241 arranged in an array on the second horizontal X2, and a gate spacer 250 formed in the stacked layer 220 and extending along the second horizontal X2 and disposed between the channel pillar array 230 and the virtual channel pillar array 240. By providing a gate spacer 250 between the channel pillar array 230 and the virtual channel pillar array 240, the semiconductor device 200 effectively avoids the problem of leakage current in the semiconductor device 200 caused by the attraction of the charge in the transition channel pillars 231 to the virtual channel pillars 241, which would deform the virtual channel pillars 241 and affect the performance of the semiconductor device 200.

[0065] In addition to the embodiments described above, other implementation methods may be provided in this disclosure. All technical solutions formed by equivalent substitutions or equivalent replacements fall within the protection scope claimed by this disclosure.

[0066] In summary, although the preferred embodiments have been disclosed above, the above preferred embodiments are not intended to limit the embodiments of this disclosure. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the embodiments of this disclosure. Therefore, the protection scope of the embodiments of this disclosure shall be determined by the scope defined in the claims.

Claims

1. A semiconductor device, the semiconductor device comprising: A stacked layer is formed by alternating layers of insulating layers and gate layers, the stacked layer extending along a first lateral direction perpendicular to the stacking direction and a second lateral direction perpendicular to the stacking direction; the first lateral direction and the second lateral direction are perpendicular to each other. A channel post array is formed in the stacked layer and includes a plurality of channel posts arranged in an array in the first transverse and the second transverse directions; A virtual channel column array is formed in the stacked layer and includes a plurality of virtual channel columns arranged in an array in the first transverse and the second transverse directions; A gate spacer is formed in the stacked layer and extends along the second lateral direction, and is disposed between the channel pillar array and the virtual channel pillar array.

2. The semiconductor device according to claim 1, wherein, The channel column array includes transition channel columns and storage channel columns arranged along the first transverse direction. The transition channel columns are located between the storage channel columns and the virtual channel columns, and the critical dimension of the transition channel columns is larger than the critical dimension of the storage channel columns.

3. The semiconductor device according to claim 1, wherein, The virtual channel pillars are positioned in the stepped area formed by the stacked layers.

4. The semiconductor device according to claim 1, wherein, The gate spacers include a plurality of them and are arranged along the first lateral spacing, and the arrangement density of the gate spacers gradually decreases from the channel pillar array toward the virtual channel pillar array.

5. The semiconductor device according to claim 1, wherein, The gate spacers include multiple ones and are arranged in a dashed shape along the second lateral spacing.

6. The semiconductor device according to claim 1, wherein, The semiconductor device further includes a gate line slit that penetrates the stacked layer along the stacking direction and extends along the first lateral direction.

7. The semiconductor device according to claim 6, wherein, The gate slot is made of the same material as the gate wire slit.

8. The semiconductor device according to claim 1, wherein, The cross-sectional shape of the gate spacer in the first lateral direction includes at least one of a rectangle, a trapezoid, and a semicircle, and the side of the gate spacer facing the virtual channel pillar array is a plane.

9. The semiconductor device according to claim 2, wherein, The density of the transition channel columns in the channel column array gradually decreases along the first transverse direction of the virtual channel column array.

10. The semiconductor device according to claim 9, wherein, The transition channel pillars have a critical dimension, which is the distance from the center of the transition channel pillar to the edge of the transition channel pillar. The critical dimension of the plurality of transition channel pillars gradually increases along the first lateral direction towards the virtual channel pillar array.

11. A method for fabricating a semiconductor device, the method comprising: Provide substrate; A stacked layer is formed, which is disposed above the substrate and is composed of an insulating layer and a gate layer stacked alternately. The stacked layer extends along a first lateral direction perpendicular to the stacking direction and a second lateral direction perpendicular to the stacking direction. The first lateral direction and the second lateral direction are perpendicular to each other. A channel column array is formed in the stacked layer and includes a plurality of channel columns arranged in an array in the first transverse and the second transverse directions; A virtual channel column array is formed in the stacked layer and includes a plurality of virtual channel columns arranged in an array in the first transverse and the second transverse directions; A gate spacer is formed in the stacked layer and extends along the second lateral direction, and is disposed between the channel pillar array and the virtual channel pillar array.

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