Three-dimensional memory and methods of making the same

Abstract

A method for forming a three-dimensional (3D) memory device is provided. The method includes providing an alternating dielectric stack (554) including first dielectric layers (556) and second dielectric layers (558) stacked alternately on a substrate (330); forming a channel structure (666) penetrating the alternating dielectric stack (554) in a first direction perpendicular to the substrate (330). The channel structure (666) includes a charge trapping layer (337-2) extending in the first direction. The method further includes removing at least one second dielectric layer (558) at a top portion of the alternating dielectric stack (554) to form a top select gate (TSG) cut channel (876) and expose a portion of the charge trapping layer (337-2) in a second direction parallel to the substrate (330). The method further includes removing the exposed portion of the charge trapping layer (337-2) inside the TSG cut channel (876); and providing a TSG conductive layer (980) inside the TSG cut channel (876).

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 2021104900254, filed on May 6, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates generally to the field of semiconductor technology, and more specifically to three-dimensional memory and methods for its fabrication. Background Technology

[0004] As memory devices shrink to smaller die sizes to reduce manufacturing costs and increase storage density, scaling planar memory cells faces challenges due to process technology limitations and reliability issues. Three-dimensional (3D) memory architectures can address the density and performance limitations of planar memory cells.

[0005] In 3D NAND flash memory, the memory array can include multiple memory strings arranged vertically on a substrate, each memory string having multiple memory cells stacked vertically on top of each other. This allows for a significant increase in memory density per unit area. To perform programming, reading, and erasing operations, each memory string can be electrically connected to the array's common source at one end and to a bit line at the other. A top-select transistor located on top of each memory string can be turned on or off via a top-select gate to control the electrical connection between the memory string and the bit line. Summary of the Invention

[0006] This disclosure describes embodiments of three-dimensional (3D) storage devices and methods for forming the same.

[0007] One aspect of this disclosure provides a method for forming a three-dimensional (3D) memory device. The method includes the following steps: forming an alternating dielectric stack comprising alternating dielectric layers and sacrificial layers on a substrate; forming a channel via penetrating the alternating dielectric stack; and sequentially disposing a memory film and a channel layer on the sidewalls of the channel via to form a channel structure; forming a top select gate (TSG) notch opening penetrating at least one sacrificial layer; sequentially removing portions of at least one sacrificial layer and a memory film corresponding to the at least one sacrificial layer via the TSG notch opening to form a TSG notch channel; and disposing a TSG dielectric layer on the inner wall of the TSG notch channel, and disposing a TSG conductive layer on the TSG dielectric layer inside the TSG notch channel.

[0008] In some embodiments, setting the TSG dielectric layer and the TSG conductive layer respectively includes setting silicon oxide and doped polysilicon.

[0009] In some embodiments, forming the channel structure further includes: forming an epitaxial plug at the bottom of the channel hole; forming a storage film on the sidewall of the channel hole and on the substrate-away surface of the epitaxial plug; and forming a channel layer on the sidewall of the storage film that contacts the epitaxial plug.

[0010] In some embodiments, after forming the channel structure, the method further includes: disposing a core-filling film on the channel layer inside the channel hole; and forming a channel top plug in contact with the channel layer at the end of the core-filling film away from the substrate.

[0011] In some embodiments, after forming the channel structure, the method further includes forming a capping layer to cover the surface of the channel structure and the alternating dielectric stacks away from the substrate.

[0012] In some embodiments, forming a TSG cutout further includes forming a TSG cutout that penetrates the cap layer and at least one sacrificial layer and extends to the top of the dielectric layer.

[0013] In some embodiments, setting a TSG dielectric layer and a TSG conductive layer inside the TSG cut channel includes: sequentially depositing a TSG dielectric layer and a TSG conductive layer on the sidewall of the TSG cut opening; and removing the TSG dielectric layer and the TSG conductive layer from the sidewall of the TSG cut opening.

[0014] In some embodiments, the method further includes filling the TSG cut opening with a dielectric material to form a TSG cut.

[0015] In some embodiments, the method further includes: forming a gate gap (GLS) opening that penetrates the alternating dielectric stack and extends into the substrate; removing a sacrificial layer of the alternating dielectric stack through the GLS opening to form a lateral channel; filling the lateral channel with a conductive material to form a second conductive layer; and filling the GLS opening with a conductive material to form a GLS.

[0016] Another aspect of this disclosure provides a three-dimensional (3D) memory. The 3D memory includes: a substrate; a film stack of alternating conductive and dielectric layers disposed on the substrate, comprising a top stack having alternating TSG conductive layers and a third dielectric layer, and a bottom stack having alternating second conductive layers and a first dielectric layer; a TSG dielectric layer located between the TSG conductive layer and the third dielectric layer, and at least partially surrounding the TSG conductive layer; and a memory string penetrating the film stack of alternating conductive and dielectric layers, and including a channel layer and a memory film radially from the inside to the outside of the memory string. The TSG dielectric layer penetrates the memory film in a direction parallel to the substrate and contacts the channel layer. The 3D memory includes a top selection transistor at the intersection of the TSG conductive layer, the TSG dielectric layer, and the channel layer.

[0017] In some embodiments, the TSG dielectric layer is silicon oxide and the TSG conductive layer is doped polycrystalline silicon.

[0018] In some embodiments, the memory string further includes: an epitaxial plug adjacent to and in contact with the substrate. A memory film extends onto the top surface of the epitaxial plug away from the substrate, exposing a portion of the top surface of the epitaxial plug. A channel layer extends onto the top surface of the epitaxial plug and contacts the exposed portion of the epitaxial plug.

[0019] In some embodiments, the 3D memory further includes a channel top plug located at the end of the memory string remote from the substrate. The channel top plug contacts the channel layer.

[0020] In some embodiments, the 3D memory further includes a cap layer disposed on the top surface of the top stack, away from the substrate. The cap layer covers the memory string.

[0021] In some embodiments, the 3D memory further includes a TSG cutout that penetrates the top stack.

[0022] In some embodiments, the 3D memory further includes a gate gap (GLS) that penetrates a stack of alternating conductive and dielectric layers.

[0023] Other aspects of this disclosure will be understood by those skilled in the art based on the specification, claims, and drawings. Attached Figure Description

[0024] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and enable those skilled in the art to make and use the present disclosure.

[0025] Figure 1 A schematic top view of an exemplary three-dimensional (3D) memory die according to some embodiments of the present disclosure is shown.

[0026] Figure 2 A schematic top view of a 3D memory die region according to some embodiments of the present disclosure is shown.

[0027] Figure 3 A perspective view of a portion of an exemplary 3D storage array structure according to some embodiments of the present disclosure is shown.

[0028] Figure 4 The illustration shows a method for forming a 3D storage device according to some embodiments of the present disclosure.

[0029] Figure 5-12 A cross-sectional view of a 3D storage structure at a specific process step according to some embodiments of the present disclosure is shown.

[0030] The features and advantages of the present invention will become more apparent from the specific embodiments described below in conjunction with the accompanying drawings, in which similar reference numerals consistently identify corresponding elements. In the drawings, similar reference numerals generally indicate elements that are identical, functionally similar, and / or structurally similar. The first appearance of an element in a figure is indicated by the leftmost (or more) numerals of the corresponding reference numerals.

[0031] Embodiments of this disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0032] Although specific constructions and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other constructions and arrangements can be used without departing from the spirit and scope of this disclosure. It will be apparent to those skilled in the art that this disclosure can also be used in a variety of other applications.

[0033] Note that references to "one embodiment," "embodiment," "exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, its effect in conjunction with other embodiments (whether explicitly described or not) on that feature, structure, or characteristic will be within the knowledge of those skilled in the art.

[0034] Generally, terms can be understood at least in part based on their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage. Additionally, also depending at least in part on the context, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors that are not necessarily explicitly described.

[0035] It should be readily understood that the meanings of “above,” “above,” and “on top” in this disclosure should be interpreted in the broadest sense, such that “above” not only means directly “on” something, but also includes the meaning of being “on” something with an intermediate feature or layer in between. Furthermore, “above” or “on top” not only means being “above” or “on top” something, but can also include the meaning of being “above” or “on top” something without an intermediate feature or layer in between (i.e., directly on something).

[0036] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein to describe the relationship of one element or feature relative to another element (or features) as shown in the figures. In addition to the orientations described in the figures, the spatial relative terms are also intended to cover different orientations of the device during use or process steps. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein can be interpreted similarly accordingly.

[0037] As used herein, the term "substrate" refers to the material on which subsequent layers of material are added. A substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where semiconductor devices are formed; therefore, unless otherwise stated, semiconductor devices are formed on the top side of the substrate. The bottom surface is opposite to the top surface, and thus the bottom surface of the substrate is opposite to the top surface of the substrate. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or a sapphire wafer.

[0038] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. Layers may include multiple layers. For example, an interconnect layer may include one or more conductive and contact layers (in which contacts, interconnects, and / or vertical interconnect accesses (VIAs) are formed) and one or more dielectric layers.

[0039] In this disclosure, for ease of description, the term "step" is used to refer to elements having substantially the same height along the vertical direction. For example, a word line and the underlying gate dielectric layer can be referred to as a "step," a word line and the underlying insulating layer can be referred to together as a "step," word lines of substantially the same height can be referred to as a "word line step" or the like, and so on.

[0040] As used herein, the term "nominal / nominally" refers to the expected or target value of a characteristic or parameter for a component or process step, set during the design phase of a product or process, and the range of values ​​higher and / or lower than the expected value. The range of values ​​may be due to slight variations in the manufacturing process or tolerances. As used herein, the term "about" indicates a value of a given quantity that may vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "about" may indicate a value of a given quantity that varies, for example, within 10%–30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0041] In this disclosure, the terms “horizontal / horizontally / laterally” refer to a lateral surface that is nominally parallel to the substrate, and the terms “vertical” or “perpendicularly” refer to a lateral surface that is nominally perpendicular to the substrate.

[0042] As used herein, the term “3D memory” refers to a three-dimensional (3D) semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as “memory strings”, such as NAND strings) on a laterally oriented substrate, such that the memory strings extend in a direction perpendicular to the substrate.

[0043] Figure 1 A top view of an exemplary three-dimensional (3D) storage device 100 according to some embodiments of the present disclosure is shown. The 3D storage device 100, such as a 3D NAND flash memory, can be any part of a memory chip (package), memory die, or memory die, and can include one or more storage surfaces 101, each storage surface including multiple storage blocks 103. The same and concurrent operations can be performed on each storage surface 101. The size of the storage block 103 can be megabytes (MB), which is the minimum size for performing an erase operation. Figure 1 As shown, the exemplary 3D storage device 100 includes four storage surfaces 101, and each storage surface 101 includes six storage blocks 103. Each storage block 103 may include a plurality of storage cells, wherein each storage cell can be addressed via interconnects such as bit lines and word lines. The bit lines and word lines may be vertically arranged (e.g., in rows and columns, respectively) to form a metallic line array. The orientation of the bit lines and word lines is... Figure 1 The blocks are labeled "BL" and "WL". In this disclosure, storage block 103 is also referred to as a "storage array" or "array". A storage array is a core area in a storage device that performs storage functions.

[0044] The 3D memory device 100 also includes a peripheral region 105, which is the area surrounding the memory surface 101. The peripheral region 105 contains a variety of digital, analog, and / or mixed-signal circuitry to support the functionality of the memory array, such as page buffers, row and column decoders, and sense amplifiers. The peripheral circuitry uses active and / or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc., as will be apparent to those skilled in the art.

[0045] Notice, Figure 1 The arrangement of storage surfaces 101 in the 3D storage device 100 shown and the arrangement of storage blocks 103 in each storage surface 101 are for illustrative purposes only and do not limit the scope of this disclosure.

[0046] refer to Figure 2 Some embodiments according to this disclosure are shown. Figure 1 An enlarged top view of region 108 in the 3D storage device 100. Region 108 of the 3D storage device 100 may include a stepped region 210 and a channel structure region 211. The channel structure region 211 may include an array of memory strings 212, each memory string including a plurality of stacked memory cells. The stepped region 210 may include a stepped structure and an array of contact structures 214 formed on the stepped structure. In some embodiments, a plurality of slot structures 216 extending in the WL direction across the channel structure region 211 and the stepped region 210 may divide the memory block into a plurality of memory fingers 218. At least some of the slot structures 216 may serve as common source contacts (e.g., array common source or ACS) for the array of memory strings 212 in the channel structure region 211. A top select gate notch 220 may be positioned, for example, in the middle of each memory finger 218 to divide the top select gate (TSG) of the memory finger 218 into two portions, thereby dividing the memory finger into two memory slabs 224, wherein memory cells sharing the same word line in the memory slabs 224 form programmable (read / write) memory pages. While erase operations on the 3D NAND memory can be performed at the block level, read and write operations can be performed at the page level. The size of a memory page can be kilobytes (KB). In some embodiments, region 108 also includes a dummy memory string 222 for process variation control during manufacturing and / or for additional mechanical support.

[0047] Figure 3A perspective view of a portion of an exemplary three-dimensional (3D) memory array structure 300 according to some embodiments of the present disclosure is shown. The memory array structure 300 includes a substrate 330, an insulating film 331 over the substrate 330, a step of a lower select gate (LSG) 332 over the insulating film 331, and multiple steps of a control gate 333, also referred to as a "word line (WL)," which is stacked on top of the LSG 332 to form a film stack 335 of alternating conductive and dielectric layers. For clarity, details are not shown. Figure 3 The dielectric layer adjacent to the step of the control gate is shown in the figure.

[0048] Each step's control gate is separated by slot structures 216-1 and 216-2 passing through the film stack 335. The memory array structure 300 also includes a step of top select gate (TSG) 334 above the stack of control gates 333. The stack of TSG 334, control gate 333, and LSG 332 is also referred to as the "gate electrode". The memory array structure 300 also includes memory strings 212 and doped source electrode regions 344 in the portion of the substrate 330 between adjacent LSGs 332. Each memory string 212 includes a channel via 336 extending through the film stack 335 of insulating film 331 and alternating conductive and dielectric layers. The memory string 212 also includes a memory film 337 on the sidewall of the channel via 336, a channel layer 338 above the memory film 337, and a core-fill film 339 surrounded by the channel layer 338. Memory cells 340 (e.g., 340-1, 340-2, 340-3) may be formed at the intersection of control gates 333 (e.g., 333-1, 333-2, 333-3) and memory strings 212. A channel layer 338 is also referred to as the channel layer 338 of the memory cell in response to a portion of the respective control gate. The memory array structure 300 also includes multiple bit lines (BLs) 341 that connect to the memory strings 212 over the TSG 334. The memory array structure 300 also includes multiple metal interconnects 343 connected to the gate electrode via multiple contact structures 214. The edges of the film stack 335 are configured in a stepped shape to allow electrical connection to each step of the gate electrode.

[0049] exist Figure 3In this illustration, for purposes of illustration, the three steps 333-1, 333-2, and 333-3 of the control gate are shown together with one step of the TSG 334 and one step of the LSG 332. In this example, each memory string 212 may include three memory cells 340-1, 340-2, and 340-3, which correspond to the control gates 333-1, 333-2, and 333-3, respectively. In some embodiments, the number of control gates and the number of memory cells may be more than three to increase the storage capacity. The memory array structure 300 may also include other structures, such as TSG notches, common source contacts (i.e., array common source), and dummy memory strings. These are not shown for simplicity. Figure 3 These structures are shown in the figure.

[0050] Traditionally, the top-select gate (TSG) is formed simultaneously with the word line (or control gate) for the memory cell, and it includes a charge-trapping storage film. When a voltage is applied to the top-select gate, the threshold voltage V of the top-select transistor... th Drift, like the threshold voltage V of a memory cell. th Similarly, variations in the threshold voltage lead to uncertainties in the switching characteristics of the top-select transistor, thus affecting the performance of 3D NAND memory. Therefore, there is a need to provide a method for forming 3D NAND memory with an improved top-select transistor.

[0051] Figure 4 A method 400 for forming a three-dimensional (3D) storage device according to some embodiments of the present disclosure is illustrated. It should be understood that the process steps shown in method 400 are not exhaustive, and other steps may be performed before, after, or between any shown steps. In some embodiments, some process steps of method 400 may be omitted, or other process steps may be included, which will not be described further here for simplicity. In some embodiments, the process steps of method 400 may be performed in different orders and / or variations.

[0052] Figure 5-12 An exemplary structure of a 3D storage device at a specific process step according to method 400 is shown.

[0053] refer to Figure 4 In process step S405, an alternating dielectric stack can be disposed on the substrate. In process step S410, a stepped structure can be formed in the alternating dielectric stack. In process step S415, an insulating layer can be disposed on the substrate, covering the stepped structure and the alternating dielectric stack. Figure 5 The figure shows a cross-sectional view of an exemplary 3D storage structure 500 according to process steps S405-S415.

[0054] like Figure 5As shown, the 3D storage structure 500 includes an alternating dielectric stack 554 having a first dielectric layer 556 and a second dielectric layer 558 alternately stacked on a substrate 330.

[0055] Substrate 330 can provide a platform for forming subsequent structures. In some embodiments, substrate 330 can be any suitable semiconductor substrate having any suitable semiconductor material, such as single-crystal, polycrystalline, or single-crystal semiconductor. For example, substrate 330 can include silicon, silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), gallium nitride, silicon carbide, III-V compounds, II-VI compounds, or any combination thereof. In some embodiments, substrate 330 can have a composite structure and include a semiconductor layer formed on the processed wafer. For example, substrate 330 can be silicon-on-insulator (SOI), germanium-on-insulator (GOI), or silicon-germanium-on-insulator (SGOI).

[0056] The front surface 330f of substrate 330 is also referred to herein as the “main surface” or “top surface” of the substrate. Material layers may be disposed on the front surface 330f of substrate 330. The “topmost” or “upper” layer is the layer furthest from or further from the front surface 330f of the substrate. The “bottommost” or “lower” layer is the layer closest to or closest to the front surface 330f of the substrate.

[0057] In some embodiments, the alternating dielectric stack 554 includes a plurality of dielectric layer pairs alternately stacked in a vertical direction (i.e., the z-direction) perpendicular to the front surface 330f of the substrate 330, wherein each dielectric layer pair includes a first dielectric layer 556 (also referred to as a "dielectric layer") and a second dielectric layer 558 (also referred to as a "sacrificial layer") different from the first dielectric layer 556. The alternating dielectric stack 554 extends in a lateral direction parallel to the front surface 330f of the substrate 330.

[0058] In the alternating dielectric stack 554, the first dielectric layer 556 and the second dielectric layer 558 alternate in a vertical direction perpendicular to the substrate 330. In other words, each second dielectric layer 558 may be sandwiched between two first dielectric layers 556, and each first dielectric layer 556 may be sandwiched between two second dielectric layers 558 (except for the bottom and top layers).

[0059] The formation of the alternating dielectric stack 554 may include configuring the first dielectric layers 556 to have the same thickness or different thicknesses. An example thickness of the first dielectric layer 556 may range from 10 nm to 500 nm, preferably about 25 nm. Similarly, the second dielectric layers 558 may have the same thickness or different thicknesses. An example thickness of the second dielectric layer 558 may range from 10 nm to 500 nm, preferably about 35 nm. It should be understood that... Figure 5 The number of dielectric layer pairs is for illustrative purposes only, and any suitable number of layers may be included in the alternating dielectric stack 554.

[0060] In some embodiments, the first dielectric layer 556 comprises any suitable insulating material, such as silicon oxide, silicon oxynitride, silicon nitride, TEOS, or silicon oxide incorporating F-, C-, N-, and / or H- groups. The first dielectric layer 556 may also comprise a high-k dielectric material, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, or lanthanum oxide film. In some embodiments, the first dielectric layer 556 may be any combination of the above materials.

[0061] The formation of the first dielectric layer 556 may include any suitable deposition method, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), rapid thermal chemical vapor deposition (RTCVD), low-pressure chemical vapor deposition (LPCVD), sputtering, metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), high-density plasma CVD (HDP-CVD), sputtering, evaporation, thermal oxidation, nitriding, any other suitable deposition method and / or combinations thereof.

[0062] In some embodiments, the second dielectric layer 558 comprises any suitable material that differs from the first dielectric layer 556 and can be selectively removed relative to the first dielectric layer 556. For example, the second dielectric layer 558 may comprise silicon oxide, silicon oxynitride, silicon nitride, TEOS, polycrystalline silicon, polycrystalline germanium, polycrystalline germanium silicon, and any combination thereof. In some embodiments, the second dielectric layer 558 further comprises an amorphous semiconductor material, such as amorphous silicon or amorphous germanium. The second dielectric layer 558 can be formed using techniques similar to those used for the first dielectric layer 556, such as CVD, PVD, ALD, sputtering, evaporation, thermal oxidation or nitriding, or any combination thereof.

[0063] In some embodiments, the first dielectric layer 556 may be silicon oxide and the second dielectric layer 558 may be silicon nitride.

[0064] In some embodiments, the alternating dielectric stack 554 may include layers other than the first dielectric layer 556 and the second dielectric layer 558, and may be made of different materials and / or have different thicknesses.

[0065] like Figure 5 As shown, the 3D memory structure 500 also includes a stepped structure 550 having a plurality of stepped steps 552 formed in alternating dielectric stacks 554 in the stepped region. A stepped step 552, or "stepped layer," refers to a stack of layers having the same lateral dimension in a surface parallel to the substrate surface 330f. Each of the stepped steps 552 terminates at a length shorter than the step below it, having… Figure 5 The horizontal dimension “a” is shown in the figure.

[0066] In some embodiments, each of the stepped steps 552 includes a pair of first dielectric layers 556 and second dielectric layers 558. In some embodiments, each of the stepped steps 552 may include two or more pairs of first dielectric layers 556 and second dielectric layers 558. Figure 5 As shown, each of the stepped steps 552 includes a pair of first dielectric layers 556 and second dielectric layers 558. In some embodiments, the second dielectric layer 558 is positioned on top of the first dielectric layer 556 in each stepped step 552. A portion of the second dielectric layer 558 is exposed at the end of the alternating dielectric stack 554 in each stepped step 552. In some embodiments, the first dielectric layer 556 is positioned on top of the second dielectric layer 558 in each stepped step 552.

[0067] The stepped structure 550 can be formed by applying repeated etch trimming processes to an alternating dielectric stack 554. The etch trimming process includes an etching process and a trimming process. During the etching process, a portion of the stepped step 552 with exposed surfaces can be removed. The remaining portion of the stepped step 552 covered by the upper layer of the stepped step or by a patterned mask is not etched. The etching depth is the thickness of the stepped step 552. In some embodiments, the thickness of the stepped step 552 is the thickness of a pair of first dielectric layers 556 and second dielectric layers 558. The etching process for the first dielectric layer 556 can be highly selective above the second dielectric layer 558, and / or vice versa. Therefore, the underlying dielectric layer pair can be used as an etch stop layer. By switching the etch process for each layer, the stepped step 552 can be etched during one etch cycle. And as a result, one of the stepped steps 552 can be formed during each etch trimming cycle.

[0068] In some embodiments, anisotropic etching, such as reactive ion etching (RIE) or other dry etching processes, can be used to etch the step 552. In some embodiments, the first dielectric layer 556 is silicon oxide. In this example, etching of the silicon oxide may include RIE using a fluorine-based gas, such as fluorocarbon (CF4), hexafluoroethane (C2F6), CHF3, or C3F6 and / or any other suitable gas. In some embodiments, the silicon oxide layer may be removed by a wet chemical agent, such as hydrofluoric acid or a mixture of hydrofluoric acid and ethylene glycol. In some embodiments, a timed etching method may be used. In some embodiments, the second dielectric layer 558 is silicon nitride. In this example, etching of the silicon nitride may include RIE using O2, N2, CF4, NF3, Cl2, HBr, BCl3, and / or combinations thereof. The methods and etchants used to remove a single layer stack should not be limited to the embodiments of this disclosure.

[0069] The trimming process involves applying a suitable etching process (e.g., isotropic dry etching or wet etching) to the patterned mask such that the patterned mask can be laterally pulled back. The lateral pull-back dimension determines the lateral dimension "a" of each step of the stepped structure 550. After trimming the patterned mask, a portion of the topmost step 552 is exposed and another portion of the topmost step 552 remains covered by the patterned mask. The next cycle of the etching trimming process restarts with the etching process. In some embodiments, the patterned mask trimming process may include dry etching, such as RIE using O2, Ar, N2, etc. Note that the number of stepped structures and dielectric layer pairs in the 3D memory structure 500 is not limited to the examples herein.

[0070] like Figure 5 As shown, the 3D memory structure 500 also includes an insulating layer 560 disposed on the substrate, which covers the stepped structure 550 and the alternating dielectric stack 554. The insulating layer 560 may include any suitable insulating material, such as silicon oxide, silicon oxynitride, silicon nitride, TEOS, spin-coated glass, low-k dielectric materials, such as carbon-doped oxides (CDO, SiOC, or SiOC:H) or fluorine-doped oxides (SiOF), etc. The insulating layer 560 can be deposited by CVD, PVD, ALD, sputtering, evaporation, etc. In some embodiments, the insulating layer 560 may have a planar top surface on the stepped structure 550 and the alternating dielectric stack 554. CMP and / or RIE etch-back can be used to planarize the insulating layer 560.

[0071] When process step S415 is completed, a stepped structure 550 is formed in the stepped area, which can be used to form electrical contact with the word lines in subsequent processes.

[0072] In some embodiments, a barrier layer 562 (also referred to as a stepped protective layer) may be provided on the stepped structure and the alternating dielectric stack 554 before the insulating layer 560 is provided. The barrier layer 562 may cover the stepped structure 550 and the alternating dielectric stack 554 on both lateral surfaces and the vertical sidewalls. The barrier layer 562 on the lateral surfaces and the vertical sidewalls may have the same or different thicknesses. The barrier layer 562 may include a thickness in the range of 10 nm to 100 nm.

[0073] In some embodiments, the barrier layer 562 can be any suitable insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, TEOS, high-k dielectric materials (Al2O3, HfO2, Ta2O3, ZrO2, La2O3, etc.), or any combination thereof. The barrier layer 562 can be formed using any suitable thin-film deposition technique, such as CVD (e.g., PECVD, LPCVD, RTCVD, HDP-CVD, MOCVD, etc.), ALD, PVD, sputtering, evaporation, etc. In some embodiments, the barrier layer 562 can act as an etch stop layer for forming contact structures on the stepped surfaces in subsequent processes. In this example, the barrier layer 562 can include any suitable insulating material other than the second dielectric layer 558. In some embodiments, the first barrier layer 562 can be silicon oxide.

[0074] In some embodiments, the 3D storage structure 500 further includes a top dielectric stack 564 disposed on the insulating layer 560 and the alternating dielectric stack 554. The top dielectric stack 564 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, TEOS, high-k dielectric materials (Al2O3, HfO2, Ta2O3, ZrO2, La2O3, etc.), or any combination thereof.

[0075] refer to Figure 4 In process step S420, multiple channel structures can be formed in the channel structure region, wherein each channel structure penetrates an alternating dielectric stack. Figure 6 A cross-sectional view of an exemplary 3D storage structure 600 according to process step S420 is shown.

[0076] like Figure 6As shown, the 3D memory structure 600 includes a plurality of channel vias 336 perpendicularly penetrating an alternating dielectric stack 554. Techniques for forming the channel vias 336 may include processes such as photolithography and etching. Etching processes for forming the channel vias 336 may also include dry etching, wet etching, or a combination thereof. In some embodiments, anisotropic etching, such as reactive ion etching (RIE), may be used to etch the alternating dielectric stack 554. In some embodiments, fluorine- or chlorine-based gases, such as fluorocarbons (CF4), hexafluoroethane (C2F6), CHF3, C3F6, Cl2, BCl3, etc., or any combination thereof, may be used. The methods and etchants used for etching the first dielectric layer 556 and the second dielectric layer 558 should not be limited to the embodiments of this disclosure.

[0077] After forming the channel via 336, a storage film 337 may be disposed on the sidewall of the channel via 336. In some embodiments, the storage film 337 may be a composite layer comprising a tunneling layer 337-1, a storage layer 337-2 (also referred to as a "charge trapping layer"), and a barrier layer 337-3. In some embodiments, the tunneling layer 337-1, the storage layer 337-2, and the barrier layer 337-3 are arranged in the order described above along a direction from the center of the channel via 336 toward the outside of the channel via 336. The tunneling layer 337-1 may comprise silicon oxide, silicon nitride, or any combination thereof. The barrier layer 337-3 may comprise silicon oxide, silicon nitride, a high-k dielectric, or any combination thereof. The storage layer 337-2 may comprise silicon nitride, silicon oxynitride, silicon, or any combination thereof. In some embodiments, the storage film 337 comprises an ONO dielectric (e.g., a tunneling layer comprising silicon oxide, a storage layer comprising silicon nitride, and a barrier layer comprising silicon oxide). The storage film 337 can be formed using a thin-film deposition process, such as ALD, CVD, PVD, sputtering, or any other suitable process. In some embodiments, the thickness of the storage film 337 can range from about 10 nm to about 50 nm.

[0078] Next, a channel layer 338 and a core-fill film 339 can be disposed in a channel via 336, wherein the channel layer 338 covers the sidewalls of the storage film 337 inside the channel via 336. The channel layer 338 can be any suitable semiconductor material, such as silicon. In some embodiments, the channel layer 338 can be amorphous silicon, polycrystalline silicon, or monocrystalline silicon. The channel layer 338 can be formed by any suitable thin-film deposition process, including but not limited to CVD, PVD, ALD, sputtering, evaporation, or combinations thereof. In some embodiments, the thickness of the channel layer 338 can range from approximately 10 nm to approximately 30 nm.

[0079] In some embodiments, a core-filled film 339 may be provided to fill the channel vias 336 to form a channel structure 666. In some embodiments, the core-filled film 339 may include one or more seams 860 in the middle. The core-filled film 339 may be any suitable insulator, such as silicon oxide, silicon nitride, silicon oxynitride, spin-coated glass, boron or phosphorus-doped silicon oxide, carbon-doped oxide (CDO or SiOC or SiOC:H), fluorine-doped oxide (SiOF), or any combination thereof. The core-filled film 339 may be deposited using, for example, ALD, PVD, CVD, spin-coating, sputtering, or any other suitable film deposition technique. The core-filled film 339 may also be formed by using repeated deposition and etch-back processes. The etch-back process may include, but is not limited to, wet etching, dry etching, or a combination thereof. In some embodiments, one or more seams may be formed in the core-filled film 339 to reduce mechanical stress.

[0080] In some embodiments, the 3D memory structure 600 further includes a channel top plug 668 at the top portion of the channel structure 666. The channel top plug 668 can form an electrical contact with the channel layer 338 inside the channel via 336. The channel top plug 668 can be amorphous silicon or polycrystalline silicon and can include metals, metal alloys and / or metal silicides, such as tungsten, titanium, tantalum, tungsten nitride, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, tungsten silicide, titanium silicide, or combinations thereof. The channel top plug 668 can be formed by a recess etching process and subsequent thin film deposition. The recess etching process includes wet etching, dry etching, or a combination thereof. The thin film deposition includes CVD, PVD, ALD, sputtering, or any other suitable process. The channel top plug 668 can serve as a drain-side contact of the channel structure.

[0081] In some embodiments, the 3D memory device 600 may further include an epitaxial plug 670 at the bottom of the channel structure 666. The epitaxial plug 670 may include any suitable semiconductor material, such as silicon, silicon-germanium, germanium, gallium arsenide, gallium nitride, III-V compound, or any combination thereof. The epitaxial plug 670 may be epitaxially grown from the substrate 330. In some embodiments, the epitaxial plug 670 may further include a polycrystalline semiconductor material, such as polycrystalline silicon. In some embodiments, a portion of the memory film 337 at the bottom of the channel via 336 may be removed, allowing the channel layer 338 to directly contact the epitaxial plug 670. The epitaxial plug 670 extends through at least one of the second dielectric layers 558 in the bottom portion of the alternating dielectric stack 554, wherein an LSG 332 (see [link to LSG]) may be formed in a subsequent process. Figure 3 The lower selection transistor is controlled by an epitaxial plug 670. In some embodiments, the epitaxial plug 670 extends through the bottommost second dielectric layer.

[0082] It should be noted that the number and arrangement of the channel structures 666 in the channel structure area can be designed according to actual storage requirements, and are not limited to... Figure 6 The example shown. As previously mentioned... Figure 2 The channel structure region 211 discussed here provides storage functionality for the three-dimensional memory.

[0083] In some embodiments, the 3D storage structure 600 further includes a plurality of dummy channel holes in the stepped region. Figure 6 (Not shown in the image). A dummy channel via (DCH) penetrates a portion of the stepped structure 550 (i.e., a portion of the alternating dielectric stack 554) and extends into the substrate 330. After the DCH is formed, any suitable insulator can be disposed within the DCH to form the dummy channel structure. In the stepped region (see, for example...), Figure 2 The virtual channel structure formed in the process can be configured to provide mechanical support for the 3D storage structure in subsequent processes.

[0084] In some embodiments, the channel structure 666 may be planarized to have a surface coplanar with the top dielectric stack 564. Planarization processes include RIE etch-back, CMP, or a combination thereof.

[0085] The 3D memory structure 600 may also include a capping layer 672 disposed on the top dielectric stack 564 to cover the channel structure 666. The capping layer 672 may include silicon oxide, silicon nitride, silicon oxynitride, TEOS, or a combination thereof. The capping layer 672 may be deposited by CVD, PVD, ALD, sputtering, or the like.

[0086] refer to Figure 4 In process step S425, a top select gate (TSG) cutout opening can be formed in the top portion of the alternating dielectric stack. Figure 7 The diagram shows a cross-sectional view of an exemplary 3D storage structure 700 according to process step S425.

[0087] like Figure 7 As shown, the 3D memory structure 700 includes a TSG cutout opening 774 that penetrates the top portion of the alternating dielectric stack 554. The TSG cutout opening 774 extends into at least one second dielectric layer 558 in the top portion of the alternating dielectric stack 554, wherein a TSG 334 (see...) can be formed in a subsequent process. Figure 3 The top-selected transistor is controlled by [the transistor]. For example... Figure 7 As shown, the TSG cutout opening 774 extends into the topmost second dielectric layer. In some embodiments, the TSG cutout opening 774 also penetrates the cap layer 672 and the top dielectric stack 564.

[0088] The TSG notch opening 774 can be formed by photolithography and etching processes. The etching process can include any suitable dry etching, wet etching, and / or a combination thereof.

[0089] refer to Figure 4 In process step S430, a TSG cut-out channel can be formed in the top portion of the alternating dielectric stack. Figure 8 A cross-sectional view of an exemplary 3D storage structure 800 according to process step S430 is shown.

[0090] like Figure 8 As shown, the 3D memory structure 800 includes a TSG notch channel 876 in the top portion of an alternating dielectric stack 554. The TSG notch channel 876 can be formed by removing a second dielectric layer 558 in the top portion of the alternating dielectric stack 554 via the TSG notch opening 774. In some embodiments, the topmost second dielectric layer 558 of the alternating dielectric stack 554 can be removed to form the TSG notch channel 876. The TSG notch channel 876 can extend laterally between adjacent first dielectric layers 556. Note that the term "laterally" as used herein refers to a plane parallel to the top surface 330f of the substrate 330. The second dielectric layer 558 in the alternating dielectric stack 554 is also referred to as a sacrificial layer and can be selectively removed between the first dielectric layers 556. In other words, the etching process of the second dielectric layer 558 can have minimal impact on the first dielectric layers 556. The second dielectric layer 558 can be removed by isotropic dry etching and / or wet etching. The plasma and / or chemicals used in dry / wet etching can travel vertically and laterally from the TSG notch opening 774. In some embodiments, the second dielectric layer 558 may be silicon nitride, and the first dielectric layer 556 may be silicon oxide. In this example, the second dielectric layer 558 can be removed by RIE using one or more etchants such as CF4, CHF3, C4F8, C4F6, and CH2F2. In some embodiments, the second dielectric layer 558 can be removed using wet etching (e.g., phosphoric acid).

[0091] After removing the second dielectric layer 558, a portion of the storage film 337 can be exposed in the TSG notch channel 876. The exposed portion of the storage film 337 within the TSG notch channel 876 can then be removed. The etching process for the exposed portion of the storage film 337 can include any suitable dry / wet etching. In some embodiments, a portion of the exposed portion of the storage film 337 within the TSG notch channel 876 can be removed. For example, a portion of the barrier layer 337-3 and the storage layer 337-2 of the storage film 337 can be removed, and at least a portion of the tunneling layer 337-1 can be retained.

[0092] After completing operation step S430, a portion of the channel layer 338 can be exposed inside the TSG cut channel 876.

[0093] refer to Figure 4 In process step S435, the TSG dielectric layer and the TSG conductive layer can be disposed inside the TSG cut channel. Figure 9 The diagram shows a cross-sectional view of an exemplary 3D storage structure 900 according to process step S435.

[0094] like Figure 9 As shown, the 3D storage structure 900 includes a TSG cutout channel 876 ( Figure 8 The TSG dielectric layer 978 and TSG conductive layer 980 (also known as the first conductive layer) are located inside the middle layer.

[0095] After removing at least the exposed charge trapping layer 337-2 within the TSG notch channel 876 of the second dielectric layer 558 and the storage film 337 as previously shown in operation step S430, the TSG dielectric layer 978 can be disposed within the TSG notch channel 876 through the TSG notch opening 774 to cover the exposed channel layer 338. The TSG dielectric layer 978 may include any suitable insulator different from the second dielectric layer 558, such that the TSG dielectric layer 978 is not removed along with the second dielectric layer 558 in subsequent processes. In some embodiments, the TSG dielectric layer 978 may also be a composite layer, wherein a key difference between the TSG dielectric layer 978 and the storage film 337 is that the TSG dielectric layer 978 does not include a storage layer or a charge trapping layer. In some embodiments, the TSG dielectric layer 978 may include, for example, silicon oxide, silicon oxynitride, and / or combinations thereof. In some embodiments, the TSG dielectric layer 978 may include oxygen-rich silicon oxynitride, wherein the oxygen content is higher than the nitrogen content. The TSG dielectric layer 978 may also include a high-k dielectric material, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, and / or any combination thereof. In some embodiments, the TSG dielectric layer 978 includes materials with a dielectric material having ... 12 cm 2 The TSG dielectric layer 978 is a dielectric material with high defect or charge trap density. It can be formed by one or more suitable deposition processes, such as CVD, PVD, and / or ALD. In some embodiments, the TSG dielectric layer 978 is silicon oxide deposited by ALD.

[0096] Next, the TSG conductive layer 980 can be disposed inside the TSG cut-out channel 876 through the TSG cut-out opening 774. The TSG conductive layer 980 can be disposed on the TSG dielectric layer 978 to form TSG 334 (e.g., in the top portion of the alternating dielectric stack 554) Figure 3 (As seen in the text).

[0097] The TSG conductive layer 980 can be formed by filling the TSG notch channel 876 with a suitable conductive material. The conductive material of the TSG conductive layer 980 may include polycrystalline semiconductors, such as polycrystalline silicon, polycrystalline germanium, polycrystalline germanium-silicon, and any other suitable material, and / or combinations thereof. In some embodiments, the polycrystalline material may be incorporated (i.e., doped) with any suitable n-type or p-type dopant, such as boron, phosphorus, arsenic, or any combination thereof. In some embodiments, the TSG conductive layer 980 may also be an amorphous semiconductor, such as amorphous silicon. Polycrystalline or amorphous silicon can facilitate easier etching processes through the TSG conductive layer 980, such as subsequent processes for forming the GLS opening 1182.

[0098] In some embodiments, the TSG conductive layer 980 may further comprise a metal or metal alloy, such as tungsten (W), aluminum (Al), titanium (Ti), copper (Cu), cobalt (Co), nickel (Ni), titanium nitride (TiN), tungsten nitride (WN), tantalum (Ta), tantalum nitride (TaN), AlTi, or any combination thereof. The TSG conductive layer 980 may be formed using suitable deposition methods, such as chemical vapor deposition (CVD) (e.g., LPCVD, PECVD, MOCVD, RTCVD, etc.), physical vapor deposition (PVD), sputtering, evaporation, atomic layer deposition (ALD), or any combination thereof. In some embodiments, the TSG conductive layer 980 comprises polycrystalline silicon in situ doped with an n-type dopant (e.g., phosphorus or arsenic).

[0099] In an example where the exposed portions of the barrier layer 337-3 and the storage layer 337-2 of the storage membrane 337 are removed from within the TSG notch channel 876, at least a portion of the tunneling layer 337-1 may serve as the TSG dielectric layer 978. In some embodiments, additional dielectric material may be deposited within the TSG notch channel 876 such that the TSG dielectric layer 978 includes at least a portion of the tunneling layer 337-1.

[0100] In some embodiments, after the TSG 334 is formed, the TSG conductive layer 980 disposed on the sidewalls and bottom of the TSG notch opening 774 can be removed by a dry or wet etching process, so that adjacent TSGs 334 can be electrically isolated through the TSG notch opening 774. In some embodiments, the TSG conductive layer 980 disposed on the top of the cap layer 672 can also be removed by a dry or wet etching process.

[0101] Upon completion of process step S435, a top-select transistor 981 can be formed at the intersection of the TSG conductive layer 980, the TSG dielectric layer 978, and the channel layer 338. The top-select transistor 981 can function as a MOSFET, where a voltage applied to the gate (i.e., the TSG conductive layer 980) can turn the channel (i.e., the corresponding portion of the channel layer 338) on or off. The gate dielectric layer of the top-select transistor 981 is the TSG dielectric layer 978, which contacts the exposed portions of the TSG conductive layer 980 and the channel layer 338. To minimize the threshold voltage variation of the top-select transistor 981, the TSG dielectric layer 978 comprises a dielectric material with minimal charge trapping. To obtain better switching characteristics, the TSG dielectric layer 978 can have a thickness thinner than the storage film 337 in the lateral direction parallel to the substrate. In other words, the thickness of the TSG dielectric layer 978 between the TSG conductive layer 980 and the channel layer 338 can be in the range of 10 nm to 30 nm. In some embodiments, to reduce leakage current, the TSG dielectric layer 978 can be thicker than the storage film 337.

[0102] refer to Figure 4 In process step S440, insulating material can be placed inside the TSG cut opening to form the TSG cut. Figure 10 A cross-sectional view of an exemplary 3D storage structure 1000 according to process step S440 is shown.

[0103] like Figure 10 As shown, the 3D storage structure 1000 includes a TSG cutout 220 (similar to...). Figure 2 The TSG cut 220 penetrates the TSG conductive layer 980 to separate the TSG 334. The TSG cut 220 may include any suitable insulating material disposed inside the TSG cut opening 774 after the TSG conductive layer 980 has been removed from the sidewalls and bottom of the TSG cut opening 774. Figure 9 The insulating material for the TSG notch 220 may include silicon oxide, silicon nitride, silicon oxynitride, boron or phosphorus-doped silicon oxide, carbon-doped oxide (CDO or SiOC or SiOC:H), or fluorine-doped oxide (SiOF), or any combination thereof. The insulating material for the TSG notch 220 may be deposited using, for example, ALD, CVD (e.g., PECVD, RTCVD, LPCVD, etc.), PVD, sputtering, evaporation, or any other suitable film deposition technique.

[0104] In some embodiments, the insulating material of the TSG cutout 220 disposed outside the TSG cutout opening 774 (e.g., on top of the capping layer 672) can be removed by dry / wet etching (e.g., RIE) and / or CMP. Any residual TSG conductive layer 980 and / or TSG dielectric layer 978 on the top of the capping layer 672 can also be removed. Therefore, the top surface of the TSG cutout 220 can be coplanar with the top surface of the capping layer 672.

[0105] As previously described, the TSG notch 220 can separate the TSG conductive layer 980 to form individual TSGs 334. Each TSG 334 can be controlled independently. In some embodiments, a top-select transistor 981 (e.g., a metal-oxide-semiconductor field-effect transistor or "MOSFET") can be formed at the intersection between the TSG 334, the TSG dielectric layer 978, and the channel layer 338 of the channel structure 666. The top-select transistor 981 can be turned on or off to control the connection between the underlying channel layer 338 (e.g., a memory cell formed in a subsequent process) and the channel top plug 668 (and the bit line formed in a subsequent process). The top-select transistor 981 formed by method 400 does not have a charge trapping layer (or storage layer). The TSG dielectric layer 978 acts as the gate dielectric layer of the top-select transistor and may include a dielectric with a minimum number of defects or charge traps. In some embodiments, the TSG dielectric layer 978 may have fewer charge traps or defects than the charge trapping layer 337-2 in the storage film 337, for example, a density of less than 10. 12 cm 2 When a voltage is applied to the TSG 334 to turn the top-select transistor 981 on or off, the threshold voltage offset of the top-select transistor 981 due to charge trapping can be reduced or eliminated. By removing the charge trapping layer 337-2 and forming a MOSFET structure using the TSG dielectric layer 978, the top-select transistor can be turned on and off at a higher speed and with less hysteresis, where the threshold voltage offset of the top-select transistor can be minimized. Charge transfer during programming and erasing cycles can also be minimized in the top-select transistor 981. Therefore, the reliability of the top-select transistor 981 can be improved. Because only a few process steps are changed, method 400 is compatible with other processes in 3D memory fabrication.

[0106] like Figure 2As shown, the TSG notch 220 extends laterally along the WL direction and can divide the memory block into multiple sub-memory cells (e.g., memory fingers 218). In some embodiments, the TSG notch 220 can further divide the memory fingers 218 into multiple memory slabs 224. The TSG notch 220 electrically isolates the TSGs 334, allowing each TSG 334 and its corresponding top select transistor to be controlled independently. Thus, each memory slab 224 can be controlled independently of each other, which effectively reduces programming, reading, and erasing times, as well as data transfer times. This improves data storage efficiency.

[0107] When process step S440 is completed, the alternating dielectric stack 554 includes two sub-stacks. The top stack includes a TSG conductive layer 980 and a first dielectric layer 556, while the bottom stack includes a first dielectric layer 556 and a second dielectric layer 558.

[0108] refer to Figure 4 In process step S445, a gate gap (GLS) opening can be formed in the alternating dielectric stack. In process step S450, the second dielectric layer in the alternating dielectric stack can be replaced by a second conductive layer to form a film stack of alternating conductive and dielectric layers. Figure 11 A cross-sectional view of an exemplary 3D storage structure 1100 according to process steps S445 and S450 is shown.

[0109] like Figure 11 As shown, the 3D memory structure 1100 includes a gate slot (GLS) opening 1182 formed in an alternating dielectric stack 554. The GLS opening 1182 vertically penetrates the TSG conductive layer 980 and the alternating dielectric stack 554. In some embodiments, the GLS opening 1182 also penetrates the cap layer 672 and the top dielectric stack 564. In some embodiments, the GLS opening 1182 extends into the substrate 330. The GLS opening 1182 can be formed by photolithography and etching processes. The etching process can include any suitable dry etching, wet etching, and / or combinations thereof. In subsequent processes, the GLS opening 1182 can be used to form, for example... Figure 2 The slit structure 216 shown is also called a GLS. Similar to GLS 216, the GLS opening 1182 can extend laterally along the WL direction (see...). Figure 2 ).

[0110] In process step S450, the second dielectric layer 558 in the alternating dielectric stack 554 and the stepped structure 550 can be removed through the GLS opening 1182. Figure 10To form lateral channels, similar to process step S430. Lateral channels may extend laterally between adjacent first dielectric layers 556. Note that the term "lateral / laterally" as used herein refers to a plane parallel to the top surface 330f of the substrate 330. A second dielectric layer 558 in the alternating dielectric stack 554, also referred to as a sacrificial layer, may be selectively removed between the first dielectric layers 556. In other words, the etching process of the second dielectric layer 558 may have minimal impact on the first dielectric layers 556. The second dielectric layer 558 may be removed by isotropic dry etching and / or wet etching. The plasma and / or chemicals used in the dry / wet etching may travel vertically and laterally from the GLS opening 1182. In some embodiments, the second dielectric layer 558 may be silicon nitride, and the first dielectric layer 556 may be silicon oxide. In this example, the second dielectric layer 558 can be removed by a RIE using one or more etchants such as CF4, CHF3, C4F8, C4F6, and CH2F2. In some embodiments, a wet etching process such as phosphoric acid can be used to remove the second dielectric layer 558.

[0111] In some embodiments, the second dielectric layer 558 may also be selectively removed from the TSG conductive layer 980, such that the TSG conductive layer 980 is not etched or is minimally etched. In some embodiments, the second dielectric layer 558 may also be selectively removed from the TSG dielectric layer 978, such that the TSG dielectric layer 978 is not etched or is minimally etched. In one example, the TSG dielectric layer 978 and the first dielectric layer 556 are silicon oxide.

[0112] Next, the second conductive layer 1184 can be disposed inside the transverse channel through the GLS opening 1182. The second conductive layer 1184 can be disposed between adjacent first dielectric layers 556. The TSG conductive layer 980, the second conductive layer 1184, and the first dielectric layer 556 can form an alternating film stack 335 of conductive and dielectric layers (e.g., Figure 3 As shown above, the membrane stack 335 may also include a TSG dielectric layer 978.

[0113] In some embodiments, the second conductive layer 1184 can be formed by filling the lateral channels with a suitable conductive material. The conductive material of the second conductive layer 1184 may include metals or metal alloys, such as tungsten (W), aluminum (Al), titanium (Ti), copper (Cu), cobalt (Co), nickel (Ni), titanium nitride (TiN), tungsten nitride (WN), tantalum (Ta), tantalum nitride (TaN), AlTi, or any combination thereof. In some embodiments, the conductive material for the second conductive layer 1184 may also include polycrystalline semiconductors, such as polycrystalline silicon, polycrystalline germanium, polycrystalline germanium-silicon, and any other suitable materials, and / or combinations thereof. In some embodiments, the polycrystalline material may incorporate any suitable n-type or p-type dopant, such as boron, phosphorus, arsenic, or any combination thereof. In some embodiments, the second conductive layer 1184 may also be an amorphous semiconductor, such as amorphous silicon. In some embodiments, a suitable deposition method may be used to deposit the conductive material, such as chemical vapor deposition (CVD) (e.g., LPCVD, PECVD, MOCVD, RTCVD, etc.), physical vapor deposition (PVD), sputtering, evaporation, atomic layer deposition (ALD), or any combination thereof. In some embodiments, the second conductive layer 1184 comprises a conductive material different from that of the TSG conductive layer 980. In some embodiments, the second conductive layer 1184 comprises tungsten (W) deposited by CVD, while the TSG conductive layer 980 comprises polycrystalline silicon doped with an n-type dopant (e.g., phosphorus).

[0114] As described above, by replacing the second dielectric layer 558 with the TSG conductive layer 980 and the second conductive layer 1184, the alternating dielectric stack 554 becomes a film stack 335 of alternating conductive and dielectric layers. Therefore, the channel structure 666 formed in the alternating dielectric stack 554... Figure 10 The middle section becomes storage string 212. The intersection of storage string 212 and membrane stack 335 forms vertically stacked storage cells 340. As described above, in some embodiments, membrane stack 335 and storage string 212 further include TSG dielectric layer 978.

[0115] It should be understood that although the film stack 335 here is formed by substitution (i.e., replacing the second dielectric layer 558 with the TSG conductive layer 980 and the second conductive layer 1184), the film stack 335 can also be formed by other means, for example, by directly depositing the TSG conductive layer 980, the second conductive layer 1184 and the first dielectric layer 556 on the substrate 330.

[0116] In some embodiments, the gate dielectric layer 1186 may be disposed within the lateral channel prior to the second conductive layer 1184. The gate dielectric layer 1186 may include any suitable insulator, such as silicon oxide, silicon nitride, silicon oxynitride, and / or any suitable combination thereof. The gate dielectric layer 1186 may also include a high-k dielectric material, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, and / or any combination thereof. The gate dielectric layer 1186 may be disposed using one or more suitable deposition processes, such as CVD, PVD, and / or ALD. The gate dielectric layer 1186 may include a dielectric material that is different from or the same as that of the TSG dielectric layer 978.

[0117] In some embodiments, a first adhesion layer 1188 may be formed on the gate dielectric layer 1186 before the second conductive layer 1184 is formed. The first adhesion layer 1188 may be used to promote adhesion between the gate dielectric layer 1186 and the second conductive layer 1184. The first adhesion layer 1188 may include, for example, tantalum nitride (TaN) and / or titanium nitride (TiN).

[0118] In some embodiments, etching and cleaning processes can be used to remove excess conductive material from the sidewalls of the second conductive layer 1184 located at the GLS opening 1182. This allows each of the second conductive layer 1184 and the TSG conductive layer 980 to be electrically isolated from each other. In some embodiments, the second conductive layer 1184 may be recessed back from the sidewalls of the GLS opening 1182. In some embodiments, excess conductive material on top of the cap layer 672 can also be removed, for example, by CMP or dry / wet etching processes.

[0119] When process step S450 is completed, the film stack 335 with alternating conductive and dielectric layers includes two sub-stacks. The top stack of the film stack 335 includes a TSG conductive layer 980 and a first dielectric layer 556, and the bottom stack of the film stack 335 includes a first dielectric layer 556 and a second conductive layer 1184.

[0120] refer to Figure 4 In process step S455, the GLS conductive core can be placed inside the GLS opening to form the GLS. Figure 12 A cross-sectional view of an exemplary 3D storage structure 1200 according to process step S455 is shown.

[0121] like Figure 12 As shown, the 3D storage structure 1200 includes GLS 216 (also known as...) Figure 2-3 The slit structure 216 is shown. The GLS 216 vertically penetrates the film stack 335 of alternating conductive and dielectric layers and extends into the substrate 330.

[0122] GLS 216 includes a GLS opening 1182 (in Figure 11 A GLS isolation layer 1290 is located on the sidewall of the second conductive layer 1184 exposed inside the GLS opening 1182. The GLS isolation layer 1290 covers the sidewall of the second conductive layer 1184. The GLS isolation layer 1290 may comprise any suitable insulator, such as silicon oxide, silicon nitride, silicon oxynitride, boron or phosphorus-doped silicon oxide, carbon-doped oxide (CDO, SiOC, or SiOC:H), or fluorine-doped oxide (SiOF), or any combination thereof. The GLS isolation layer 1290 may be deposited using, for example, ALD, CVD (e.g., PECVD, RTCVD, LPCVD, etc.), PVD, sputtering, evaporation, or any other suitable film deposition technique.

[0123] In some embodiments, before depositing the GLS isolation layer 1290, a portion of the second conductive layer 1184 disposed on the bottom of the GLS opening 1182 can be removed by a dry or wet etching process. Therefore, a portion of the substrate 330 can be exposed inside the GLS opening 1182 before depositing the GLS isolation layer 1290. In some embodiments, a portion of the GLS isolation layer 1290 disposed on the bottom of the GLS opening 1182 can also be removed by a dry or wet etching process after depositing the GLS isolation layer 1290 to expose the portion of the substrate 330 inside the GLS opening 1182.

[0124] GLS 216 also includes a GLS conductive core 1294 disposed within the GLS opening 1182. The GLS conductive core 1294 is filled with a conductive material in the GLS opening 1182. The GLS conductive core 1294 can contact the exposed portion of the substrate within the GLS opening 1182 to form an electrical connection with the substrate 330.

[0125] In some embodiments, the conductive core 1294 may comprise a metal or metal alloy, such as tungsten (W), aluminum (Al), titanium (Ti), copper (Cu), cobalt (Co), nickel (Ni), titanium nitride (TiN), tungsten nitride (WN), tantalum (Ta), tantalum nitride (TaN), AlTi, or any combination thereof. In some embodiments, the conductive core 1294 may also comprise a polycrystalline semiconductor, such as polycrystalline silicon, polycrystalline germanium, polycrystalline germanium-silicon, and any other suitable material, and / or combinations thereof. In some embodiments, the polycrystalline material may incorporate any suitable n-type or p-type dopant, such as boron, phosphorus, arsenic, or any combination thereof. In some embodiments, the conductive core 1294 may also comprise an amorphous semiconductor, such as amorphous silicon. In some embodiments, the conductive core 1294 may also comprise a metal silicide, such as WSi. x CoSi x NiSi x TiSix or AlSi x In some embodiments, the conductive core 1294 may comprise any combination of the conductive materials described above. The conductive core 1294 may be formed using any suitable deposition method, such as CVD (e.g., LPCVD, RTCVD, PECVD, etc.), PVD, ALD, sputtering, evaporation, plating, or any combination thereof. In some embodiments, the conductive core 1294 comprises tungsten (W) deposited by CVD.

[0126] In some embodiments, the GLS 216 may further include a second adhesion layer 1292 disposed on a sidewall of the GLS isolation layer 1290 within the GLS opening 1182. The second adhesion layer 1292 may be used to facilitate adhesion between the GLS isolation layer 1290 and the GLS conductive core 1294. In some embodiments, the second adhesion layer 1292 may contact an exposed portion of the substrate 330 within the GLS opening 1182, wherein the second adhesion layer 1292 may facilitate adhesion between the GLS conductive core 1294 and the substrate 330. The second adhesion layer 1292 may include a thin conductive film, such as tantalum nitride (TaN) and / or titanium nitride (TiN).

[0127] In some embodiments, the GLS contact structure 1296 may be formed on the top portion of the GLS 216, contacting the GLS conductive core 1294 at the end remote from the substrate 330. First, the GLS conductive core 1294 may be recessed downwards using a dry or wet etching process to form a cavity on top. Then, a conductive material may be disposed within the cavity. The GLS contact structure 1296 may comprise any suitable conductive material, such as tungsten, cobalt, copper, aluminum, titanium, nickel, titanium nitride, tungsten nitride, tantalum, tantalum nitride, AlTi, or any combination thereof.

[0128] In some embodiments, the GLS contact structure 1296, GLS conductive core 1294, second adhesion layer 1292, and GLS isolation layer 1290 located outside the GLS opening 1182 can be removed by dry or wet etching processes and / or CMP. As a result, GLS 216 can be coplanar with the capping layer 672.

[0129] As mentioned earlier, GLS 216 can divide a storage block into multiple functional units (e.g., Figure 2 (Memory reference 218). GLS 216 can also provide mechanical support in the channel structure region 211. GLS 216 can be provided to the substrate 330 or the array common source ( Figure 12 Electrical connections (not shown). In some embodiments, GLS 216 can be used for electrical connections with peripheral circuitry fabricated on substrate 330.

[0130] According to some embodiments, this disclosure also provides a 3D memory device. The structure of the 3D memory device is as follows: Figure 12 The above can be shown and summarized as follows.

[0131] 3D storage device 1200 includes a film stack 335 of alternating conductive and dielectric layers, having a top stack 335-1 and a bottom stack 335-2. The top stack 335-1 includes one or more TSG conductive layers 980 (also referred to as first conductive layers) and one or more first dielectric layers 556. The first conductive layers 980 and first dielectric layers 556 are alternately stacked on the bottom stack 335-2 in a first direction perpendicular to the substrate 330. The bottom stack 335-2 includes a plurality of first dielectric layers 556 and a plurality of second conductive layers 1184, wherein the first dielectric layers 556 and second conductive layers 1184 are alternately stacked on the substrate 330 in the first direction. Note that the top stack 335-1 and the bottom stack 335-2 may include different dielectric layers. For example, the top stack 335-1 may include a third dielectric layer different from the first dielectric layer 556, wherein the third dielectric layer and the first conductive layer 980 may be alternately stacked on the bottom stack 335-2. The film stack 335 extends in a surface parallel to the front surface 330f of the substrate 330. In some embodiments, the film stack 335 may also include other materials or layers. For example, one or more dielectric layers may be disposed between the top stack 335-1 and the bottom stack 335-2.

[0132] The first dielectric layer 556 comprises any suitable insulating material, such as silicon oxide, silicon oxynitride, silicon nitride, TEOS, or silicon oxide incorporating F-, C-, N-, and / or H- groups. The first dielectric layer 556 may have the same or different thicknesses, ranging from 10 nm to 500 nm. In some embodiments, the first dielectric layer 556 may be silicon oxide with a thickness of approximately 25 nm.

[0133] The first conductive layer 980 and the second conductive layer 1184 may comprise any suitable metal or metal alloy, such as tungsten (W), aluminum (Al), titanium (Ti), copper (Cu), cobalt (Co), nickel (Ni), titanium nitride (TiN), tungsten nitride (WN), tantalum (Ta), tantalum nitride (TaN), AlTi, or any combination thereof. The first conductive layer 980 and the second conductive layer 1184 may comprise polycrystalline semiconductors, such as polycrystalline silicon, polycrystalline germanium, polycrystalline germanium-silicon, and any other suitable materials, and / or combinations thereof. In some embodiments, the polycrystalline material may be incorporated (i.e., doped) with any suitable n-type or p-type dopant, such as boron, phosphorus, arsenic, or any combination thereof. In some embodiments, the first conductive layer 980 and the second conductive layer 1184 may also comprise amorphous semiconductors (e.g., amorphous silicon) or any combination of the above-described conductive materials. The first conductive layer 980 and the second conductive layer 1184 may have the same or different conductive materials. The first conductive layer 980 and the second conductive layer 1184 may have the same or different thicknesses, ranging from 10 nm to 500 nm. In some embodiments, the second conductive layer 1184 comprises W with a thickness of about 35 nm, and the first conductive layer 980 comprises phosphorus-doped polycrystalline silicon with a thickness of about 50 nm.

[0134] The film stack 335 may further include a gate dielectric layer 1186 surrounding a second conductive layer 1184 in the bottom stack 335-2 and a TSG dielectric layer 978 surrounding a first conductive layer 980 in the top stack 335-1. The gate dielectric layer 1186 and the TSG dielectric layer 978 may include any suitable insulator, such as silicon oxide, silicon oxynitride, and / or any suitable combination thereof. The gate dielectric layer 1186 and the TSG dielectric layer 978 may also include a high-k dielectric material, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, and / or any combination thereof.

[0135] In the bottom stack 335-2, the gate dielectric layer 1186 contacts a portion of the storage film 337 and the second conductive layer 1184, wherein a portion of the storage film 337 contacts the channel layer 338. As previously described, the storage film 337 includes a storage layer comprising a charge-trapping dielectric material. The charge trapped (or stored) in the storage layer can cause a threshold voltage shift in the corresponding channel layer. Conversely, in the top stack 335-1, the TSG dielectric layer 978 contacts a portion of the channel layer 338 and the TSG conductive layer 980. Unlike the storage film 337 (e.g., the storage layer), the TSG dielectric layer 978 comprises a dielectric material with a smaller number of charge traps, such that the threshold voltage shift in the channel layer 338 can be minimized. In some embodiments, in the top stack 335-1, the TSG conductive layer 980 and / or the TSG dielectric layer 978 penetrate laterally at least into the charge trapping layer 337-2 of the storage film 337 to separate the charge trapping layer 337-2 along a second direction parallel to the substrate 330.

[0136] In some embodiments, the film stack 335 may further include a first adhesion layer 1188 sandwiched between the gate dielectric layer 1186 and the second conductive layer 1184. In some embodiments, the film stack 335 may further include a first adhesion layer 1188 sandwiched between the TSG dielectric layer 978 and the first conductive layer 980. The first adhesion layer 1188 may be used to promote adhesion between the gate dielectric layer 1186 and the second conductive layer 1184 and / or between the TSG dielectric layer 978 and the first conductive layer 980. The first adhesion layer 1188 may include, for example, tantalum nitride (TaN) and / or titanium nitride (TiN).

[0137] The 3D storage device 1200 also includes a stepped structure 550 formed in a film stack 335 within a stepped region 210. The stepped structure 550 includes a plurality of stepped steps. A stepped step, or “stepped layer,” refers to a stack of layers having the same lateral dimensions, parallel to the first conductive layer 980, the second conductive layer 1184, and the first dielectric layer 556. Each of the stepped steps terminates at a length shorter than the step below it.

[0138] The 3D storage device 1200 also includes an insulating layer 560 disposed on the stepped structure 550 and the film stack 335. The insulating layer 560 includes silicon oxide, silicon oxynitride, silicon nitride, TEOS, spin-coated glass, and low-k dielectric materials, such as carbon-doped oxides (CDO, SiOC, or SiOC:H) or fluorine-doped oxides (SiOF). In some embodiments, the insulating layer 560 may have a planar surface on the stepped structure 550.

[0139] The 3D memory device 1200 also includes a plurality of memory strings 212 located in the channel structure region 211, wherein the memory strings 212 penetrate the film stack 335 in a first direction. In some embodiments, the memory strings further extend into the substrate 330.

[0140] The 3D storage device 1200 includes a plurality of vertically stacked memory cells 340 formed at the intersection of a second conductive layer 1184 and a memory string 212 in a lower stack 335-2. The second conductive layer 1184 can act as word lines 333 (in... Figure 3 (in) to address memory cell 340. The second conductive layer 1184 located at the bottom portion of the second stack 335-2 (i.e., closer to the substrate 330) can act as the lower select gate (LSG) 332 (in Figure 3 (middle) to turn on or off the lower selection transistor of memory string 212, so that memory string 212 can interact with substrate 330 or the array common source in substrate 330 (middle) Figure 12 (Not shown in the image) Electrical connection or disconnection.

[0141] In some embodiments, the memory string 212 may have a cylindrical shape. The memory string 212 may include a core-filled film 339 located at a center, wherein the core-filled film 339 may be surrounded by a channel layer 338. The core-filled film 339 may include any suitable insulator, such as silicon oxide, silicon nitride, silicon oxynitride, spin-coated glass, boron or phosphorus-doped silicon oxide, carbon-doped oxide (CDO or SiOC or SiOC:H), fluorine-doped oxide (SiOF), or any combination thereof. The channel layer 338 may include any suitable semiconductor, such as polycrystalline silicon with a thickness ranging from about 10 nm to about 30 nm.

[0142] The bottom portion of the memory string 212 extending through the bottom stack 335-2 (where memory cells 340 are formed) also includes a memory film 337 covering the sidewalls of the channel layer 338 (i.e., surrounding the channel layer 338). The memory film 337 may be a composite layer comprising a tunneling layer 337-1, a memory layer 337-2 (also referred to as a "charge trapping layer"), and a barrier layer 337-3. In some embodiments, the tunneling layer 337-1, the memory layer 337-2, and the barrier layer 337-3 are arranged in the order described above in a direction from the center of the memory string 212 toward the outside of the memory string 212. The tunneling layer 337-1 may comprise silicon oxide, silicon nitride, or any combination thereof. The barrier layer 337-3 may comprise silicon oxide, silicon nitride, a high dielectric constant (high k) dielectric, or any combination thereof. The memory layer 337-2 may comprise silicon nitride, silicon oxynitride, silicon, or any combination thereof. In some embodiments, the storage film 337 includes an ONO dielectric (e.g., a tunneling layer including silicon oxide, a storage layer including silicon nitride, and a barrier layer including silicon oxide). In some embodiments, the thickness of the storage film 337 may be in the range of about 10 nm to about 50 nm.

[0143] The top portion of the memory string 212 extends through the top stack 335-1, wherein a top select transistor 981 may be formed at the intersection of the first conductive layer 980, the TSG dielectric layer 978 (and / or the tunneling layer 337-1), and the channel layer 338. The top select transistor 981 at the intersection between the first conductive layer 980 and the channel layer 338 does not include the charge trapping layer 337-2 of the memory film 337. That is, the charge trapping layer 337-2 is separated by a lateral structure along a second direction parallel to the substrate, wherein the lateral structure includes the first conductive layer 980. In some embodiments, the lateral structure further includes the TSG dielectric layer 978, wherein the TSG dielectric layer 978 is sandwiched between a portion of the TSG conductive layer 980 and the channel layer 338 in the second direction, and the TSG dielectric layer 978 contacts the charge trapping layer 337-2 and the TSG conductive layer 980 in the first direction. In some embodiments, the lateral structure further includes a tunneling layer 337-1 of the storage film, wherein the tunneling layer 337-1 is sandwiched between the TSG conductive layer 980 and the channel layer 338 in a second direction. A top selection transistor 981 is formed at the intersection of the TSG conductive layer 980 and the channel layer 338 in the second direction. This can be achieved by using a TSG 334 (in...) Figure 3 A voltage is applied to the first conductive layer 980 in the middle to turn the top selection transistor 981 on or off.

[0144] In some embodiments, the memory string 212 further includes an epitaxial plug 670 located at the bottom of the memory string 212. The epitaxial plug 670 may comprise any suitable semiconductor material, such as silicon, silicon germanium, germanium, gallium arsenide, gallium nitride, III-V compounds, or any combination thereof. In some embodiments, the epitaxial plug 670 may also comprise a polycrystalline semiconductor material, such as polycrystalline silicon. The epitaxial plug 670 extends through at least one of the second conductive layers 1184 at the bottom portion of the bottom stack 335-2, wherein a lower selection transistor may be formed at the intersection between the epitaxial plug 670 and at least one of the second conductive layers 1184 at the bottom portion of the bottom stack 335-2. The epitaxial plug 670 may be connected at a first end to the channel layer 338 of the memory string 212 and at a second end opposite to the first end to the substrate 330.

[0145] In some embodiments, the storage string 212 may further include a channel top plug 668 configured to provide electrical contact with the channel layer 338. (Bit lines of the 3D storage device 1200) Figure 12 (Not shown) The memory cell 340 can be addressed via the channel top plug 668. The channel top plug 668 may be amorphous silicon or polycrystalline silicon and may include metals, metal alloys and / or metal silicides, such as tungsten, titanium, tantalum, tungsten nitride, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, tungsten silicide, titanium silicide or combinations thereof.

[0146] In some embodiments, the 3D memory device 1200 further includes a TSG notch 220 extending vertically in a first direction within the top stack 335-1. The TSG notch 220 extends through the first conductive layer 980 and may be filled with an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, boron or phosphorus-doped silicon oxide, carbon-doped oxide (CDO, SiOC, or SiOC:H), or fluorine-doped oxide (SiOF), or any combination thereof. The TSG notch 220 may provide electrical isolation between adjacent TSGs 334. By forming the TSG notch 220, the first conductive layer 980 can be divided into two or more independently controllable TSGs 334.

[0147] The 3D memory device 1200 also includes a GLS 216 that perpendicularly penetrates the film stack 335 in a first direction. In some embodiments, the GLS 216 further extends into the substrate 330. The GLS 216 may include a GLS conductive core 1294 and a GLS isolation layer 1290 covering the sidewalls of the GLS conductive core 1294. In some embodiments, the GLS conductive core 1294 contacts the substrate 330 and can provide electrical connection to the substrate 330.

[0148] The GLS isolation layer 1290 may include any suitable insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, TEOS, etc. The GLS conductive core 1294 may include any suitable conductive material, such as tungsten (W), aluminum (Al), titanium (Ti), copper (Cu), cobalt (Co), nickel (Ni), titanium nitride (TiN), tungsten nitride (WN), tantalum (Ta), tantalum nitride (TaN), AlTi, or any combination thereof. In some embodiments, the conductive core 1294 may also include a polycrystalline semiconductor, such as polycrystalline silicon, polycrystalline germanium, polycrystalline germanium silicon, and any other suitable material, and / or combinations thereof. In some embodiments, the polycrystalline material may incorporate any suitable n-type or p-type dopant, such as boron, phosphorus, arsenic, or any combination thereof. In some embodiments, the conductive core 1294 may also include an amorphous semiconductor, such as amorphous silicon. In some embodiments, the conductive core 1294 may also include a metal silicide, such as WSi. x CoSi x NiSi x TiSi x or AlSi x In some embodiments, the conductive core 1294 may comprise any combination of the aforementioned conductive materials. In some embodiments, the conductive core 1294 comprises tungsten (W).

[0149] In some embodiments, the GLS 216 may further include a second adhesion layer 1292 sandwiched between the GLS conductive core 1294 and the substrate 330, and between the GLS conductive core 1294 and the GLS isolation layer 1290. The second adhesion layer 1292 may be used to promote adhesion between the GLS conductive core 1294 and the substrate 330 and / or the GLS isolation layer 1290. The second adhesion layer 1292 may include a thin conductive film, such as tantalum nitride (TaN) and / or titanium nitride (TiN).

[0150] In some embodiments, GLS 216 further includes a GLS contact structure 1296 that contacts the GLS conductive core 1294 on its top (end away from the substrate). The GLS contact structure 1296 may include any suitable conductive material, such as tungsten, cobalt, copper, aluminum, titanium, nickel, titanium nitride, tungsten nitride, tantalum, tantalum nitride, AlTi, or any combination thereof.

[0151] In some embodiments, the 3D storage device 1200 further includes a top dielectric stack 564 disposed on the insulating layer 560 and the film stack 335. In some embodiments, the 3D storage device 1200 further includes a capping layer 672 disposed on the top dielectric stack 564, which covers the memory string 212. In some embodiments, the memory string 212 also penetrates the top dielectric stack 564 and is coplanar with the top dielectric stack 564. In some embodiments, the GLS 216 and TSG notches 220 also penetrate the capping layer 675 and the top dielectric stack 564, and are coplanar with the capping layer 672.

[0152] As described above, the channel layer 338 of the memory string 212 can be connected to the bit line via a channel top plug 668, wherein the connection can be controlled by a top-select transistor 981. In this disclosure, the top-select transistor 981 is configured as a MOSFET, wherein the TSG dielectric layer 978 may be the gate dielectric of the MOSFET, and at least the charge trapping layer 337-2 of the memory film 337 is removed along a second direction at the intersection between the first conductive layer 980 and the channel layer 338. While the charge trapping layer 337-2 can provide charge trapping and storage for the memory cell 340, such that the threshold voltage of the memory cell 340 can be offset according to the voltage applied to the word line 333, such threshold voltage offset for the top-select transistor 981 is undesirable. By removing the charge trapping layer 337-2 between the first conductive layer 980 and the channel layer 338, the switching characteristics of the top-select transistor 981 can be improved. The TSG dielectric layer 978 may comprise a material different from the memory layer (or charge trapping layer) 337-2 of the memory film 337. Similarly, the first conductive layer 980 may also comprise a different material than the second conductive layer 1184. Therefore, the top selection transistor 981 can be optimized independently of the memory cell 340.

[0153] Notice, Figure 12 The arrangement or layout of TSG cutouts 220 and GLS 216 in the diagram is shown as an example only and should not be construed as limiting. Figure 2 As shown, GLS 216 can extend along the WL direction in a surface parallel to the top surface 330f of the substrate 330. GLS 216 can divide the second conductive layer 1184 into multiple electrodes (e.g., word lines 333), which are electrically isolated from each other and can be controlled independently. Therefore, GLS 216 can divide the memory array into, for example, multiple memory fingers 218, where memory strings 212 in the same memory finger 218 can share the same word line 333 and memory strings 212 in different memory fingers 218 can be controlled by individual word lines 333.

[0154] The TSG notch 220 can extend along the WL direction in a surface parallel to the top surface 330f of the substrate 330. The TSG notch 220 can divide the first conductive layer 980 into multiple electrically isolated and independently controllable electrodes (e.g., TSG 334). Therefore, the TSG notch 220 can further divide each memory finger 218 into multiple memory slabs 224, where memory strings 212 in the same memory slab 224 can be controlled by the same TSG 334 and memory strings 212 in different memory slabs 224 can be controlled by individual TSG 334. Thus, memory strings 212 in the memory array can be addressed with smaller cells during programming and read operations. The performance of the 3D NAND memory can be improved accordingly.

[0155] In summary, this disclosure provides a method for forming a three-dimensional (3D) memory device. The method includes the steps of: forming an alternating dielectric stack on a substrate, wherein the alternating dielectric stack includes a first dielectric layer and a second dielectric layer alternately stacked on the substrate; forming a channel structure penetrating the alternating dielectric stack in a first direction perpendicular to the substrate, wherein the channel structure includes a charge trapping layer extending in the first direction; removing at least one second dielectric layer at a top portion of the alternating dielectric stack to form a top select gate (TSG) notch channel and exposing a portion of the charge trapping layer in a second direction parallel to the substrate; removing the exposed portion of the charge trapping layer within the TSG notch channel; and forming a TSG conductive layer within the TSG notch channel.

[0156] This disclosure also provides a three-dimensional (3D) memory device. The 3D memory device includes a film stack having a bottom stack and a top stack. The bottom stack includes a first dielectric layer and a second conductive layer alternately stacked on a substrate, and the top stack includes a first conductive layer stacked on the bottom stack. The 3D memory device also includes a memory string penetrating the film stack in a first direction perpendicular to the substrate, wherein the memory string includes a charge trapping layer extending in the first direction. The charge trapping layer is separated by a lateral structure including the first conductive layer along a second direction parallel to the substrate.

[0157] The foregoing description of the specific embodiments so fully reveals the general nature of this disclosure that others can readily modify and / or adapt such specific embodiments for various applications by applying knowledge within the art, without requiring excessive experimentation and without departing from the general concept of this disclosure. Therefore, based on the disclosure and teachings presented herein, such modifications and adaptations are intended to fall within the meaning and scope of equivalents of the disclosed embodiments. It should be understood that phrases or terms in this document are for descriptive and not limiting purposes, and that the terminology or phrases in this specification should be interpreted by those skilled in the art based on the disclosure and teachings.

[0158] Embodiments of this disclosure have been described above with the aid of functional building blocks that illustrate specific implementations of functions and their relationships. For ease of description, the boundaries of these functional building blocks have been arbitrarily defined herein. Alternative boundaries may be defined provided the specified functions and their relationships are properly performed.

[0159] The summary and abstract may set forth one or more exemplary embodiments of the present disclosure as conceived by the inventors, but not necessarily all exemplary embodiments, and therefore are not intended to limit the present disclosure and the appended claims in any way.

[0160] The scope and extent of this disclosure should not be limited by any of the exemplary embodiments described above, and should be defined only by the following claims and their equivalents.

Claims

1. A method for forming a three-dimensional storage device, comprising: An alternating dielectric stack is provided, the alternating dielectric stack comprising a first dielectric layer and a second dielectric layer alternately stacked on a substrate; A channel structure is formed penetrating the alternating dielectric stack in a first direction perpendicular to the substrate, wherein the channel structure includes a charge trapping layer extending in the first direction; At least one second dielectric layer at the top portion of the alternating dielectric stack is removed to form a top selected gate cut-out channel, and a portion of the charge trapping layer is exposed in a second direction parallel to the substrate; Remove the exposed portion of the charge trapping layer inside the top select gate cut-out channel; A top selection gate conductive layer is disposed inside the top selection gate notch channel; Forming a gate slot opening that penetrates the alternating dielectric stack in the first direction; and The remaining second dielectric layer is removed through the gate gap opening, and the second dielectric layer is replaced with a second conductive layer to form a bottom stack, wherein the bottom stack comprises the second conductive layer and the first dielectric layer alternately stacked on the substrate; Specifically, a third dielectric layer is formed through the gate gap opening before the second conductive layer is formed. At the location corresponding to the second conductive layer, the third dielectric layer is located between the channel structure and the second conductive layer in the second direction, and At a location corresponding to the top selected gate conductive layer, the top selected gate conductive layer is located between the channel structure and the third dielectric layer in the second direction.

2. The method according to claim 1, further comprising: A top selected gate cutout opening is formed in at least one second dielectric layer extending in the first direction to the top portion of the alternating dielectric stack; as well as The at least one second dielectric layer is removed through the top selected gate cutout opening.

3. The method according to claim 2, further comprising: An insulating material is disposed inside the top select gate cutout opening to form a top select gate cutout, wherein the top select gate cutout separates the top select gate conductive layer into top select gates that are electrically isolated from each other.

4. The method according to claim 1, further comprising: Before setting the top selected gate conductive layer, a top selected gate dielectric layer is set, which includes fewer charge traps than the charge trapping layer.

5. The method according to claim 4, wherein, Setting the top selected gate dielectric layer includes setting silicon oxide, silicon oxynitride, or a combination thereof.

6. The method according to claim 1, wherein, Setting the top selected gate conductive layer includes setting polysilicon doped with n-type dopant.

7. The method according to claim 1, further comprising: A gate gap isolation layer is provided on the sidewall of the gate gap opening to form a gate gap, wherein the gate gap separates the second conductive layer into electrodes that are electrically isolated from each other.

8. The method according to claim 7, further comprising: After the gate gap isolation layer is applied, the gate gap opening is filled with a gate gap conductive core to provide an electrical connection with the substrate.

9. The method according to claim 1, wherein, Replacing the second dielectric layer with the second conductive layer includes: The second dielectric layer is removed from the gate slot opening to form a lateral channel in the second direction between the first dielectric layers; and A second conductive layer is disposed inside the transverse channel, wherein the second conductive layer comprises a conductive material different from the top selected gate conductive layer.

10. The method according to claim 9, wherein, The second conductive layer may be provided with tungsten, aluminum, titanium, cobalt, nickel, titanium nitride, tungsten nitride, tantalum, tantalum nitride, or any combination thereof.

11. The method according to claim 9, wherein, Removing the second dielectric layer includes selectively etching the second dielectric layer relative to the top selected gate conductive layer and the first dielectric layer.

12. The method according to claim 1, wherein, The formation of the channel structure includes: A channel hole is formed that penetrates the alternating dielectric stack in the first direction; A storage membrane is disposed on the sidewall of the channel hole, comprising: A barrier layer, a charge trapping layer, and a tunneling layer are sequentially disposed, wherein the charge trapping layer comprises a charge trapping dielectric material; A channel layer is formed on the sidewall of the storage membrane; and The channel holes are filled with a core-filled membrane.

13. The method according to claim 12, wherein, The barrier layer, the charge trapping layer and the tunneling layer are sequentially disposed of by sequentially disposing of silicon oxide, silicon nitride and silicon oxide.

14. A three-dimensional storage device, comprising: The membrane stack includes: The bottom stack comprises a first dielectric layer and a second conductive layer alternately stacked on a substrate; and The top stack includes a first conductive layer stacked on the bottom stack; A storage string penetrating the film stack in a first direction perpendicular to the substrate, wherein: The storage string includes a charge trapping layer extending in the first direction; and The charge trapping layer is separated by a lateral structure including the first conductive layer; The grid gap penetrating the membrane stack in the first direction; and Second dielectric layer, Wherein, at the position corresponding to the second conductive layer, the second dielectric layer is located between the memory string and the second conductive layer in a second direction perpendicular to the first direction; and At the location corresponding to the first conductive layer, the first conductive layer is located between the second dielectric layer and the memory string in the second direction.

15. The three-dimensional storage device according to claim 14, further comprising: A top select gate cutout is filled with an insulating material, wherein the top select gate cutout penetrates the first conductive layer in the first direction and separates the first conductive layer into top select gates that are electrically isolated from each other.

16. The three-dimensional storage device according to claim 14, wherein, The first conductive layer comprises a conductive material different from that of the second conductive layer.

17. The three-dimensional storage device according to claim 16, wherein, The first conductive layer comprises polycrystalline silicon doped with an n-type dopant.

18. The three-dimensional storage device according to claim 16, wherein, The second conductive layer comprises tungsten, aluminum, titanium, cobalt, nickel, titanium nitride, tungsten nitride, tantalum, tantalum nitride, or any combination thereof.

19. The three-dimensional storage device according to claim 14, wherein, The storage string also includes: Storage membrane, including: Tunneling layer; The charge trapping layer; and Barrier layer, wherein: The tunneling layer, the charge trapping layer, and the blocking layer are arranged in a direction from the interior of the memory string toward the exterior of the memory string; and The charge trapping layer includes a charge trapping material; and A channel layer extends in the first direction and covers the sidewalls of the storage membrane.

20. The three-dimensional storage device according to claim 19, wherein: The tunneling layer comprises silicon oxide; The charge trapping layer comprises silicon nitride; and The barrier layer comprises silicon oxide.

21. The three-dimensional storage device according to claim 14, wherein, The lateral structure also includes a top selected gate dielectric layer, which includes fewer charge traps than the charge trapping layer.

22. The three-dimensional storage device according to claim 21, wherein, The top selected gate dielectric layer includes silicon oxide, silicon oxynitride, or a combination thereof.

23. The three-dimensional storage device according to claim 21, wherein, The top selected gate dielectric layer contacts the charge trapping layer and the first conductive layer in the first direction.

24. The three-dimensional storage device according to claim 14, wherein, The gate gap includes a gate gap isolation layer that contacts the second conductive layer.

25. The three-dimensional storage device according to claim 24, wherein, The gate gap also includes a gate gap conductive core and is configured to provide an electrical connection with the substrate.

26. The three-dimensional storage device according to claim 14, wherein, The intersection point between the lateral structure and the memory string along the second direction is configured to act as a metal-oxide-semiconductor field-effect transistor (MOSFET).

27. The three-dimensional storage device according to claim 24, wherein, The gate gap isolation layer comprises at least one of the following materials: silicon oxide, silicon nitride, silicon oxynitride, TEOS, boron or phosphorus doped silicon oxide, carbon doped oxide, fluorine doped oxide, or any combination thereof, and the second dielectric layer comprises at least one of the following materials: hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, or any combination thereof.

28. The three-dimensional storage device according to claim 14, wherein, The second dielectric layer comprises a high-k dielectric material.

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