Thin film resistors (TFRs) formed in integrated circuit devices using wet etching of a dielectric cap

Abstract

A method for forming an integrated thin film resistor (TFR) in an integrated circuit (IC) device including an IC element and an IC element contact is provided. A TFR film layer and a TFR dielectric layer are formed over an IC structure, and a wet etch is performed to define a dielectric cap having a sloped lateral edge over the TFR film layer. An exposed portion of the TFR film layer is etched to define a TFR element. A TFR contact etch forms a contact opening over the TFR element, and a metal layer is formed to form a metal layer connection to the IC element contact and the TFR element. The sloped edge of the dielectric cap can improve removal of metal adjacent to the TFR element to prevent electrical shorts in the completed device. A TFR anneal to reduce TCR of the TFR is performed at any suitable time prior to forming the metal layer.

Description

[0001] Related patent applications

[0002] This application claims priority to jointly owned U.S. Provisional Patent Application No. 62 / 982,107, filed February 27, 2020, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] This disclosure relates to methods for forming thin-film resistors, such as systems and methods for forming thin-film resistors integrated in semiconductor integrated circuit (IC) devices. Background Technology

[0004] Many integrated circuit (“IC”) devices incorporate thin-film resistors (TFRs), which offer a variety of advantages over other types of resistors. For example, TFRs can be highly accurate and can be fine-tuned to provide very precise resistance values. Furthermore, TFRs typically have low parasitic components, which provides favorable high-frequency behavior. Additionally, TFRs often have a low temperature coefficient of resistance (TCR), for example, after a suitable annealing process that “tunes” the TCR to near zero, providing stable operation over a wide range of operating temperatures. TFR annealing can be performed above 500°C (e.g., in the range of 500°C to 525°C) to optimize the TCR value.

[0005] TFRs can comprise any suitable resistive film formed on or within an insulating substrate. Some common IC integrated TFR resistive film materials include SiCr, SiCCr, TaN, and TiN, but any other suitable material can also be used. Manufacturing integrated TFRs typically requires adding multiple processes to the back-end IC integration flow, such as several expensive photomask processes. Reducing the number of such steps, especially the number of photomask processes, to lower the cost of manufacturing integrated TFRs would be advantageous.

[0006] Another issue concerns the formation and annealing of TFRs in IC devices that use aluminum interconnect layers (e.g., interconnect layers formed of aluminum, aluminum-copper, or aluminum-silicon-copper) due to the relatively low melting point of aluminum. Common aluminum interconnect layers are formed as a stack, for example, a Ti layer followed by a TiN layer, then an AlSiC layer (or an AlCu or Al layer), followed by a second Ti layer, and finally a second TiN layer. Typical TFR annealing can involve temperatures of 500°C or higher, which can negatively impact such aluminum interconnects, where the acceptable annealing temperature limit is approximately 450°C. For example, in the aforementioned aluminum interconnect stack, if TFRs are formed and annealed after the aluminum interconnects are formed (e.g., at temperatures of 500°C or higher), TiAl3 will form at the grain boundaries within the interconnect stack. This increases the sheet resistance of the interconnects (e.g., by 50 times or more), and this increased sheet resistance can lead to electromigration problems in the IC structure. Summary of the Invention

[0007] Embodiments of the present invention address various problems of conventional TFR integration by forming a thin-film resistor (TFR) after the formation of IC elements (e.g., memory devices) and contacts (e.g., tungsten vias), but before the formation of the first metal / interconnect layer (typically referred to as "Metal 1" layer). By forming the TFR before forming the Metal 1 layer, TFR annealing can be performed at temperatures that would negatively affect the material of the Metal 1 layer, such as when aluminum (or other metals with low melting temperatures) is used for the Metal 1 layer. Therefore, forming the TFR (e.g., aluminum Metal 1 layer) before forming the Metal 1 layer allows for TFR annealing at optimal temperatures (e.g., to optimize the TFR film's TCR value), such as annealing at temperatures of 500°C or higher (e.g., in the range of 500°C to 525°C). Thus, embodiments of the present invention allow for the formation of TCR and optimal annealing in IC production flows utilizing aluminum interconnects.

[0008] As used herein, “forming” any particular material layer (or other structure) may include depositing the material layer, reinforcing the material layer (e.g., reinforcing an oxide layer), or otherwise forming the material layer, and may include various process steps known in the art for forming various types of layers in an IC structure.

[0009] Furthermore, as used herein, an “etching process” may include a single etch or multiple etches, which may include different etch chemistry compositions or other etch parameters.

[0010] In some implementations, the process of forming a TFR involves only adding two photomasks to the background IC production flow (i.e., IC production flow without forming a TFR).

[0011] In some embodiments, a disclosed method for forming a TFR in an IC device includes forming a cap-like oxide layer over a TFR film (e.g., a SiCCr film) and performing wet etching to remove portions of the cap-like oxide layer, thereby forming an oxide cap over the TFR film. Wet etching (compared to dry etching) can form a sloping (i.e., non-vertical) lateral edge of the oxide cap over the TFR film. The sloping edge of the oxide cap can facilitate (e.g., make it easier) the removal of metal adjacent to the TFR element (e.g., portions of deposited metal layer 1) to prevent electrical short circuits (often referred to as "longitudinal beams") in the complete device.

[0012] In one aspect of the invention, a method for forming an integrated thin-film resistor (TFR) in a semiconductor integrated circuit device is provided. An integrated circuit (IC) structure is formed, including a plurality of IC elements and a plurality of conductive IC element contacts connected to the plurality of IC elements. A TFR film layer is formed over the IC structure, and a TFR dielectric layer is formed over the TFR film layer. A wet etching process is performed to remove selected portions of the TFR dielectric layer, thereby leaving a TFR dielectric cap over the TFR film layer, wherein the wet etching stops at the TFR film layer, and wherein the wet etching defines a sloping lateral edge of the TFR dielectric cap. A TFR etching process is performed to remove selected portions of the TFR film layer (e.g., those not under the TFR dielectric cap), thereby defining a TFR element, wherein the sloping lateral edges of the TFR dielectric cap are aligned over the corresponding lateral edges of the TFR element. Then, TFR contact etching is performed to form TFR contact openings on the TFR dielectric cap above the TFR element, and a metal layer (e.g., "Metal 1" layer) is deposited above the conductive IC element contacts and above the TFR dielectric cap, extending into the TFR contact openings and contacting the TFR element.

[0013] TFR annealing can be performed at some point after the TFR film is formed but before the metal layer is deposited, for example, to reduce the thermal resistance coefficient (TCR) of the TFR film. For example, TFR annealing can be performed after the formation of the TFR film and the TFR dielectric layer, but before wet etching to define the TFR dielectric cap, or it can be performed after the TFR etching defining the TFR element, or at any other time after the formation of the TFR film but before the metal layer is deposited.

[0014] In some embodiments, the step of forming the metal layer includes depositing a conformal metal layer over the TFR dielectric cap and performing metal etching to remove selected portions of the conformal metal layer. The deposited conformal metal layer includes a sloping metal region extending over a corresponding sloping lateral edge of the TFR dielectric cap, wherein the sloping metal region has a lower height at a first location adjacent to the corresponding lateral edge of the TFR element compared to a second location above the top upper surface of the TFR dielectric cap. The metal etching for removing selected portions of the conformal metal layer includes removing a portion of the sloping metal region at the first location adjacent to the corresponding lateral edge of the TFR element. The lower height of the sloping metal region at the first location can allow for reduced etching time or intensity to remove the full thickness of the sloping metal region at the first location (e.g., compared to a similar structure where the TFR dielectric cap has a vertical lateral edge (i.e., deviating from a square edge) rather than a sloping lateral edge produced by wet etching of the TFR dielectric layer).

[0015] In one embodiment, the integrated circuit structure includes a memory cell or transistor structure, the memory cell or transistor structure including at least one conductive IC element contact connected to at least one of the source region, drain region and gate region of the memory cell or transistor structure.

[0016] In some implementations, the TFR film includes silicon chromium carbide (SiCCr), silicon chromium (SiCr), chromium silicon nitride (CrSiN), tantalum nitride (TaN), tantalum silicide (Ta2Si), or titanium nitride (TiN).

[0017] In one embodiment, the metal interconnect layer comprises aluminum.

[0018] In one embodiment, the TFR dielectric layer includes an oxide layer.

[0019] In one embodiment, an etch stop layer is formed over the IC structure prior to the formation of the TFR film, such that the TFR film is formed over the etch stop layer.

[0020] In one implementation, TFR etching includes dry etching.

[0021] In one embodiment, TFR annealing includes annealing at a temperature of at least 500°C. For example, TFR annealing may include annealing at a temperature of 515°C ± 10°C for 15 to 60 minutes (e.g., 30 minutes).

[0022] In another aspect of the invention, a method for forming an integrated thin-film resistor (TFR) in a semiconductor integrated circuit device is provided. An integrated circuit (IC) structure is formed, including a plurality of IC elements and a plurality of conductive IC element contacts connected to the plurality of IC elements. A first etch stop layer is formed over the IC structure. A TFR film layer is formed over the first etch stop layer, and a TFR dielectric layer is formed over the TFR film layer. A first photomask is formed and patterned over a portion of the TFR dielectric layer. A first etch process is performed to remove exposed portions of the TFR dielectric layer, thereby leaving a TFR dielectric cap below the first photomask and above the TFR film layer. The first etch process may include wet etching stopped at the TFR film, and the wet etching may define a sloping lateral edge of the TFR dielectric cap (e.g., as described above). A second dry etching process is performed to remove exposed portions of the TFR film layer, thereby defining a TFR element. A second photomask is formed and patterned to have at least one second mask opening aligned over the TFR element. A third etch process is performed to form at least one TFR contact opening in the TFR dielectric cap over the TFR element. A metal interconnect layer (e.g., "metal 1" layer) is formed over multiple conductive IC element contacts and over the TFR dielectric cap and the underlying TFR element, such that the formed metal interconnect layer extends into at least one TFR contact opening to contact the underlying TFR element. A third photomask is formed and patterned. Finally, a fourth etching process is performed to remove selected portions of the metal interconnect layer, thereby defining multiple metal interconnect elements.

[0023] TFR annealing is performed at some point after the TFR film is formed but before the metal interconnect layer is formed, for example, to reduce the thermal resistance coefficient (TCR) of the TFR film. For example, TFR annealing may be performed before or after the first etching process, before or after the second etching process, before or after the third etching process, or at any other time after the TFR film is formed but before the metal interconnect layer is formed.

[0024] In some implementations, as described above, the sloping lateral edges of the TFR dielectric can facilitate (e.g., make it easier) the removal of metal adjacent to the TFR element (e.g., a portion of the deposited metal layer 1) to prevent electrical short circuits (often referred to as “longitudinal beams”) in the complete device.

[0025] In one embodiment, the integrated circuit structure includes a memory cell or transistor structure, the memory cell or transistor structure including at least one conductive IC element contact connected to at least one of the source region, drain region and gate region of the memory cell or transistor structure.

[0026] In some implementations, the TFR film includes silicon chromium carbide (SiCCr), silicon chromium (SiCr), chromium silicon nitride (CrSiN), tantalum nitride (TaN), tantalum silicide (Ta2Si), or titanium nitride (TiN).

[0027] In one embodiment, the metal interconnect layer comprises aluminum.

[0028] In one embodiment, the TFR dielectric layer includes an oxide layer.

[0029] In one implementation, TFR annealing is performed before the metal interconnect layer is formed.

[0030] In some embodiments, TFR annealing includes annealing at a temperature in the range of 500°C to 525°C. For example, in some embodiments, TFR annealing includes annealing at a temperature of 515°C ± 10°C for 15 to 60 minutes (e.g., 30 minutes).

[0031] In one embodiment, the third etching process includes wet etching. In another embodiment, the third etching process includes dry etching.

[0032] In one embodiment, the fourth etching process defines a TFR interconnect element that provides a conductive connection between the TFR element and at least one of a plurality of conductive IC element contacts.

[0033] On the other hand, a semiconductor device is provided that includes a thin-film resistor (TFR) produced according to the disclosed method. Attached Figure Description

[0034] Example aspects of this disclosure are described below with reference to the accompanying drawings, in which:

[0035] Figures 1 to 12 The steps of an exemplary method for integrating a thin-film resistor (TFR) into a semiconductor integrated circuit (IC) device according to an exemplary embodiment of the present invention are shown; and

[0036] Figures 13A to 13C and Figures 14A to 14C This illustrates how the angled lateral edges of the TFR oxide cap can prevent or reduce electrical short circuits (often referred to as "longitudinal beams") in integrated TFRs. More specifically, Figures 13A to 13C The image shows a selected portion of the metal layer removed from a TFR oxide cap with sloping lateral edges. Figures 14A to 14C The image shows a selected portion of the metal layer deposited over a TFR oxide cap with vertical (“off-square”) lateral edges.

[0037] It should be understood that reference numerals for any illustrated element appearing in multiple different figures have the same meaning in all figures, and any illustrated element mentioned or discussed herein in the context of any particular figure also applies to every other figure (if any) in which the same illustrated element is shown. Detailed Implementation

[0038] Embodiments of the present invention provide an improved technique for integrating thin-film resistors (TFRs) into semiconductor integrated circuit (IC) devices, which offers cost reductions compared to conventional techniques, for example, by allowing TFR integration in conjunction with aluminum interconnects. In some embodiments, the TFR is formed after the IC element and IC element contacts (e.g., tungsten vias) are formed, but before the formation of the first metal / interconnect layer (“Metal 1” layer). This allows TFR annealing (e.g., to optimize the TCR value of the TFR film) to be performed, for example, at temperatures of 500°C or higher (e.g., in the range of 500°C to 525°C). Because the aluminum interconnects are formed only after TFR annealing (which are typically not resistant to the high temperatures experienced during typical TFR annealing), the annealed TFR can be integrated into IC devices using aluminum interconnects.

[0039] Furthermore, in some embodiments, the TFR may include an oxide cap (e.g., a SiCCr element) formed over the TFR element, wherein the cap oxide includes a sloping lateral edge aligned above the lateral edge of the TFR element, which can prevent or reduce the occurrence of electrical short circuits (commonly referred to as "beams") between the TFR element and adjacent metal structures (e.g., metal 1 structures) during operation of the IC device. In some embodiments, the cap oxide with sloping lateral edges can be formed by forming a cap oxide layer over the TFR film and performing wet etching to define the oxide cap with sloping lateral edges.

[0040] Figures 1 to 12 An exemplary method for integrating a thin-film resistor (TFR) into a semiconductor integrated circuit (IC) device according to an exemplary embodiment is shown.

[0041] Figure 1An exemplary integrated circuit (IC) structure 10 is shown (e.g., during the fabrication of an IC device). In this example, the IC structure 10 includes a transistor structure 12 formed over a substrate 13, wherein a plurality of conductive contacts 14 (e.g., tungsten vias) extend through an integral insulating region 20 formed over the transistor structure 12. However, the IC structure 10 may include any other IC device or structure, such as one or more wholly or partially memory cells or memory cell structures and conductive contacts associated with such structures. In this exemplary embodiment, the integral insulating region 20 includes (a) a high-density plasma (HDP) metal pre-dielectric (PMD) oxide layer 20A (e.g., formed after CMP); (b) a PMD oxide film 20B, such as PMD P TEOS (phosphorus-doped tetraethyl orthosilicate film); and (c) a PMD capping layer 20C.

[0042] Figure 1 It can represent the state during the IC manufacturing process after the formation of the tungsten through-hole 14 and the chemical mechanical polishing (W CMP) process at the top of the structure 10.

[0043] Next, as Figure 2 As shown, a TFR layer stack 30 is formed over the overall insulating region 20 and the conductive contact 14. First, a dielectric etch stop layer 32 (e.g., a SiN layer) may be formed, for example, to protect the tungsten via 14 from... Figure 5 The effect of subsequent TFR etching is shown. A thin resistive film layer (TFR film layer) 34 can then be formed on the first dielectric etch stop layer 32. The TFR film layer 34 may include SiCCr, SiCr, TaN, TiN, or any other suitable TFR material.

[0044] In some embodiments, TFR annealing can be performed at this time point, for example, to tune or optimize the temperature coefficient of resistance (TCR) of the TFR film 34. For example, annealing can be performed at a temperature ≥500°C. In some embodiments, TFR annealing may include annealing at 515°C ± 10°C for 15 to 60 minutes (e.g., 30 minutes). In other embodiments, it can be performed at any other time point during the process, as described below. Figure 10 TFR annealing is performed before the first metal layer / interconnect layer 60 (e.g., "metal 1" layer). For example, in some embodiments, TFR annealing may be performed before the formation of the layer described below. Figure 2 TFR annealing is performed after the TFR contact dielectric layer 36 is described. In other embodiments, TFR annealing may be performed after etching the TFR film layer 34 to define the TFR element 34A, as described below. Figure 5 and Figure 6As described above. In other embodiments, TFR annealing can be performed after TFR contact etching, as described below. Figure 9 As stated above.

[0045] After TFR annealing, a TFR contact dielectric layer 36 can be formed on the TFR film layer 34. In this embodiment, the TFR contact dielectric layer 36 includes an oxide layer.

[0046] like Figure 3 As shown, a first photomask 40 can be formed and patterned (e.g., using known photolithography techniques) to form a TFR, in this example, at a location laterally offset from the underlying transistor structure 12.

[0047] like Figure 4 As shown, wet etching can then be performed to remove the exposed portion of the TFR oxide layer 36 to define an oxide cap 36A below the photomask 40 and above the TFR film layer 34. As shown, the wet etching can be designed to stop at the TFR film layer 34 and can define a sloping (i.e., non-horizontal and non-vertical) lateral edge 44 of the TFR oxide cap 36A.

[0048] like Figure 5 As shown, dry etching can then be performed to remove the exposed portion of the TFR film layer 34, thereby defining the TFR element 34A below the oxide cap 36A. The dry etching can be designed to stop on the SiN etch stop layer 32. As shown, the inclined lateral edge 44 of the TFR oxide cap 36A formed by the above wet etching is aligned above the corresponding lateral edge 48 of the TFR element 34A. See below, for example, with reference to... Figures 13A to 13C and Figures 14A to 14C The sloping lateral edge 44 of the TFR oxide cap 36A can facilitate the removal of selected portions of the deposited metal layer 60 adjacent to the TFR element 34A to prevent electrical short circuits (commonly referred to as "longitudinal beams") in the complete device.

[0049] like Figure 6 As shown, the retained portion of the photoresist 40 can be stripped. In some embodiments, because the underlying tungsten contacts 14 are protected by the SiN etch stop layer 32, chemical cleaning can be used.

[0050] like Figure 7 As shown, the exposed portion of the SiN etch stop layer 32 can be removed, for example, by performing a gentle SiN removal etching, preferably with high selectivity for oxides, thereby protecting the underlying tungsten contacts 14. 32A indicates the retained portion of the SiN etch stop layer 32 beneath the TFR element 34A.

[0051] like Figure 8As shown, a second photomask 50 can then be formed and patterned to define a pair of mask openings 52 aligned above the TFR element 34A. TFR contact etching can then be performed to define a pair of TFR contact openings 56 in the TFR oxide cap 36A, stopping on the TFR element 34A, such that the TFR contact etching exposes the upper surface of the TFR element 34A within the TFR contact openings 56. The TFR contact etching can be wet etching or dry etching. Wet etching can improve metal flow during subsequent metal deposition (see...). Figure 9 However, this may increase the size of the TFR contact opening 56.

[0052] like Figure 9 As shown, the retained portion of the second photomask 50 can be removed, for example, by performing resist stripping.

[0053] like Figure 10 As shown, IC device processing can continue by forming a first metal layer / interconnect layer, referred to as "Metal 1" layer 60. In the illustrated embodiment, Metal 1 layer 60 comprises aluminum. In other embodiments, Metal 1 layer 60 may comprise copper or other metals. As shown, Metal 1 layer 60 extends into the TFR contact opening 56 formed in the TFR oxide cap 36A, thereby contacting the TFR element 34A on the opposite side of the TFR element 34A. Metal 1 layer 60 also extends over and contacts the tungsten contact 14.

[0054] Next, as Figure 11 As shown, a third photomask 70 can be formed, patterned, and etched to define a plurality of mask openings 72A, 72B, 72C to pattern the underlying metal layer 1.

[0055] Finally, as Figure 12 As shown, a plurality of metal layer openings 61A, 61B, 61C and aluminum metal elements (e.g., interconnect elements) 62A to 62D can be defined by performing metal etching through mask openings 72A, 72B, 72C to etch selected portions of aluminum metal layer 60. After metal etching, the retained photoresist material 70 can then be removed. For example, as shown, the metal etching can define aluminum interconnect elements 62A and 62B in contact with tungsten via 14, and aluminum interconnect elements 62C and 62D in contact with the opposite side of TFR element 34A. In this example illustration, the first aluminum interconnect element 62C is conductively connected to a first side of TFR element 34A via tungsten via 14 connected to the source or drain region of transistor 12, and the second interconnect element 62D is conductively connected to a second side of TFR element 34A with other IC element structures (not shown). TFR element 34A, the first interconnect element 62C, and the second interconnect element 62D together define the integrated TFR represented at 80.

[0056] As described above, the sloping lateral edge 44 of the TFR oxide cap 36A can facilitate the removal of selected portions of the metal layer 60 adjacent to selected lateral edges of the TFR element 34A, for example, to prevent electrical short circuits (“longitudinal beams”) caused by retained portions of the metal layer 60 (after metal etching) between interconnect elements 62C and 62D, which physically connect interconnect elements 62C and 62D, i.e., metal contacts on opposite sides of the TFR element 34A.

[0057] Figures 13A to 13C and Figures 14A to 14C A comparative example illustration is provided showing how the sloping lateral edge 44 of the TFR oxide cap 36A and a similar structure of the TFR oxide cap having vertical (“off-square” lateral edges) lateral edge can facilitate the removal of selected portions of the metal layer 60 (to physically separate interconnect elements 62C and 62D from each other). Figures 13A to 13C It is by Figure 11 and 12 The diagram shows a cross-sectional view of a selected portion of the IC structure 10 defined by the cutting line AA, which extends into the page, such that... Figures 13A to 13C The cross-section shown is vertical. Figures 1 to 12 The cross-section shown. Conversely, Figures 14A to 14C This is a cross-sectional view of a selected portion of IC structure 10', which is similar to IC structure 10 but has the same characteristics as... Figures 1 to 12 and Figures 13A to 13C The TFR oxide cap 36A in the middle has an inclined lateral edge 44 opposite to the TFR oxide cap having a vertical ("off-square") lateral edge.

[0058] Figure 13A and Figure 14A This illustrates the deposition of a metal layer 60 on a surface with a sloping lateral edge 44 (hereinafter referred to as the sloping oxide cap edge 44). Figure 13A Selected portions of IC structure 10 after the TFR oxide cap 36A is deposited, and selected portions of IC structure 10' after the metal layer 60' is deposited above the TFR oxide cap 36A' having a vertical lateral edge 44' (hereinafter referred to as vertical oxide cap edge 44'). Deposition (denoted as T) 金属 The same metal thickness is used for metal layer 60 and metal layer 60'.

[0059] therefore, Figure 13A Corresponding to Figure 11 The state of the IC structure 10 shown is after the photomask 70 is formed and patterned over the metal layer 60, and before the metal is etched to define metal elements 62A to 62D. Figure 13A As shown in the figure, the cross section shown is located at Figure 11 Within the mask opening 72C shown. In this example, the metal 60 in the shown cross-section should be completely removed by metal etching through the mask opening 72C to remove any conductive connection provided by the metal 60 between the metal interconnect element 62C and the metal interconnect element 62D (i.e., the metal contacts on the opposite side of the TFR element 34A), thereby preventing electrical short circuits (“longitudinal beams”) across the TFR element 34A. Figure 13A and Figure 14A As shown, the thickest portions of metal layers 60 and 60' are positioned adjacent to the lateral edges 48 and 48' of TFR elements 34A and 34A', typically indicated at positions 64 and 64', and therefore the metal etching should be sufficient to remove the full metal thickness at these locations. As will be explained below, the inclined oxide cap edge 44 reduces the metal thickness at these locations, thus reducing the required metal etching parameters, such as etching time or etching intensity.

[0060] Figure 13A and Figure 13B The metal layers 60' and 60' shown may each comprise an aluminum layer, such as Al, AlCu, and AlSiCu, applied as a sputtered film. As is known in the art, physical sputtered films such as Al, AlCu, and AlSiCu are typically not perfectly conformal. A “slice” pattern occurs above the upper corner of the physical structure, for example, as shown in the image. Figure 13A The 66 locations shown, and in Figure 14A At position 66'. As shown in the figure, with... Figure 14A Compared to the vertical oxide cap edge 44' shown, Figure 13A The sloping oxide cap edge 44 shown reduces the degree of "slicing" at the upper corner. This reduced "slicing" effect, along with the downward sloping profile of the metal layer 60 above the sloping oxide cap edge 44, results in a lower vertical metal thickness T adjacent to the lateral edge 48 of the TFR element 34A. 金属_倾斜_盖 (that is, in) Figure 13A (At position 64 shown), the vertical metal thickness T is less than that adjacent to the lateral edge 48' of the TFR element 34A' of IC structure 10'. 金属_方形_盖 (that is, in) Figure 14A (The location shown is at 64'). Therefore, compared to T 金属_倾斜_盖 With smaller T 金属_方形_盖 It can be seen that the maximum vertical thickness of the metal to be removed during metal etching (to prevent electrical short circuits across TFR element 34A or across TFR element 34A') is reduced due to the inclined oxide cap edge 44 (compared to the vertical oxide cap edge 44').

[0061] Figure 13B and Figure 14BThe diagram shows selected portions of IC structure 10 and IC structure 10' during metal etching to remove their respective metal layers 60 and 60', which indicates... Figure 11 and Figure 12 The temporal states between the states shown. In particular, Figure 13B and Figure 14B This shows the state during etching, in which each metal layer 60 and metal layer 60' (each having a thickness T) 金属 The horizontal region of the 34A and 34A' has been removed, while the regions of metal layer 60 and metal layer 60' at the lateral edges 48 and 48' of each TFR element 34A and 34A' remain. As shown in the figure, the region with the inclined oxide cap edge 44 ( Figure 13B The maximum retained metal thickness T in the structure 金属_倾斜_盖 Smaller than the structure with a square oxide cap edge of 44' ( Figure 14B The maximum retained metal thickness T in ) 金属_方形_盖 Therefore, a shorter etching time (or etching intensity) is required for complete removal.

[0062] Figure 13C and Figure 14C The diagram shows selected portions of IC structures 10 and 10' after an additional etching time (over-etching), particularly in the thickest region of metal layer 60 (at T). 金属_倾斜_盖 The time at which the part was completely removed. Therefore... Figure 13C Corresponding to Figure 12 The state of IC structure 10 is shown. As shown in the figure, at the edge 44' of the square oxide cap ( Figure 14C In the structure of IC structure 10, when the metal layer 60 ( Figure 13C When ) has been completely removed, the thickness of the metal at this point is 60' (T) 金属_方形_盖 The area (represented by the reference point) remains unchanged. Therefore, the angled oxide cap edge 44 formed in the IC structure 10 reduces the required etching time (or etching intensity) to completely remove the metal 60 to prevent electrical short circuits across the TFR element 34A. The reduced etching time (or etching intensity) allows for a thinner photoresist 70 (…). Figure 11 This allows for a more compact IC structure 10 (e.g., with the use of a square cap-shaped edge 44'). Figures 14A to 14C Compared to the IC structure of the previous generation, the metal line spacing is reduced. This reduction in metal line spacing allows for an overall reduction in the size of the IC structure 10, which allows for more IC devices per chip, thus reducing the cost per device.

[0063] Although this disclosure describes the disclosed embodiments in detail, it should be understood that various changes, substitutions and modifications can be made to these embodiments without departing from the spirit and scope of the invention.

Claims

1. A method for forming an integrated thin-film resistor (TFR) in a semiconductor integrated circuit device, the method comprising: An integrated circuit (IC) structure is formed, the IC structure including multiple IC elements and multiple conductive IC element contacts connected to the multiple IC elements; A TFR film layer is formed on top of the formed IC structure; A TFR dielectric layer is formed on top of the TFR film layer; A first etching is performed to remove selected or exposed portions of the TFR dielectric layer, thereby defining a TFR dielectric cap over the TFR film layer, wherein the first etching stops at the TFR film layer, and wherein the first etching defines an inclined lateral edge of the TFR dielectric cap. A second etching is performed to remove selected or exposed portions of the TFR film layer, thereby defining a TFR element, wherein the inclined lateral edges of the TFR dielectric cap are aligned above the corresponding lateral edges of the TFR element; A third etching is performed to form a TFR contact opening in the TFR dielectric cap above the TFR element; as well as A metal layer is formed, which extends above the conductive IC element contacts and above the TFR dielectric cover, and extends into the TFR contact opening and contacts the TFR element; and The TFR film or the TFR element is annealed at a certain time after the TFR film is formed and before the metal layer is formed.

2. The method of claim 1, wherein the formed IC structure comprises a memory cell or a transistor structure, the memory cell or transistor structure comprising at least one conductive IC element contact connected to at least one of the source region, drain region and gate region of the memory cell or the transistor structure.

3. The method according to any one of claims 1 to 2, wherein the TFR film comprises silicon chromium carbide (SiCCr), silicon chromium (SiCr), chromium silicon nitride (CrSiN), tantalum nitride (TaN), tantalum silicide (Ta2Si), or titanium nitride (TiN).

4. The method according to any one of claims 1 to 2, wherein the metal layer comprises aluminum.

5. The method according to any one of claims 1 to 2, wherein the TFR dielectric layer comprises an oxide layer.

6. The method according to any one of claims 1 to 2, wherein the second etching comprises dry etching.

7. The method according to any one of claims 1 to 2, wherein annealing the TFR film or the TFR element comprises annealing at a temperature of at least 500°C.

8. The method according to any one of claims 1 to 2, wherein annealing the TFR film or the TFR element comprises annealing at a temperature of 515°C ± 10°C for 15 to 60 minutes.

9. The method according to any one of claims 1 to 2, wherein: Forming the metal layer includes: A conformal metal layer is deposited over the TFR dielectric cap; and Perform metal etching to remove selected or exposed portions of the conformal metal layer; and The deposited conformal metal layer includes a tilted metal region extending above a corresponding tilted lateral edge of the TFR dielectric cap. The tilted metal region has a lower height at a first location adjacent to a corresponding lateral edge of the TFR element compared to a second location above the top surface of the TFR dielectric cap. The metal etching removes the sloping metal region at the first location adjacent to the corresponding lateral edge of the TFR element, wherein the lower height of the sloping metal region at the first location allows for reduced etching time or intensity to remove the full thickness of the sloping metal region at the first location.

10. The method according to any one of claims 1 to 2, further comprising forming an etch stop layer over the IC structure and forming the TFR film layer over the etch stop layer.

11. The method according to any one of claims 1 to 2, wherein: The first etching is a wet etching; The second etching is a TFR etching; The third etching is TFR contact etching.

12. The method according to any one of claims 1 to 2, wherein: The method further includes forming a first etch stop layer over the IC structure; The TFR film layer is further formed above the first etch stop layer; The method further includes forming and patterning a first photomask over a portion of the TFR dielectric layer; The TFR dielectric cover is further defined below the first photomask; The metal layer is a metal interconnect layer and is located below the TFR element; The method further includes forming and patterning a third photomask; The method further includes performing a fourth etching process to remove selected portions of the metal interconnect layer, thereby defining a plurality of metal interconnect elements.

13. The method of claim 12, wherein the inclined lateral edge of the TFR dielectric cap reduces the likelihood of an electrical short circuit at the metal interconnect element.

14. The method of claim 12, wherein the third etching comprises wet etching.

15. The method of claim 12, wherein the fourth etching process defines a contact element that provides a conductive connection between the TFR element and at least one of the plurality of conductive IC element contacts.

16. An integrated thin-film resistor (TFR) formed by the method according to any one of claims 1 to 15.

17. A semiconductor integrated circuit device, the semiconductor integrated circuit device comprising the integrated thin-film resistor according to claim 16.

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