Turn-on time acceleration of cascode amplifier

Abstract

Various methods and circuit arrangements for reducing the on-time of cascaded amplifiers are proposed. According to one aspect, during the inactive mode of amplifier operation, a configurable switching arrangement of cascaded transistors coupled to the amplifier shorts the gate of the cascaded transistors to a reference ground. During the active mode of amplifier operation, the configurable switching arrangement couples a gate capacitor, pre-charged to a voltage higher than the gate bias voltage of the cascaded transistors, to the gate of the cascaded transistors. This ensures that the cascaded transistors turn on much faster than with conventional cap-grounded methods, thus providing the final current flowing through the cascaded amplifier in a shorter time without limiting the on-time of the input transistors. The gate bias voltage is coupled to the gate capacitor via a resistor. Relationships between the pre-charge voltage and the minimum saturation voltage and threshold voltage of the transistors in the cascaded amplifier are also provided.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Nonprovisional Application No. 16 / 692,750, filed November 22, 2019, the entire contents of which are incorporated herein by reference. This application may also relate to U.S. Patent No. 10,038,418 B1, published July 31, 2018, entitled “Optimized Multi Gain LNA Enabling Low Current and High Linearity Including Highly Linear Active Bypass,” the entire disclosure of which is incorporated herein by reference. Background Technology

[0003] This application relates to amplifiers. In particular, this application relates to the on-time of cascode amplifiers. Background Technology

[0005] In recent years, in radio frequency (RF) applications, such as power amplifiers (PAs) in the transmitter section of RF front-end communication systems or low-noise amplifiers (LNAs) in the receiver section of RF front-end communication systems, stacked cascaded amplifiers, which use multiple transistors arranged in a stacked manner (stacked transistors), have become dominant in the amplification stage of the amplifier. Due to the large number of transistors in the stack, the voltage handling performance of the amplifier is improved, allowing for higher power and higher voltage output. Since the stacked transistors include individual low-voltage transistors capable of withstanding voltages significantly lower than the amplifier's output voltage, it is important to bias the stacked low-voltage transistors to keep operation within their permissible voltage range. This voltage compliance of the stacked low-voltage transistors must be maintained during each period of the operating mode, where the amplifier can operate according to different operating modes, such as active (amplification, conduction, activated) and inactive (no amplification, deactivated) modes.

[0006] Figure 1A A prior art configuration of a stacked cascaded amplifier (100) is shown, which includes features for receiving an input RF signal RF. IN The input transistor M1, which is used to amplify the input RF signal, is... OUT The cascaded output transistor M2 is connected in series. The bypass capacitor (C) B1 C OUTThis can be used to connect the low-frequency (e.g., DC) bias voltage supplied to the stack of transistors (transistor stack) with RF. IN and RF OUT Signal decoupling. It should be noted that, as those skilled in the art will readily understand, depending on the selected capacitance value, the capacitor (C) B1 C OUT It can also be part of a corresponding matching network coupled to the input and output of a stacked cascaded amplifier (100). Supply voltage V DD Through inductor L D Coupled to the drain of output transistor M2 and referenced to ground V GND (e.g., GND or AC ground) via optional inductor L G (For example, a degraded inductor) is coupled to the source of the input transistor M1. It should be noted that although the amplifier (100) is shown with two stacked transistors, it may have a greater number of stacked transistors, wherein the number n of stacked transistors can be any integer greater than or equal to 2, and can be the supply voltage V. DD The voltage level is a function of the allowable voltage range (e.g., processing voltage) of the transistor (M1, M2, ..., Mn).

[0007] exist Figure 1A In the prior art amplifier (100), the bias of transistors M1 and M2 can be achieved via, for example, corresponding series resistors R. B1 and R B2 The bias voltages Vbias1 and Vbias2, coupled to the gate of the transistor, are used to provide this bias. Figure 1A As shown, coupled to the series resistor R B2 The configurable switching arrangement (110) between the gate of the cascaded transistor M2 and the gate of the cascaded transistor M2 can also control the effective voltage at the gate of the cascaded transistor M2 to operate the amplifier (100) according to different operating modes, including: an active mode in which the voltage is controlled via a current flowing through the amplifier (100) (i.e., at the supply voltage V coupled to M2). DD With reference ground V coupled to M1 GND The current between (between) is used to amplify the input RF signal. IN ; and an inactive (e.g., standby, idle) mode, in which no current flows through the amplifier (100) and therefore no input RF signal RF is generated. IN Magnification.

[0008] like Figure 1AAs shown, during operation in active mode, the series-connected switch SW21 of the configurable switch arrangement (110) can be closed to couple the bias voltage Vbias2 to the gate of the cascaded transistor M2, while the shunting switch SW22 of the configurable switch arrangement (110) can be opened to prevent shunting of the gate of the cascaded transistor M2 (i.e., shorting to Vbias2). GND Therefore, during operation in active mode, the switch arrangement (110) effectively controls the gate voltage V at the gate of transistor M2 based on the voltage provided by the bias voltage Vbias2. G_M2 On the other hand, in Figure 1B During operation in the inactive mode shown, the series-connected switch SW21 of the configurable switch arrangement (110) can be disconnected to decouple the bias voltage Vbias2 from the gate of the cascaded transistor M2, while the shunt switch SW22 of the configurable switch arrangement (110) can be closed to shunt or short-circuit the gate of the cascaded transistor M2 to Vbias2. GND Therefore, during operation in the inactive mode, the switching device (110) shorts the gate of transistor M2 to V. GND To achieve this gate voltage V at the gate G_M2 Effective control is equal to the reference ground V GND .

[0009] Further reference Figure 1A In the prior art configuration shown, during operation in active mode, the shunt gate capacitor C coupled to the gate of the cascaded transistor M2... B2 The gate of M2 is configured to be shorted at the operating frequency of the amplifier (100) (e.g., the frequency of the RF signal) to provide a common-gate configuration for the cascaded transistor M2. On the other hand, at the operating frequency of the amplifier (100), the source of the input transistor M1 is directly connected (without an optional inductor L). G ) or via optional inductor L G Coupled to a reference ground to provide a common-source configuration for the input transistors. Generally, the stacked cascaded amplifiers described in this disclosure include a common-source input transistor and one or more common-gate cascaded transistors.

[0010] Those skilled in the art will understand that because the gate of the cascaded transistor M2 is shorted (e.g., to GND) during operation in the inactive mode, the cascaded transistor M2 is turned off and no current flows through it. Therefore, immediately afterward, the operating mode is changed from the inactive mode (e.g., ... Figure 1B Switch to active mode (e.g., Figure 1A At the time point thereafter, cascaded transistor M2 remains off, and no current can flow through it until the gate voltage V of transistor M2 reaches zero.G_M2 A sufficiently high level is reached to turn on transistor M2. However, the time required to reach such a sufficiently high level for transistor M2 to turn on can be based on the gate capacitor C. B2 The capacitance (i.e., size, value) is a function of the charging time constant. It should be noted that the input transistor M1 has its own startup time and can have circuit enhancements to achieve a fast startup time, which is faster than the startup time of the cascaded transistor M2. Therefore, this disclosure focuses primarily on the startup time of the cascaded transistor M2. The corresponding delay between the start of conduction (on-state) of the cascaded transistor M2 and the start of conduction of the input transistor M1 can result in an undesirable additional delay before the amplifier (100) can operate according to expected performance. In some cases, such an additional delay can increase the amplifier's on-time by up to one microsecond or more.

[0011] Because the gate capacitor C B2 The capacitance can be based on: i) the operating frequency of the RF signal used to provide the common-gate configuration of transistor M2, and ii) the filtering effect of the bias circuitry used to reduce noise from the bias voltages (e.g., Vbias1, Vbias2) generated in the stack of transistors (M1, M2), so it is not possible to increase the gate capacitor C. B2 The capacitance is used to reduce the associated charging time constant, and thus reduce the on-time of the prior art amplifier (100). The teachings of this disclosure provide a way to reduce or accelerate the on-time without compromising the gate capacitor C. B2 The effectiveness of the solution. Summary of the Invention

[0012] According to a first aspect of this disclosure, a radio frequency (RF) amplifier circuit is provided, comprising: a transistor stack including a common-source input transistor and one or more common-gate cascaded transistors including an output transistor, the transistor stack being coupled between a power supply voltage and a reference ground; a configurable switch arrangement coupled to the gate of the cascaded transistors among the one or more common-gate cascaded transistors, the configurable switch arrangement comprising: i) a shunt switch configured to selectively couple the gate of the cascaded transistors to the reference ground; ii) a precharge switch configured to selectively couple a first terminal of a gate capacitor to a precharge voltage; and iii) a series-connected switch configured to selectively couple the first terminal of a gate capacitor to the gate of the cascaded transistors; and a series-connected resistor, wherein... The resistor is coupled at a first terminal to a first terminal of a capacitor and configured to be coupled at a second terminal of the resistor to a bias voltage for the cascaded transistors. The RF amplifier circuit is configured to operate according to an active mode for amplifying the input RF signal supplied to the input transistors via the final current flowing through the transistor stack, and an inactive mode in which no current flows through the transistor stack. During at least a portion of the inactive mode, a shunt switch is closed, a precharge switch is closed, and a series-connected switch is open. During at least a portion of the active mode, a shunt switch is open, a precharge switch is open, and a series-connected switch is closed. The precharge voltage has a higher level than the bias voltage level of the cascaded transistors during the active mode.

[0013] According to a second aspect of this disclosure, a method for reducing the on-time of a cascaded amplifier is proposed, the method comprising: coupling the gate of a cascaded transistor of the cascaded amplifier to a reference ground via a first switch during at least a portion of an inactive mode of operation of the cascaded amplifier, thereby preventing current from flowing through the cascaded transistor; and coupling the gate of the cascaded transistor to a gate capacitor pre-charged to a pre-charge voltage level at a switching time between operation from the inactive mode to the active mode via a second switch during at least a portion of an active mode of operation of the cascaded amplifier, the pre-charge voltage level being higher than the gate bias voltage of the cascaded transistor during operation in the active mode. Attached Figure Description

[0014] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate one or more embodiments of this disclosure and, together with the description of exemplary embodiments, serve to illustrate the principles and implementation of this disclosure.

[0015] Figure 1AThe prior art configuration of stacked cascaded amplifiers during the active mode of amplifier operation is shown.

[0016] Figure 1B It shows Figure 1A The existing technology of stacking cascaded amplifiers is configured during the inactive mode of amplifier operation.

[0017] Figure 2A The configuration of a stacked cascaded amplifier according to an embodiment of this disclosure is shown.

[0018] Figure 2B It shows Figure 2A The configuration of the stacked cascaded amplifiers during the inactive mode of amplifier operation.

[0019] Figure 2C It shows Figure 2A The configuration of the stacked cascaded amplifiers during the active mode of amplifier operation.

[0020] Figure 3 A configuration of a stacked cascaded amplifier for a stacking height n is shown according to an exemplary embodiment of this disclosure.

[0021] Figure 4 The configuration of a multi-branch cascaded amplifier is shown, where each branch is based on... Figure 3 Stacked cascaded amplifiers in configuration.

[0022] Figure 5 This is a flowchart illustrating various steps in a method for reducing the on-time of a cascaded amplifier.

[0023] Similar reference numerals and markings in the various figures indicate similar parts. Detailed Implementation

[0024] Throughout this disclosure, embodiments and variations are described for the purpose of illustrating the use and implementation of the inventive concept in various ways. These illustrative descriptions should be understood as presenting examples of the inventive concept and not as limiting the scope of the concept disclosed herein.

[0025] exist Figures 1A to 1BIn the prior art configuration shown, since the cascaded transistor M2 does not turn on as quickly as the input transistor M1 after the mode switch from inactive to active mode, the current through the amplifier (100) for a given bias voltage to the input transistor M1 may not be the desired current. This is because while the input transistor M1 has reached its saturation operating region to control the nominal (e.g., final) current through the amplifier (100) via the applied bias voltage Vbias1, the cascaded transistor M2 may still be operating in its subthreshold region and therefore cannot carry such a nominal current through its drain-to-source conduction path. This mismatch between the desired nominal current through the amplifier (100) and the potentially significantly smaller effective current through the amplifier (100) when the cascaded transistor is not fully turned on can further deteriorate the operation of the amplifier (100) if the current through the amplifier is controlled via a feedback loop, as such a feedback loop can, for example, further increase the bias voltage Vbias1 to the gate of the input transistor M1 to compensate for the mismatch and thus further increase the on-time of the amplifier (100).

[0026] The above-mentioned problems of the prior art amplifier (100) are solved by means of the teachings of this disclosure: the gate capacitor C B2 Precharge to a sufficiently high voltage so that when the gate capacitor C B2 When coupled to the gate node of cascaded transistor M2, it immediately provides operation of cascaded transistor M2 in its saturation region after a mode switch from inactive to active mode. Therefore, after the mode switch, cascaded transistor M2 can immediately provide the current required for the bias of input transistor M1 through its drain-to-source conduction path. This ensures that input transistor M1 has a sufficient drain-to-source voltage V. DS This provides redundancy, allowing it to conduct as long as its own bias voltage is available. Since the input transistor M1 may take some time to stabilize to its final operating point (i.e., operating bias point), during this time, the pre-charged gate capacitor C... B2 Discharge can be made toward the bias voltage Vbias2 to operate the cascaded transistor M2 according to its final operating point and taking into account the current controlled / requested by the input transistor M1. It should be noted that the bias voltage Vbias2 is inherently higher than the bias voltage Vbias1 to ensure amplifier operation. Because of the... Figure 1A Compared to the level of the gate bias voltage Vbias2 provided by the existing technology configuration in a fully discharged state, the gate capacitor C B2 It can discharge to the gate bias voltage Vbias2 level more quickly, and because the cascaded transistor M2 starts operating in its saturation region instead of according to... Figure 1AThe existing technology is configured to begin operation in its transistor region, thus allowing for accelerated turn-on time of the amplifier according to this teaching. When the stack height is greater than 2 (e.g., Figure 1A and Figure 1B In the case of transistors M1 and M2 shown, a similar pre-charge can be provided to the gate capacitors of any of the cascaded transistors in the stacked cascaded amplifier, including scaling the voltage for the pre-charge of the gate capacitors relative to the respective locations of the cascaded transistors within the stack. It should be noted that C is typically chosen... B2 The value (capacitance) is used to optimize RF performance, and therefore C B2 This value can be substantially greater than the gate-to-source capacitance Cgs of M2. Therefore, when the switch (e.g., SW21) is closed, C B2 The charge is shared with Cgs_ of M2, but due to C B2 Large, therefore will be close to V DD2 The value begins. Then, the bias will be determined according to the RC time constant (e.g., by C). B2 and R B2 The provided voltage stabilizes at Vbias2. This causes an initial Vg2 bias voltage overshoot, but this is far superior to the situation where the device (M2) is in a subthreshold condition with Vg2 starting at ground, as configured according to the prior art.

[0027] Figure 2A A configuration of a stacked cascaded amplifier (200) according to an embodiment of this disclosure is shown. Apart from the structure of the configurable switch arrangement (210), this configuration is similar to that of the referenced... Figure 1A The configuration described is similar. According to an embodiment of this disclosure, the switch arrangement (210) can be configured to connect the gate capacitor C... B2 Precharge to precharge voltage V DD2 The pre-charge voltage V DD2 It is high enough to operate the cascaded transistor M2 in the saturation region immediately after the amplifier switches from inactive to active mode.

[0028] like Figure 2A As shown, the configurable switch arrangement (210) includes: i) a series-connected switch SW21 coupled to the gate node of the cascaded transistor M2 and carrying stored in the gate capacitor C. B2 The voltage of the gate capacitor C B2 ii) Shunt switch SW22, which is coupled between the gate node of cascaded transistor M2 and reference ground V. GND Between, and iii) the pre-charge switch SW23, which is coupled to the pre-charge voltage V DD2 With gate capacitor C B2Between the terminals. It should be noted that switches SW21, SW22, and SW23 can be any type of switch known to those skilled in the art, including electromechanical switches, MEMS switches, semiconductor switches, and transistor switches, as long as they provide sufficiently low cutoff capacitance when open and sufficiently low on-resistance when closed, so as to, for example, not affect the operation of the amplifier or have a negligible effect on the operation of the amplifier during active operation.

[0029] according to Figure 2B In the embodiment of this disclosure shown, during the inactive mode (or part thereof) of amplifier (200) operation, the series-connected switch SW21 is turned off, and thus the gate capacitor C is turned off. B2 The voltage across the terminals is decoupled from the gate node of the cascaded transistor M2, and the shunt switch SW22 is closed, thus shorting the gate node of the cascaded transistor M2 to reference ground V. GND On the other hand, the pre-charge switch SW23 is closed, and therefore the gate capacitor C... B2 Precharged to the level of precharge voltage V DD2 The provided voltage level. Therefore, during the inactive mode (or part thereof) of operation, the switching arrangement (210) can be configured to: i) reduce the gate voltage V of the cascaded transistor M2 to: G_M2 Set as reference V GND Level, ii) the gate capacitor C B2 Precharge to precharge voltage V DD2 , and iii) carrying the pre-charge voltage V DD2 Gate capacitor C B2 The terminals are decoupled from the gate node of the cascaded transistor M2. It should be noted that because the gate voltage V... G_M2 Set to zero volts, the cascaded transistor M2 is completely off because no current flows through it. Furthermore, during operation of the amplifier (200) in its inactive mode, the bias voltage Vbias1 to the input transistor M1 also completely turns it off. Those skilled in the art will understand that if the corresponding gate-to-source voltage V... GS Less than the threshold voltage V of the transistor th The transistor is said to be cut off when the gate-to-source voltage V is at its maximum. On the other hand, if the corresponding gate-to-source voltage V... GS Greater than the threshold voltage V th The transistor is said to be turned on, in which case, for a given gate-to-source voltage V... GS A transistor can operate with lower on-resistance and lower drain-to-source current in the transistor's operating region (i.e., the ohmic region), or with higher on-resistance and higher drain-to-source current in the transistor's saturation operating region.

[0030] according to Figure 2C In the embodiment of this disclosure shown, during the active mode (or part thereof) of amplifier (200) operation, the series-connected switch SW21 is closed, and thus the gate capacitor C is closed. B2 The voltage across the terminals is coupled to the gate node of the cascaded transistor M2, and the shunt switch SW22 is turned off, thus connecting the gate node of the cascaded transistor M2 to the reference ground V. GND Decoupling. On the other hand, the precharge switch SW23 is turned off, and therefore the gate capacitor C... B2 From the precharge voltage level V DD2 Discharge to the voltage level provided by the bias voltage Vbias2. Therefore, during the active mode (or part thereof) of operation, the switching arrangement (210) can be configured to: i) discharge the gate voltage V of the cascaded transistor M2 to the voltage level provided by the bias voltage Vbias2. G_M2 Set in the gate capacitor C B2 The levels provided at both ends, ii) will affect the gate capacitor C B2 With pre-charge voltage V DD2 Decoupling, and iii) connecting the gate node of the cascaded transistor M2 to the reference ground V GND Decoupling. Therefore, after the amplifier (200) switches from inactive to active mode, the cascaded transistor M2 is immediately biased to operate in its saturation region, and thus the current through such a transistor can support the required current as proposed by the input transistor M1 based on the bias voltage Vbias1 to the input transistor M1. When the input transistor M1 stabilizes to its expected (i.e., final) operating point, the cascaded transistor M2 also stabilizes to its expected operating point, while the gate capacitor C... B2 Discharge to the bias voltage Vbias2 level. Therefore, as referenced above... Figure 1A and Figure 1B Compared to the prior art configuration described herein, the on-time of the amplifier (200) after mode switching is accelerated (reduced). As used herein, on-time can refer to the amount of time taken immediately after mode switching to reach either of the following states: a) the amplifier operates within 0.5 dB of its (steady-state, final) gain, or b) the current through the amplifier is within 10% of the final current.

[0031] According to the implementation of this disclosure, in Figure 2A During the inactive mode operation of the amplifier (200), the capacitor coupled to the gate capacitor C B2 Pre-charge voltage V DD2This ensures that after the mode switch from inactive to active mode, the cascaded transistor M2 immediately operates in its saturation operating region. As described above, such operation of the cascaded transistor M2 ensures that the current demand of the input transistor M1 is met while it stabilizes to its final operating point. Since such current demand can become quite large once the input transistor M1 has transitioned to its saturation operating region, according to an exemplary embodiment of this disclosure, the pre-charge voltage V... DD2 Make: V DD2 > V DSAT_M1 + V TH_M2 , where V DSAT_M1 V represents the minimum drain-to-source voltage required for the input transistor M1 to operate in its saturation region, and V TH_M2 This represents the threshold voltage of the cascaded transistor M2. Because V DSAT_M1 It also indicates the common drain-source node N connected in series between the two transistors M1 and M2. M2_M1 The voltage at that point, so by setting the pre-charge voltage V DD2 This value ensures that when the input transistor M1 reaches its saturation operating region after mode switching, the gate-to-source voltage V of the cascaded transistor M2 is maintained. GS The threshold voltage V of the cascaded transistor M2 is greater than TH_M2 Therefore, the cascaded transistor M2 is turned on and operates in its saturation region. Those skilled in the art will clearly understand that SW21 must be turned off before SW22 and SW23 are turned on.

[0032] Figure 3 A configuration of a stacked cascaded amplifier (300) for a stack height n is shown according to an exemplary embodiment of this disclosure, where n is an integer equal to or greater than 2. Figure 3 As shown, for each of the cascaded transistors (M2, ..., Mn), a transistor with the same characteristics as the one referenced above can be provided. Figures 2A to 2C The structure and operation are similar to those described for a configurable switch arrangement (210). As described above, during the inactive mode of amplifier (300) operation, each such arrangement (210) can selectively couple the gate capacitors (C) to the gate nodes of the respective cascaded transistors (M2, ..., Mn). B2 ..., C Bn Precharge to precharge voltage (V) DD2 ... V DDnThis allows each of the cascaded transistors (M2, ..., Mn) to immediately operate in its respective saturation operating region after the amplifier (300) switches from inactive to active mode. Because each source node in the cascaded transistors (M2, ..., Mn) sees a different voltage, the precharge voltage (V) can be adjusted according to the position of the cascaded transistors (M2, ..., Mn) within the stack of transistors (M1, ..., Mn). DD ... V DDn Prescale.

[0033] Continue to refer to Figure 3 According to an exemplary embodiment of this disclosure, for 2 ≤ k ≤ n, the pre-charge voltage V DDk Make: V DDk > V DSAT_M1 + V DSAT_M2 + V DSAT_M（k-1） + V TH_Mk , where V DSAT_Mp V represents the minimum drain-to-source voltage required to operate the transistor (M1, M2, ..., Mn) in its saturation region, and V TH_Mk This represents the threshold voltage of the cascaded transistor Mk in the stack (M1, ..., Mn). Because Vddk-V th_Mk It also represents the common drain-source node N connected in series between two transistors Mk and M(k-1). Mk_M（k-1） The voltage at that point, so by setting the pre-charge voltage V DDk This value ensures that when the input transistor M1 reaches its saturation operating region after mode switching, the gate-to-source voltage V of any cascaded transistor Mk in the cascaded transistors (M2, ..., Mn) is constant. GS Greater than the corresponding threshold voltage V TH_Mk Therefore, the current demand posed by the input transistor M1 during the transition of the amplifier (300) to the on state can be satisfied by a series-connected cascaded transistors (M2, ..., Mn) operating in their respective saturation operating regions. Those skilled in the art will readily understand that if transistors Mk and Mp have different characteristics (e.g., different sizes, gate widths, and / or gate lengths), then the voltage V... DSAT_Mk and V TH_Mk Can be related to voltage V DSAT_Mp and V TH_Mp No. When using transistors with the same characteristics in a stack, the pre-charge voltage V... DDK The above expression can be simplified to: for 2 ≤ k ≤ n, V DDk > (k-1)*V DSAT_M + VTH , where V DSAT_M V represents the minimum drain-to-source voltage required for each transistor in the stack (M1, M2, ..., Mn) to operate in its saturation region, and V TH This represents the threshold voltage of each transistor in the stack.

[0034] The teachings of this disclosure can be applied to amplifiers operating as power amplifiers (PAs) in the transmitter section of an RF front-end communication system, or to amplifiers operating as low-noise amplifiers (LNAs) in the receiver section of an RF front-end communication system. According to some exemplary embodiments of this disclosure, the amplifier according to these teachings can be as follows: Figure 4 This is a portion of the multi-branch cascaded amplifier (400) shown. Figure 4 In this multi-branch configuration, which includes multiple, p branches, one or more of the amplifier branches (300) can be selectively turned on or off, for example, by the desired gain or effective final current of the multi-branch cascaded amplifier (400). The on and off of the branches can be provided by a configurable switch arrangement (210) of cascaded transistors (e.g., M1, ..., Mn) coupled to one or more branches. Figure 4 The configuration shown according to this disclosure enables the acceleration of multiple, p branches (3001, ..., 300) of a multi-branch cascaded amplifier (400). p Branches in ) (300 k The conduction time of the multi-branch cascaded amplifier. Those skilled in the art will readily recognize the structure and operating principles of the multi-branch cascaded amplifier. More information about multi-branch cascaded amplifiers can be found, for example, in U.S. Patent No. 9,929,701B1 cited above. It should be noted that the cascaded transistor M2 does not necessarily need to be pulled to ground in the inactive state as shown in the figures, but can instead be, for example, taking into account the corresponding bias voltage (e.g., V). DD The voltage level is pulled to a different voltage to protect transistor M2 from overvoltage conditions, for example.

[0035] Figure 5This is a flowchart (500) illustrating the steps of a method for reducing the on-time of a cascaded amplifier. As can be seen from the flowchart (500), the method includes: according to step (510), during at least a portion of the inactive mode of operation of the cascaded amplifier, coupling the gate of a cascaded transistor of the cascaded amplifier to a reference ground via a first switch to prevent current from flowing through the cascaded transistor; and according to step (520), during at least a portion of the active mode of operation of the cascaded amplifier, coupling the gate of the cascaded transistor to a gate capacitor pre-charged to a pre-charge voltage level at the switching time between operation from the inactive mode to the active mode via a second switch to provide a final current flowing through the cascaded amplifier, the pre-charge voltage level being higher than the gate bias voltage of the cascaded transistor during operation in the active mode.

[0036] It should be noted that various embodiments of the amplifier circuit according to this disclosure can be implemented as a monolithic integrated circuit (IC) based on any manufacturing techniques and processes known to those skilled in the art.

[0037] Applications of novel devices and systems, including those with various implementations, include electronic circuit systems used in high-speed computers, communication and signal processing circuit systems, modems, single-processor or multi-processor modules, single or multiple embedded processors, data switches, and dedicated modules including multi-layer, multi-chip modules. Such devices and systems can also be included as sub-components within various electronic systems, such as televisions, cellular phones, personal computers (e.g., laptops, desktops, handhelds, tablets, etc.), workstations, radios, video players, audio players (e.g., MP3 players), vehicles, medical devices (e.g., heart monitors, blood pressure monitors, etc.), and so on. Some implementations may include multiple methods.

[0038] The term "MOSFET" technically refers to a metal-oxide-semiconductor semiconductor; another synonym for MOSFET is "MISFET," used for metal-insulator-semiconductor FETs. However, "MOSFET" has become a common label for most types of insulated-gate FETs ("IGFETs"). Nevertheless, it is well known that the term "metal" in the names MOSFET and MISFET is now generally inappropriate, as the previously used metal gate material is now typically a polycrystalline silicon layer (polysilicon). Similarly, "oxide" in the name MOSFET may be inappropriate, as different dielectric materials are used to achieve a strong channel with a smaller applied voltage. Therefore, the term "MOSFET" as used herein should not be literally understood as limited to metal-oxide-semiconductor semiconductors, but generally includes IGFETs.

[0039] As will be readily apparent to those skilled in the art, various embodiments of the invention can be implemented to meet a wide range of specifications. Unless otherwise stated above, the selection of appropriate component values ​​is a matter of design choice, and various embodiments of the invention can be implemented using any suitable IC technology (including, but not limited to, MOSFET and IGFET structures), or in hybrid or discrete circuit forms. Integrated circuit implementations can be fabricated using any suitable substrate and process, including but not limited to standard bulk silicon, silicon-on-insulator (SOI), silicon-on-sapphire (SOS), GaN HEMT, GaAs pHEMT, and MESFET technologies. However, the inventive concepts described above are particularly useful for SOI-based fabrication processes (including SOS) and fabrication processes with similar characteristics. CMOS fabrication on SOI or SOS achieves low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high-frequency operation (above approximately 10 GHz, and particularly, above approximately 20 GHz). Monolithic IC implementations are particularly useful because, with careful design, parasitic capacitance can generally be kept low (or minimized, consistent across all cells, allowing for compensation of parasitic capacitance).

[0040] Voltage levels can be adjusted or voltage and / or logic signal polarities can be reversed according to specific specifications and / or implementation technologies (e.g., NMOS, PMOS, or CMOS, and enhancement-mode or depletion-mode transistor devices). Component voltage, current, and power handling capabilities can be adapted as needed, for example, by adjusting device size, "stacking" components (especially FETs) in series to handle higher voltages, and / or using multiple components in parallel to handle higher currents. Additional circuit components can be added to enhance the capabilities of the disclosed circuit and / or provide additional functionality without significantly altering the function of the disclosed circuit.

[0041] The examples described above are provided to give those skilled in the art a complete disclosure and description of how to make and use embodiments of the gate driver for the stacked transistor amplifiers used in this disclosure, and are not intended to limit the scope of the invention as perceived by the applicant. Such embodiments can be used, for example, in mobile handheld devices used in current communication systems (e.g., WCDMA, LTE, WiFi, etc.), where it may be necessary to amplify signals with frequency content above 100 MHz and power levels above 50 mW. Those skilled in the art will discover other suitable implementations of the presented embodiments.

[0042] Modifications to the above embodiments of the methods and systems disclosed herein that will be apparent to those skilled in the art are intended to fall within the scope of the appended claims. All patents and publications referenced in the specification indicate the skill level of those skilled in the art to which this disclosure pertains. All references cited in this disclosure are incorporated by way of reference as if each reference had been individually incorporated in its entirety by way of reference.

[0043] It should be understood that this disclosure is not limited to a particular method or system, which can of course vary. It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be restrictive. As used in this specification and the appended claims, unless otherwise clearly stated, the singular forms “a,” “an,” and “the” include plural indicators. Unless otherwise clearly stated, the term “a plurality” includes two or more indicators. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains.

[0044] Some embodiments of this disclosure have been described. However, it should be understood that various modifications can be made without departing from the spirit and scope of this disclosure. Therefore, other embodiments are within the scope of the appended claims.

Claims

1. A radio frequency (RF) amplifier circuit, comprising: a) A transistor stack comprising a common-source input transistor and one or more common-gate cascaded transistors including an output transistor, the transistor stack being coupled between a power supply voltage and a reference ground. b) A configurable switch arrangement coupled to the gate of a cascaded transistor in one or more common-gate cascaded transistors, the configurable switch arrangement comprising: b1) A shunt switch configured to selectively couple the gate of the cascaded transistor to the reference ground; b2) A pre-charge switch configured to selectively couple a first terminal of the gate capacitor to a pre-charge voltage; and b3) A series-connected switch configured to selectively couple the first terminal of the gate capacitor to the gate of the cascaded transistor, and c) A series-connected resistor, coupled at its first terminal to the first terminal of the capacitor, and the series-connected resistor is configured to be coupled at its second terminal to a bias voltage for the cascaded transistor. The RF amplifier circuit is configured to operate according to at least an active mode and an inactive mode. The active mode amplifies the input RF signal supplied to the input transistor via a final current flowing through the transistor stack, while the inactive mode has no current flowing through the transistor stack. During at least a portion of the operation in the inactive mode, the shunt switch is closed, the precharge switch is closed, and the series-connected switch is open. During operation in at least a portion of the activity mode, the shunt switch is open, the precharge switch is open, and the series-connected switch is closed. The pre-charge voltage has a higher level than the bias voltage level of the cascaded transistor during operation in the active mode.

2. The RF amplifier circuit according to claim 1, wherein During operation in the portion of the inactive mode, the configurable switch arrangement couples the gate of the cascaded transistor to the reference ground, and During operation in the portion of the active mode, the configurable switch arrangement couples the gate of the cascaded transistor to the gate capacitor, which is precharged with the precharge voltage.

3. The RF amplifier circuit according to claim 1, in, The one or more common-gate cascaded transistors are composed of the output transistor, and Wherein, the pre-charge voltage is greater than the sum of the following: i) The threshold voltage of the output transistor, and ii) The minimum drain-to-source voltage value of the input transistor for operating the input transistor in its saturation region.

4. The RF amplifier circuit according to claim 1, in, The one or more common-gate cascaded transistors consist of a plurality of n series-connected transistors arranged according to the following sequence: from the first cascaded transistor coupled to the input transistor to the nth cascaded transistor serving as the output transistor, and Wherein, for the cascaded transistor that is the kth cascaded transistor in the sequence, the pre-charge voltage is greater than the sum of the following: a) The threshold voltage of the k-th cascaded transistor, b) The sum of (k-1) voltages, where each of the (k-1) voltages is the minimum drain-to-source voltage of the corresponding cascaded transistor arranged between the input transistor and the k-th cascaded transistor in the sequence, and c) The minimum drain-to-source voltage value of the input transistor for operating the input transistor in its saturation region.

5. The RF amplifier circuit according to claim 4, in, The RF amplifier circuit includes an additional (n-1) configurable switch arrangement, and Each configurable switch is coupled to the corresponding k-th cascaded transistor among the plurality of n series-connected transistors, where k ranges from a value of 1 to a value of n.

6. The RF amplifier circuit according to claim 1, wherein: Each of the shunt switch, the precharge switch, and the series-connected switch is one of the following: a) an electromechanical switch, b) a MEMS switch, and c) a transistor switch.

7. The RF amplifier circuit according to claim 1, wherein, The common-source input transistor and the one or more common-gate cascaded transistors include metal-oxide-semiconductor (MOS) field-effect transistors (FETs).

8. The RF amplifier circuit according to claim 7, wherein, The transistor is manufactured using one of the following: a) silicon-on-insulator (SOI) technology, b) silicon-on-sapphire (SOS) technology, and c) bulk silicon (Si) technology.

9. The RF amplifier circuit according to claim 1, wherein, The RF amplifier circuit is monolithically integrated.

10. A multi-branch cascaded amplifier, comprising multiple amplification branches, each amplification branch comprising the RF amplifier circuit of claim 1. in, The drain of the output transistor of each of the amplification branches is coupled to the common output node of the multi-branch cascaded amplifier.

11. An electronic module comprising the RF amplifier circuit according to claim 1.

12. A radio frequency (RF) front-end communication system, comprising: The receiver section is used to receive RF signals according to different operating modes, and the receiver section includes the RF amplifier circuit of claim 1, wherein the RF amplifier operates as a low-noise amplifier (LNA).

13. A method for reducing the on-time of a cascaded amplifier, the method comprising: During at least a portion of the inactive mode of operation of the cascade amplifier, the gate of the cascade transistor of the cascade amplifier is coupled to a reference ground via a first switch, thereby preventing current from flowing through the cascade transistor. as well as During at least a portion of the active mode of operation of the cascade amplifier, the gate of the cascade transistor is coupled via a second switch to a gate capacitor that is precharged to a precharge voltage level at the switching time between operation from the inactive mode to the active mode, in order to provide the final current flowing through the cascade amplifier, the precharge voltage level being higher than the gate bias voltage of the cascade transistor during operation in the active mode.

14. The method according to claim 13, in, The cascaded transistor is one of one or more common-gate cascaded transistors in the cascaded amplifier, including the output transistor.

15. The method according to claim 14, in, The one or more common-gate cascaded transistors are composed of the output transistor, and Wherein, the pre-charge voltage is greater than the sum of the following: i) The threshold voltage of the output transistor, and ii) The minimum drain-to-source voltage value of the input transistor of the cascaded amplifier for enabling the input transistor to operate in its saturation region.

16. The method according to claim 14, in, The one or more common-gate cascaded transistors consist of a plurality of n series-connected transistors arranged according to the following sequence: from the first cascaded transistor coupled to the input transistor of the cascaded amplifier to the nth cascaded transistor serving as the output transistor, and Wherein, for the cascaded transistor that is the kth cascaded transistor in the sequence, the pre-charge voltage is greater than the sum of the following: a) The threshold voltage of the k-th cascaded transistor, b) The sum of (k-1) voltages, where each of the (k-1) voltages is the minimum drain-to-source voltage of the corresponding cascaded transistor arranged between the input transistor and the k-th cascaded transistor in the sequence, and c) The minimum drain-to-source voltage value of the input transistor for operating the input transistor in its saturation region.

17. The method according to claim 13, in, The coupling of the gate of the cascaded transistor during the portion of the inactive mode and the portion of the active mode is provided via a configurable switch arrangement coupled to the gate of the cascaded transistor, the configurable switch arrangement comprising: i) The first switch is configured to selectively couple the gate of the cascaded transistor to the reference ground; ii) A pre-charge switch configured to selectively couple a first terminal of the gate capacitor to a pre-charge voltage; and iii) The second switch is configured to selectively couple the first terminal of the gate capacitor to the gate of the cascaded transistor.

Images