Scalable pixel size image sensor

Abstract

By controlling the readout time of the intra-pixel transmission gates associated with the corresponding photodetectors and the tiered transistors coupled between the transmission gates of the corresponding clusters for the photodetectors and the shared reset node, the photodetectors within the integrated circuit pixel array can be dynamically configured as any one of at least three uniform aspect ratio, size-scaled pixel coverage areas.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Provisional Application No. 62 / 938,203, filed November 20, 2019, which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to integrated circuit image sensors. Attached Figure Description

[0004] In the accompanying drawings, various embodiments disclosed herein are illustrated by way of example and not limitation, and similar reference numerals denote similar elements, wherein:

[0005] Figure 1 An embodiment of an image sensor with a scalable pixel array is shown;

[0006] Figure 2 It shows the result of Figure 1 An exemplary sequence of control signals generated by the line controller to enable post-exposure correlated double sampling (CDS) readout with minimum pixel size and maximum conversion gain;

[0007] Figure 3 It shows the result of Figure 1 An exemplary sequence of control signals generated by the line controller to enable post-exposure CDS readout at intermediate pixel size and maximum conversion gain;

[0008] Figure 4 An exemplary sequence of control signals read out by the CDS after enabling exposure is shown at maximum pixel size and maximum x4-pitch conversion gain.

[0009] Figure 5 The alternating high and low conversion gains that can be selected during x4-pitch (maximum pixel size) readout are shown, along with a simplified circuit model of the gain-dependent capacitor.

[0010] Figure 6 The continuous x4-pitch high-gain and low-gain CDS readout execution is shown to obtain the benefits of low photosensitivity (high-gain readout) and brightness difference (low-gain readout);

[0011] Figure 7 An exemplary charge transfer plot of x4-pitch two-phase (dual-gain / dual-charge-transfer) readout is shown;

[0012] Figure 8An exemplary charge transfer diagram for alternative multi-gain readouts with respect to x4-pitch (maximum size) pixels is shown, wherein reset state sampling for both gain configurations is performed before signal state sampling for either gain configuration, and wherein optical charge is cumulatively transferred to the aggregate source follower capacitance in successive charge transfer operations;

[0013] Figure 9 An exemplary set of nine conversion gains that can be selected during x2-spacing and x1-spacing (middle and minimum pixel sizes) readout is shown;

[0014] Figure 10 An exemplary x2-pitch readout control sequence for generating CDS readout with dual (two different) conversion gains is shown;

[0015] Figure 11 An exemplary x2-pitch readout control sequence for generating CDS readouts at high conversion gain, medium conversion gain, and low conversion gain is shown;

[0016] Figure 12 An alternative three-gain readout sequence for the x2 (middle) pixel configuration is shown, the implementation of which is substantially based on Figure 8 The described cumulative charge transfer operation;

[0017] Figure 13 A modulated exposure readout sequence is shown, which can be applied to increase the dynamic range in the pixel-size scalable image sensor embodiments disclosed herein;

[0018] Figure 14 Showing the target Figure 13 The following is an example diagram showing the modulation exposure time, net output signal voltage level versus increased photon flux density;

[0019] Figure 15 This shows the case of individual subpixels. Figure 13 The cumulative interval method that scales proportionally;

[0020] Figure 16 It shows Figure 1 The excerpt of the pixel array architecture shows the constituent elements of an exemplary color filter array (CFA) and the constituent microlenses of a microlens array, which can be positioned above the pixel array to realize a color-sensitive optical system.

[0021] Figure 17 and 18 It shows Figure 1 Alternative embodiments of the pixel units have a single four-way shared output node and a pair of two-way shared output nodes, respectively;

[0022] Figure 19A -19G shows that it can be used Figure 1 Non-exhaustive instances of readout sequences used within the pixel architecture; and

[0023] Figure 20 Alternative pixel cell structures with independently switched, binary-weighted, dynamically switching gain capacitors are shown to enable the programming selection of additional capacitors. Detailed Implementation

[0024] In the various embodiments disclosed herein, photodetectors within an integrated circuit pixel array can be dynamically configured as any one of at least three uniform aspect ratio, size-scaled pixel coverage areas. In those uniform aspect ratio embodiments and others, photodetectors within an integrated circuit pixel array can be dynamically configured as any one of at least three uniform aspect ratio, size-scaled pixel coverage areas—an arrangement in which each segmented transistor shields the floating diffusion node for the corresponding photodetector cluster from the PVT-sensitive (process voltage temperature sensitive) drain capacitance of the shared reset transistor (reducing the net capacitance at a given floating diffusion node and thus increasing conversion gain and reducing readout noise for small signal levels). In embodiments enabling uniform aspect ratio size scaling, the photodetector clusters interconnected by segmented transistors have a combined aspect ratio that matches (or nominally matches) the aspect ratio of each individual photodetector cluster and each individual photodetector. Therefore, the readout signal can be generated specifically in response to (i) the photocharge accumulated within a single photodetector element to achieve a minimum effective pixel size (maximum spatial resolution within the pixel array), (ii) the photocharge accumulated within a cluster of photodetectors to achieve a larger effective pixel size, and (iii) the photocharge accumulated within a cluster of photodetectors interconnected by multiple banding transistors to achieve a larger maximum effective pixel size (minimum spatial resolution within the pixel array). In other embodiments, the banding transistors are selectively activated during high-resolution readouts (i.e., any readout smaller than the maximum effective pixel size) to achieve variable conversion gain, including multiple readouts per exposure with corresponding conversion gains. To further extend the range and / or resolution of the optional conversion gain, one or more additional capacitive elements can be coupled to a shared reset node (in parallel or series with a reset transistor) via the dynamic conversion gain transistor(s). In several embodiments, the additional transistor switched capacitors are programmably scalable to enable runtime calibration of the optional conversion gain. In other embodiments, a photocharge clearing / storage operation is performed for a subset of photodetectors with extended dynamic range. These and other features and embodiments are discussed in further detail below.

[0025] Figure 1 An embodiment of an image sensor 100 is shown, having a scalable pixel array 101, a color filter array 103 (overlaying the scalable pixel array), a row signal generator 105, and a column readout circuit 107. Referring to schematic diagram 110 and the corresponding layout diagram 112, each scalable “pixel cell” 120 includes four photodetector clusters 115 disposed in a corresponding quadrant of the pixel cell. Each of the four photodetectors within a given cluster (represented by “SWn”, where SW refers to the photocharge storage well of the photodetector and “n” refers to the photodetector index, ranging from 1 to 16) is coupled via a corresponding transmission gate (TGn) to a shared floating diffusion node for the cluster (FD1 for the upper left cluster, FD2 for the upper right cluster, FD3 for the lower left cluster, and FD4 for the lower right cluster), and each cluster floating diffusion node is coupled via a corresponding binning transistor 117 to a shared / shared reset node 120. In the illustrated embodiment, each banding transistor is controlled by a corresponding per-pixel row banding signal (BIN1, BIN2, BIN3, BIN4), although in an alternative embodiment a single banding signal can control all four banding transistors. Each photodetector cluster and its associated transmission gate's floating diffusion node are coupled to a corresponding amplifier transistor 121, which drives the corresponding cluster output lines (i.e., OUT1, OUT2, OUT3, OUT4) via a readout selection transistor 123. As shown in shaded region 130, each individual photodetector, along with its transmission gate (TG) and TG-interconnected floating diffusion node, readout circuitry (implemented by transistors 121, 123), banding transistor 117, reset node 120, reset transistor 125 (and optional dynamic switching gain capacitor 127 and transistor 129), is referred to herein as a subpixel, and a group of subpixels sharing the same floating diffusion node (FD) and readout circuitry is referred to herein as a subpixel cluster sharing the FD (or simply a subpixel cluster).

[0026] exist Figure 1 In one embodiment, each cluster of output lines (OUT1–OUT4) is biased by its respective current source to operate each of the four amplifier transistors 121 as a respective source follower (SF), wherein the voltage at the source terminal of the amplifier transistor (“source follower transistor”) follows the voltage at the gate of the amplifier transistor. Common-source amplification schemes or other schemes may be implemented in alternative embodiments or (and / or programmably selected) configurations (e.g., programmably selected configurations). Similarly, each photodetector element (represented from an operational perspective by “SW” as a photoelectric charge storage trap) is connected via… Figure 1The embodiments implemented use sub-diffraction-limited (SDL) pinned photodiodes (PPDs), which are pinned photodiodes having a smaller coverage area (i.e., layout area) than the Airy disk for the wavelength of light passing through the overlapping elements of the color filter array. In alternative embodiments, the size of the individual photodetector element may be greater than or nominally equal to the diffraction limit. Moreover, although the various embodiments given herein assume that the photodetector element is a pinned photodiode (pinned PD), any other feasible photodetector element may be used in all cases.

[0027] Still referencing Figure 1 The schematic diagrams and layouts 110 and 112 show that the transmission gates and binning transistors make it possible to select any single photodiode (PD) within any four-PD cluster as the minimum effective pixel size within the pixel unit for a single readout—that is, turning on the transmission gate corresponding to the single photodiode enables photocharge transfer to the cluster floating diffusion node (FD), thereby generating a signal on the cluster output line that nominally matches (with possible DC offset) the voltage on the cluster FD. By turning on all the transmission gates within a given cluster (simultaneously or interleaved within the readout interval) to select an intermediate effective pixel size with the same aspect ratio as the nominal minimum effective pixel size, photocharge from the four cluster photodiodes is transferred to their shared floating diffusion (i.e., "binding" the photocharge from the same cluster photodiodes within the cluster FD) to generate the corresponding x4 PD pixel signal. The maximum effective pixel size also has the same aspect ratio as the minimum coverage pixel nominal (and therefore the aspect ratio also matches the intermediate pixels), and the maximum effective pixel size can be selected by charge binning the output of the four intermediate pixels (i.e., each of the four clusters), that is, turning on all transmission gates (TG1-TG16) in pixel unit 120 during a given readout interval and also turning on the four binning transistors 117 to electrically couple the four cluster floating diffusion nodes (FD1-FD4) to each other.

[0028] Because the segmentation transistor 117 (i.e., the transistor controlled by the individual signals BIN1-BIN4, and therefore sometimes referred to here as the signal name) is in Figure 1In each cluster embodiment, the output remains disconnected for small-sized pixel readouts and intermediate-sized pixel readouts. Any one of the four small pixels (i.e., single-PD pixels or sub-pixels) within a given cluster can be read out simultaneously with any one of the small pixels in the other three clusters (i.e., the four small pixels in each cluster are read out concurrently via their respective readout circuits), and the four intermediate-sized (4-PD) pixels can also be read out concurrently via their respective readout circuits. Conversely, all four banding transistors are turned on for the largest-sized (16-PD) pixel readout, such that the same charge banding voltage is applied to all four readout circuits (i.e., the same voltage present at the gates of all four source follower transistors 121), and therefore each readout circuit, when activated (i.e., by turning on the readout selection transistor for the readout circuit), should produce the nominally identical output voltage on the corresponding output lines OUT1–OUT4. In several embodiments, the outputs of all four readout circuits can be sampled by the column readout circuit (107) during maximum-size pixel readout to generate four nominally identical pixel values ​​through an algorithmic combination or selection of individual pixel values ​​(e.g., in the analog domain, or in the digital domain after analog-to-digital conversion of individual signals within circuit 107). Alternatively, the signals generated on the four output lines coupled to a given column of pixel cell 120 can be evaluated during system startup or production-time testing to determine the lowest-noise output line for each pixel cell within a given row, storing (e.g.) a bitmap that can be applied to control the readout selection transistor for the pixel cell and / or which of the four output lines for each pixel cell is sampled during task-mode operation (i.e., driving a given one of the output lines for each pixel cell). To reduce mapping data overhead, a shared row mapping (rather than independent mapping for each row) can be applied to all rows of pixel cells to select one of the output lines for maximum-size pixel readout. In other embodiments, the default readout circuit (e.g., the circuit driving OUT1) can be selected during maximum pixel readout (readout selection transistor turned on), while all other readout circuits remain unselected. Furthermore, as described below, photocharge from all or any subset of photodiodes within a given cluster can be binned with photocharge from all or any subset of photodiodes within one, two, or all other clusters, and read out concurrently and independently from any unbinded cluster with binned cluster readout. More generally, two independent readout signals can be generated concurrently under the following binning transistor configuration:

[0029] The segmented transistor is turned on. Concurrent independent reads 0 4 1 4 2 3 3 2

[0030] Table 1

[0031] The uniform aspect ratio of the minimum, middle, and maximum pixel size configurations (also referred to as small, medium, and large pixels or pixel sizes in this paper) is sometimes referred to in this paper as pixel pitch, i.e., the PD-normalized dimension across the row and / or column axes of the pixel array, and therefore as... Figure 1 As shown at point 140, these are referred to as 1x spacing (1PD, minimum pixel size), 2x spacing (4PD, middle pixel size), or 4x spacing (16PD, maximum pixel size). Furthermore, while individual photodiodes are depicted in layout view 112 with a substantially square aspect ratio (i.e., for a unit aspect ratio, the width is nominally equal to the height), photodiodes can have non-square aspect ratios (e.g., width = f * height, where '*' is depicted as multiplication, and 'f' = 16 / 9, 16 / 10, 3 / 2, 4 / 3, etc.), which remain in the middle (2x spacing) and large (4x spacing) pixels. Moreover, the photocharge accumulated within individual photodiodes can be graded in various combinations, in addition to all combinations of PD per cluster or all PD per pixel unit discussed so far—see below. Figure 19A - The options discussed in 19G.

[0032] Still referencing Figure 1 Floating diffusion reset within a given sub-pixel cluster is achieved via a corresponding banding transistor – turning on the banding transistor for the cluster to couple the cluster-FD to reset node 120, and simultaneously turning on reset transistor 125 and (in Figure 1 In the embodiment, the dynamic conversion gain (DCG) transistor 129 is used. The same applies to individual photodiodes – they are reset along with the FD by turning on the corresponding transmission gate. This “indirect reset” operation and structure – which switchesably couples the floating diffusion node (and optionally one or more photodiodes) of a given sub-pixel cluster to a cluster-shared reset voltage via banding transistors for the sub-pixel cluster – offers several advantages over conventional implementations with reset transistors directly coupled to the floating diffusion node. First, the reset transistor overhead within the pixel cell is reduced by a factor of four per readout compared to conventional reset transistor structures. Furthermore, the parasitic capacitance on the individual FD node is significantly reduced when the source / drain of only one transistor (the banding transistor) is coupled to the cluster FD (not counting the cluster transmission gate), resulting in a significantly improved signal-to-noise ratio and thus improved low-light performance compared to conventional charge banding architectures with banding transistors and reset transistors connected in parallel with the floating diffusion node. In other words, the banding transistor shields the cluster FD from the PVT-sensitive parasitic capacitance of the reset transistor, realizing a "banding-shielded reset" architecture, in which the banding current and the reset current (during charge banding and reset operations, respectively) are conducted to / from the given cluster FD via the banding transistor 117.

[0033] continue Figure 1The dynamic conversion gain (DCG) transistor 119 is coupled between a capacitive element 127 (e.g., implemented by a metal-oxide-semiconductor (MOS) transistor having both drain and source terminals commonly coupled to a bias voltage CAPB, where CAPB is, for example, a dedicated or shared ground or other bias potential) and a shared reset node 120, and can therefore be turned on or off with one or more clustering transistors to enable multiple different conversion gains relative to a given photocharge transfer and pixel readout. More specifically, the maximum conversion gain with respect to photocharge transfer within a given cluster (and subsequent readout via the cluster readout circuitry) is achieved by turning off the clustering transistors (e.g., deasserting BIN1 to transfer charge to FD1), and a gradually decreasing conversion gain is achieved by turning on the clustering transistors for individual clusters (i.e., turning off the clustering transistors 117 for all other clusters) while simultaneously turning off the DCG transistor—by reducing the parasitic capacitance (C) of the shared reset node. SP Adding capacitor FD1 to establish a gradually increasing capacitance (i.e., C) at the gate of source follower 121. SFG =C SP +C FD C SFG It is the capacitance at the gate of the source follower transistor 121, C SP It is the parasitic capacitance of shared reset node 120 and C FD It is a floating diffusion capacitor), and the conversion gain is further reduced by turning on the DCG transistor together with BIN1 (i.e., the conversion gain is related to C). SFG Inversely proportional, where C SFG =C SP +C FD +C CAP And C CAP(This refers to the capacitor of element 127). As described below, three additional different conversion gains (CGs) can be achieved by turning on the banding transistors 117 for one, two, or three other sub-pixel clusters (concurrently turning on the banding transistors for clusters containing (multiple) sub-pixels) without turning on the DCG transistor, and three additional CGs (a total of nine different CGs) can be achieved by turning on one, two, or three other banding transistors together with the DCG transistor. Thus, in addition to uniform aspect ratio pixel size scaling, pixel unit 120 enables each pixel readout (small, medium, or large) to be performed with one or more dynamically selected conversion gains. Furthermore, as described below, the effective exposure interval (photocharge accumulation interval) of any one or more photodiodes contributing to a given readout signal can be dynamically adjusted to provide enhanced dynamic range (extended maximum distinguishable illuminance intensity) and thus provide another axis of variation. This multivariable operability is illustrated at 150, showing pixel size scaling, variable application conversion gain, and variable effective exposure interval along a conceptually orthogonal axis of runtime variable operation.

[0034] Figure 2 It shows the result of Figure 1 The line controller (line signal generator) generates an exemplary sequence of control signals that enable post-exposure correlated double sampling (CDS) readout with minimum pixel size (x1 spacing) and maximum conversion gain (CG). In the described example (and other signal timing diagrams discussed below), the control signals are conceptually grouped and applied as a whole to a pixel unit (“unit” signal 171), to an entire sub-pixel cluster (cluster signal 173), or to individual sub-pixels (for clusters 1–4, sub-pixel signals 1751–1754).

[0035] Figure 2 The readout sequence enables concurrent CDS readout and generates a corresponding digital pixel value for each subpixel within a row of pixel units (16*M digital pixel values ​​in a sensor with M columns of pixel units), and repeats / iterates this readout sequence for each row of pixel units to achieve rolling shutter readout. Row readout begins (after the exposure interval after the photocharge has accumulated in the corresponding photodiode) at 181, asserting the readout selection signal (RS) to couple the source terminals of each cluster of source follower transistors to the corresponding output line (and thus enable...). Figure 1The signal is sampled within the column readout circuit 107. Shortly thereafter, the banding transistors of all sub-pixel clusters pulse together with the DCG transistor and the reset transistor (i.e., turn on and then off BIN1, BIN2, BIN3, BIN4, RG, and DCG, as shown at 183) to reset all floating diffusion nodes (and the shared reset node). A reset state sample is captured at 185 (reading the reset level of each cluster of floating diffusion nodes), followed by pulse processing of the selected (single) transmission gate within each sub-pixel cluster as shown at 187 (to transfer photocharge from the selected sub-pixel to the cluster FD), and then a signal state sample is taken at 189. The reset state sample is subtracted from the signal state sample (i.e., at 189). Figure 1 The readout circuit 107 is used to generate CDS (pseudo-differential) digital pixel values, which are sampled in the analog domain following the ADC or in the digital domain (after both samples have been digitized separately). In the example shown, the initial CDS readout sequence—reset, reset state sampling, charge transfer, and signal state sampling—is implemented concurrently with respect to sub-pixels 1, 5, 9, and 13 (one sub-pixel per cluster with reset state and signal state sampling via the corresponding cluster output lines OUT1–OUT4), and then repeated three times (for sub-pixels 2, 6, 10, 14; then sub-pixels 3, 7, 11, 15; then sub-pixels 4, 8, 12, 16) to complete the minimum pixel size (maximum resolution) readout.

[0036] Figure 3 It shows the result of Figure 1 An exemplary sequence of control signals generated by the line signal generator (i.e., a readout sequence repeated for each row of pixel units to affect the rolling shutter readout) is used to enable CDS readout after exposure at intermediate pixel size (x2 pitch) and maximum conversion gain. As shown, after the reset operation at 191 (and during the readout selection signal assertion) and the reset state sampling at 193, as shown at 195, the transmission gates of all four photodiodes in a given cluster are simultaneously pulsed (so that all TGs within the 16-PD pixel unit are pulsed) to affect the intra-cluster charge binning readout. That is, the accumulated photocharge in each photodiode of a given cluster is transferred to the shared floating diffusion node (intra-cluster charge binning) of that cluster to generate a corresponding x2-pitch output signal on each of the output lines OUT1–OUT4 via the cluster source follower transistor and the readout selection transistor, for the signal state sampling at 197. Figure 4An exemplary control signal sequence for post-exposure CDS readout is shown, enabled with maximum pixel size (x4 pitch) and maximum x4-pitch conversion gain. The signal sequence is similar to that for x2 pixel pitch readout, but four BIN transistors are turned on during charge transfer and signal state sampling operations throughout the reset state sampling to switchably couple the four floating diffusion nodes per cluster to each other, thus forming a uniform pixel cell width capacitance from all PDs (…). Figure 1 In this example, the charge of the 16 PDs is transferred to the pixel cell width capacitance. Because the signal level at the gate of each of the four source follower transistors is nominally identical, one (or more) of the predetermined output lines can be sampled to obtain x4-pitch reset state and signal state samples.

[0037] Figure 5 Alternating high and low conversion gains selectable during x4-pitch (maximum pixel size) readout are shown, illustrating a simplified circuit model of CG-related capacitor 201, truth table 203, which shows the control signal states for high and low conversion gains at x4-pitch high (i.e., DCG = 0 or 1 for high CG and low CG respectively, while asserting BIN1-BIN4 for both CGs to establish a large pixel size), and exemplary graph 205 showing the pixel output voltage (the analog readout signal generated on OUTn) versus total photocharge accumulation (the net accumulation across all PDs of the pixel unit). Referring to circuit model 201 and truth table 203, four floating diffusion nodes (by capacitor C...) are also shown. FD1 C FD2 C FD3 C FD4 The modeling elements are switchably coupled to each other (via BIN1, BIN2, BIN3, BIN4) and share a reset node (C). SP The parasitic capacitive coupling of the source follower transistor (CSFG) causes the net capacitance at the gate of the output circuit source follower transistor (CSFG) to be nominally equal to C when the dynamic gain control transistor is off (DCG = 0). SP +4C FD (Assuming each cluster has the same floating diffusion capacitance—in an alternative embodiment, the capacitance can be intentionally varied from cluster to cluster). When the DCG transistor is turned on, C SFG Add C DCG Thus achieving 4C FD +C SP +C DCG If the conversion gain is related to the net capacitance C SFG Inversely proportional (e.g., such as) Figure 5As shown in Table 203, the deassertion and assertion of the DCG signal produce relatively high and relatively low conversion gains, respectively, and thus relatively high and relatively low output voltage slopes, as shown in curve 205. In the low-light range shown in shaded region 207 (within curve 205), the high-gain signal provides substantially better noise performance (due to lower input reference noise resulting from the higher conversion gain), while higher illuminance intensities beyond shaded region 207 (which saturates the high-gain output) can be distinguished by the lower-gain output.

[0038] Figure 6 This illustrates consecutive x4-pitched high-gain CDS readouts and low-gain CDS readouts, performed to obtain the benefits of low light sensitivity (high-CG readout) and bright light differentiation (low-CG readout), and thus extending the dynamic range beyond that achievable with a single conversion gain. In one embodiment, output saturation occurs when the voltage level at the gate of the source follower transistor reaches the photodiode pinning voltage, such that after high-CG photocharge transfer, the photodiode retains more PD-accumulated photocharge than that required to raise the source follower gate potential to the pinning voltage. Therefore, in the absence of an illuminance level that saturates the low-gain output (extremely bright light), the photocharge transferred in the high-gain readout and the photocharge transferred in the low-gain readout constitute complementary portions of the total photocharge accumulated within the PD during the previous exposure interval, such that the high-CG readout and low-CG readout can be summed (in the analog or digital domain) to produce a pixel output value with a higher dynamic range than that achievable with a single gain readout. Figure 7 An exemplary charge transfer diagram illustrates this x4-pitch dual-gain / dual-charge transfer operation. As shown, during bright light exposure (250), photocharge (Q) accumulates within the pinned photodiodes (collectively, “PPDs”) of the pixel unit. When in a high-gain configuration (DCG = 0), the source follower gate capacitance (i.e., C1) is... SF = Parasitic capacitance of floating diffusion nodes and reset nodes in the segmented transistor interconnect) is reset at 251 (pre-charged to a relatively high predetermined potential, e.g., V PIX or V DD ), and then a reset state sampling is performed at position 253. At position 255, for promoting PPD (e.g., Figure 1 The transmission gates (PD1-PD16) in the architecture are pulsed to enable charge transfer to C1. SF In the middle, the C1 SFFill (with a fraction of Q, q1) until the photodiode pinning voltage, thus leaving a photocharge q2 (q2 = Q - q1) within the PPD, as shown at 256. After obtaining a signal state sample at 257 (the initial CDS sampling operation is completed at 253 with a reset state sample), DCG is asserted to reduce the conversion gain (by increasing the source follower capacitance to C2). SF =C1 SF +C DCG ), followed by C2 at position 261. SF The process involves a reset, a reset state sample at position 263, a residual charge transfer at position 265, and a final signal state sample at position 267 (the final CDS sample is completed at position 263 using the reset state sample). In one embodiment, the initial and final CDS samples are digitized separately and then added in the digital domain to produce a final pixel value with a x4-pitch pixel spacing. Alternatively, two CDS samples can be added in the analog domain (e.g., within a sample-and-hold circuit, an auto-zero / integrating amplifier, etc.) and then digitized to produce the final pixel output value.

[0039] Under low light conditions ( Figure 7 (As shown at point 270 in the text), the initial photocharge transfer can completely clear the PPD—a condition determined by comparing the initial CDS sample (before or after conversion to the digital domain) with a threshold (i.e., VPIN) corresponding to the charge transfer saturation point. With the initial photocharge transfer completely clearing the PPD, the results from the final charge transfer and CDS sampling can be discarded in the analog or digital domain—for example, by zeroing the final CDS result before adding it to the initial CDS value (or suppressing the addition of the final CDS result or even performing the final CDS sampling).

[0040] Figure 8 An alternative multi-gain readout for x4-pitch (maximum size) pixels is shown, wherein reset state sampling for both gain configurations is performed before signal state sampling for either gain configuration, and wherein photocharge is cumulatively transferred to the source follower capacitor during successive charge transfer operations. More specifically, at the end of the exposure interval, where photocharge Q accumulates within the photodiode's collection group (i.e., within the PPD), the pixel unit is configured to the lowest gain configuration (DCG = 1) and then reset (pulse processing of BIN1–BIN4 and RST signals while DCG remains high). Thereafter, successive reset state sampling is captured with gradually increasing conversion gain—at C2 SF The reset state sample is captured at (301, DCG=1) and then at C1. SFA reset state sample is captured at (303, after switching DCG to 0), and then a series of charge transfer / signal state sampling operations are performed with a gradually decreasing conversion gain as shown at (305 and 307) (with a conversion gain reduction inserted at 309). Under low-light conditions that produce a complete PPD clear (i.e., q1 = Q, q2 = 0), the high-CG CDS readout can be digitized separately (i.e., the high-CG reset state sample at 303 is subtracted from the high-CG signal state sample at 305 in either the analog or digital domain) to produce the pixel output value, where the low-CG readout (the CDS formed by the initial reset state sample and the final signal state sample) can be discarded, cleared, or otherwise omitted. Conversely, under brighter light conditions, the low-CG CDS readout (the low-CG reset state sample at 301 and the low-CG signal state sample at 307) can be digitized separately to produce the pixel output value, where the high-CG readout is omitted. In this accumulated charge transfer (or continuous reset state sampling / signal state sampling) readout method, the signals output from both the high-gain and low-gain readouts can be evaluated to determine which one to apply (as the final pixel output value) and which one to discard. The following diagram illustrates one implementation of the decision logic, where "Thresh1" is greater than V. PIN A slightly positive voltage level, while "Thresh2" is higher than V. RST A slightly negative voltage level (note that, in) Figure 8 In the embodiments, V RST V PIN correct):

[0041]

[0042] Table 2

[0043] Still referencing Figure 8 Instead of a threshold-based selection between low-CG and high-CG readouts, the readouts can be normalized (e.g., scaled according to the ratio of the two gains) and then combined to smooth the transition between high-gain readouts only and low-gain readouts only. More generally, in all multi-gain readouts described herein, in column readout circuits (e.g., Figure 1 In the analog or digital domain of element 107 or other on-chip or off-chip circuitry, the readout signals / values ​​obtained at different gains can be normalized (e.g., based on the CG ratio and / or other information determined during runtime and / or production time calibration) to enable a weighted combination of pixel output signals / values.

[0044] Figure 9An exemplary group of nine conversion gains selectable during x2-pitch and x1-pitch (middle and minimum pixel sizes) readout is shown. A simplified circuit model 331 illustrates capacitors that can be grouped in various combinations to produce different conversion gains (relative to individual photodiode displays, but equally applicable to parallel charge transfer from two, three, or all four PDs within a given cluster), and truth table 333 shows the control signal states that produce different conversion gains. The top and bottom entries in Table 333 (designated CG1 and CG9, respectively) correspond to the maximum and minimum conversion gain configurations, while the conversion gain of the entries between the extremes can be determined according to C... FD (FD capacitor), C SP (Reset node parasitic) and C DCG The relationship between the (dynamic gain capacitors) is distributed in various orders. In one embodiment, during image sensor enable (e.g., performing a calibration operation, wherein the bias voltage applied to the source and drain of the MOS-based capacitor and / or the switching combination of a variable number of component capacitor elements is iteratively adjusted), the dynamic gain capacitors are programmably adjusted to target values ​​that produce a desired gain distribution, including (e.g., but not limited to):

[0045] *C CDG =C FD To produce a decreasing, relatively linear conversion gain step size from CG1 to CG9, as shown in 335;

[0046] *C DCG =C FD / 2-C SP To provide 0.5*C between settings CG1 and CG6. FD Gain step size;

[0047] *C DCG =C FD -C SP By setting CG1, CG6, CG7, CG8, and CG9 from C FD Up to 5C FD Generate five nominal linear gain steps; or

[0048] Or go to *C DCG =n*C FD (where n>1) to enable a bundled gain distribution with relatively fine gain steps in the high gain range from CG1 to CG5 and relatively fine gain steps in the low gain range from CG6 to CG9, and a relatively wide gap between these two ranges (e.g., the gap width according to the programmable factor 'n').

[0049] Figure 10An exemplary x2-pitch readout control sequence is shown, which produces CDS readouts with dual (two different) conversion gains—one dual CDS readout is set for each of the four 2x-pitch (intermediate size) pixels, and thus a total of eight consecutive CDS readouts. As shown, the CDS readout at each gain setting begins at C SFG Reset operation (i.e., concurrent pulses RST, DCG, and BIN1-BIN4 to reset / precharge the capacitance (C) at the gate of the source follower transistor of the corresponding output line). SFG In C) SFG After reset, a reset state sample is captured (351), followed by photocharge transfer (353), and then signal state sampling (355). During high-CG readout (361, 363, 365, 367), DCG and BIN1–BIN4 are reduced during charge transfer and signal state sampling to produce a conversion gain CG1, as shown... Figure 9 As shown in Table 333. Conversely, in the intermediate-CG readouts (362, 364, 366, 368), DCG is decremented during charge transfer and signal state sampling while BIN1–BIN4 are asserted to produce the conversion gain CG5 (according to…). Figure 9 ).

[0050] Figure 11 An exemplary x2-pitch readout control sequence is shown, which produces CDS readouts at high, medium, and low conversion gains—setting a triple CDS readout for each of the four 2x-pitch (intermediate size) pixels, resulting in a total of 12 consecutive CDS readouts. Figure 10 As shown, the CDS readout at each gain setting is in C SFG The reset operation begins, and the C SFG The reset operation is followed by reset state sampling, photocharge transfer, and then signal state sampling. During high-CG readout, DCG and BIN1–BIN4 are reduced during charge transfer and signal state sampling to produce a conversion gain CG1 (according to…). Figure 9 Table 333). Read out in the middle -CG (in Figure 11 In the process designated as "intermediate-CG", DCG is decremented during charge transfer and signal state sampling, while BIN1-BIN4 are asserted to produce the conversion gain CG5 (according to...). Figure 9 Furthermore, in the low-CG readout, both DCG and BIN1-BIN4 are asserted to produce the conversion gain CG9 during charge transfer and signal state sampling operations (also shown in the low-CG readout). Figure 9 (In Table 333). Note that... Figure 10 and Figure 11The high-gain readout is performed sequentially relative to each sub-pixel cluster. Since BIN1-BIN4 remain off during the readout photocharge transfer and signal state sampling components, the high-gain readout can be performed concurrently for the four sub-pixel clusters (driving the readout signals of each cluster to the output lines OUT1-OUT4).

[0051] Figure 12 An alternative triple-CG readout sequence is shown for the x2 (middle) pixel configuration, in which reference is implemented. Figure 8 The commonly described cumulative charge transfer operation. That is, for each of the four x2-pitch pixels, a reset state sample is captured for use in a progressively increasing conversion gain configuration (such as...). Figure 9 The CG1, CG5, and CG9 shown in Table 333 are followed by continuous signal state sampling with a gradually decreasing conversion gain (i.e., the cumulative transfer of photocharge to the gate capacitance of the source follower transistor for the target output line). As per [reference to...] Figure 8 As described in the x4-spacing cumulative charge transfer sequence, the CDS readout at each conversion gain can be used to determine which of the three CDS readouts (high CG, medium CG, or low CG) will be applied to produce the pixel output value. Furthermore, the time interval between a given charge transfer and the corresponding signal state sample can differ from the time interval shown—for example, providing a longer delay between events with high conversion gain to allow for relatively small, low-light signal stabilization.

[0052] Figure 13 A modulated exposure readout sequence is illustrated that can be applied to increase the dynamic range of the pixel-size scalable image sensor embodiments described herein. In the depicted example, monotonic (continuous, uninterrupted) photocharge accumulation within the constituent photodiodes of the x2-pitch pixels begins at progressively later times within a given exposure interval, thereby effectively scaling the output signal contribution from the photodiodes to enable intensity differences at illumination levels that would otherwise saturate the x2 pixel output. Reference is made to a cluster of photodiodes with photodiode traps SW1–SW4 (i.e., Figure 1 The photodiodes PD1-PD4 within the upper left cluster of the pixel unit continuously accumulate photocharge within SW1 (PD1) throughout the entire exposure interval (“exp int”), and after diverging at 25%, 50%, and 75% of the exposure interval, respectively, the photocharge is cleared (“transferred”) from SW2, SW3, and SW4—that is, the continuous photocharge within SW2, SW3, and SW4 exceeds 75%, 50%, and 25% of the total exposure interval, respectively. Therefore, it is assumed that the steady-state incident luminance with respect to the PD cluster is within the object exposure interval (which may be, for example, 1 / 30 of a second). th 1 / 60 of a second thOn SW1, or significantly longer or brighter than any of these times, the photocharge accumulated in SW2, SW3, and SW4 will be 75%, 50%, and 25% of the photocharge accumulated in SW1, respectively. Exemplary control signals issued to achieve the photocharge clearing operation are shown at the 25% and 75% frame points (resolved at 421 and 423) in consecutive exposure intervals—by pulse-processing their respective transmission gates together with DCG, RST, and BIN1–BIN4 (to switchably couple the selected photodiodes to a reset potential) to reset the selected photodiodes (PD2, PD6, PD10, and PD14 in charge clearing operation 421, and PD4, PD8, PD12, and PD16 in operation 423), while all other transmission gates remain open.

[0053] Figure 13 A significant result of the method (scaled photocharge accumulation) is that SW1-SW4 will perform well under different illuminance intensities (i.e., at illuminance levels such as...). Figure 14 The different photon flux densities shown indicate that full-well saturation is achieved, and more specifically, at corresponding illuminance intensities inversely proportional to the effective photocharge accumulation interval. Therefore, from Figure 14 As can be seen from the graph of the net output signal voltage level (i.e., the signal generated on OUT1 in response to the segmented charges from SW1–SW4) versus the increased photon flux density, the pixel output voltage exhibits an inflection point (decreasing slope) at each PD saturation (reaching full-well capacity), and is therefore characterized by an initial slope in illuminance range R1 and three gradually decreasing slopes in illuminance ranges R2, R3, and R4, respectively. In one embodiment, each of the four output signal slopes is determined during system calibration, and the pixel signal level at the transition (breakpoint) from one slope to the next is marked. This information is then applied during pixel readout (and / or post-readout processing) to extrapolate a signal output that would result in no saturation of the photodiode. In one embodiment, for example, the digital pixel output is compared to a set of thresholds corresponding to slope transition points to indicate one of the four output signal ranges (one of the four illuminance ranges), and then a correction value (Δ) to be added to the original pixel value to produce the extrapolated pixel output value is determined. extr —Based on the difference between the slope of the target range and the slope of range 1, where, in the case of the signal in range R3 or range R4, there are segmented contributions from all previous slopes.

[0054] Still referencing Figure 13 and Figure 14In x2-spacing and x4-spacing pixel size configurations (i.e., charge-banding operation), when the incident scene content is identical to each PD in the charge-banding PD group (i.e., within a clustered 2×2 PD group in x2-spacing readout and within a 4×4 PD of pixel units in x4-spacing readout), exposure time-modulated readouts will typically produce deterministic linearization (i.e., enabling the linear extrapolation discussed above). When the point spread function (PSF) of the optics is smaller than the selectable pixel size (e.g., smaller than a 2×2 PD group and / or a 4×4 PD group), per-pixel illumination uniformity can be achieved by dynamically expanding the circle of confusion of the optics to match the effective pixel size. Therefore, in several embodiments, one or more optical low-pass filters (e.g., one for each scaled pixel size larger than the inherent circle of confusion of the optics) are mechanically or otherwise coupled in the optical path (e.g., after the main lens but before any microlens overlay) to extend the optical system's circle of confusion to a dimension of the selected pixel size, and thus ensure that all PDs within the charge banding group are subjected to the same scene content and light level. Note that the pixel size-selected circle of confusion customization is optional, as the high dynamic range and higher frame rate obtained through multi-integral time charge banding may still have acceptable imaging artifacts even when the optical system's circle of confusion is smaller than the effective pixel size.

[0055] Figure 15 This is shown in the context of individual sub-pixels. Figure 13 The proportionally scaled accumulation interval method—that is, performing charge clearing operations on the corresponding photodiodes at progressively later intervals—gradually shortens the continuous (effective) charge accumulation interval by 1 / n of the exposure interval, and thus by 6.25% in this n=16PD example. Figure 13 As shown, the cumulative interval scaling (where the incident photon flux density remains constant throughout the exposure interval) causes each PD to reach the full well at progressively later times, and thus, in the x4-spacing readout (from the photocharge of all 16 PD photocharge bins), an output signal is generated that transitions between 16 progressively different slopes at a fixed (determinable) illuminance intensity (i.e., as...). Figure 14 As shown, but with a shortened per-slope interval. Therefore, the original pixel values ​​at any slope where one or more PDs are saturated can be extrapolated to an accurate estimate of the pixel values ​​that would result in PD unsaturation, thereby extending the dynamic range of the image sensor.

[0056] Figure 16 It shows Figure 1This is an excerpt of a pixel array architecture, illustrating the constituent elements of an exemplary color filter array (CFA) and the constituent microlenses of a microlens array that can be positioned above the pixel array to implement a color-sensitive optical system. In the illustrated embodiment, the CFA implements a Bayer pattern (two diagonal green CFA elements sharing a center point with a pair of diagonal red / blue CFA elements), where each CFA element covers a photodiode of a given 4-PD cluster—that is, the complete Bayer pattern per 16-PD pixel unit. In other embodiments, the CFA can be implemented by filter elements whose size is determined to match individual photodiodes (e.g., the complete Bayer pattern per 4-PD cluster) or to match pixel units (uniformly color filtering all 16 PDs of the pixel unit), allowing light with wavelengths different from red / green / blue (including infrared or other invisible ranges) to pass through and having a color pattern different from the Bayer mosaic. Similarly, the size of individual microlenses can be to match a 4-PD cluster (or the entire 16-PD pixel unit) instead of an individual photodiode. Furthermore, as referenced... Figure 13 and 14 The discussed one or more low-pass filters may participate in operation to expand the circle of confusion of the optical system according to the selected (effective) pixel size (e.g., for x2-pitch pixel size as shown at 491 and for x4-pitch pixel size as shown at 493), and thus ensure that all PDs within the charge binning group are affected by the same scene content and brightness level.

[0057] Figure 17 and 18 It shows Figure 1 Alternative embodiments of the pixel units each have a single four-way shared output node (i.e., a pixel unit coupled to a single output line 501) and a pair of bidirectional shared output nodes (pixel units coupled to two output lines 521, 522). Figure 17 In this embodiment, four read select transistors (1231-1234) receive corresponding read select signals (RS1, RS2, RS3, RS4) to enable any cluster output circuit to drive the four shared output lines at a given time. Therefore, Figure 2 The x1-spacing readout sequence shown will lack the four-way parallelism of each readout, instead being implemented by 16 consecutive CDS readouts relative to 16 PDs. Similarly, for Figure 3 The x2-spacing readout sequence shown is 4 consecutive clusters (x2-spacing) readouts instead of 4 parallel cluster readouts. Figure 18 The dual-output channel embodiment in Figure 1 Each cluster of output lines and Figure 17The four-way shared output lines strike a ground in the middle, thus allowing parallelism in the readout of the PDs within the left and right halves of the pixel unit (the two output lines can alternatively be coupled to the top and bottom pairs of the PD clusters, respectively, with the RS1 / RS2 signal connections rotated accordingly), and therefore eight consecutive readouts are made to sample all PDs in the x1-pitch configuration, and two consecutive readouts are made to sample all 4-PD clusters in the x2-pitch configuration. Although in Figure 17 and 18 The diagram illustrates a source follower amplification scheme (each output line biased by a current source), but in alternative embodiments, common-source or other amplification schemes can be implemented. Furthermore, while different BIN signals (BIN1, BIN2, BIN3, BIN4) are applied to the four banding transistors, in alternative embodiments, a shared control signal can be coupled to all or any subset of the banding transistors—the same applies to… Figure 1 Variants of the architecture.

[0058] Figures 19A to 19G It shows that it can be used Figure 1 A non-exhaustive example of the readout sequence used within the pixel architecture masks the individual PDs within the 16-PD pixel units read out during each stage of a given sequence. Therefore, Figure 19A It shows the result of Figure 2 The control sequence enables four-level x1-spacing readout. Figure 19B A two-stage readout sequence is shown, in which a row of aligned PD pairs (instead of all four PDs) is read from each cluster in a given readout stage, and the PD pairs are alternated in successive stages. Figure 19C It shows something similar to Figure 19B Each cluster is read out in PD-pairs, but the PD-pairs are column-aligned rather than row-aligned. Figure 19D and 19E The additional PD-pair readout sequence per cluster is shown, but there are misaligned PD pairs within row-aligned clusters. Figure 19D ) and each cluster of diagonally aligned PDs ( Figure 19E ). Figure 19F The readout sequence is shown, in which three PDs of each cluster are read out in the initial stage to affect the readout of the peripheral PDs relative to the pixel unit. The remaining "inner" PDs are read out from each cluster in the second stage to affect the readout of the pixel unit core PD. Figure 19G The diagram shows the corresponding to each Figure 3 and Figure 4 The x2-spacing readout sequence (all four 4-PD clusters are read out independently and concurrently) and the x4-spacing readout sequence are shown.

[0059] Figure 20 The dynamically switching gain capacitor C with binary weighting and independent switching is shown. U and 2CU An alternative pixel cell architecture is provided to enable programmable selection of any of the three additional capacitors at a linear ratio (i.e., as shown in Table 600) or any other feasible ratio. In several embodiments, for example, the programmable selection (e.g., a control value stored in a programmable register of the imaging IC) enables runtime calibration of the dynamic gain capacitors to influence the desired conversion gain distribution (e.g., as shown in Table 600). Figure 5 and 9 (as shown) and / or minimum or maximum conversion gain. In Figure 20 In this embodiment, the reset transistor 125 is directly coupled to the reset voltage supply (V in this example) at the reset node 120. DD Between, rather than via an indirect coupling in a DCG transistor—also possible Figure 1 The arrangement is implemented in a single DCG-transistor embodiment. Simultaneously, two binary-weighted DCG capacitors are shown (i.e., twice the capacitance that is switchably coupled to node 120 via DCG2, and twice the capacitance that is switchably coupled to node 120 via DCG1). Equal or completely different capacitances with non-binary ratios can be implemented in alternative embodiments, and more than two independently switched capacitors can be included. Furthermore, although the two capacitor elements are shown as being disposed within the same pixel cell, individual capacitor elements (which can be more than two) can be physically disposed in adjacent rows of pixel cells and thus shared by adjacent rows (i.e., to reduce the MOS element count per pixel cell).

[0060] The various pixel unit circuit architectures and layouts, imaging circuit architectures, color filter arrays, microlens arrays, readout methods, etc., disclosed herein can be described using computer-aided design tools and, based on their behavior, register transfers, logic components, transistors, layout geometry, and / or other characteristics, are represented as data and / or instructions embodied in various computer-readable media. Formats in which such circuit, layout, and architecture expressions can be implemented include, but are not limited to, formats supporting behavioral languages ​​such as C, Verilog, and VHDL, formats supporting register-level description languages ​​such as RTL, and formats supporting geometric description languages ​​such as GDSII, GDSIII, GDSIV, CIF, MEBES, and any other suitable formats and languages. Computer-readable media in which such formatted data and / or instructions can be implemented include (but are not limited to) various forms of computer storage media (e.g., optical, magnetic, or semiconductor storage media, whether independently distributed or "in-situ" stored in the operating system in the manner described).

[0061] When received within a computer system via one or more computer-readable media, this data- and / or instruction-based representation of the circuitry and device architecture can be processed by a processing entity within the computer system (e.g., one or more processors) in conjunction with the execution of one or more other computer programs, including but not limited to netlist generators, location and routing programs, to generate a representation or image of the physical representation of such circuitry and architecture. Such a representation or image can then be used in device manufacturing, for example, by enabling the generation of one or more masks used to form various components of the circuitry in the device manufacturing process.

[0062] In the foregoing description and accompanying drawings, specific terms and reference numerals have been set forth to provide a full understanding of the disclosed embodiments. In some cases, terms and reference numerals may imply details not required for implementing those embodiments. For example, any of the following may differ from those in the alternative embodiments described above: a specific time interval, transistor type, signal polarity, array dimension, relative control pulse timing, number / type of photodetector elements, photocarrier polarity, etc. Signal paths depicted or described as individual signal lines may alternatively be implemented by a multi-conductor signal bus, and may include multiple conductors for each transmitted signal (e.g., differential or pseudo-differential signaling). The term “coupled” as used herein refers to both direct connections and connections via one or more intermediate functional components or structures. Programming of operating parameters (effective pixel size, applied conversion gain, charge banding configuration, net dynamic conversion gain capacitance, output signal interpolation or other processing parameters, scaled cumulative interval, subpixel readout sequence, output signal selection threshold, etc.) or any other configurable parameters can be achieved (e.g., but not limited to) loading control values ​​into registers or other storage circuits within the aforementioned imaging IC in response to host instructions (and thus controlling the operating aspects of the device and / or establishing a device configuration) or through a one-time programming operation (e.g., blowing a fuse within the configuration circuit during device production), and / or connecting one or more selected pins or other contact structures of the device to a reference voltage line (also known as bundling) to establish a specific device configuration or operating aspect of the device. The terms “exemplary” and “example” are used to indicate examples, not preferences or requirements. Furthermore, the terms “may” and “can” are used interchangeably to indicate optional (permissible) subject matter. The omission of any term should not be construed as implying a requirement for a given feature or technique.

[0063] Various modifications and changes can be made to the embodiments presented herein without departing from the broader spirit and scope of this disclosure. For example, features or aspects of any embodiment may be used in combination with or in place of corresponding features or aspects of any other embodiment. Therefore, the specification and drawings are to be considered illustrative rather than restrictive.

Claims

1. An integrated circuit image sensor, comprising: Four sets of photoelectric detection elements are set in the corresponding image sensor areas with shared angles; Four readout circuits, each coupled to a corresponding set of photodetectors in the four sets of photodetectors, each readout circuit having: Floating diffusion nodes; A first transmission gate is coupled between the floating diffusion node and the constituent photoelectric detection elements of the corresponding group of photoelectric detection elements in the four groups of photoelectric detection elements; as well as An amplifier transistor having a gate terminal coupled to the floating diffusion node; Reset node; A reset transistor, the reset transistor being coupled between the reset node and the reset voltage supply; Multiple segmented transistors, each of the segmented transistors being coupled between the reset node and the floating diffusion node of the corresponding readout circuit in the readout circuit; A gain control transistor, the gain control transistor being coupled between the reset node and the reset transistor; as well as A capacitor element coupled between the gain control transistor and the reset transistor.

2. The integrated circuit image sensor of claim 1, wherein each of the four readout circuits comprises three additional transmission gates, each of the additional transmission gates being coupled between the floating diffusion node of the readout circuit and three additional constituent photodetectors within a corresponding set of photodetectors in the four sets of photodetectors, such that each readout circuit is coupled to a corresponding set of four photodetectors, and wherein each set of four photodetectors has an aggregate aspect ratio that nominally matches the aspect ratio of an individual photodetector within the set of four photodetectors.

3. The integrated circuit image sensor according to claim 2, wherein the four groups of photoelectric detection elements have an aspect ratio that nominally matches the aspect ratio of the four photoelectric detection elements in each corresponding group.

4. The integrated circuit image sensor of claim 1, wherein the gain control transistor is coupled between the reset node and the reset transistor such that both the reset transistor and the gain control transistor must be presented in a drain-to-source conducting state to charge the reset node via the reset voltage supply.

5. The integrated circuit image sensor of claim 1, further comprising a control signal generator for: During the first, second, and third consecutive phases of the multi-stage readout operation, a first transmission gate pulse, a second transmission gate pulse, and a third transmission gate pulse are asserted at the gate of the first transmission gate, each of the first, second, and third transmission gate pulses enabling photocharge transfer from one of the photodetectors to the floating diffusion node. During the first phase of the multi-stage readout operation, the banding transistor and the gain control transistor are kept in a non-conducting state to achieve a first conversion gain for the photocharge transfer enabled by the first transmission gate pulse. During the second phase of the multi-stage readout operation, at least one of the banding transistors is switched to the on state, and the gain control transistor is maintained in the off state to achieve a second conversion gain for the photocharge transfer enabled by the second transmission gate pulse, the second conversion gain being lower than the first conversion gain. as well as During the third stage of the multi-stage readout operation, when at least one of the segmentation transistors is in the on state, the gain control signal is switched to the on state to achieve a third conversion gain for the photocharge transfer enabled by the third transmission gate pulse, the third conversion gain being lower than the second conversion gain.

6. The integrated circuit image sensor of claim 1, further comprising a control signal generator for: During the first and second consecutive phases of the multi-stage readout operation, a first transmission gate pulse and a second transmission gate pulse are asserted at the gate of the first transmission gate, each of the first and second transmission gate pulses enabling photocharge transfer from one of the photodetectors to the floating diffusion node. During the first stage of the multi-stage readout operation, the banding transistor is kept in a non-conducting state to achieve a first conversion gain for the photocharge transfer enabled by the first transmission gate pulse. as well as During the second phase of the multi-stage readout operation, at least one of the segmentation transistors is switched to an on state to achieve a second conversion gain for the photocharge transfer enabled by the second transmission gate pulse, the second conversion gain being lower than the first conversion gain.

7. The integrated circuit image sensor of claim 6, wherein the control signal generator additionally asserts, during each of the first and second reset intervals preceding the first and second stages of the multi-stage readout operation, a control pulse on the reset transistor and a control pulse on at least one of the segmentation transistors, to couple the reset voltage supply to the floating diffusion node of at least one readout circuit in the readout circuit.

8. The integrated circuit image sensor of claim 6, wherein the control signal generator outputs a control signal to reset the constituent photodetector elements in each group of photodetector elements at time-interleaved offsets within the exposure interval.

9. The integrated circuit image sensor according to any one of claims 1-8, further comprising: A color filter array having corresponding color filter elements disposed on the four sets of photoelectric detection elements and organized into a mosaic color pattern; as well as A microlens array having a corresponding microlens element disposed on each constituent photodetector element in each group of photodetector elements.

10. The integrated circuit image sensor according to any one of claims 1-8, wherein two of the four readout circuits are commonly coupled to a first output line, and the other two of the four readout circuits are commonly coupled to a second output line.

11. A method of operating within an integrated circuit pixel array, the integrated circuit pixel array having four sets of photodetectors disposed in corresponding pixel array regions having a shared angle, a reset node, four floating diffusion nodes, four readout circuits respectively coupled to the four floating diffusion nodes, and four segmentation transistors coupled between the reset node and a corresponding floating diffusion node among the four floating diffusion nodes, the method comprising: During the reset interval, the reset transistor is switched to the on state to couple the reset node to the reset voltage supply; During the reset interval, the segmented transistor is switched to the on state to couple the corresponding floating diffusion node to the reset node, such that each of the floating diffusion nodes is charged to the reset potential by the reset voltage supply. as well as A gain control transistor coupled between the reset node and the reset transistor is switched, wherein the gain control transistor is switched in combination with the banding transistor to apply multiple different conversion gains to a given photocharge transfer from the four sets of photodetectors during the readout interval.

12. The method of claim 11, further comprising: The method further includes generating a first output signal corresponding to the reset potential of the corresponding floating diffusion node via a readout circuit in the readout circuit, wherein generating the first output signal includes generating the first output signal while the banding transistor is held in the on state, the method further includes: switching the banding transistor to a non-conducting state, and generating a second output signal while the banding transistor is held in the non-conducting state, wherein generating the first output signal includes generating the first output signal during a first reset state sampling interval, and generating the second output signal includes generating the second output signal during a second reset state sampling interval occurring after the first reset state sampling interval, the method further includes: maintaining the reset transistor in the non-conducting state, and maintaining the reset transistor in the non-conducting state from the beginning of the first reset state sampling interval to the end of the second reset state sampling interval.

13. The method of claim 11, wherein the four floating diffusion nodes are respectively coupled to the four groups of photodetectors via four transmission gates of corresponding groups, the method further comprising: The pixel size value is stored in a programmed register, which indicates a predetermined number of non-zero transmission gates. After the reset interval occurs, the predetermined number of non-zero transmission gates in each group of four transmission gates are switched to the on state to enable photocharge transfer from the corresponding predetermined number of non-zero photodetectors in each of the four groups of photodetectors to the corresponding floating diffusion node.

14. The method according to claim 11, 12 or 13, wherein the method further comprises: During the reset interval, the gain control transistor is switched to the on state to couple the reset voltage supply to the reset node via the reset transistor and the gain control transistor.

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