A firmware update method, device and data system

Abstract

This invention discloses a firmware update method, device, and data system. The firmware update method is applied to a first device, which includes at least one PCI configuration space for configuring functions for the first device. The method specifically includes: configuring firmware update capability in a first PCI configuration space within the at least one PCI configuration space; and updating first firmware to the first device based on the firmware update capability.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and in particular to a firmware update method, device and data system. Background Technology

[0002] In the field of memory, a memory system can be configured with one or more communication interfaces to communicate with one or more components in the host. Currently, the most widely used interface is the Peripheral Component Interconnect Express (PCIe). As the functionality of the PCIe interface continues to improve, the corresponding firmware in the memory system also needs to be upgraded accordingly. However, current upgrade methods are limited by the tools provided by the vendors, making firmware upgrades complex and inconvenient for practical testing and maintenance personnel. Summary of the Invention

[0003] In view of this, embodiments of the present invention provide a firmware update method, device, and data system, providing a convenient and quick firmware update method to easily and quickly upgrade the firmware in PCIe type devices without the need for driver tools.

[0004] To achieve the above objectives, the technical solution of the present invention is implemented as follows:

[0005] In a first aspect, the present invention provides a firmware update method, applied to a first device having at least one external device interconnect PCI configuration space, the method comprising:

[0006] The firmware update capability is configured in the first PCI configuration space within the at least one PCI configuration space.

[0007] The first firmware is updated to the first device based on the firmware update capability.

[0008] In a second aspect, the present invention also provides a first device, the first device comprising a processor and at least one external device interconnect PCI configuration space, wherein;

[0009] The processor is configured to: configure firmware update capability in a first PCI configuration space within the at least one PCI configuration space; and update first firmware to the first device based on the firmware update capability.

[0010] Thirdly, embodiments of the present invention also provide a data system.

[0011] The data system includes a host and a first device; wherein the first device includes at least one external device interconnect PCI configuration space and communicates with the host through at least one of the following interfaces: PCI interface, PCI-X interface, and PCIe interface;

[0012] The host sends a configuration request to the first device;

[0013] The first device receives the configuration request through a first interface and configures firmware update capability in the first PCI configuration space in at least one PCI configuration space based on the configuration request; the first interface is one of PCI interface, PCI-X interface, and PCIe interface;

[0014] The host sends one or more write commands containing data related to the first firmware to the first device;

[0015] The first device receives one or more write commands through the first interface and writes the data related to the first firmware to the corresponding position of the first data structure corresponding to the firmware update capability; upon receiving an update command, it updates the first firmware to the first device based on the update command.

[0016] This invention provides a firmware update method, device, and data system. The firmware update method is applied to a first device having at least one PCI configuration space. The method includes: configuring firmware update capability in the first PCI configuration space; and updating first firmware to the first device based on the firmware update capability. The firmware update method and device provided by this invention, by defining a new firmware update capability in the PCI configuration space of the first device, enables the updating of the first firmware through this firmware update capability. This allows for convenient and quick firmware upgrades without the need for driver tools. Furthermore, the firmware update method provided by this invention can be applied to different types of devices with PCI configuration spaces, demonstrating a certain degree of universality. Attached Figure Description

[0017] In accompanying drawings that are not necessarily drawn to scale, the same reference numerals can describe similar components in different views. The same numbers with different letter suffixes can represent different instances of similar components. The accompanying drawings generally illustrate the various embodiments discussed in this document by way of example, not limitation.

[0018] Figure 1 This is a schematic diagram of the structure of a data system provided in an embodiment of the present invention;

[0019] Figure 2 This is a schematic diagram of the structure of a storage device provided in an embodiment of the present invention;

[0020] Figure 3 A perspective view of a portion of an exemplary embodiment of a single-block three-dimensional memory array provided in an embodiment of the present invention;

[0021] Figure 4 This is a schematic diagram of the array structure of the storage unit provided in an embodiment of the present invention;

[0022] Figures 5A to 5C This is a schematic diagram of the communication topology of a data system with a PCIe interface provided in an embodiment of the present invention;

[0023] Figure 6 A schematic diagram of a layered structure with a PCIe interface provided for an embodiment of the present invention;

[0024] Figure 7A and Figure 7B A schematic diagram of the configuration space provided in an embodiment of the present invention;

[0025] Figure 8 A flowchart illustrating the firmware update method provided in an embodiment of the present invention;

[0026] Figure 9 A schematic diagram of the relationship between various capabilities in the configuration space provided in this embodiment of the invention. Figure 1 ;

[0027] Figure 10 This is a schematic diagram illustrating the relationship between various capabilities in the configuration space provided in the embodiments of the present invention. Figure 2 ;

[0028] Figure 11 This is a schematic diagram of the firmware update process for the first device provided in an embodiment of the present invention. Figure 1 ;

[0029] Figure 12 This is a schematic diagram of the firmware update process for the first device provided in an embodiment of the present invention. Figure 2 ;

[0030] Figure 13 This is a schematic diagram of the structure of the first device provided in an embodiment of the present invention. Detailed Implementation

[0031] Various embodiments of the invention are described in more detail below with reference to the accompanying drawings. Other embodiments, variations of any disclosed embodiment, can be formed by different configurations or arrangements of the elements and features in the embodiments of the invention. Therefore, the embodiments of the invention are not limited to those set forth herein. Rather, the described embodiments are provided so that the embodiments of the invention are thorough and complete, and fully convey the scope of the embodiments of the invention to those skilled in the art. It should be noted that references to "embodiment," "another embodiment," etc., do not necessarily indicate only one embodiment, and different references to any such phrases do not necessarily refer to the same embodiment. It should be understood that although the terms "first," "second," "third," etc., may be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element having the same or similar name. Therefore, a first element in one embodiment may also be referred to as a second or third element in another embodiment without departing from the spirit and scope of the embodiments of the invention.

[0032] The accompanying drawings are not necessarily drawn to scale, and in some cases, the scale may be enlarged to clearly show the features of the embodiments. When an element is referred to as a connection or coupling to another element, it should be understood that the former may be directly connected to or coupled to the latter, or may be electrically connected to or coupled to the latter via one or more intermediate elements between the two. Furthermore, it should be understood that when an element is referred to as being "between" two elements, the element may be the only element between the two elements, or there may be one or more intermediate elements.

[0033] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, singular forms are intended to include plural forms unless the context clearly indicates otherwise. Unless otherwise stated or clearly understood from the context, the articles “a” and / or “an” used in embodiments of the invention and the appended claims should be interpreted as meaning “one or more”. It should be further understood that the terms “comprising,” “including,” “containing,” and “comprising” as used in embodiments of the invention specify the presence of the stated element and do not exclude the presence or addition of one or more other elements. The term “and / or” as used in embodiments of the invention includes any and all combinations of one or more of the associated listed items. Unless otherwise defined, all terms used in embodiments of the invention, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains in light of embodiments of the invention. It should be further understood that unless explicitly defined in embodiments of the invention, terms such as “belong to” as defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of embodiments of the invention and related technologies, and should not be interpreted in an idealized or overly formal manner.

[0034] In the following description, numerous specific details are set forth to provide a thorough understanding of the invention, which can be practiced without some or all of these specific details. In other instances, well-known processing structures and / or processes have not been described in detail so as not to unnecessarily obscure the invention. It should also be understood that, in some cases, unless otherwise specifically apparent to those skilled in the art, a feature or element described with respect to one embodiment may be used alone or in combination with other features or elements of another embodiment. Various embodiments of the invention are described in detail below with reference to the accompanying drawings. The following description focuses on detail to facilitate understanding of embodiments of the invention. Well-known technical details may have been omitted so as not to obscure the features and aspects of the embodiments of the invention.

[0035] This invention relates to a method, apparatus, and data system that enables a host to conveniently and quickly update the firmware of a memory system. The main idea can be described as follows: when a device containing a memory system or other device has configuration space, the configuration space is used to configure firmware update capabilities, and then these firmware update capabilities are used to update the device containing the memory system or other device with the required new firmware.

[0036] The embodiments of the present invention will be further described in detail below with reference to the accompanying drawings and specific examples.

[0037] Figure 1This is a schematic diagram of the structure of a data system provided in an embodiment of the present invention. The data system 100 may include a host 101 and one or more first devices 102; the host 101 communicates with the one or more first devices 102 via a communication interface. Some of the one or more first devices 102 may include a memory system 200. The host 101 and / or the memory system 200 may be included in various products, such as Internet of Things (IoT) devices, such as refrigerators or other devices, sensors, motors, mobile communication devices, automobiles, autonomous vehicles, etc., to support product processing, communication, or control.

[0038] The memory system 200 may include a memory controller 1021 and one or more memory devices 1022, wherein one of the memory devices 1022 is, for example... Figure 2 As shown, a memory array 1022-1 comprising a stack of multiple individual memory dies and a control circuit 1022-2 coupled to the periphery of the memory array 1022-1 are included. The memory array 1022-1 can be stacked in two or three dimensions (3D), such as a stack of two-dimensional or three-dimensional (3D) NAND dies. One implementable structure is as follows: Figure 3 As shown. Figure 3 This is a perspective view showing a portion of an exemplary embodiment of a single-block three-dimensional memory array provided by an embodiment of the present invention.

[0039] It should be noted that the memory array 1022-1 in the storage device 1022 has multiple memory blocks, and its exemplary structure is as follows: Figure 4 As shown, the memory array is divided into BLOCK1-BLOCKT, each containing multiple memory blocks, where T is a positive integer and is generally a large number. Each memory block contains a set of NAND strings, which are accessed via bit lines BL0-BLM-1 and a set of common word lines WL0-WLN-1, where M and N are both integers greater than 1. One terminal of the NAND string is connected to the corresponding bit line via the top select gate SGD (controlled by the top select gate line SGDL), and the other terminal is connected to the source line via the bottom select gate SGS (controlled by the bottom select gate line SGSL). Each memory block is divided into multiple pages. In some embodiments, memory blocks are conventional erase units, and pages are conventional programming units. In other embodiments, other units of erasure and programming may also be used. In an example, Figure 4 The physical structure of the memory cells in the illustrated memory array does not limit the scope of the invention.

[0040] In this invention, Figure 4 The memory array shown can be arranged in a 3D QLC structure. It should be noted that other structural arrangements do not limit the scope of the present invention.

[0041] Figure 3 This shows one of the blocks. (Reference) Figure 3 The storage block 30 comprises multiple layers stacked on a substrate (not shown) and parallel to the surface of the substrate. Figure 3 The diagram shows four word lines (WL) on four layers, which may be designated WL0 to WL3. The memory block 30 also has multiple vias perpendicular to the word lines. The intersection of a word line and a via forms a memory cell; therefore, a via can also be referred to as a memory cell string. Those skilled in the art should understand that the number of word lines and memory cell strings in the memory block 30 is not limited to specific values. For example, the memory block 30 may include 64 word lines, with 64 word lines intersecting a memory cell string to form 64 memory cells along the memory cell string. Furthermore, the memory block 30 may include a number of memory cell strings on the order of hundreds of thousands, millions, or even larger, with a single word line including millions of memory cells formed by its intersection with, for example, millions of memory cell strings. The memory cells in storage block 30 can be single-level memory cells or multi-level memory cells. A single-level memory cell can be a single-level cell (SLC) capable of storing 1 bit; a multi-level memory cell can be a multi-level cell (MLC) capable of storing 2 bits, a three-level cell (TLC) capable of storing 3 bits, a four-level cell (QLC) capable of storing 4 bits, or a five-level cell (PLC) capable of storing 5 bits. For example... Figure 3 As shown, memory block 30 also includes bit lines (BL), bit line selectors (BLS, also known as top select gate line SGDL), source lines (SL), and source select lines (SLS, also known as bottom select gate line SGSL). These circuit lines, together with word lines (WL), enable addressing of any memory cell in memory block 30.

[0042] In some embodiments, such as Figure 2 The memory device 1022 shown further includes read / write circuitry, a row decoder, and a column decoder. In some embodiments, various peripheral circuits access the memory array 1022-1 in a symmetrical manner on opposite sides of the memory array 1022-1 to reduce the density of access circuitry on each side by half. The read / write circuitry includes multiple sensing blocks SB for parallel reading or programming of pages in the memory array 1022-1. The memory array 1022-1 can be addressed via word lines through the row decoder and bit lines through the column decoder. In some embodiments, the memory array 1022-1, control circuitry 1022-2, read / write circuitry, row decoder, and column decoder can be fabricated on a chip, wherein... Figure 2The dashed box can also represent a chip. And it is transmitted between the memory controller 1021 and the chip via signal line 1022-3. Figure 2 The diagram also illustrates the arrangement of multiple dummy cells, dummy word lines, and dummy bit lines (not shown) within the dummy memory areas DMX and DMY, such as... Figure 2 The dummy memories DMX1-DMX2 and DMY1-DMY2 shown are arranged along the side of the memory array 1022-1 and are used for read / write tests after the memory system is completed.

[0043] Control circuitry 1022-2 is configured to cooperate with read / write circuitry to perform memory operations on memory array 1022-1. The control circuitry includes a state machine, an on-chip address decoder, and a power control module. The state machine is configured to provide chip-level control for memory operations; the on-chip address decoder is configured to provide an address interface between the address used by the host or memory system controller and the hardware address used by the row and column decoders. The power control module is configured to control the power and voltage supplied to the word lines and bit lines during each memory operation.

[0044] In 3D architecture semiconductor memory technology, stacking vertical structures in memory arrays increases the number of layers and physical pages, thereby increasing the density of the memory system. In one embodiment, memory system 200 can be a discrete memory or memory component of host 101. In other embodiments, memory system 200 can also be part of an integrated circuit, such as a system-on-a-chip (SoC). In this case, memory system 200 is stacked or otherwise assembled with one or more components of host 101.

[0045] exist Figure 1 In the data system 100, the host 101 may include a host processor and host RAM, wherein the host RAM may include DRAM, SDRAM, or any other suitable volatile or non-volatile memory device. The memory system 200 may be provided with one or more communication interfaces for communicating with one or more components of the host 101. The one or more communication interfaces may be a Serial Advanced Technology Attachment (SATA) interface, a High-Speed ​​Peripheral Component Interconnect (PCIe) interface, a PCI interface, a PCI-X interface, a Universal Serial Bus (USB) interface, a Universal Flash Memory (UFS) interface, or an eMMC interface. TM Interfaces, etc.

[0046] Among them, the PCIe interface is currently the most commonly used. It is a serial bus, unlike the single-channel SATA, PCIe connections can expand bandwidth by increasing the number of channels, offering great flexibility. More channels mean faster speeds, but also higher costs, larger space requirements, and higher power consumption. The PCIe interface evolved from PCI interface technology, but it is faster than PCI and PCI-X interfaces. This is because PCIe has a fundamental difference in physical transmission compared to PCI and PCI-X: as data transfer rates increase, due to bus clock frequency limitations, PCIe's serial data transmission is faster than the parallel data transmission of PCI and PCI-X. In some embodiments, in a data system 100, various devices with PCIe interfaces (hereinafter referred to as PCIe devices) can communicate with the host 101 using a tree topology, specifically as follows... Figure 5A As shown, the entire topology formed by various devices with PCIe interfaces (hereinafter referred to as the PCIe topology) can be a tree structure. The Root Complex (RC) is the root of the tree; it represents the host processor (which can be implemented by the CPU) in the data system 100 and communicates with other parts of the data system 100. For example, the CPU accesses the host RAM (memory) through it, and accesses other devices in the PCIe topology, such as the first device 102, through the RC. The RC is internally complex. In summary, the RC can implement an internal PCIe bus and extend several PCIe ports through several PCIe bridges, specifically as follows... Figure 5B As shown.

[0047] like Figure 5C As shown, in a PCIe topology, a switch expands PCIe ports. The port closest to the RC (Regulator / Controller) is called the upstream port, and the ports branching off from it are called downstream ports. A switch has only one upstream port, but can expand to several downstream ports. Downstream ports can directly connect to endpoints, such as PCIe devices; for example, the first device 102. Downstream ports can also connect to the switch to expand even more ports, such as... Figure 5C EP1, EP2, EP3, etc.

[0048] In some embodiments, PCIe devices can be implemented in a tiered manner, such as... Figure 6As shown, it defines three layers: the Transaction Layer, the Data Link Layer, and the Physical Layer (including logical and electrical submodules). Each layer has a different function but serves the upper layer. PCIe data transmission is in the form of packets, and each layer's packets have a fixed format. In some embodiments, each Endpoint and each Switch in the PCIe topology must implement the aforementioned three layers.

[0049] In a PCIe topology, each PCIe device (such as the aforementioned Endpoint and Switch) has a space where the host 101 can access information about its coupled PCIe devices and configure them. This space can be called the PCIe configuration space, which is a specific implementation of the PCI configuration space described in this embodiment. This configuration space is predefined by the protocol; what content is placed where is defined. This configuration space existed in the PCI and PCI-X era, and its structure can be as follows... Figure 7A As shown. With the advent of the PCIe era, its structure can... Figure 7B As shown. The entire configuration space can be a collection of registers, consisting of two parts: a 64-byte header and a 192-byte capability data structure (the structure of the PCI and PCI-X era); in the PCIe era, the configuration space structure, in addition to the above, also includes a 3840-byte capability data structure. Here, capability refers to the capabilities that this PCIe device possesses under a certain function. The specific capabilities can be configured through the 64-byte header.

[0050] In some embodiments, each PCIe device has at least one configuration space, as a PCIe device may have multiple functions, such as functioning as both a hard drive and a network card, with each function corresponding to a configuration space. In other embodiments, the configuration space corresponding to each function may contain one or more Capabilities.

[0051] Figure 1The data system 100 operates as follows: A memory controller 1021 receives instructions from a host 101 and communicates with the storage device 1022. For example, the memory controller 1021 may execute write or erase instructions to transfer data to one or more memory cells, planes, sub-blocks, blocks, or pages within the storage device 1022; or the memory controller 1021 may execute read instructions to transfer data to the host 101. In hardware, the memory controller 1021 may include one or more controller units, circuits, or components configured to control access across the storage device 1022 and provide a translation layer between the host 101 and the memory system 200. The memory controller 1021 may also include one or more input / output (I / O) circuits, lines, or interfaces to transfer data to or from the storage device 1022. The memory controller 1021 may also include a memory management unit and an array control unit.

[0052] The memory management unit may include circuit hardware or firmware, such as multiple components or integrated circuits associated with various memory management functions. To describe the technical solution of the present invention, NAND memory is used as an example for contextual description of memory operation or management functions. Those skilled in the art should understand that other forms of non-volatile memory may have similar memory operation or management functions. The management functions of NAND memory may include wear leveling, such as garbage collection or recycling, error detection or correction, block retirement, or one or more other memory management functions. The memory management unit may process instructions from host 101 into commands recognizable by the memory system 200, for example, parsing or formatting instructions received from host 101 into commands related to the operation of the memory device 1022; or the memory management unit may also generate device commands for the array control unit or one or more other components of the memory system 200, such as commands to implement various memory management functions.

[0053] The memory management unit can be configured to include a set of management tables for maintaining various information associated with one or more components of the memory system 200, such as various information related to the memory array coupled to the memory controller 1021, or one or more memory cells. For example, the management tables may include information such as block age, block erase count, error history, or one or more error counts for one or more blocks of memory cells coupled to the memory controller 1021. Error counts may include operation error counts, read bit error counts, etc. In some embodiments, if the detected error count exceeds a certain threshold, the bit error is an uncorrectable bit error. In some embodiments, the management tables may maintain counts of correctable or uncorrectable bit errors, etc.

[0054] The management table may also contain one or more L2P tables, which contain one or more L2P pointers that associate logical addresses with physical addresses at the memory array of the storage device 1022. In some embodiments, the management table may contain unencrypted L2P tables and / or encrypted L2P tables. Unencrypted L2P tables may include L2P pointers indicating unencrypted logical addresses and unencrypted physical addresses; encrypted L2P tables may contain encrypted L2P pointers indicating encrypted physical addresses and unencrypted logical addresses. In practical applications, the management table may be displayed at the memory management unit, i.e., the management table may be stored in the RAM of the memory controller 1021. In other embodiments, the management table may also be stored in the memory array within the storage device 1022. In use, the memory management unit may read a portion or all of the cached management table from the RAM of the memory controller 1021; it may also read the management table from the memory array within the storage device 1022.

[0055] The array control unit may include circuitry or components configured to control the following related memory operations: writing data to one or more memory cells coupled to the memory system 200 of the memory controller 1021, reading data from the one or more memory cells, or erasing the one or more memory cells. The array control unit may receive commands sent by the host 101, or host commands generated internally by the memory management unit; these host commands may be related to wear leveling, error detection, or correction.

[0056] The array control unit may also include an error correction code (ECC) component, which may contain an ECC engine or other circuitry for detecting or correcting errors associated with writing or reading data from one or more memory cells coupled to the memory system 200 of the memory controller 1021. The memory controller 1021 is configured to effectively detect and recover from various operational or data storage-related error events, such as bit errors, operational errors, etc., while maintaining the integrity of data transferred between the host 101 and the memory system 200, or maintaining the integrity of stored data, for example, by using redundant RAID storage. Failed memory resources, such as memory cells, memory arrays, pages, blocks, etc., may be removed or decommissioned to prevent future errors.

[0057] exist Figure 1In the data system 100, the memory controller 1021 further includes an encryption / decryption unit configured to perform cryptographic operations on data, such as encrypting an unencrypted physical address and decrypting an encrypted physical address as described in this invention. In some embodiments, the encryption / decryption unit may be implemented in hardware, software, or a combination of both. For example, the encryption / decryption unit may contain instructions that execute at a processor or similar hardware component of the memory controller 1021. In some embodiments, the encryption / decryption unit may include transfer hardware for performing cryptographic operations.

[0058] The memory array in the storage device 1022 may include, for example, a number of memory cells arranged in one or more devices, one or more planes, one or more sub-blocks, one or more blocks, one or more pages, etc. As an example, a 48GB TLC NAND memory system may include 18,592 bytes (B) of data per page (16,384 + 2,208 bytes), 1,536 pages per block, 548 blocks per plane, and four or more planes per device. As another example, a 32GB MLC memory system (storing two bits of data per cell (i.e., four programmable states)) may include 18,592 bytes (B) of data per page (16,384 + 2,208 bytes), 1,024 pages per block, 548 blocks per plane, and four planes per device, but requires half the write time and doubles the program / erase (P / E) cycles compared to the corresponding TLC memory system. Other examples may include other numbers or arrangements. In some instances, the memory system or a portion thereof may selectively operate in SLC mode or in the desired MLC mode (e.g., TLC, QLC, etc.).

[0059] The memory array in the storage device 1022 includes one or more physical address locations. A physical address location is a location on the memory array in the storage device 1022 that is uniquely associated with a physical address. In operation, data is typically written to or read from the memory system 200 in units of pages and erased in units of blocks. However, one or more memory operations (e.g., read, write, erase, etc.) may be performed on larger or smaller groups of memory cells as needed. Therefore, in some instances, a physical address location may include more or less than one page. The data transfer size of the memory system 200 is typically referred to as a page, while the data transfer size of the host is typically referred to as a sector.

[0060] While a page of data may include several bytes of user data (e.g., a data payload comprising several data sectors) and its corresponding metadata, the page size typically refers only to the number of bytes used to store the user data. As an example, a 4KB data page may include 4KB of user data (e.g., eight sectors with a presentation sector size of 512B) and several bytes of metadata corresponding to the user data (e.g., 32B, 54B, 224B, etc.), such as integrity data (e.g., error detection or correction code data), address data (e.g., logical address data, etc.), or other metadata associated with the user data. The physical address location used to store metadata, etc., may be referred to as the hyper-supply physical address location.

[0061] Different types of memory cells or the memory device 1022 may provide different page sizes, or may require different amounts of metadata associated with them. For example, different memory system types may have different bit error rates, which can result in different amounts of metadata necessary to ensure the integrity of data pages (e.g., a memory system with a higher bit error rate may require more bytes of error correction code data than a memory system with a lower bit error rate). For example, a multi-level cell (MLC) NAND flash device may have a higher bit error rate than a corresponding single-level cell (SLC) NAND flash device. Therefore, an MLC device may require more bytes of metadata for error data than a corresponding SLC device.

[0062] Figure 1The first device 102 in the illustrated data system 100 frequently requires firmware updates during development and use. In actual use, the first device 102 may be different types of PCIe devices, such as the aforementioned hard drives, network cards, etc.; depending on its position in the PCIe topology, the first device 102 may also be an Endpoint, a Switch, etc.; the first device may also be a PCIe device provided by different vendors. Those skilled in the art should know that different types of PCIe devices have their own defined firmware update methods and may require different driver tools to complete firmware updates. In some embodiments, the firmware update method for PCIe devices may include: First, in-band update, which is configured by a debugger via computer within the storage space. For example, for PCIe devices of the Non-Volatile Memory Host Controller Interface Specification (NVMHCIS), or simply NVM Express (NVMe), the firmware in the device can be updated using commands in the NVMe standard, vendor-specific methods (VU, Vender Unique), etc. The second method is out-of-band updates, which utilize the external interface of the PCIe device to obtain the firmware to be updated from the host. These interfaces include the System Management Bus (SMBus) interface and the Universal Asynchronous Receiver / Transmitter (UART) interface. By connecting the host to the Boot pin on the printed circuit board (PCB) of the PCIe device, the firmware to be updated obtained from the host is transmitted to the PCIe device to achieve firmware updates. The third method uses debugging instruments, such as the Joint Test Action Group (JTAG), an international standard test protocol mainly used for internal chip testing; and the Enhanced Joint Test Action Group (EJTAG), a specification extended from JTAG, which is a hardware / software subsystem that implements a set of hardware-based debugging features inside the processor to support on-chip debugging.

[0063] Of the three firmware update methods mentioned above, the in-band update method requires the application layer protocol of the data system 100 to be available. Those skilled in the art should know that different PCIe devices may correspond to different application layers. Therefore, the methods and driver tools used for device firmware updates are also diverse. For example, the firmware update methods for NVMe PCIe devices, Ethernet Card PCIe devices, and Graphics Processing Unit (GPU) PCIe devices are all different. This explains why, before updating the firmware of a certain type of PCIe device (e.g., an NVMe SSD), the NVMe SSD needs to be set to Read-Only Memory (ROM) mode. In ROM mode, a protocol stack runs to prepare for the firmware update. In this ROM mode, different PCIe devices correspond to different application layer protocols, requiring different drivers, and thus requiring tools that match the drivers to complete the firmware update of the PCIe device. The above three firmware update methods are cumbersome and costly for different PCIe devices, and are not universally applicable.

[0064] Based on this, in order to solve the above-mentioned technical problems, such as Figure 8 As shown, it illustrates a flowchart of a firmware update method provided by an embodiment of the present invention. Figure 8 In this context, the method is applied to a first device having at least one PCI configuration space, and the specific method flow may include:

[0065] S801: Configure firmware update capability in the first PCI configuration space of the at least one PCI configuration space;

[0066] S802: Update the first firmware to the first device based on the firmware update capability.

[0067] It should be noted that the first device mentioned here can be any device described above that has at least one of a PCIe interface, a PCI interface, or a PCI-X interface. Since we have now entered the PCIe era, unless otherwise specified, the following embodiments described in this invention use various devices with a PCIe interface as examples to illustrate the concept of this invention.

[0068] Here, based on the foregoing description of PCIe devices, the first device can correspond to one or more functions, each function corresponds to a configuration space, and each function can correspond to one or more capabilities. Therefore, the first device can have at least one configuration space for configuring its own functions. The relationship between various capabilities and headers in the configuration space corresponding to a certain function can be as follows: Figure 9 As shown. In Figure 9 The example below uses three capabilities as an example. Here, Header, Capability_1, Capability_2, and Capability_3 are connected in sequence to form a linked list.

[0069] As an optional implementation, S801 may include:

[0070] Define a first data structure corresponding to the firmware update capability in the first PCI configuration space;

[0071] Based on the first data structure, the firmware update capability is added to the first capability linked list to form the second capability linked list, so that the firmware update capability is configured in the first PCI configuration space; wherein, the first capability linked list is a linked list that already has capabilities in the first PCI configuration space.

[0072] Here, the first PCI configuration space is one of the at least one PCI configuration spaces. In some embodiments, if the first device has multiple functions, the first PCI configuration space is determined according to the user's need to update a specific function in the first device. For example, if the first device has the aforementioned hard drive and network card functions, and the user wants to update the firmware of the hard drive function, then the first PCI configuration space should be the configuration space corresponding to the hard drive function. That is, this describes adding a custom new capability to the capability list that can already be implemented in the first PCI configuration space of the first device to form a new capability list, so that the first device can implement the new capability. When the new capability is the firmware update capability described in the embodiments of the present invention, an optional configuration process may specifically include the following steps:

[0073] First, a first data structure corresponding to the firmware update capability is defined in the first PCI configuration space. An optional first data structure is shown in Table 1 below. This first data structure may include a basic information field, a command information field, a receipt information field, and a data information field. The basic information field may include pointer information, identification information of the type to which the firmware update capability belongs, length information of the first data structure, version information of the firmware update capability, and identity information of the firmware update capability under its type, etc.

[0074] Table 1

[0075] Basic Information Field Command information field Receipt Information Field Data Information Domain

[0076] In some embodiments, the pointer information is used to point to the next capability, indicating the position of the firmware update capability in the capability chain.

[0077] In some embodiments, the firmware update capability may be of two types: one is a standard protocol capability; the other is an extended capability. Standard protocol capabilities are those specified in the protocol; extended capabilities are those that are extended beyond the standard protocol capabilities based on different functions, devices, or developers.

[0078] In some embodiments, the type identification information can be used to indicate whether the firmware update capability is an extended function in the first device or a standard protocol capability in the first device. For example, if the identifier 0xB indicates an extended function provided by the developer, then the identifier information of the type in the first data structure of the firmware update capability is 0xB.

[0079] In some embodiments, a device may contain more than one capability of the same type. For example, the first device may have three extended capabilities. How are these three capabilities distinguished? They are distinguished based on the identity information. This identity information can be any identifier that a host can recognize, such as characters or numbers.

[0080] In some embodiments, the command information field, receipt information field, and data information field can respectively represent commands used for interaction between the host and the first device, receipts of the execution status of these commands, and data-related information within the firmware update capability. The commands can refer to commands used in the firmware update embodiments of this invention, such as data write commands and update commands. The data-related information can include the first firmware, the length of the first firmware, and the offset of the address where the first firmware is located. It should be noted that, as described above, the configuration space can be implemented using a series of registers; therefore, the information in the command information field, receipt information field, and data information field of the first data structure can be cached in the corresponding registers. In some embodiments, the data information field can also be divided into an offset subfield, a data subfield, and a length subfield, used to store the data address offset of the first firmware, the first firmware, and the data length of the first firmware, respectively.

[0081] Secondly, obtain the existing capabilities and the first capability linked list formed by the existing capabilities, wherein the first capability linked list is the linked list of capabilities formed in the first PCI configuration space.

[0082] Then, based on the first data structure, the firmware update capability is added to the first capability linked list to form a second capability linked list. One approach is to set the pointer information of the last capability in the first capability linked list to point to the firmware update capability, thereby ensuring that the firmware update capability is configured in the first PCI configuration space. Alternatively, it can be added between any two capabilities in the first capability linked list as needed, i.e., the second capability linked list is reconstructed as needed.

[0083] For example, as mentioned above Figure 9 The PCIe device shown has three capabilities configured in a certain configuration space. Firmware update capability is then configured in this configuration space. The relationships between the various capabilities in this configuration space after configuration are as follows: Figure 10 As shown in the diagram. The Header, Capability_1, Capability_2, Capability_3, and Firmware Update Capability (FWupdate Capability) are sequentially linked to form a linked list, which is also known as the second capability linked list.

[0084] After the aforementioned configuration is completed, the first device has firmware update capabilities. In this case, in some embodiments, S802 may include:

[0085] Receive one or more write commands containing data related to the first firmware;

[0086] Write the data related to the first firmware into the corresponding position of the first data structure;

[0087] Upon receiving an update command, the first firmware is updated to the corresponding storage area of ​​the first device based on the update command.

[0088] It should be noted that the data related to the first firmware may include the length of the first firmware, the first firmware itself, and the offset of the address where the first firmware is placed. The location where the data is written to the corresponding position in the first data structure refers to the data information field in the aforementioned first data structure. In some embodiments, the data information field can be implemented by a set of registers. In this case, the data related to the first firmware is written into the corresponding registers to await the arrival of an update command, updating the first firmware to the specified location (storage area) of the first device. That is, subsequently, upon receiving an update command, the first firmware is updated to the corresponding storage area of ​​the first device based on the update command.

[0089] It's important to understand that PCIe devices have a three-layer architecture: transaction layer, data link layer, and physical layer. Data transmission between the host and a PCIe device, and between PCIe devices themselves, uses a packet format. The transaction layer packages the request based on the type, destination address, and other relevant attributes of the request from the upper layer (software layer or application layer), generating a Transaction Layer Packet (TLP). These TLPs then pass through the data link layer and physical layer before finally reaching the target device. PCIe devices have different spaces: memory space (or address space), I / O space, and configuration space. The address space is used for large-volume data read / write operations. Different TLP types are used for accessing different spaces. Configuration TLP is used for accessing the configuration space; memory TLP is used for accessing the memory space; and I / O TLP is used for accessing the I / O space. The firmware update method provided in this embodiment of the invention writes the first firmware into the firmware update capability defined in the configuration space. Therefore, this embodiment of the invention uses Configuration TLP to place the data, update commands, and receipts related to the first firmware into the corresponding positions of the first data structure of the firmware update capability.

[0090] It should be noted that currently, the maximum capacity of a single TLP is 4KB. If the data length exceeds 4KB, it needs to be transmitted in multiple TLPs. In other words, when the data length related to the first firmware exceeds 4KB, it needs to be transmitted in multiple TLPs. That is, one or more write commands are required to write the data related to the first firmware to the storage area (register) corresponding to the firmware update capability.

[0091] It should be noted that the host will only send an update command after all data transmissions related to the first firmware are completed. When the first device receives the update command, it updates the first firmware to the corresponding storage area of ​​the first device based on the update command. Specifically, after receiving the update command, it reads the first firmware stored in the aforementioned data information field and updates the first firmware to the specified storage area, such as the RAM of the memory array or memory controller.

[0092] It should be understood that the aforementioned write or update commands are all sent by the host coupled to the first device through the operating system. Specifically, the host interacts with the firmware update capability of the first device through the setPCI command in the operating system. During data transmission, the data is transmitted to the first device in the form of Configuration TLP data packets. In other words, the user writes the aforementioned write or update commands through the setPCI command, and the write or update commands reach the first device in the form of Configuration TLP data packets during transmission.

[0093] In some embodiments, the method further includes:

[0094] Receive a read command, and based on the read command, provide a flag indicating that the first firmware update was successful, to indicate that the first firmware update is complete.

[0095] It should be noted that, after the update is completed, a flag indicating that the first firmware update is complete is sent to the host. Since access to the configuration space is usually initiated by the host, the flag indicating that the first firmware update is complete can be stored in the receipt information field of the first data structure and read by the host.

[0096] In other embodiments, the method further includes:

[0097] Receive an activation command carrying an activation method; activate the first firmware based on the activation method in the activation command.

[0098] It should be noted that the transmission method of the activation command here is similar to that described above, and will not be described in detail here. The activation method can be defined by the user; for example, the activation method can be immediate activation, or activation after the next power-on of the PCIe device, etc.

[0099] To understand the firmware update method provided in this embodiment of the invention, the firmware update process of the first device after configuring firmware update capability can be referred to... Figure 11 As shown.

[0100] exist Figure 11 The firmware update process is as follows:

[0101] 1. The host sends an updated firmware to the PCIe device:

[0102] a. Write the data content of the first firmware to be updated into the data subfield of the data information field of the first data structure for firmware update capability;

[0103] b. Write the data address offset of the first firmware update in this iteration to the offset subfield of the data information field;

[0104] c. Write the data length of the first firmware update to the length subfield of the data information field;

[0105] 2. Same as 1, until all data related to the first firmware has been updated;

[0106] d. Write the update command to the command information field;

[0107] e. Read the receipt field until the update command is found to have been executed successfully;

[0108] 3. Send activation command to PCIe device:

[0109] f. Write the activation method to the data information field;

[0110] g. Write the activation command to the command field;

[0111] h. Read the receipt field until the activation command is successfully executed.

[0112] It should be noted that the process described in step 1 is a specific implementation of the aforementioned step of receiving one or more write commands containing data related to the first firmware and writing the data related to the first firmware to the corresponding location in the first data structure (steps a, b, c). The process described in step 2 is a specific implementation of the aforementioned step of receiving an update command and updating the first firmware to the corresponding storage area of ​​the first device based on the update command (step d), and receiving a read command and feeding back an identifier indicating that the first firmware update was successful to indicate that the first firmware update was complete (step e). The process described in step 3 is a specific implementation of the aforementioned step of receiving an activation command carrying an activation method and activating the first firmware based on the activation method in the activation command (steps g, h). It should be understood that, under normal circumstances, step 1 is executed before steps 2 to complete the firmware transfer first and then implement the firmware update. The execution of step 3 does not immediately follow steps 1 and 2; it can be executed when activation is required.

[0113] The aforementioned operation of configuring firmware update capability in the first PCI configuration space can be performed only when the PCIe device performs its first firmware update. Subsequent firmware updates can directly implement this firmware update capability. Therefore, in some embodiments, before configuring firmware update capability in the first PCI configuration space of the at least one PCI configuration space, the method further includes:

[0114] The operating system in the host machine, which is coupled to itself, is used to detect whether the firmware update capability is configured in the first PCI configuration space.

[0115] In some embodiments, detecting whether the firmware update capability is configured in the first PCI configuration space using the operating system in the self-coupled host may include:

[0116] Receive a view command; execute the view command based on the operating system to obtain configuration information of the at least one PCI configuration space included in the first device; determine whether the firmware update capability is configured in the first PCI configuration space based on the configuration information.

[0117] It should be noted that the viewing command mentioned can refer to the lsPCI command in the PCIe protocol standard. The lsPCI command displays information about all PCIe devices in the data system, using the lsPCI-x / -xxx / -xxxx command format to display the configuration space of the PCI devices in hexadecimal format. -xxx indicates devices where reading the configuration space will crash; -xxxx indicates the configuration space of PCI-x2.0 or PCI-e bus extensions. In this embodiment of the invention, the lsPCI-x / -xxx / -xxxx command is executed in the operating system coupled to the first device to display the configuration space of the first device, thereby determining the configuration information of the at least one PCI configuration space, and then determining whether the firmware update capability is configured in the first PCI configuration space based on the configuration information. The operating system can be Linux or an similar operating system.

[0118] In some embodiments, the method includes:

[0119] If it is determined that the firmware update capability is not configured in the first PCI configuration space, it is configured in the manner described above; and after configuration, the first firmware is updated to the first device based on the firmware update capability.

[0120] In some embodiments, the method further includes:

[0121] If it is determined that the firmware update capability is already configured in the first PCI configuration space, the first firmware is directly updated to the first device based on the firmware update capability.

[0122] To better understand the above description, please refer to... Figure 12 The diagram shows the firmware update process. Figure 12 The firmware update process included in the document is as follows:

[0123] First step, the data system starts up to 100%.

[0124] This can be the power-on startup option.

[0125] The second step is for the system's operating system to detect whether the first device has firmware update capability.

[0126] This could be the operating system running, where the host sends the `lsPCI-x / -xxx / -xxxx` command to the first device to display the first device's configuration space, and checks whether the first device has firmware update capabilities from the displayed configuration space; if it does, the host will display the firmware update capability; otherwise, it will not display the firmware update capability.

[0127] The third step is for users to discover the ability to update firmware;

[0128] This refers to the ability to view the firmware update capability when the first device has the firmware update capability.

[0129] The fourth step is to update the firmware when needed by the user, even without a driver.

[0130] It should be noted that the specific update steps have been described in detail above and will not be repeated here.

[0131] Fifth step: Reboot the first device as needed to activate the new firmware.

[0132] It should be noted that this describes an optional activation method. The specific activation method has been described in detail above and will not be repeated here.

[0133] In some embodiments, the first device includes at least one of the following interfaces: PCI interface, PCI-X interface, and PCIe interface.

[0134] It should be noted that devices with PCI, PCI-X, or PCIe interfaces have configuration space. Therefore, the first device includes at least one of the following interfaces: PCI, PCI-X, or PCIe.

[0135] In some embodiments, if the first device has multiple functions, and if each function needs to be updated with firmware, firmware update capability needs to be configured in the configuration space corresponding to each function so that each function can be upgraded with firmware in the future.

[0136] The firmware update method provided in this embodiment of the invention defines a new firmware update capability in the configuration space of the first device, and uses this firmware update capability to update the first firmware. It can conveniently and quickly upgrade the firmware without the need for driver tools. Moreover, the firmware update method provided by this invention can be used for different types of devices with configuration spaces, and has a certain degree of universality.

[0137] The same inventive concept as described above, such as Figure 13 The present invention also provides a first device 130, the first device comprising a processor 1301 and at least one PCI configuration space 1302, wherein;

[0138] The processor is configured to: configure firmware update capability in a first PCI configuration space within the at least one PCI configuration space; and update first firmware to the first device based on the firmware update capability.

[0139] It should be noted that the processor here refers to the processor in the first device. This processor may be the same type as the host processor or a different processor; they are processors used in different architectures.

[0140] In some embodiments, configuring firmware update capability in the first PCI configuration space within the at least one PCI configuration space includes:

[0141] Define a first data structure corresponding to the firmware update capability in the first PCI configuration space;

[0142] Based on the first data structure, the firmware update capability is added to the first capability linked list to form the second capability linked list, so that the firmware update capability is configured in the first PCI configuration space.

[0143] The first capability linked list is a linked list of capabilities that have already been formed in the first PCI configuration space.

[0144] In some embodiments, updating the first firmware to the first device based on the firmware update capability includes:

[0145] Receive one or more write commands containing data related to the first firmware;

[0146] Write the data related to the first firmware into the corresponding position of the first data structure;

[0147] Upon receiving an update command, the first firmware is updated to the corresponding storage area of ​​the first device based on the update command.

[0148] In some embodiments, the processor is further configured to: receive a read command, and based on the read command, feed back an identifier indicating that the first firmware update was successful, to indicate that the first firmware update is complete.

[0149] In some embodiments, the processor is further configured to: receive an activation command carrying an activation method; and activate the first firmware based on the activation method in the activation command.

[0150] In some embodiments, the first device is coupled to a host; before configuring firmware update capability in the first PCI configuration space of the at least one PCI configuration space, the processor is further configured to: detect whether the firmware update capability is configured in the first PCI configuration space using the operating system in the host coupled to itself.

[0151] In some embodiments, detecting whether the firmware update capability is configured in the first PCI configuration space using the self-coupled operating system in the host includes:

[0152] Receive a view command; execute the view command based on the operating system to obtain configuration information of the at least one PCI configuration space included in the first device; determine whether the firmware update capability is configured in the first PCI configuration space based on the configuration information.

[0153] In some embodiments, the processor is configured to: upon determining that the firmware update capability has been configured in the first PCI configuration space, directly update the first firmware to the first device based on the firmware update capability.

[0154] In some embodiments, the first device communicates with the coupled host through at least one of the following interfaces: PCI interface, PCI-X interface, and PCIe interface.

[0155] In some embodiments, the first device is a storage terminal; or, the first device is a switch bridge.

[0156] In some embodiments, the storage terminal includes a memory system; wherein the memory system includes one or more memory devices; and a memory controller coupled to the one or more memory devices for controlling the one or more memory devices.

[0157] It should be noted that the memory controller is a form of processor; that is, in the storage terminal, the processor is the memory controller.

[0158] In some embodiments, the storage device includes: a memory array comprising a plurality of memory blocks; and a control circuit coupled to the memory array for controlling the memory array.

[0159] In some embodiments, the memory array is a three-dimensional NAND memory array.

[0160] It should be noted that the first device and the aforementioned firmware update method belong to the same inventive concept. The first device uses the aforementioned method when processing firmware updates. Therefore, the terms mentioned here have been explained in detail above and are equally applicable here, and will not be repeated here.

[0161] Based on the same inventive concept as described above, embodiments of the present invention also provide a data system, the data system comprising a host and a first device; wherein, the first device includes at least one PCI configuration space for configuring functions for the first device, and communicates with the host through at least one of the following interfaces: a PCI interface, a PCI-X interface, and a PCIe interface;

[0162] The host sends a configuration request to the first device;

[0163] The first device receives the configuration request through a first interface and configures firmware update capability in the first PCI configuration space in at least one PCI configuration space based on the configuration request; the first interface is one of PCI interface, PCI-X interface, and PCIe interface;

[0164] The host sends one or more write commands containing data related to the first firmware to the first device;

[0165] The first device receives one or more write commands through the first interface and writes the data related to the first firmware to the corresponding position of the first data structure corresponding to the firmware update capability; upon receiving an update command, it updates the first firmware to the first device based on the update command.

[0166] It should be noted that the configuration request here is the aforementioned TLP format data packet.

[0167] In some embodiments, the host sends an activation command carrying an activation method to the first device;

[0168] The first device receives an activation command carrying an activation method through the first interface; and activates the first firmware based on the activation method in the activation command.

[0169] In some embodiments, the first device is a storage terminal; or, the first device is a conversion bridge.

[0170] In some embodiments, the storage terminal includes a memory system; wherein the memory system includes one or more memory devices; and a memory controller coupled to the one or more memory devices for controlling the one or more memory devices.

[0171] In some embodiments, the storage device includes: a memory array comprising a plurality of memory blocks; and a control circuit coupled to the memory array for controlling the memory array.

[0172] In some embodiments, the memory array is a three-dimensional NAND memory array.

[0173] It should be noted that the data system includes the aforementioned first device, and therefore, the two have the same technical features. The terms appearing in the data system have all been explained in detail in the aforementioned description of the first device, and the same applies here, so they will not be repeated here.

[0174] The above description is intended to be illustrative and not restrictive. For example, the above examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used, such as those that may be used by one of ordinary skill in the art upon reading the above description. It should be understood that it is not intended to interpret or limit the scope or meaning of the claims. Furthermore, in the above detailed description, various features may be combined together to simplify the invention. This should not be construed as meaning that any unclaimed disclosed feature is essential to any claim. Rather, the subject matter of the disclosure may lie in fewer than all features of a particular disclosed embodiment. Therefore, the appended claims are thus incorporated into the detailed description, wherein each claim is an independent, separate embodiment, and these embodiments are contemplated to be combined with each other in various combinations or substitutions. The scope of the invention should be determined by reference to the appended claims and the full scope of their equivalents.

Claims

1. A firmware update method, characterized in that, The method, applied to a first device having at least one external device interconnect PCI configuration space, includes: Configure firmware update capability in the first PCI configuration space within at least one PCI configuration space; The first firmware is updated to the first device based on the firmware update capability; The provision of firmware update capability in the first PCI configuration space within at least one PCI configuration space includes: Define a first data structure corresponding to the firmware update capability in the first PCI configuration space; Based on the first data structure, the firmware update capability is added to the first capability linked list to form the second capability linked list, so that the firmware update capability is configured in the first PCI configuration space; wherein, the first capability linked list is a linked list that already has capabilities in the first PCI configuration space.

2. The method according to claim 1, characterized in that, Updating the first firmware to the first device based on the firmware update capability includes: Receive one or more write commands containing data related to the first firmware; Write the data related to the first firmware into the corresponding position of the first data structure; Upon receiving an update command, the first firmware is updated to the corresponding storage area of ​​the first device based on the update command.

3. The method according to claim 2, characterized in that, The method further includes: Receive a read command, and based on the read command, provide a flag indicating that the first firmware update was successful, to indicate that the first firmware update is complete.

4. The method according to claim 1, characterized in that, The method further includes: Receive an activation command carrying an activation method; activate the first firmware based on the activation method in the activation command.

5. The method according to claim 1, characterized in that, Before configuring firmware update capability in the first PCI configuration space within at least one PCI configuration space, the method further includes: The operating system in the host machine, which is coupled to itself, is used to detect whether the firmware update capability is configured in the first PCI configuration space.

6. The method according to claim 5, characterized in that, The step of detecting whether the firmware update capability is configured in the first PCI configuration space using the operating system in the self-coupled host includes: Receive a view command; execute the view command based on the operating system to obtain configuration information of the at least one PCI configuration space included in the first device; determine whether the firmware update capability is configured in the first PCI configuration space based on the configuration information.

7. The method according to claim 6, characterized in that, The method further includes: If it is determined that the firmware update capability is already configured in the first PCI configuration space, the first firmware is directly updated to the first device based on the firmware update capability.

8. The method according to any one of claims 1 to 7, characterized in that, The first device includes at least one of the following interfaces: PCI interface, PCI-X interface, and PCIe interface.

9. A first device, characterized in that, The first device includes a processor and at least one external device interconnect PCI configuration space, wherein; The processor is configured to: configure firmware update capability in a first PCI configuration space within at least one PCI configuration space; update first firmware to the first device based on the firmware update capability; wherein configuring firmware update capability in the first PCI configuration space within at least one PCI configuration space includes: defining a first data structure corresponding to the firmware update capability in the first PCI configuration space; adding the firmware update capability to a first capability linked list based on the first data structure to form a second capability linked list, such that the firmware update capability is configured in the first PCI configuration space; wherein the first capability linked list is a linked list of capabilities already formed in the first PCI configuration space.

10. The first device according to claim 9, characterized in that, The processor is further configured to: receive an activation command carrying an activation method; and activate the first firmware based on the activation method in the activation command.

11. The first device according to claim 9, characterized in that, The first device is coupled to a host; before configuring firmware update capability in the first PCI configuration space of the at least one PCI configuration space, the processor is further configured to: use the operating system in the host coupled to itself to detect whether the firmware update capability is configured in the first PCI configuration space.

12. The first device according to claim 11, characterized in that, The step of detecting whether the firmware update capability is configured in the first PCI configuration space using the self-coupled operating system in the host includes: Receive a view command; execute the view command based on the operating system to obtain configuration information of the at least one PCI configuration space included in the first device; determine whether the firmware update capability is configured in the first PCI configuration space based on the configuration information.

13. The first device according to claim 12, characterized in that, The processor is configured to: upon determining that the firmware update capability has been configured in the first PCI configuration space, directly update the first firmware to the first device based on the firmware update capability.

14. The first device according to any one of claims 9 to 13, characterized in that, The first device further includes at least one of the following interfaces: a PCI interface, a PCI-X interface, and a PCIe interface, for enabling the first device to communicate with a coupled host.

15. The first device according to claim 14, characterized in that, The first device is a storage terminal; or, the first device is a conversion bridge.

16. The first device according to claim 15, characterized in that, The storage terminal includes a memory system; wherein the memory system includes one or more memory devices; and a memory controller coupled to the one or more memory devices for controlling the one or more memory devices.

17. The first device according to claim 16, characterized in that, The storage device includes: a memory array comprising a plurality of memory blocks; and a control circuit coupled to the memory array for controlling the memory array.

18. The first device according to claim 17, characterized in that, The memory array is a three-dimensional NAND memory array.

19. A data system, characterized in that, The data system includes a host and a first device; wherein the first device includes at least one external device interconnect PCI configuration space and communicates with the host through at least one of the following interfaces: PCI interface, PCI-X interface, and PCIe interface; The host sends a configuration request to the first device; The first device receives the configuration request through a first interface and configures firmware update capability in a first PCI configuration space in at least one PCI configuration space based on the configuration request; the first interface is one of a PCI interface, a PCI-X interface, and a PCIe interface; The host sends one or more write commands containing data related to the first firmware to the first device; The first device receives one or more write commands through the first interface and writes the data related to the first firmware into the corresponding position of the first data structure corresponding to the firmware update capability; upon receiving an update command, it updates the first firmware to the first device based on the update command. The configuration of firmware update capability in a first PCI configuration space within at least one PCI configuration space based on the configuration request includes: defining a first data structure corresponding to the firmware update capability in the first PCI configuration space; adding the firmware update capability to a first capability linked list based on the first data structure to form a second capability linked list, thereby configuring the firmware update capability in the first PCI configuration space; wherein the first capability linked list is a linked list of capabilities already formed in the first PCI configuration space.

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