Simulation method of integrated circuit and simulation system thereof

Abstract

The embodiment of the present disclosure relates to the technical field of semiconductor, and provides a simulation method and simulation system of an integrated circuit, which are applied to a server and include the following steps: receiving a unit list provided by a client; receiving an initial netlist provided by the client, the initial netlist including a plurality of semiconductor devices and connection relationships between the semiconductor devices in the unit list; importing parasitic parameter information of at least part of the semiconductor devices in the unit list into the initial netlist to generate a result netlist; and simulating the integrated circuit based on the result netlist. The embodiment of the present disclosure is at least beneficial to improving the simulation accuracy of simulating the integrated circuit.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, a simulation method and system for an integrated circuit. Background Technology

[0002] With continuous advancements in manufacturing processes, the performance impact of parasitic effects, such as parasitic capacitance, on integrated circuits has become increasingly significant, especially for deep submicron integrated circuit designs. Specifically, integrated circuits contain multiple electronic components, each potentially generating parasitic capacitance, which can affect the actual circuit. Post-simulation testing can be used to verify whether circuits containing parasitic capacitance meet design requirements. Currently, after extracting parasitic capacitance parameters, these parameters are listed one by one in the code segment to form a flat parasitic parameter netlist for integrated circuit simulation.

[0003] However, the time spent extracting parasitic capacitance parameters and the excessively large file size of the resulting parasitic parameter netlist both affect the simulation speed and accuracy of integrated circuit simulation. Summary of the Invention

[0004] This disclosure provides a simulation method and system for integrated circuits, which at least helps to improve the simulation accuracy of integrated circuits.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a method for simulating an integrated circuit. The method is applied to a server and includes: receiving a cell list provided by a client; receiving an initial netlist provided by the client, the initial netlist including a plurality of semiconductor devices and connection relationships between the semiconductor devices in the cell list; importing parasitic parameter information of at least some of the semiconductor devices in the cell list into the initial netlist to generate a result netlist; and simulating the integrated circuit based on the result netlist.

[0006] In some embodiments, the cell list includes a first cell list and a second cell list, and the simulation method further includes: dividing the semiconductor device in the initial netlist into multiple modules based on the cell list; generating the result netlist further includes: providing a first file containing parasitic parameter information of at least some of the modules in the first cell list; extracting parasitic parameter information of at least some of the modules in the second cell list; and importing the parasitic parameter information of the first file and at least some of the modules in the second cell list into the initial netlist to generate the result netlist.

[0007] In some embodiments, in the second unit list, the module includes an input terminal and an output terminal; the extraction of parasitic parameter information of at least a portion of the modules in the second unit list includes at least one of the following: extracting parasitic parameter information between the input terminal and the semiconductor device, extracting parasitic parameter information between the semiconductor device and the output terminal, or extracting parasitic parameter information between the semiconductor devices.

[0008] In some embodiments, in the second unit list, the module includes at least two semiconductor devices electrically connected to the same input terminal and / or the same output terminal; the generated result netlist includes: a superposition of parasitic parameter information of at least two semiconductor devices electrically connected to the same input terminal and / or the same output terminal using a code.

[0009] In some embodiments, the semiconductor device includes transistors, and the gates of a plurality of transistors are electrically connected to the same input terminal. The step of importing the parasitic parameter information of the module in the second unit list into the initial netlist includes: defining the parasitic parameter information between the input terminal and the semiconductor device, including the parasitic capacitance between the gates of the plurality of transistors and the input terminal, and the gate of a single transistor having a standard parasitic capacitance between the input terminal and the input terminal, wherein the relationship between the parasitic capacitance and the standard parasitic capacitance is: Cg = C1 * N, where Cg represents the parasitic capacitance, C1 represents the standard parasitic capacitance, and N represents the number of the same transistor gates connected to the input terminal.

[0010] In some embodiments, the transistor is divided into a first transistor and a second transistor, wherein the thickness of the gate oxide layer in the second transistor is greater than the thickness of the gate oxide layer in the first transistor; the step of importing the parasitic parameter information of the module in the second cell list into the initial netlist includes: using different labels to characterize the standard parasitic capacitance between the first transistor and the input terminal and the standard parasitic capacitance between the second transistor and the input terminal.

[0011] In some embodiments, the cell list includes at least two electrically connected semiconductor devices; the generated netlist further includes: importing parasitic parameter information between the two electrically connected semiconductor devices into the initial netlist, and the parasitic parameter information between the two semiconductor devices corresponds to the output terminal of the preceding semiconductor device or the input terminal of the following semiconductor device.

[0012] In some embodiments, a portion of the modules in the first unit list includes a first basic unit, and the first file does not include at least some parasitic parameter information of the first basic unit; the step of generating the resulting netlist further includes: extracting at least some parasitic parameter information of the first basic unit; and importing at least some parasitic parameter information of the first basic unit into the initial netlist to form the resulting netlist.

[0013] In some embodiments, the generated netlist further includes: receiving a second file provided by the client, the second file including parasitic parameter information of some of the modules in the cell list; importing the second file into the initial netlist; wherein the first cell list includes a third basic cell, the second file includes parasitic parameter information of the third basic cell, and before importing the second file into the initial netlist, the parasitic parameter information corresponding to the third basic cell in the second file is removed.

[0014] In some embodiments, the generation of the netlist further includes: receiving a second file provided by the client, the second file including parasitic parameter information of a portion of the modules in the unit list; importing the second file into the initial netlist; wherein the second unit list includes a fourth basic unit, the second file includes parasitic parameter information of the fourth basic unit, and extracting parasitic parameter information of at least a portion of the modules in the second unit list does not include extracting parasitic parameter information corresponding to the fourth basic unit.

[0015] In some embodiments, generating the resulting netlist further includes copying the initial netlist to obtain a reference netlist and renaming the reference netlist.

[0016] In some embodiments, the initial netlist includes multiple subnetlists, and the semiconductor devices constitute multiple subnetlists respectively; the step of generating the result netlist includes: renaming the subnetlists for which no additional parasitic parameter information has been added.

[0017] According to some embodiments of this disclosure, another aspect of this disclosure also provides a simulation method for an integrated circuit, the method being applied to a client, comprising: providing a cell list and sending the cell list to a server; providing an initial netlist and sending the initial netlist to the server, the initial netlist including a plurality of semiconductor devices and connection relationships between the semiconductor devices in the cell list.

[0018] In some embodiments, the simulation method further includes: providing a second file, the second file being parasitic parameters of a portion of the semiconductor devices in the cell list; and sending the second file to the server.

[0019] In some embodiments, the unit list includes a first unit list and a second unit list, both of which include modules composed of a plurality of the semiconductor devices, and the server includes a first file containing parasitic parameter information of at least some of the modules in the first unit list; providing the second file includes: estimating the parasitic parameters of at least some of the modules in the second list.

[0020] According to some embodiments of this disclosure, another aspect of this disclosure also provides an integrated circuit simulation system, including: a server configured to implement the simulation method as described in any of the preceding claims; and a client configured to implement the simulation method as described in any of the preceding claims.

[0021] The technical solutions provided in this disclosure have at least the following advantages:

[0022] Importing parasitic parameter information of at least some semiconductor devices from the cell list into the initial netlist is beneficial for realistically simulating the parasitic effects between semiconductor devices when an integrated circuit is working, thereby improving the simulation accuracy of integrated circuit simulation. Attached Figure Description

[0023] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings represent similar elements. Unless otherwise stated, the figures in the drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 A flowchart illustrating a simulation method for an integrated circuit applied to a server, as provided in an embodiment of this disclosure;

[0025] Figure 2 A partial circuit diagram of a module in an integrated circuit provided in an embodiment of this disclosure;

[0026] Figure 3 Another partial circuit diagram of a module in an integrated circuit provided in an embodiment of this disclosure;

[0027] Figure 4 This is another partial circuit diagram of a module in an integrated circuit provided in an embodiment of the present disclosure;

[0028] Figure 5 This is a schematic diagram of a module in an integrated circuit provided in an embodiment of the present disclosure;

[0029] Figure 6 Another schematic diagram of a module in an integrated circuit provided in an embodiment of this disclosure;

[0030] Figure 7 A flowchart illustrating a simulation method for an integrated circuit applied to a client, as provided in another embodiment of this disclosure;

[0031] Figure 8 A schematic diagram of the functional modules of an integrated circuit simulation system provided in yet another embodiment of this disclosure. Detailed Implementation

[0032] As can be seen from the background technology, the simulation accuracy of integrated circuit simulation needs to be improved.

[0033] This disclosure provides a simulation method and system for integrated circuits. In the simulation method, parasitic parameter information of at least some semiconductor devices in the cell list is imported based on the initial netlist. This is beneficial for realistically simulating the parasitic effects between semiconductor devices when the integrated circuit is working, thereby improving the simulation accuracy of the integrated circuit simulation.

[0034] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0035] This disclosure provides an embodiment of an integrated circuit simulation method applied to a server. The following will describe in detail the integrated circuit simulation method provided by this disclosure in conjunction with the accompanying drawings. Figure 1 A flowchart illustrating a simulation method for an integrated circuit applied to a server, as provided in an embodiment of this disclosure; Figure 2 A partial circuit diagram of a module in an integrated circuit provided in an embodiment of this disclosure; Figure 3 Another partial circuit diagram of a module in an integrated circuit provided in an embodiment of this disclosure; Figure 4 This is another partial circuit diagram of a module in an integrated circuit provided in an embodiment of the present disclosure; Figure 5 This is a schematic diagram of a module in an integrated circuit provided in an embodiment of the present disclosure; Figure 6 This is a schematic diagram of another structure of a module in an integrated circuit provided in an embodiment of the present disclosure.

[0036] refer to Figure 1 The simulation method for integrated circuits is applied to servers, and the simulation method for integrated circuits includes the following steps:

[0037] S101: Receive the unit list provided by the client;

[0038] S102: Receive the initial netlist provided by the client. The initial netlist includes several semiconductor devices and the connection relationships between the semiconductor devices in the cell list.

[0039] S103: Import parasitic parameter information of at least some of the semiconductor devices in the cell list into the initial netlist to generate the result netlist.

[0040] S104: Simulate the integrated circuit based on the resulting netlist.

[0041] Understandably, based on the initial netlist and cell list provided by the client, the server can learn which semiconductor devices are included in the integrated circuit to be simulated, as well as the electrical connection relationships between the semiconductor devices in the integrated circuit. The server can then extract and record the parasitic parameter information between the semiconductor devices based on the type of semiconductor device and the electrical connection relationships between them.

[0042] In some embodiments, the cell list may include a first cell list and a second cell list. The simulation method may further include: dividing the semiconductor devices in the initial netlist into multiple modules based on the cell list; generating a result netlist; and may further include: providing a first file containing parasitic parameter information of at least some modules in the first cell list; extracting parasitic parameter information of at least some modules in the second cell list; and importing the parasitic parameter information of at least some modules in the first file and the second cell list into the initial netlist to generate a result netlist.

[0043] In some embodiments, the first file includes an SPF file. An SPF (Standard Parasitic Format) file is a standard medium file used in the integrated circuit design flow to transmit interconnect parasitic parameters. An SPF file can describe various interconnect parasitic models. In some embodiments, EDA (Electronic Design Automation) tools can be used to extract the SPF file from the integrated circuit to be simulated.

[0044] In some embodiments, the number of semiconductor devices contained in the modules in the first unit list is less than the number of semiconductor devices contained in the modules in the second unit list. For example, the first unit list may include semiconductor devices in the memory array region of an integrated circuit, and the second unit list may include semiconductor devices in the peripheral region of an integrated circuit.

[0045] It should be noted that the more semiconductor devices there are in a certain area of ​​an integrated circuit, the longer it takes for the server to extract parasitic parameter information between the semiconductor devices in that area, and the accuracy of the extracted parasitic parameter information is difficult to control. Therefore, the modules in the integrated circuit are classified and integrated into a first unit list or a second unit list. For example, modules that take less time to extract parasitic parameter information are integrated into the first unit list, that is, modules containing fewer semiconductor devices are integrated into the first unit list, while modules that take longer to extract parasitic parameter information are integrated into the second unit list, that is, modules containing more semiconductor devices are integrated into the second unit list. Then, a tool for extracting parasitic parameter information is used to extract parasitic parameter information from at least some modules in the first unit list to generate a first file. It should be noted that in practical applications, the parasitic parameter information of most modules in the first unit list can be extracted using this tool. The parasitic parameter information of at least some modules in the second unit list is easier to extract than that of other modules in the second unit list. Therefore, this tool can be used to extract the parasitic parameter information of the modules whose parasitic parameters are easy to extract. Then, the generated first file and the extracted parasitic parameter information of at least some modules in the second unit list are imported into the initial netlist to generate the result netlist.

[0046] This approach allows for the consideration of parasitic effects from both the first and second unit lists. Furthermore, the server utilizes tools to extract parasitic parameters from the first unit list, where the extraction process is quick, and also extracts parasitic parameters from some modules in the second unit list. Therefore, while extracting parasitic parameters from as many modules as possible through the server, it also considers that parasitic parameters from some modules are difficult to extract via the server. Subsequently, parasitic parameter information can be estimated for modules for which no parasitic parameter extraction has been performed. This approach helps improve the simulation speed of the integrated circuit under simulation while ensuring its accuracy, and also reduces the difficulty of software simulation.

[0047] In some embodiments, the second unit list includes modules with input terminals and output terminals. Extracting parasitic parameter information from at least some modules in the second unit list includes at least one of the following: extracting parasitic parameter information between the input terminal and the semiconductor device, extracting parasitic parameter information between the semiconductor device and the output terminal, or extracting parasitic parameter information between semiconductor devices. This improves the comprehensiveness of the parasitic parameter information extracted by the server, that is, it takes into account as many structures as possible that may produce parasitic effects on the modules in the second unit list, thereby further improving the simulation accuracy of the integrated circuit to be simulated.

[0048] In some embodiments, in the second unit list, the module includes at least two semiconductor devices electrically connected to the same input and / or output; the generated result netlist includes: a superposition of parasitic parameter information of at least two semiconductor devices electrically connected to the same input and / or output, represented by a single code.

[0049] In the integrated circuit to be simulated, there are often multiple semiconductor devices with the same port electrically connected to the same input or output terminal of other semiconductor devices. In this case, for any two electrically connected semiconductor devices, the difference in parasitic effects between them is not significant, that is, the difference in parasitic parameters between them is negligible. In other words, the parasitic parameters between them are almost identical. Therefore, compared to sequentially using codes to represent the parasitic parameter information of each semiconductor device in the resulting netlist (i.e., one code corresponds to one semiconductor device), this embodiment uses a single code to represent the superposition of parasitic parameter information of at least two semiconductor devices electrically connected to the same input and / or output terminal. This simplifies the resulting netlist, thereby reducing its size and improving the simulation speed of the integrated circuit to be simulated while maintaining the simulation accuracy.

[0050] It should be noted that the above embodiments only use at least two semiconductor devices electrically connected to the same input terminal and / or output terminal as examples. In practical applications, for other electrical connection relationships that make the parasitic effects between at least two semiconductor devices almost indistinguishable, the above-mentioned method of "using a code to characterize the superposition of parasitic parameter information of at least two semiconductor devices" can also be used to simplify the resulting netlist.

[0051] The following describes in detail, through two embodiments, the superposition of parasitic parameter information of at least two semiconductor devices electrically connected to the same input and / or output terminal using a single code.

[0052] In some embodiments, reference Figure 2 The semiconductor device includes transistors, and the gates 100 of multiple transistors are electrically connected to the same input terminal 101. Importing the parasitic parameter information of the modules in the second unit list into the initial netlist includes the following steps:

[0053] The parasitic parameter information between the input terminal 101 and the semiconductor device is defined as follows: the parasitic capacitance between the gate 100 of multiple transistors and the input terminal 101, and the standard parasitic capacitance between the gate 100 of a single transistor and the input terminal 101. The relationship between the parasitic capacitance and the standard parasitic capacitance is: Cg = C1 * N.

[0054] Where Cg represents parasitic capacitance, C1 represents standard parasitic capacitance, and N represents the number of identical transistor gates 100 connected to input terminal 101.

[0055] It should be noted that, for ease of illustration, Figure 2 In the above example, a square represents the port corresponding to the transistor gate 100, and a combination of squares and triangles represents the input terminal 101. However, in practical applications, the specific representation of the transistor gate 100 and the input terminal 101 is not limited. It is understood that the above embodiment only uses the superposition of parasitic capacitance information as an example. In practical applications, parasitic parameter information includes parameters such as parasitic capacitance, parasitic resistance, and parasitic capacitance. Parasitic resistance information and parasitic capacitance information can also be superimposed using the above method to simplify the resulting netlist.

[0056] In some examples, the encoding can be: Cg1 A 0c = 'Cthin*(1+1)' represents the superposition of parasitic parameter information of two semiconductor devices electrically connected to the same input terminal 101. Here, Cg1 represents the number of the parasitic capacitance between input terminal 101 and ground in the integrated circuit; A represents that one end of the parasitic capacitance is located at circuit node A; 0 represents that the other end of the parasitic capacitance is grounded; c represents the capacitance value of the parasitic capacitance between input terminal 101 and ground; Cthin represents the standard parasitic capacitance between a single semiconductor device and input terminal 101; and (1+1) represents the number of gates of the semiconductor devices electrically connected to the same input terminal 101. It should be noted that the above example only uses the superposition of parasitic parameter information of two semiconductor devices electrically connected to the same input terminal 101. In practical applications, the number of semiconductor devices electrically connected to the same input terminal 101 can also be 3, 4, or 5, etc.

[0057] In some embodiments, the transistor is divided into a first transistor and a second transistor, wherein the thickness of the gate oxide layer in the second transistor is greater than the thickness of the gate oxide layer in the first transistor. The step of importing the parasitic parameter information of the modules in the second cell list into the initial netlist includes: using different labels to characterize the standard parasitic capacitance between the first transistor and the input terminal and the standard parasitic capacitance between the second transistor and the input terminal. This allows subsequent operators to obtain more information about the integrated circuit to be simulated based on the resulting netlist, facilitating the correction of the integrated circuit.

[0058] For example, Cthin can be used to characterize the standard parasitic capacitance between the first transistor and the input terminal 101, and Cthick can be used to characterize the standard parasitic capacitance between the second transistor and the input terminal 101. In practical applications, other easily distinguishable labels can also be used to represent the standard parasitic capacitance between the first transistor and the second transistor and the input terminal 101.

[0059] In other embodiments, reference is made to Figure 3The semiconductor device includes transistors. The first terminals 102 of multiple transistors are electrically connected to the same output terminal 103. Importing the parasitic parameter information of the modules in the second unit list into the initial netlist includes the following steps: defining the parasitic parameter information between the output terminal 103 and the semiconductor device, including the parasitic capacitance between the first terminals 102 and the output terminal 103 of multiple transistors, and the reference parasitic capacitance between the first terminals 102 and the output terminal 103 of a single transistor. The relationship between the parasitic capacitance between the first terminals 102 and the output terminal 103 of multiple transistors and the reference parasitic capacitance is: cout = C2 * N.

[0060] Where cout represents the parasitic capacitance between the first terminal 102 of multiple transistors and the output terminal 103, C2 represents the reference parasitic capacitance, and N represents the number of first terminals 102 of transistors connected to the output terminal 103.

[0061] It should be noted that, for ease of illustration, Figure 3 In the example, a square represents the first terminal 102 of the transistor, and a combination of square and triangle represents the output terminal 103. In practical applications, the specific representation of the first terminal 102 and the output terminal 103 of the transistor is not limited. It is understood that the above embodiment only uses the superposition of parasitic capacitance information as an example. In practical applications, parasitic parameter information includes parameters such as parasitic capacitance, parasitic resistance, and parasitic resistance information. Parasitic resistance information and parasitic capacitance information can also be superimposed using the above method to simplify the resulting netlist.

[0062] In some examples, the encoding can be: cout1 Y 0c='CapO*(1+1)' represents the superposition of parasitic parameter information of two semiconductor devices electrically connected to the same output terminal 103. Here, cout1 represents the number of the parasitic capacitance between output terminal 103 and ground in the integrated circuit; Y represents that one end of the parasitic capacitance is located at the Y circuit node; 0 represents that the other end of the parasitic capacitance is grounded; c represents the capacitance value of the parasitic capacitance between output terminal 103 and ground; CapO represents the reference parasitic capacitance between a single semiconductor device and output terminal 103; and (1+1) represents the number of semiconductor devices electrically connected to the same output terminal 103. It should be noted that the above only represents the superposition of parasitic parameter information of two semiconductor devices electrically connected to the same output terminal 103. In practical applications, the number of semiconductor devices electrically connected to the same output terminal 103 can also be 3, 4, or 5, etc.

[0063] In some embodiments, reference Figure 4The second unit list includes at least two electrically connected semiconductor devices 104. Generating the resulting netlist may further include importing parasitic parameter information between the two electrically connected semiconductor devices 104 into the initial netlist, whereby the parasitic parameter information between the two semiconductor devices 104 corresponds to the output terminal of the preceding semiconductor device or the input terminal of the following semiconductor device. This avoids the situation where, when importing parasitic parameter information for the preceding semiconductor device, the parasitic parameter information between the two semiconductor devices 104 is also imported, and vice versa. This prevents the parasitic parameter information between the two electrically connected semiconductor devices 104 from being repeatedly imported into the initial netlist, thereby simplifying the netlist structure to improve simulation speed while simultaneously improving simulation accuracy.

[0064] In some examples, the following encoding can be used: c1 net5 0c = 'Cgatein' represents the parasitic parameter information between two electrically connected semiconductor devices 104. Here, c1 represents the number of the parasitic capacitance between the connection node and ground in the integrated circuit; net5 represents the number of the connection node, indicating that one end of the parasitic capacitance is located at the connection node, facilitating quick location lookup of each connection node in the integrated circuit; 0 represents the other ground of the parasitic capacitance; c represents the parasitic capacitance between the connection node and ground; and Cgatein represents the reference value of the parasitic capacitance between the connection node and ground. It is understood that the above embodiment only uses the encoding of parasitic capacitance information as an example. In practical applications, parasitic parameter information includes parameters such as parasitic capacitance and parasitic resistance. Parasitic resistance and parasitic capacitance information can also be encoded using the above method.

[0065] In some embodiments, reference Figure 5 The first unit list includes a first basic unit 111 in some modules 10, and the first file does not include at least some parasitic parameter information in the first basic unit 111; the step of generating the result netlist may further include: extracting at least some parasitic parameter information of the first basic unit 111; and importing at least some parasitic parameter information of the first basic unit 111 into the initial netlist to form the result netlist.

[0066] When using the tool to extract parasitic parameter information to generate the first file for some modules, some basic units in the module are skipped, meaning that the parasitic parameter information inside the skipped basic units is not extracted. Therefore, extracting this part of the parasitic parameter information and importing it into the initial netlist is beneficial to further improve the simulation accuracy.

[0067] In some embodiments, the first basic unit 111 further includes a second basic unit 112, and the first file includes parasitic parameter information of the second basic unit 112; at least a portion of the parasitic parameter information of the received first basic unit 111 does not include the parasitic parameter information of the second basic unit 112. Thus, when extracting the parasitic parameter information of the first basic unit 111, the parasitic parameter information of the second basic unit 112 is not extracted, avoiding the situation where "the extracted parasitic parameter information also includes the parasitic parameter information of the second basic unit 112 when the first file already contains the parasitic parameter information of the second basic unit 112," thereby preventing the parasitic parameter information of the second basic unit 112 from being repeatedly imported into the initial netlist. This facilitates both simplifying the structure netlist to improve simulation speed and improving simulation accuracy.

[0068] In some embodiments, reference Figure 6 In addition to the first basic unit 111 and the second basic unit 112 located within the first basic unit 111, the partial module 10 of the first unit list also includes: a fifth basic unit 115 located within the first basic unit 111 and containing the second basic unit 112; and a sixth basic unit 116 listed alongside the first basic unit 111. The first file includes parasitic parameter information for the second basic unit 112 and the sixth basic unit 116. At least a portion of the parasitic parameter information extracted from the first basic unit 111 does not include the parasitic parameter information for the second basic unit 112, but includes the parasitic parameter information for the fifth basic unit 115; that is, only the parasitic parameter information for the first basic unit 111 and the fifth basic unit 115 can be extracted.

[0069] In some embodiments, generating the resulting netlist may further include: receiving a second file provided by a client, the second file including parasitic parameter information of some modules in the cell list; importing the second file into the initial netlist; wherein the first cell list includes a third basic cell, the second file includes parasitic parameter information of the third basic cell, and before importing the second file into the initial netlist, the parasitic parameter information corresponding to the third basic cell in the second file is removed.

[0070] Since the first file contains parasitic parameter information for the third basic unit in the first unit list, and the second file provided by the client also includes parasitic parameter information for some modules in the unit list, there is a possibility of duplicate importing of the parasitic parameter information corresponding to the third basic unit when importing the first and second files into the initial netlist. Therefore, removing the parasitic parameter information corresponding to the third basic unit from the second file before importing it into the initial netlist helps avoid the situation where "the parasitic parameter information of the third basic unit provided by the client is also imported into the initial netlist when the first file already contains it." This avoids the repeated import of the parasitic parameter information of the third basic unit into the initial netlist, thereby improving simulation accuracy while simplifying the structure netlist to improve simulation speed.

[0071] In some embodiments, generating the resulting netlist may further include: receiving a second file provided by a client, the second file including parasitic parameter information of some modules in the cell list; importing the second file into the initial netlist; wherein the second cell list includes a fourth basic cell, the second file includes parasitic parameter information of the fourth basic cell, and extracting parasitic parameter information of at least some modules in the second cell list does not include extracting parasitic parameter information corresponding to the fourth basic cell.

[0072] It should be noted that the second file includes a BA (back annotated) file, which can be a file containing parasitic parameter information of the semiconductor device estimated by the operator at the client based on practical experience. In some embodiments, the BA file is generated by the operator pre-extracting parasitic parameter information of several key modules and then manually annotating it on the corresponding modules. This helps to ensure improved simulation accuracy while avoiding the need for re-extraction every time a simulation is performed, thus improving simulation efficiency.

[0073] If the operator has already evaluated the parasitic parameters of the fourth basic unit in the second unit list to generate a BA file for the server, then the parasitic parameter information of the modules in the second unit list can be imported into the initial netlist without considering the parasitic parameters of the fourth basic unit. This avoids the parasitic parameter information of the fourth basic unit being repeatedly imported into the initial netlist, which helps to improve simulation accuracy while simplifying the structure netlist to improve simulation speed.

[0074] In some embodiments, generating the resulting netlist may further include copying the initial netlist to obtain a reference netlist and renaming the reference netlist. For example, the reference netlist file formed after copying the initial netlist is a file with the suffix -org. In practical applications, other suffixes can also be used to rename the reference netlist. Thus, after importing the parasitic parameter information of the modules in the first file and the second unit list into the initial netlist to generate the resulting netlist, it is beneficial for operators to use the reference netlist to identify which positions in the resulting netlist have changed and to check whether the changes are correct.

[0075] In some embodiments, the initial netlist includes multiple subnetlists, with several semiconductor devices each constituting a subnetlist. The step of generating the result netlist includes renaming the subnetlists for which no additional parasitic parameter information has been added. For example, the subnetlist file without additional parasitic parameter information is a file with the suffix -org. In practical applications, other suffixes can also be used to rename the subnetlists for which no additional parasitic parameter information has been added. Since the subnetlists for which additional parasitic parameter information has been added have different suffixes than those for which no additional parasitic parameter information has been added, it is beneficial to further improve the efficiency for operators to know which subnetlists in the result netlist have changed, and to check whether the changes are correct.

[0076] In summary, importing parasitic parameter information of at least some semiconductor devices from the cell list into the initial netlist is beneficial for realistically simulating the parasitic effects between semiconductor devices during integrated circuit operation, thereby improving the simulation accuracy of integrated circuit simulation.

[0077] Another embodiment of this disclosure provides a method for simulating an integrated circuit, applied to a client. The method for simulating an integrated circuit provided in another embodiment of this disclosure will be described in detail below with reference to the accompanying drawings. Figure 7 A flowchart of a simulation method for an integrated circuit applied to a client, provided as another embodiment of this disclosure.

[0078] refer to Figure 7 The simulation method for integrated circuits is applied to the client side, and the simulation method for integrated circuits includes the following steps:

[0079] S201: Provide a list of units and send the list of units to the server.

[0080] S202: Provide an initial netlist and send the initial netlist to the server. The initial netlist includes several semiconductor devices and the connection relationships between the semiconductor devices in the cell list.

[0081] It should be noted that the server itself provides a first file. Since the first file only contains parasitic parameter information for modules and / or semiconductor devices whose parasitic parameter information is easily extracted, for modules and / or semiconductor devices whose parasitic parameters are not extracted, the operator can estimate the parasitic parameter information of these modules and / or semiconductor devices on the client side and send the estimation results to the server. This allows the server to generate a result netlist based on the first file and the file received from the client to simulate the integrated circuit. This helps to more comprehensively consider the parasitic effects in the integrated circuit to be simulated, thereby improving the simulation accuracy of the integrated circuit simulation.

[0082] In some embodiments, the simulation method may further include: providing a second file containing parasitic parameters of a portion of semiconductor devices in the cell list; and sending the second file to a server. This helps avoid the situation where "the client has already evaluated the parasitic parameters of that portion of semiconductor devices when providing the second file, and then the server evaluates the parasitic parameters of that portion of semiconductor devices again," thus preventing the parasitic parameter information of that module from being repeatedly imported into the initial netlist. This helps to improve simulation accuracy while simplifying the netlist structure to increase simulation speed.

[0083] In some embodiments, the unit list includes a first unit list and a second unit list, both of which include modules composed of multiple semiconductor devices, and the server includes a first file containing parasitic parameter information of at least some modules in the first unit list; providing a second file includes: estimating the parasitic parameters of at least some modules in the second unit list.

[0084] In some embodiments, the number of semiconductor devices contained in the modules in the first unit list is less than the number of semiconductor devices contained in the modules in the second unit list. For example, the first unit list may include semiconductor devices in the memory array area of ​​an integrated circuit, and the second unit list may include semiconductor devices in the peripheral area of ​​an integrated circuit. Thus, parasitic parameter information is extracted from at least a portion of the modules in the first unit list using a tool for extracting parasitic parameter information to generate a first file. The parasitic parameter information of at least a portion of the modules in the second unit list is estimated by the client and transmitted to the server. The client-side estimation of parasitic parameter information for at least a portion of the modules in the second unit list takes less time than the server-side extraction of parasitic parameter information for those modules. Therefore, while considering the parasitic effects of modules in both the first and second unit lists as much as possible, the server can be used to extract parasitic parameter information from modules with shorter extraction times, while the client can be used to estimate parasitic parameter information from modules with longer extraction times. This helps to improve the simulation speed of the integrated circuit under simulation while ensuring the simulation accuracy of the integrated circuit being simulated, and also helps to reduce the difficulty of software simulation. In some embodiments, the simulation method may further include: providing a labeling module and a circuit schematic of the integrated circuit to be simulated, to label the added parasitic parameter information in the circuit schematic. It is understood that after estimating the parasitic parameter information of at least some semiconductor devices in the predicted unit list, the parasitic parameter information can not only be sent to a server for simulation testing of the integrated circuit to be simulated, but also back-annotated to the circuit schematic. This facilitates subsequent operations by allowing operators to understand which modules and which basic units in the integrated circuit to be simulated have parasitic parameters estimated by the client, and to help operators analyze the accuracy of the estimated parasitic parameters.

[0085] In summary, when simulating an integrated circuit, relying on the client to estimate the parasitic parameter information of at least some semiconductor devices in the cell list and sending the parasitic parameter information to the server helps to more comprehensively consider the parasitic effects in the integrated circuit to be simulated, thereby improving the simulation accuracy of the integrated circuit simulation.

[0086] Another embodiment of this disclosure provides an integrated circuit simulation system for implementing the integrated circuit simulation method provided in the foregoing embodiments. The integrated circuit simulation system provided in another embodiment of this disclosure will be described in detail below with reference to the accompanying drawings. Figure 8 A schematic diagram of the functional modules of an integrated circuit simulation system provided in yet another embodiment of this disclosure.

[0087] refer to Figure 8The integrated circuit simulation system includes: a server 105, configured to implement an integrated circuit simulation method for a server as described in one embodiment of the present disclosure; and a client 106, configured to implement an integrated circuit simulation method for a client as described in another embodiment of the present disclosure.

[0088] Server 105 can generate an initial netlist based on the circuit schematic of the integrated circuit to be simulated, and client 106 can generate a cell list based on the initial netlist. Client 106 can also estimate the parasitic parameter information of at least some semiconductor devices in the cell list and send it to server 105. Thus, through the interaction between server 105 and client 106, it is beneficial to consider the parasitic effects in the integrated circuit to be simulated more comprehensively, thereby improving the simulation accuracy of the integrated circuit.

[0089] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A simulation method for integrated circuits, characterized in that, The method is applied to a server and includes: Receive the list of units provided by the client; Receive an initial netlist provided by the client, the initial netlist including a number of semiconductor devices and the connection relationships between the semiconductor devices in the cell list; Parasitic parameter information of at least a portion of the semiconductor devices in the cell list is imported into the initial netlist to generate a result netlist; The integrated circuit is simulated based on the resulting netlist; The cell list includes a first cell list and a second cell list, and the simulation method further includes: dividing the semiconductor device in the initial netlist into multiple modules based on the cell list; The generated result netlist also includes: A first file is provided, the first file containing parasitic parameter information of at least a portion of the modules in the first unit list; Receive a second file provided by the client, the second file including parasitic parameter information of some of the modules in the unit list; The first unit list includes a third basic unit, and the second file includes parasitic parameter information of the third basic unit. Before importing the second file into the initial netlist, the parasitic parameter information corresponding to the third basic unit in the second file is removed. The second file and the first file, after removing duplicates, are imported into the initial netlist to generate the result netlist.

2. The simulation method as described in claim 1, characterized in that, In the second unit list, the module includes an input terminal and an output terminal; The generated netlist also includes: Extract parasitic parameter information between the input terminal and the semiconductor device, extract parasitic parameter information between the semiconductor device and the output terminal, or extract parasitic parameter information between the semiconductor devices.

3. The simulation method as described in claim 2, characterized in that, In the second unit list, the module includes at least two semiconductor devices electrically connected to the same input terminal and / or the same output terminal; The generated netlist includes: a superposition of parasitic parameter information of at least two semiconductor devices electrically connected to the same input terminal and / or output terminal, represented by a single code.

4. The simulation method as described in claim 2 or 3, characterized in that, The semiconductor device includes transistors, and the gates of a plurality of transistors are electrically connected to the same input terminal. The step of importing the parasitic parameter information of the modules in the second unit list into the initial netlist includes: The parasitic parameter information between the input terminal and the semiconductor device is defined as follows: the parasitic capacitance between the gates of multiple transistors and the input terminal, and a standard parasitic capacitance between the gate of a single transistor and the input terminal. The relationship between the parasitic capacitance and the standard parasitic capacitance is: Cg = C1 * N, where Cg represents the parasitic capacitance, C1 represents the standard parasitic capacitance, and N represents the number of identical transistor gates connected to the input terminal.

5. The simulation method as described in claim 4, characterized in that, The transistor is divided into a first transistor and a second transistor, wherein the thickness of the gate oxide layer in the second transistor is greater than the thickness of the gate oxide layer in the first transistor; The step of importing the parasitic parameter information of the modules in the second unit list into the initial netlist includes: using different labels to characterize the standard parasitic capacitance between the first transistor and the input terminal and the standard parasitic capacitance between the second transistor and the input terminal.

6. The simulation method as described in claim 1, characterized in that, The second unit list includes at least two electrically connected semiconductor devices; The generated netlist further includes: importing parasitic parameter information between two electrically connected semiconductor devices into the initial netlist, wherein the parasitic parameter information between the two semiconductor devices corresponds to the output terminal of the preceding semiconductor device or the input terminal of the following semiconductor device.

7. The simulation method as described in claim 1, characterized in that, The first unit list includes a first basic unit in some of the modules, and the first file does not include at least some of the parasitic parameter information in the first basic unit; The steps for generating the resulting netlist also include: Extract at least some of the parasitic parameter information of the first basic unit; At least some of the parasitic parameter information of the first basic unit is imported into the initial netlist to form the result netlist.

8. The simulation method as described in claim 1, characterized in that, The generated netlist further includes: receiving a second file provided by the client, the second file including parasitic parameter information of some of the modules in the cell list; and importing the second file into the initial netlist; The second unit list includes a fourth basic unit, and the second file includes parasitic parameter information of the fourth basic unit. Extracting parasitic parameter information of at least a portion of the modules in the second unit list does not include extracting parasitic parameter information corresponding to the fourth basic unit.

9. The simulation method as described in claim 1, characterized in that, The generated netlist also includes copying the initial netlist to obtain a reference netlist and renaming the reference netlist.

10. The simulation method as described in claim 1 or 9, characterized in that, The initial netlist includes multiple subnetlists, and the semiconductor devices respectively constitute the multiple subnetlists; The steps for generating the resulting netlist include: Rename the subnet table for which no additional parasitic parameter information has been added.

11. A simulation method for integrated circuits, characterized in that, The method is applied to the client and includes: Provide a list of units and send the list of units to the server; An initial netlist is provided and sent to the server. The initial netlist includes a number of semiconductor devices and the connection relationships between the semiconductor devices in the cell list. A second document is provided, which contains parasitic parameters of a portion of the semiconductor devices in the unit list; Send the second file to the server; The unit list includes a first unit list and a second unit list. Both the first unit list and the second unit list include modules composed of multiple semiconductor devices. The server includes a first file, which includes parasitic parameter information of at least some of the modules in the first unit list. The second document is provided, including: estimating parasitic parameters of at least some of the modules in the second unit list.

12. A simulation system for an integrated circuit, characterized in that, include: A server configured to implement the simulation method as described in any one of claims 1 to 10; A client configured to implement the simulation method as described in claim 11.

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