Semiconductor device

Abstract

The present application provides a semiconductor device capable of improving heat dissipation characteristics. When viewed from a first surface, a first member having the first surface includes a plurality of circuit blocks arranged in an area inside the first surface. A second member is joined in surface contact with the first surface of the first member. The second member includes a plurality of first transistors connected in parallel with each other to constitute a first amplification circuit. A conductor protrusion protrudes from the second member to an opposite side of the first member side. The plurality of first transistors are arranged in an area that does not overlap any of the plurality of circuit blocks of the first member when viewed from above.

Description

Technical Field

[0001] This invention relates to semiconductor devices. Background Technology

[0002] RF front-end modules, which integrate high-frequency signal transmission and reception functions, are assembled in electronic devices used for mobile communications, satellite communications, and other applications. An RF front-end module includes: a monolithic microwave integrated circuit (MMIC) with high-frequency amplification capabilities, a control IC for controlling the high-frequency amplification circuit, a switching IC, a duplexer, etc.

[0003] Patent Document 1 discloses a miniaturized high-frequency module achieved by stacking a control IC on an MMIC. The high-frequency module disclosed in Patent Document 1 includes an MMIC mounted on a module substrate and a control IC stacked on the MMIC. The electrodes of the MMIC, the electrodes of the control IC, and the electrodes on the module substrate are electrically connected by wire bonding.

[0004] Patent Document 1: U.S. Patent Application Publication No. 2015 / 0303971.

[0005] High-frequency amplifier circuits, for example, use heterojunction bipolar transistors (HBTs). During operation, HBTs generate collector losses and thus heat. This heat causes a temperature rise in the HBT, which in turn increases the collector current. If this positive feedback condition is met, it can lead to thermal runaway of the HBT. To avoid thermal runaway, the upper limit of the HBT's output power is limited.

[0006] To achieve high output in high-frequency amplifier circuits, it is preferable to improve the heat dissipation characteristics of semiconductor devices, including HBTs. However, the high-frequency module disclosed in Patent Document 1 is insufficient to meet the recent demands for high output in high-frequency amplifier circuits. Summary of the Invention

[0007] The purpose of this invention is to provide a semiconductor device that can improve heat dissipation characteristics.

[0008] According to one aspect of the present invention, a semiconductor device is provided, comprising:

[0009] A first component has a first surface, and when viewed from above, the first component includes a plurality of circuit blocks disposed in a region inside the first surface;

[0010] The second component, which is in surface contact with the first surface of the first component, includes a plurality of first transistors connected in parallel to form a first amplifier circuit; and

[0011] The conductor protrusion extends from the second component to the opposite side of the first component.

[0012] When viewed from above, the aforementioned plurality of first transistors are disposed in an area that does not overlap with any of the plurality of circuit blocks of the aforementioned first component.

[0013] The heat generated by the first transistor is conducted through two heat conduction paths: one from the first transistor to the first component, and another via the conductor protrusion. Therefore, the heat dissipation characteristics of the first transistor can be improved. Attached Figure Description

[0014] Figure 1 It is a block diagram including a high-frequency module of a semiconductor device according to the first embodiment.

[0015] Figure 2 This is a diagram showing the top view of the positional relationship of the circuit components of the high-frequency module according to the first embodiment.

[0016] Figure 3 This is a schematic cross-sectional view of a semiconductor device according to the first embodiment.

[0017] Figure 4A This is an equivalent circuit diagram of each of the plurality of units constituting the first amplifier circuit of the semiconductor device according to the first embodiment. Figure 4B It is a schematic cross-sectional view of a unit that constitutes a first amplifier circuit formed in the second component.

[0018] Figure 5A This is a schematic diagram showing the in-plane arrangement of each circuit block when viewed from above on the first surface of the semiconductor device according to the first embodiment. Figure 5B This is a top view showing the arrangement of the multiple transistors that make up the first amplifier circuit.

[0019] Figures 6A to 6F The accompanying drawing is a cross-sectional view of a semiconductor device during an intermediate stage of manufacturing.

[0020] Figures 7A to 7C The attached figure is a cross-sectional view of a semiconductor device during an intermediate stage of manufacturing. Figure 7D It is a cross-sectional view of a completed semiconductor device.

[0021] Figure 8 This is a schematic diagram showing the in-plane arrangement of each circuit block of the semiconductor device according to the second embodiment.

[0022] Figure 9 This is a schematic diagram showing the in-plane arrangement of each circuit block of the semiconductor device according to the third embodiment.

[0023] Figure 10 This is a schematic diagram showing the in-plane arrangement of each circuit block of the semiconductor device according to the fourth embodiment.

[0024] Figure 11This is a schematic diagram showing the in-plane arrangement of each circuit block of the semiconductor device according to the fifth embodiment.

[0025] Figure 12 This is a schematic diagram showing the in-plane arrangement of each circuit block of the semiconductor device according to the sixth embodiment.

[0026] Figure 13 This is a schematic diagram showing the in-plane arrangement of each circuit block of the semiconductor device according to the seventh embodiment.

[0027] Explanation of reference numerals in the attached figures

[0028] 20…High-frequency module; 21…Module substrate; 30…Semiconductor device; 31…First component; 31A…First surface; 32…Second component; 41…Band selection switch for transmission; 42…First control circuit; 43…Input switch; 50…High-frequency amplifier circuit; 51…First amplifier circuit of the final stage; 52…Second amplifier circuit of the primary stage; 53…Bias circuit; 55…Area where multiple transistors of the first amplifier circuit are distributed; 61…Wiring; 62, 63…Pads; 67…Interlayer insulating film; 68…Protective film; 70…Duplexer; 71…Low-noise amplifier; 72…Antenna switch; 73…Band selection switch for reception; 74…Output terminal selection switch; 75…Second control circuit; 76…Output matching circuit; 82…Conductor protrusion; 82A…Cu pillar; 82B…Solder layer; 82C…Conductor protrusion for collector; 82E…Conductor protrusion for emitter; 83… …Conductor protrusion; 101…Substrate semiconductor layer; 101A…Conductive region; 101B…Component separation region; 102B…Base layer; 102B…Base layer; 102C…Collector layer; 102E…Emitter layer; 103B…Base electrode; 103C…Collector electrode; 103E…Emitter electrode; 104B…Base wiring; 104BB…Base bias wiring; 104C…Collector wiring; 104E…Emitter… Emitter wiring; 105E…Emitter wiring; 105RF…High-frequency signal input wiring; 111…Interlayer insulating film; 112…Interlayer insulating film; 200…Main substrate; 201…Release layer; 202…Component forming layer; 204…Connector support; 210…Substrate; 311…Substrate…312…Multilayer wiring structure; 313…Metal pattern; 314…Through hole; 315, 316…Wiring; 317…First component protective film. Detailed Implementation

[0029] [First Embodiment]

[0030] Reference Figures 1 to 7D The accompanying drawings illustrate a semiconductor device according to a first embodiment. The semiconductor device according to the first embodiment described below is a high-frequency power amplifier.

[0031] Figure 1 This is a block diagram of a high-frequency module 20 including the semiconductor device according to the first embodiment. The high-frequency module 20 includes: a semiconductor device 30 according to the first embodiment, an output matching circuit 76, multiple duplexers 70, an antenna switch 72, two receiving band selection switches 73, two low-noise amplifiers 71, a receiving output terminal selection switch 74, and a second control circuit 75. These circuit components are flip-chip mounted on a module substrate. The high-frequency module 20 has the function of transmitting and receiving in frequency division duplex (FDD) mode.

[0032] The semiconductor device 30 includes a first component 31 and a second component 32 coupled to the first component 31. For example, the first component 31 is made of an elemental semiconductor system, and the second component 32 is made of a compound semiconductor system. An input switch 43, a first control circuit 42, and a frequency band selection switch 41 are formed in the first component 31. A high-frequency amplifier circuit 50, consisting of a first amplifier circuit 51 and a second amplifier circuit 52 forming a two-stage structure, and a bias circuit 53 are formed in the second component 32. The second amplifier circuit 52 is the primary amplifier circuit, and the first amplifier circuit 51 is the final stage amplifier circuit. Figure 1 In the diagram, a relatively light shading line is added to the circuit block disposed on the first component 31, and a relatively dark shading line is added to the circuit block disposed on the second component 32. The bias circuit 53 supplies bias current to the first amplifier circuit 51 and the second amplifier circuit 52 according to the control signal from the first control circuit 42.

[0033] The two input contacts of input switch 43 are connected to high-frequency signal input terminals IN1 and IN2 respectively, which are provided on the module substrate. High-frequency signals are input from the two high-frequency signal input terminals IN1 and IN2. Input switch 43 selects one of the two input contacts and inputs the high-frequency signal input to the selected contact to the high-frequency amplifier circuit 50.

[0034] The high-frequency signal amplified by the high-frequency amplifier circuit 50 is input to one input contact of the frequency band selection switch 41 through the output matching circuit 76. The frequency band selection switch 41 selects one contact from multiple output contacts, so that the high-frequency signal amplified by the high-frequency amplifier circuit 50 is output from the selected output contact.

[0035] Two of the multiple output contacts of the frequency band selection switch 41 are connected to auxiliary output terminals PAAUX1 and PAAUX2 respectively, which are provided on the module substrate. The other six contacts are connected to the transmit input ports of multiple duplexers 70 prepared for each frequency band. The frequency band selection switch 41 has the function of selecting one duplexer 70 from the multiple duplexers 70 prepared for each frequency band.

[0036] Antenna switch 72 has multiple contacts on the circuit side and two contacts on the antenna side. Two of the multiple contacts on the circuit side of antenna switch 72 are connected to the transmit signal input terminals TRX1 and TRX2, respectively. The other six contacts on the circuit side are connected to the input / output shared ports of multiple duplexers 70. The two contacts on the antenna side are connected to antenna terminals ANT1 and ANT2, respectively. Antennas are connected to antenna terminals ANT1 and ANT2, respectively.

[0037] Antenna switch 72 connects two antenna-side contacts to two contacts selected from a plurality of contacts on the circuit side. When communicating using a single frequency band, antenna switch 72 connects one contact on the circuit side and one contact on the antenna side. The high-frequency signal, amplified by high-frequency amplifier circuit 50 and passed through duplexer 70 for the corresponding frequency band, is transmitted from the antenna connected to the selected antenna-side contact.

[0038] Each of the two receiving band selection switches 73 has four input contacts and one output contact. Three of the four input contacts of each of the two band selection switches 73 are connected to the receiving output port of the duplexer 70. The remaining contact of each of the two band selection switches 73 is connected to the auxiliary input terminals LNAAUX1 and LNAAUX2, respectively.

[0039] The output contacts of the two receiver band selection switches 73 are respectively connected to the two low-noise amplifiers 71. The two receiver band selection switches 73 respectively enable the received signal that has passed through the duplexer 70 to be input to the low-noise amplifier 71.

[0040] The contacts on the two circuit sides of the output terminal selection switch 74 are connected to the output ports of the two low-noise amplifiers 71, respectively. The contacts on the three terminal sides of the output terminal selection switch 74 are connected to the receive signal output terminals LNAOUT1, LNAOUT2, and LNAOUT3, respectively. The received signal, amplified by the low-noise amplifier 71, is output from the receive signal output terminal selected by the output terminal selection switch 74.

[0041] Power supply voltages are applied to the first amplifier circuit 51 and the second amplifier circuit 52 from the power supply terminals VCC1 and VCC2 located on the module substrate, respectively.

[0042] The first control circuit 42 is connected to the power supply terminal VIO1, the control signal terminal SDATA1, and the clock terminal SCLK1. The first control circuit 42 controls the bias circuit 53, the input switch 43, and the frequency band selection switch 41 based on the control signal given to the control signal terminal SDATA1.

[0043] The second control circuit 75 is connected to the power supply terminal VIO2, the control signal terminal SDATA2, and the clock terminal SCLK2. The second control circuit 75 controls the low-noise amplifier 71, the receiver band selection switch 73, and the output terminal selection switch 74 based on the control signal provided to the control signal terminal SDATA2.

[0044] The module substrate also includes a power supply terminal VBAT and a drain voltage terminal VDD2. Power is supplied from the power supply terminal VBAT to the bias circuit of the high-frequency amplifier circuit 50 and the first control circuit 42. The power supply voltage is applied to the low-noise amplifier 71 from the drain voltage terminal VDD2.

[0045] Figure 2 This diagram shows the top-view positional relationship of the circuit components of the high-frequency module 20 according to the first embodiment. A semiconductor device 30, multiple duplexers 70, a low-noise amplifier 71, an antenna switch 72, and other surface-mount passive components are mounted on the module substrate 21. The first component 31 of the semiconductor device 30 is larger than the second component 32 in top view and includes the second component 32.

[0046] The first component 31 includes a frequency band selection switch 41, a first control circuit 42, and an input switch 43. Figure 2 The area enclosed by dashed lines indicates the region containing circuit blocks such as the frequency band selection switch 41, the first control circuit 42, and the input switch 43. Here, a circuit block represents a collection of multiple circuit elements, such as semiconductor elements and passive components, constructed to achieve a certain function, as well as the wiring connecting these circuit elements to each other. Generally, the circuit is designed on a per-circuit-block basis and laid out on the semiconductor substrate on a per-circuit-block basis.

[0047] The output matching circuit 76 is composed of passive components such as inductors disposed within the module substrate and capacitors surface-mounted on the module substrate. In top view, the inductors constituting the output matching circuit 76 are positioned overlapping the semiconductor device 30. In this specification, the state of "two components overlapping in top view" includes a state where one component contains another component, a state where a portion of one component overlaps with a portion of another component, and a state where the outer perimeters of the two components coincide.

[0048] Figure 3 This is a schematic cross-sectional view of the semiconductor device 30 according to the first embodiment. The first component 31 includes: a substrate 311, a multilayer wiring structure 312 disposed on the substrate 311, and a first component protective film 317 covering the surface of the multilayer wiring structure 312. The substrate 311 includes a semiconductor portion of an elemental semiconductor system. For example, a silicon substrate or a silicon-on-insulator (SOI) substrate is used as the substrate 311. Band selection switch 41 ( Figure 1), First control circuit 42 ( Figure 1 ) and input switch 43 ( Figure 1 It is composed of semiconductor elements formed on the surface layer of substrate 311 and wiring within multilayer wiring structure 312. Figure 3 The area forming the input switch 43 is shown enclosed by a dashed line. Let the outermost surface of the first component 31 be referred to as the first surface 31A. An opening is provided in a portion of the first component protective film 317, and a metal film 318 is filled in the opening. The upper surfaces of the first component protective film 317 and the metal film 318 correspond to the first surface 31A.

[0049] The second component 32 is bonded to the first component 31 on its first surface 31A. Furthermore, in a top view, at least a portion of the second component 32 overlaps with at least a portion of the metal film 318, and the second component 32 is in surface contact with the metal film 318. An interlayer insulating film 67 is disposed on the first surface 31A to cover the second component 32. Multiple openings are provided at predetermined locations on the interlayer insulating film 67. Pads 62 and 63 and wiring 61 are disposed on the interlayer insulating film 67. The wiring layer on which the pads 62 and 63 and wiring 61 are disposed is sometimes referred to as a rewiring layer. The wiring 61 within the rewiring layer is sometimes referred to as rewiring.

[0050] Wiring 61 connects the circuit formed in the second component 32 and the circuit formed in the first component 31 through an opening provided in the interlayer insulating film 67. For example, wiring 61 is connected to the input switch 43 via wiring 315 within the multilayer wiring structure 312. For example, wiring 61 is used for... Figure 1 The connections shown include the input switch 43 to the second amplifier circuit 52, the first control circuit 42 to the second amplifier circuit 52, and the first control circuit 42 to the first amplifier circuit 51.

[0051] Pad 62 is included in the second component 32 when viewed from above and is connected to the circuitry formed in the second component 32. Other pads 63 are disposed outside the second component 32 when viewed from above and are connected to the input switch 43 formed in the first component 31 via wiring 316 in the multilayer wiring structure 312.

[0052] A protective film 68 is disposed on the interlayer insulating film 67 to cover the redistribution layer. The protective film 68 has openings that expose a portion of the upper surface of each of the pads 62 and 63. Conductor protrusions 82 and 83 are disposed on the pads 62 and 63, respectively. The conductor protrusion 82 includes a Cu pillar 82A connected to the pad 62 and a solder layer 82B disposed on the upper surface of the Cu pillar 82A. Such a conductor protrusion 82 is referred to as a Cu pillar bump.

[0053] Alternatively, a lower bump metal layer can be disposed on the bottom surface of the Cu pillar 82A to improve adhesion. Other conductor protrusions 83 also have the same stacked structure as conductor protrusions 82. Furthermore, conductor protrusions 82, 83, etc., can also use Au bumps, solder ball bumps, or conductor pillars erected on pads instead of Cu pillar bumps. Like Au bumps, bumps that do not carry a solder layer are also called pillars. Conductor pillars erected on pads are also called terminals.

[0054] Conductor protrusion 82 is used for example Figure 1 The diagram shows the connection between power terminal VCC1 and the first amplifier circuit 51, the connection between power terminal VCC2 and the second amplifier circuit 52, and the connection between the first amplifier circuit 51 and the output matching circuit 76. Furthermore, the conductor protrusion 82 is used to connect the grounding conductor within the second component 32 to the grounding conductor of the module substrate.

[0055] Conductor protrusion 83 is used for example Figure 1 The connection shown includes the input switch 43 to the high-frequency signal input terminals IN1 and IN2, the connection of the first control circuit 42 to the power supply terminal VIO1, the control signal terminal SDATA1 and the clock terminal SCLK1, the connection of the frequency band selection switch 41 to the output matching circuit 76, and the connection of multiple duplexers 70.

[0056] Multiple vias 314 are disposed within the multilayer wiring structure 312. These vias connect at least one layer of metal pattern 313 in the thickness direction, and the metal patterns 313 are either connected to each other or to a metal film 318 and a metal pattern 313. The multiple metal patterns 313 overlap with a portion of the second component 32 when viewed from above. The metal pattern 313 disposed in the lowest wiring layer is connected to the substrate 311 via the multiple vias 314. The metal patterns 313 are not electrically connected to any circuit block of the first component 31. The metal film 318, the metal patterns 313, and the vias 314 function as a heat conduction path from the second component 32 to the substrate 311. Furthermore, the conductor protrusion 82, in addition to functioning as a current path, also functions as a heat conduction path from the second component 32 to the module substrate.

[0057] Figure 4A It is the first amplifier circuit 51 constituting the semiconductor device according to the first embodiment. Figure 1 The equivalent circuit diagram of each unit of the multiple units of the amplifier circuit 51. The first amplifier circuit 51 is composed of multiple units connected in parallel. In addition, the second amplifier circuit 52 ( Figure 1 It also has the same circuit structure as the first amplifier circuit 51. However, the number of units constituting amplifier circuit 52 is less than the number of units constituting amplifier circuit 51.

[0058] Each unit includes: a transistor Q, an input capacitor Cin, and a ballast resistor Rb. The base of transistor Q is connected to the high-frequency signal input wiring 105RF via the input capacitor Cin. Furthermore, the base of transistor Q is connected to the base bias wiring 104BB via the ballast resistor Rb. The emitter of transistor Q is grounded. The collector of transistor Q is connected to the collector wiring 104C. A power supply voltage is applied to the collector of transistor Q via the collector wiring 104C, and an amplified high-frequency signal is output from the collector.

[0059] Figure 4B It constitutes the first amplifier circuit 51 formed in the second component 32. Figure 1 This is a schematic cross-sectional view of one unit of the first component 31. The second component 32 includes a substrate semiconductor layer 101. The second component 32 is bonded to the first component 31 by means of surface contact between the substrate semiconductor layer 101 and the first component 31. The substrate semiconductor layer 101 is divided into a conductive region 101A and a device separation region 101B. The substrate semiconductor layer 101 is, for example, made of GaAs. The conductive region 101A is formed of n-type GaAs, and the device separation region 101B is formed by ion implantation of insulating impurities into the n-type GaAs layer.

[0060] A transistor Q is disposed on a conductive region 101A. Transistor Q includes a collector layer 102C, a base layer 102B, and an emitter layer 102E, sequentially stacked from the conductive region 101A. The emitter layer 102E is disposed on a portion of the base layer 102B. As an example, the collector layer 102C is formed of n-type GaAs, the base layer 102B is formed of p-type GaAs, and the emitter layer 102E is formed of n-type InGaP. That is, transistor Q is a heterojunction bipolar transistor.

[0061] A base electrode 103B is disposed on the base layer 102B and is electrically connected to the base layer 102B. An emitter electrode 103E is disposed on the emitter layer 102E and is electrically connected to the emitter layer 102E. A collector electrode 103C is disposed on the conductive region 101A. The collector electrode 103C is electrically connected to the collector layer 102C via the conductive region 101A.

[0062] An interlayer insulating film 111 is disposed on the substrate semiconductor layer 101 to cover the transistor Q, collector electrode 103C, base electrode 103B, and emitter electrode 103E. The first layer interlayer insulating film 111 is formed of an inorganic insulating material such as SiN. Multiple openings are provided at predetermined positions on the interlayer insulating film 111.

[0063] An emitter wiring 104E, a base wiring 104B, a collector wiring 104C, and a base bias wiring 104BB are disposed on the interlayer insulating film 111. A ballast resistor element Rb is also disposed on the interlayer insulating film 111. The emitter wiring 104E is connected to the emitter electrode 103E through an opening in the interlayer insulating film 111. The base wiring 104B is connected to the base electrode 103B through other openings in the interlayer insulating film 111. The collector wiring 104C is connected to the collector electrode 103C through other openings in the interlayer insulating film 111.

[0064] The base wiring 104B extends into the region where no transistor Q is configured, and its front end overlaps with one end of the ballast resistor element Rb. In the overlapping portion, the base wiring 104B is electrically connected to the ballast resistor element Rb. The other end of the ballast resistor element Rb overlaps with the base bias wiring 104BB. In the overlapping portion, the ballast resistor element Rb is electrically connected to the base bias wiring 104BB.

[0065] A second interlayer insulating film 112 is disposed on the interlayer insulating film 111 to cover the emitter wiring 104E, base wiring 104B, base bias wiring 104BB, and ballast resistor element Rb of the first layer. The second interlayer insulating film 112 is also formed of an inorganic insulating material such as SiN.

[0066] A second layer of emitter wiring 105E and a high-frequency signal input wiring 105RF are disposed on the interlayer insulating film 112. The second layer of emitter wiring 105E is connected to the first layer of emitter wiring 104E through an opening in the interlayer insulating film 112. A portion of the high-frequency signal input wiring 105RF overlaps with the first layer of base wiring 104B when viewed from above. An input capacitor Cin is formed in the overlapping area.

[0067] A third interlayer insulating film 67 is provided to cover the emitter wiring 105E and the high-frequency signal input wiring 105RF of the second layer. The third interlayer insulating film 67 is formed, for example, of an organic insulating material such as polyimide. Furthermore, as... Figure 3 As shown, the interlayer insulating film 67 of the third layer extends onto the first component 31.

[0068] Pads 62 are disposed on the interlayer insulating film 67 of the third layer. Pads 62 are connected to the emitter wiring 105E of the second layer through openings provided in the interlayer insulating film 67.

[0069] Figure 5AThis is a schematic diagram showing the in-plane arrangement of the circuit blocks when viewed from above on the first surface 31A of the semiconductor device 30 according to the first embodiment. The multiple circuit blocks formed on the first component 31 include a frequency band selection switch 41, a first control circuit 42, and an input switch 43. When viewed from above on the first surface 31A, these circuit blocks are arranged in the region inside the first surface 31A.

[0070] The multiple circuit blocks formed in the second component 32 include a final-stage first amplifier circuit 51, a primary-stage second amplifier circuit 52, and a bias circuit 53. Figure 5A In the diagram, a shading line sloping downwards to the right is added to the circuit blocks formed on the first component 31. A shading line sloping upwards to the right is added to the areas of the second amplifier circuit 52 and the area where the bias circuit 53 is configured on the second component 32. Figures 8-13 The same shading is also added to the attached diagram.

[0071] Figure 5B This represents the multiple transistors Q that constitute the first amplifier circuit 51. Figure 4A , Figure 4B A top-view diagram of the configuration of the multiple transistors Q. Each of the multiple transistors Q includes a collector layer 102C and a base layer 102B. In top view, the outer periphery of the collector layer 102C is almost flush with the outer periphery of the base layer 102B. In top view, the emitter layer 102E (… Figure 4B The transistor Q is contained within the base layer 102B. Viewed from above, each transistor Q has an angle in one direction (…). Figure 5B A shape that is longer in the vertical direction. Multiple transistors Q have parallel long sides, and multiple transistors Q are orthogonal to the long side direction (…). Figure 5B Arranged in the left and right directions.

[0072] Multiple transistors Q are distributed within region 55. Region 55, where multiple transistors Q are distributed, is defined, for example, as a minimal convex polygon containing multiple transistors Q when viewed from above.

[0073] Alternatively, multiple columns of transistors Q can be arranged in a direction orthogonal to the direction in which the transistors Q are arranged. In this case, the smallest convex polygon containing all the transistors Q included in the multiple transistor columns can be defined as the region 55 where the multiple transistors Q are distributed.

[0074] like Figure 5A As shown, a region 55 containing multiple transistors Q is arranged within the circuit block constituting the first amplifier circuit 51. Conductor protrusions 82E and 82C are respectively connected to the emitters and collectors of the multiple transistors Q. In top view, the conductor protrusion 82E for the emitter encompasses the region 55 containing the multiple transistors Q. In addition, the circuit block constituting the first amplifier circuit 51 also contains... Figure 4A as well as Figure 4B The input capacitor Cin and the ballast resistor element Rb are shown.

[0075] The first amplifier circuit 51 does not overlap with any circuit block formed in the first component 31. Therefore, the region 55 where the plurality of transistors Q are distributed also does not overlap with any circuit block formed in the first component 31. Furthermore, each of the plurality of transistors Q also does not overlap with any circuit block formed in the first component 31. In top view, a multilayer wiring structure 312 is arranged in the region overlapping with the circuit blocks constituting the first amplifier circuit 51. Figure 3 The metal pattern 313, the through hole 314, and the metal film 318 within the ) Figure 3 ).

[0076] Each circuit block constituting the second amplifier circuit 52 and the bias circuit 53 overlaps with any circuit block formed in the first component 31. For example, the circuit block constituting the second amplifier circuit 52 overlaps with the circuit block constituting the input switch 43 and the first control circuit 42 formed in the first component 31, and the circuit block constituting the bias circuit 53 overlaps with the circuit block constituting the first control circuit 42 and the frequency band selection switch 41 formed in the first component 31. In this way, a circuit block in the second component 32 that is not a circuit block constituting the first amplifier circuit 51 can overlap across multiple circuit blocks in the first component 31, or, as other structures, can overlap with a single circuit block in the first component 31.

[0077] Next, refer to Figures 6A to 7D The accompanying drawings illustrate a method for manufacturing a semiconductor device 30 according to a first embodiment. Figures 6A to 7C The accompanying drawing is a cross-sectional view of the semiconductor device 30 during an intermediate stage of manufacturing. Figure 7D This is a cross-sectional view of the completed semiconductor device 30.

[0078] like Figure 6A As shown, a release layer 201 is epitaxially grown on a single-crystal mother substrate 200 of a compound semiconductor such as GaAs, and a device forming layer 202 is formed on the release layer 201. A device forming layer 202 is formed on the device forming layer 202. Figure 4B The second component 32 shown includes transistor Q, a first wiring layer, a second wiring layer, etc. These circuit elements and wiring layers are formed using conventional semiconductor processes. Figure 6A In this section, the element structure formed on the element forming layer 202 is omitted from the description. In this stage, the element forming layer 202 is not separated into individual second components 32.

[0079] Next, as Figure 6B As shown, the resist pattern (not shown) is used as an etching mask to form the element layer 202 ( Figure 5AThe element forming layer 202 is patterned, along with the release layer 201. Figure 5A It is separated into individual second components 32.

[0080] Next, as Figure 6C As shown, the connecting support 204 is attached to the separated second component 32. Thus, multiple second components 32 are interconnected via the connecting support 204. Furthermore, it is possible to leave [something] on [the surface]. Figure 6B The resist pattern is used as an etching mask in the patterning process, and the resist pattern is placed between the second component 32 and the connecting support 204.

[0081] Next, as Figure 6D As shown, the release layer 201 is selectively etched onto the mother substrate 200 and the second component 32. This peels the second component 32 and the connecting support 204 from the mother substrate 200. To selectively etch the release layer 201, a compound semiconductor with an etching resistance different from both the mother substrate 200 and the second component 32 is used as the release layer 201.

[0082] like Figure 6E As shown, a structure is prepared to be formed on the first component 31 ( Figure 3 The input switch 43 and the multi-layer wiring structure 312 ( Figure 3 The substrate 210, etc. At this stage, the substrate 210 is not separated into individual first components 31.

[0083] like Figure 6F As shown, the second component 32 is bonded to the substrate 210. The bonding between the second component 32 and the substrate 210 is via van der Waals bonds or hydrogen bonds. Alternatively, the second component 32 can be bonded to the substrate 210 via electrostatic bonding, covalent bonding, eutectic alloy bonding, etc. For example, if a portion of the surface of the substrate 210 is formed of Au, the second component 32 can be brought into close contact with the Au region and pressure applied to bond the two together.

[0084] Next, as Figure 7A As shown, the connecting support 204 is peeled off from the second component 32. After peeling off the connecting support 204, as... Figure 7B As shown, an interlayer insulating film 67 and a redistribution layer are formed on the substrate 210 and the second component 32. The redistribution layer includes wiring 61, pads 62, and 63 (…). Figure 3 )wait.

[0085] Next, as Figure 7C As shown, a protective film 68 is formed on the redistribution layer, and an opening is formed at a predetermined position on the protective film 68. Then, conductor protrusions 82 are formed within the openings and on the protective film 68. Other conductor protrusions 83 are formed simultaneously with the formation of the conductor protrusions 82. Figure 3)wait.

[0086] Finally, as Figure 7D As shown, substrate 210 is cut. This yields semiconductor device 30.

[0087] Next, the superior effects of the first embodiment will be explained.

[0088] In the first embodiment, as Figure 3 As shown, a heat conduction path is formed from the second component 32 toward the first component 31. Since the second component 32 is in surface contact with the first component 31, the second component 32 and the first component 31 are thermally coupled with low thermal resistance. Furthermore, since a metal pattern 313 and a via 314 are disposed within the multilayer wiring structure 312 directly beneath the second component 32, the thermal resistance of the heat conduction path from the second component 32 to the substrate 311 is lower compared to a structure where the entire area of ​​the multilayer wiring structure 312 directly beneath the second component 32 is formed of insulating material. Moreover, since the metal pattern 313 is not electrically connected to any circuit block of the first component 31, the metal pattern 313, functioning as a heat conduction path, does not affect the operation of the circuit blocks of the first component 31. Additionally, the metal pattern 313 can also be electrically connected to a grounding conductor within the first component 31.

[0089] Heat conducted from the second component 32 to the first component 31 diffuses into the first component 31. The heat diffused into the first component 31 radiates from the surface of the first component 31 to the outside. When the semiconductor device 30 is mounted on the module substrate and covered by molding resin, heat is conducted from the first component 31 to the molding resin.

[0090] Furthermore, the conductor protrusion 82 functions as a heat conduction path from the second component 32 to the module substrate. Thus, heat dissipation occurs through two paths: the heat conduction path from the second component 32 towards the module substrate and the heat conduction path from the second component 32 towards the first component 31. Therefore, the heat dissipation characteristics from the second component 32 can be improved. To achieve a sufficiently improved heat dissipation characteristic, it is preferable that the semiconductor portion of the substrate 311 of the first component 31 uses a compound semiconductor with a higher thermal conductivity than the semiconductor element formed in the second component 32, such as elemental semiconductors like Si or Ge. Additionally, as the semiconductor element formed in the second component 32, to amplify high-frequency signals, it is preferable to use a compound semiconductor-based semiconductor element with a higher electron mobility than the semiconductor portion of the substrate 311 of the first component 31.

[0091] Region 55 in the second component 32, which constitutes the distribution of multiple transistor Qs in the first amplifier circuit 51 Figure 5A Heat is particularly easily generated in the region 55 where multiple transistors Q are distributed to the substrate 311 of the first component 31. Figure 3 The thermal resistance of the heat conduction path of the transistor is preferably configured in metal pattern 313 so that, when viewed from above, the region 55 where the multiple transistor Q distributions are distributed is contained within metal pattern 313. Figure 3 Furthermore, the metal film 318 is preferably configured such that, when viewed from above, the region 55 where the multiple transistor Qs are distributed is contained within the metal film 318. Figure 3 )middle.

[0092] Because a high-frequency current larger than that of the second amplifier circuit 52 or the bias circuit 53 flows to the first amplifier circuit 51, the first amplifier circuit 51 is prone to becoming a source of noise. In the first embodiment, because the first amplifier circuit 51 (when viewed from above) Figure 5A The circuit does not overlap with any of the circuit blocks of the first component 31, thus achieving the excellent effect that the circuit blocks of the first component 31 are less affected by the noise generated by the first amplifier circuit 51.

[0093] Additionally, in the first embodiment, when viewed from above, the second amplifier circuit 52 and the bias circuit 53 of the second component 32 ( Figure 5A It overlaps with any circuit block of the first component 31. Therefore, the size of the semiconductor device 30 when viewed from above can be reduced.

[0094] Next, a variation of the first embodiment will be described.

[0095] In the first embodiment, the metal film 318 ( Figure 3 The first component 31 has multiple metal patterns 313 and multiple through holes 314 within its multilayer wiring structure 312. Figure 3 The heat conduction path formed by the metal film 318, the metal pattern 313, and the multiple vias 314 may not necessarily contact the second component 32 and the substrate 311. For example, the heat conduction path formed by the multiple metal patterns 313 and the multiple vias 314 may also be thermally coupled to the second component 32 and the substrate 311 via the insulating film. In this case, the insulating film functions as part of the heat conduction path from the second component 32 to the substrate 311. Alternatively, the metal film 318 may not be provided, and the entire area of ​​the first surface 31A may be used as the first component protective film 317. In this case, the portion of the first component protective film 317 that contacts the second component 32 mainly functions as a heat conduction path.

[0096] Furthermore, without the metal pattern 313 and via 314, the thermal resistance of the heat conduction path from the second component 32 to the substrate 311 becomes high. However, if sufficient heat dissipation characteristics from the first amplifier circuit 51 are obtained, the metal pattern 313 and via 314 may not be provided. In this case, the insulating film included in the multilayer wiring structure 312 functions as a heat conduction path.

[0097] According to the first embodiment, the high-frequency amplifier circuit 50 of the semiconductor device 30 ( Figure 1 The high-frequency amplifier circuit 50 is a two-stage structure consisting of the primary second amplifier circuit 52 and the final first amplifier circuit 51, but it can also be configured as a multi-stage structure with three or more stages. In this case, the region 55 where the multiple transistors Q of the final first amplifier circuit 51 are distributed... Figure 5A It may also not overlap with any of the circuit blocks of the first component 31.

[0098] In the first embodiment, although the semiconductor device 30 is mounted on the high-frequency module 20 of the frequency division duplex (FDD) mode ( Figure 1 However, it can also be used in high-frequency modules in time-division duplex (TDD) mode.

[0099] When the semiconductor device 30 is mounted in a TDD-type high-frequency module, the bandwidth selection switch 41 can be replaced with a transmit / receive switching switch. The transmit / receive switching switch has two contacts and one common terminal. One of the two contacts is connected via an output matching circuit 76 (…). Figure 1 The first amplifier circuit 51 of the final stage is connected to the other contact, which is connected to the low-noise amplifier 71 used to amplify the received signal. Figure 1 ) connect, or via the receiving band selection switch 73 ( Figure 1 The transmit / receive switch is connected to the low-noise amplifier 71. The common terminal is connected to the antenna terminal via a filter. For example, the transmit / receive switch is connected to the band selection switch 41 of the first embodiment (…). Figure 5A Similarly, when viewed from above, it overlaps with the bias circuit 53 of the second component 32.

[0100] [Second Embodiment]

[0101] Next, refer to Figure 8 The semiconductor device according to the second embodiment will be described below. Hereinafter, the semiconductor device will be described in relation to the referenced... Figures 1 to 7D The structure common to the semiconductor device according to the first embodiment, as illustrated in the accompanying drawings, is omitted from the description.

[0102] Figure 8 This is a schematic diagram showing the in-plane arrangement of each circuit block of the semiconductor device 30 according to the second embodiment. In the first embodiment ( Figure 5AIn the first embodiment, a portion of the circuit block constituting the band selection switch 41 overlaps with the second component 32. In contrast, in the second embodiment, when viewed from above, the circuit block constituting the band selection switch 41 does not overlap with the second component 32, but is disposed outside the second component 32.

[0103] The circuit block of the bias circuit 53 constituting the second component 32 overlaps with the circuit block of the input switch 43 constituting the first component 31 and the circuit block of the first control circuit 42. The circuit block of the second amplifier circuit 52 constituting the second component 32 overlaps with the circuit block of the first control circuit 42 constituting the first component 31.

[0104] Next, the superior effects of the second embodiment will be explained.

[0105] In the second embodiment, similarly to the first embodiment, the heat dissipation characteristics of transistor Q in the first amplifier circuit 51 can be improved. Furthermore, in the second embodiment, since the circuit block constituting the band selection switch 41 does not overlap with the second component 32 when viewed from above, the excellent effect of easily ensuring input-output isolation is achieved. Specifically, the high-frequency signal transmitted in the band selection switch 41 is less likely to pass through the second component 32 and interact with the high-frequency amplifier circuit 50 (…). Figure 1 The input side is coupled. This results in the excellent effect of making it difficult to generate oscillations in the high-frequency amplifier circuit 50.

[0106] Next, a variation of the second embodiment will be described. In the second embodiment, the semiconductor device 30 is mounted in an FDD-type high-frequency module, but it can also be mounted in a TDD-type high-frequency module. When the semiconductor device 30 is mounted in a TDD-type high-frequency module, it is only necessary to replace the frequency band selection switch 41 with a transmit / receive switching switch. In this case, the structure can be configured such that, when viewed from above, the circuit block constituting the transmit / receive switching switch does not overlap with the second component 32, but is disposed outside the second component 32.

[0107] [Third Embodiment]

[0108] Next, refer to Figure 9 The semiconductor device according to the third embodiment will be described below. Hereinafter, the semiconductor device will be described in relation to the referenced... Figure 8 The structure common to the semiconductor device according to the second embodiment is omitted from the description.

[0109] Figure 9 This is a schematic diagram showing the in-plane arrangement of each circuit block of the semiconductor device 30 according to the third embodiment. In the second embodiment ( Figure 8In the first embodiment, when viewed from above, the circuit block constituting the input switch 43 overlaps with the second component 32. In contrast, in the third embodiment, when viewed from above, the circuit block constituting the input switch 43 does not overlap with the second component 32.

[0110] Next, the superior effects of the third embodiment will be explained.

[0111] In the third embodiment, similarly to the second embodiment, the heat dissipation characteristics of the transistor Q in the first amplifier circuit 51 can be improved. Furthermore, in the third embodiment, neither the circuit block constituting the input switch 43 connected to the input side of the high-frequency amplifier circuit 50 nor the band selection switch 41 connected to the output side overlaps with the second component 32. Therefore, the input-output isolation of the high-frequency amplifier circuit 50 can be further improved.

[0112] [Fourth Embodiment]

[0113] Next, refer to Figure 10 The semiconductor device according to the fourth embodiment will be described below. Hereinafter, the semiconductor device will be described in relation to the referenced... Figure 9 The structure common to the semiconductor device according to the third embodiment is omitted from the description.

[0114] Figure 10 This is a schematic diagram showing the in-plane arrangement of the circuit blocks of the semiconductor device 30 according to the fourth embodiment. In the third embodiment, the circuit block of the second amplifier circuit 52 constituting the second component 32 overlaps with the circuit block of the first control circuit 42 constituting the first component 31. In contrast, in the fourth embodiment, the circuit block of the second amplifier circuit 52 constituting the second component 32 does not overlap with any circuit block of the first component 31.

[0115] Next, the superior effects of the fourth embodiment will be explained.

[0116] Similar to the third embodiment, the heat dissipation characteristics of transistor Q in the first amplifier circuit 51 can be improved in the fourth embodiment. Furthermore, in the fourth embodiment, since the circuit blocks of the second amplifier circuit 52 constituting the second component 32 do not overlap with any circuit block of the first component 31, the impact of noise generated in the second amplifier circuit 52 on the circuit formed in the first component 31 can be reduced.

[0117] Alternatively, the regions where the multiple transistors constituting the second amplifier circuit 52 are distributed can be configured so that they do not overlap with any circuit block of the first component 31, while other regions of the second amplifier circuit 52 overlap with any circuit block of the first component 31. Even in this case, the heat dissipation characteristics of the multiple transistors constituting the second amplifier circuit 52 are improved.

[0118] [Fifth Embodiment]

[0119] Next, refer to Figure 11 The semiconductor device according to the fifth embodiment will be described below. Hereinafter, the semiconductor device will be described in relation to the referenced... Figure 10 The structure common to the semiconductor device according to the fourth embodiment is omitted from the description.

[0120] Figure 11 This is a schematic diagram showing the in-plane arrangement of each circuit block of the semiconductor device 30 according to the fifth embodiment. In the fourth embodiment ( Figure 10 In the first embodiment, when viewed from above, the circuit blocks of the first amplifier circuit 51 and the second amplifier circuit 52 constituting the second component 32 do not overlap with any circuit block of the first component 31, and the circuit block of the bias circuit 53 constituting the second component 32 overlaps with the circuit block of the first control circuit 42 constituting the first component 31. In contrast, in the fifth embodiment, when viewed from above, no circuit block of the second component 32 overlaps with any circuit block of the first component 31. In other words, when viewed from above, no circuit block of the first component 31 overlaps with any circuit block of the second component 32.

[0121] Next, the superior effects of the fifth embodiment will be explained.

[0122] Similar to the fourth embodiment, the heat dissipation characteristics of transistor Q in the first amplifier circuit 51 can be improved in the fifth embodiment. Furthermore, in the fifth embodiment, the circuit formed in the first component 31 is less susceptible to the effects of heat or noise from the second component 32. The first control circuit 42 of the first component 31 includes, for example, a charge pump that obtains a predetermined voltage. The charge pump or digital circuitry of the first control circuit 42 can easily become a noise source for the analog circuitry. In the fifth embodiment, since the second component 32 does not overlap with any circuit block of the first component 31, the circuitry of the second component 32 is less susceptible to the effects of noise sources from the first component 31.

[0123] In the fifth embodiment, since neither the second component 32 nor any circuit block of the first component 31 overlaps, the top-view size of the semiconductor device 30 is larger than the size of the semiconductor device 30 in any of the first to fourth embodiments. The semiconductor device 30 can be selected based on the required level of noise countermeasures, and the structure of that embodiment can be chosen accordingly.

[0124] [Sixth Embodiment]

[0125] Next, refer to Figure 12 The semiconductor device according to the sixth embodiment will be described below. Hereinafter, the device will be described in relation to the referenced semiconductor device. Figures 1 to 7DThe structure common to the semiconductor device according to the first embodiment, as illustrated in the accompanying drawings, is omitted from the description.

[0126] Figure 12 This is a schematic diagram showing the in-plane arrangement of each circuit block of the semiconductor device 30 according to the sixth embodiment. In the first embodiment ( Figure 1 , Figure 5A , Figure 5B In the first embodiment, the second amplifier circuit 52 of the primary stage of the high-frequency amplifier circuit 50 is formed in the second component 32. In contrast, in the sixth embodiment, the second amplifier circuit 52 is formed in the first component 31. The second component 32 has the first amplifier circuit 51 and the bias circuit 53.

[0127] When viewed from above, the circuit block of the bias circuit 53 constituting the second component 32 overlaps with the circuit block of the input switch 43 constituting the first component 31. When viewed from above, the circuit block of the first amplifier circuit 51 constituting the second component 32 does not overlap with any circuit block of the first component 31.

[0128] Next, the superior effects of the sixth embodiment will be explained.

[0129] Similar to the first embodiment, the heat dissipation characteristics of the transistor Q in the first amplifier circuit 51 can be improved in the sixth embodiment. Furthermore, in the sixth embodiment, since the second amplifier circuit 52 is formed in the first component 31, the size of the second component 32 can be reduced. Generally, substrates based on elemental semiconductors such as silicon are cheaper than substrates based on compound semiconductors such as GaAs. Moreover, semiconductor manufacturing processes based on elemental semiconductors are easier to reduce in cost compared to semiconductor manufacturing processes based on compound semiconductors. In the sixth embodiment, by reducing the size of the second component 32, which includes a compound semiconductor element, the cost of the semiconductor device 30 can be reduced.

[0130] [Seventh Embodiment]

[0131] Next, refer to Figure 13 The semiconductor device according to the seventh embodiment will be described below. Hereinafter, the device will be described in relation to the referenced semiconductor device. Figure 12 The structure common to the semiconductor device according to the sixth embodiment is omitted from the description.

[0132] Figure 13 This is a schematic diagram showing the in-plane arrangement of the circuit blocks of the semiconductor device 30 according to the seventh embodiment. In the sixth embodiment, the second amplifier circuit 52 is formed in the first component 31, but the bias circuit 53 remains in the second component 32. In contrast, in the seventh embodiment, the bias circuit 53 is also formed in the first component 31.

[0133] Next, the superior effects of the seventh embodiment will be explained.

[0134] In the seventh embodiment, both the second amplifier circuit 52 and the bias circuit 53 are formed in the first component 31. Only the final stage of the first amplifier circuit 51 remains in the second component 32. Therefore, in the seventh embodiment, the second component 32 can be further reduced in size compared to the sixth embodiment. As a result, the cost of the semiconductor device 30 can be further reduced.

[0135] The above embodiments are illustrative examples; of course, parts of the structures shown in different embodiments can be replaced or combined. The same effects resulting from the same structures in multiple embodiments are not mentioned sequentially in each embodiment. Furthermore, the present invention is not limited to the above embodiments. For example, those skilled in the art will understand that various changes, improvements, combinations, etc., can be made.

Claims

1. A semiconductor device comprising: A first component has a first surface, and when viewed from above, the first component includes a plurality of circuit blocks disposed in a region inside the first surface; The second component is surface-contactly bonded to the first surface of the first component and includes a plurality of first transistors, which are connected in parallel to form a first amplifier circuit; and The conductor protrusion extends from the second component to the opposite side of the first component. The aforementioned plurality of first transistors are disposed in an area that does not overlap with any of the plurality of circuit blocks of the aforementioned first component when viewed from above. One of the circuit blocks in the first component constitutes a frequency band selection switch. The frequency band selection switch causes a high-frequency signal input to an input contact to be output to one output contact selected from the plurality of output contacts. The input contact is input with a high-frequency signal output from the first amplifier circuit. The circuit block constituting the aforementioned frequency band selection switch is positioned on the outside of the aforementioned second component when viewed from above.

2. A semiconductor device comprising: A first component has a first surface, and when viewed from above, the first component includes a plurality of circuit blocks disposed in a region inside the first surface; The second component is surface-contactly bonded to the first surface of the first component and includes a plurality of first transistors, which are connected in parallel to form a first amplifier circuit; and The conductor protrusion extends from the second component to the opposite side of the first component. The aforementioned plurality of first transistors are disposed in an area that does not overlap with any of the plurality of circuit blocks of the aforementioned first component when viewed from above. One of the circuit blocks in the first component constitutes an input switch, which allows a high-frequency signal selected from the plurality of input contacts to be input to the first amplifier circuit. The circuit block constituting the input switch is positioned outside the second component when viewed from above.

3. The semiconductor device according to claim 1 or 2, wherein, The second component overlaps with at least one of the multiple circuit blocks of the first component when viewed from above.

4. The semiconductor device according to claim 1 or 2, wherein, The second component further includes at least one second transistor, which constitutes a second amplifier circuit connected to the front end of the first amplifier circuit. The aforementioned at least one second transistor is disposed in a region that does not overlap with any of the multiple circuit blocks of the aforementioned first component when viewed from above.

5. The semiconductor device according to claim 1 or 2, wherein, One of the multiple circuit blocks of the first component described above constitutes a second amplifier circuit connected to the front end of the first amplifier circuit described above. The second component includes a bias circuit that supplies bias current to the first amplifier circuit, and the bias circuit overlaps with at least one of the plurality of circuit blocks of the first component.

6. The semiconductor device according to claim 1 or 2, wherein, One of the multiple circuit blocks of the first component constitutes a bias circuit that supplies bias current to the first amplifier circuit.

7. The semiconductor device according to claim 1 or 2, wherein, When viewed from above, the second component does not overlap with any of the multiple circuit blocks of the first component.

8. The semiconductor device according to claim 1 or 2, wherein, The first component includes: a semiconductor substrate and a multilayer wiring structure disposed on one surface of the semiconductor substrate. The first surface mentioned above is the surface of the aforementioned multi-layer wiring structure. The aforementioned multilayer wiring structure overlaps with the aforementioned second component and includes a metal pattern that is not electrically connected to any of the aforementioned multiple circuit blocks.

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