Electrostatic discharge (ESD) protection structure, ESD protection circuit, chip

Abstract

This disclosure relates to the field of semiconductor technology, and proposes an electrostatic discharge (ESD) protection circuit and structure, and a chip. The ESD protection structure includes a semiconductor substrate, a first N-type well, a second N-type well, and a first P-type well located within the semiconductor substrate, and a first P-type doped portion, a first N-type doped portion, a second N-type doped portion, a second P-type doped portion, a third N-type doped portion, and a third P-type doped portion and a fourth N-type doped portion located within the first P-type well. The first P-type well is located between the first N-type well and the second N-type well; the third N-type doped portion, the first P-type doped portion, and the fourth N-type doped portion are electrically connected; the second P-type doped portion and the second N-type doped portion are connected to a first signal terminal of the ESD protection structure, and the first N-type doped portion and the third P-type doped portion are connected to a second signal terminal of the ESD protection structure. This structure can achieve bidirectional ESD discharge.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to an electrostatic discharge (ESD) protection structure, an ESD protection circuit, and a chip. Background Technology

[0002] Chips typically require an electrostatic discharge (ESD) protection circuit to discharge static electricity from the chip and prevent damage to the internal circuitry.

[0003] In related technologies, electrostatic discharge protection circuits typically employ a two-diode and clamping circuit architecture. However, the diodes only provide a unidirectional electrostatic discharge path to the power supply and ground terminals. If the electrostatic discharge path through the clamping circuit is too long or the parasitic resistance is too large, excessive voltage will occur at the signal transmission terminal when electrostatic discharge occurs, thereby causing the internal circuitry of the chip to fail.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] According to one aspect of this disclosure, an electrostatic discharge (ESD) protection structure is provided, the ESD protection structure comprising: a semiconductor substrate, a first N-type well, a second N-type well, a first P-type well, a first P-type doped portion, a first N-type doped portion, a second N-type doped portion, a second P-type doped portion, a third N-type doped portion, a third P-type doped portion, and a fourth N-type doped portion. A first N-type well is located within the semiconductor substrate; a second N-type well is located within the semiconductor substrate; a first P-type well is located within the semiconductor substrate and between the first N-type well and the second N-type well; a first P-type doped portion is located within the first P-type well; a first N-type doped portion is located within the first P-type well; a second N-type doped portion is located within the first P-type well and is spaced apart from the first P-type doped portion and the first N-type doped portion; a third N-type doped portion is located within the first N-type well and is spaced apart from the second P-type doped portion; a fourth N-type doped portion is located within the second N-type well and is spaced apart from the third P-type doped portion; wherein the third N-type doped portion, the first P-type doped portion, and the fourth N-type doped portion are electrically connected, the second P-type doped portion and the second N-type doped portion are connected to the first signal terminal of the electrostatic protection structure, and the first N-type doped portion and the third P-type doped portion are connected to the second signal terminal of the electrostatic protection structure.

[0006] In one exemplary embodiment of this disclosure, the electrostatic protection structure further includes: a second P-type well, a third N-type well, a fourth P-type doped portion, a fifth N-type doped portion, a sixth N-type doped portion, a fifth P-type doped portion, a seventh N-type doped portion, and a sixth P-type doped portion. The second P-type well is located within the semiconductor substrate and is situated on the side of the second N-type well away from the first P-type well; the third N-type well is located within the semiconductor substrate and is situated on the side of the second P-type well away from the second N-type well; the fourth P-type doped portion is located within the second P-type well; the fifth N-type doped portion is located within the second P-type well and is spaced apart from the fourth P-type doped portion; the sixth N-type doped portion is located within the second P-type well and is spaced apart from the fourth P-type doped portion and the fifth N-type doped portion; the fifth P-type doped portion is located within the third N-type well; and the seventh N-type doped portion is located within the sixth P-type well. The third N-type doped section is located within the second N-type doped well and is spaced apart from the fifth P-type doped section; the sixth P-type doped section is located within the second N-type doped well and is spaced apart from the fourth N-type doped section and the third P-type doped section; wherein, the third N-type doped section, the first P-type doped section, the fourth N-type doped section, the fourth P-type doped section, and the seventh N-type doped section are electrically connected, the first N-type doped section, the third P-type doped section, the sixth P-type doped section, and the sixth N-type doped section are connected to the second signal terminal of the electrostatic protection structure, and the fifth P-type doped section and the fifth N-type doped section are connected to the third signal terminal of the electrostatic protection structure.

[0007] In one exemplary embodiment of this disclosure, the electrostatic protection structure further includes a ninth diode, the cathode of which is connected to the first P-type doped portion, and the anode of which is connected to the third N-type doped portion and the fourth N-type doped portion.

[0008] In one exemplary embodiment of this disclosure, the electrostatic protection structure further includes: a ninth diode and a tenth diode, wherein the cathode of the ninth diode is connected to the first P-type doped portion, and the anode is connected to the third N-type doped portion, the fourth N-type doped portion, and the seventh N-type doped portion; the cathode of the tenth diode is connected to the fourth P-type doped portion, and the anode is connected to the third N-type doped portion, the fourth N-type doped portion, and the seventh N-type doped portion.

[0009] In one exemplary embodiment of this disclosure, the semiconductor substrate is a P-type semiconductor substrate.

[0010] In one exemplary embodiment of this disclosure, the electrostatic protection structure further includes an N-type deep well, which is located within the semiconductor substrate, wherein the first P-type well, the second P-type well, the first N-type well, the second N-type well, and the third N-type well are all located within the N-type deep well.

[0011] In one exemplary embodiment of this disclosure, the third N-type doped portion, the first P-type doped portion, the fourth N-type doped portion, the fourth P-type doped portion, and the seventh N-type doped portion are electrically connected by wires; the second P-type doped portion and the second N-type doped portion are connected to the first signal terminal of the electrostatic protection structure by conductive lines; the first N-type doped portion, the third P-type doped portion, the sixth P-type doped portion, and the sixth N-type doped portion are connected to the second signal terminal of the electrostatic protection structure by conductive lines; and the fifth P-type doped portion and the fifth N-type doped portion are connected to the third signal terminal of the electrostatic protection structure by conductive lines.

[0012] According to one aspect of this disclosure, an electrostatic discharge (ESD) protection circuit is provided, comprising: a first signal terminal, a second signal terminal, a first PNP transistor, a first NPN transistor, a first diode, a second diode, a second PNP transistor, a second NPN transistor, a third diode, and a fourth diode. The emitter of the first PNP transistor is connected to the first signal terminal, its base is connected to a first node, and its collector is connected to a second node; the collector of the first NPN transistor is connected to the first node, its base is connected to the second node, and its emitter is connected to the second signal terminal; the anode of the first diode is connected to the first signal terminal, and its cathode is connected to the first node; the anode of the second diode is connected to the second node, and its cathode is connected to the second signal terminal; the emitter of the second PNP transistor is connected to the second signal terminal, its base is connected to the first node, and its collector is connected to the second node; the collector of the second NPN transistor is connected to the first node, its base is connected to the second node, and its emitter is connected to the first signal terminal; the anode of the third diode is connected to the second signal terminal, and its cathode is connected to the first node; the anode of the fourth diode is connected to the second node, and its cathode is connected to the first signal terminal; wherein the first node and the second node are connected.

[0013] In one exemplary embodiment of this disclosure, the electrostatic discharge protection circuit includes: a third signal terminal, a fourth PNP transistor, a fourth NPN transistor, a seventh diode, an eighth diode, a third PNP transistor, a third NPN transistor, a fifth diode, and a sixth diode. The emitter of the third PNP transistor is connected to the second signal terminal, its base is connected to a first node, and its collector is connected to the third node; the collector of the third NPN transistor is connected to the first node, its base is connected to the third node, and its emitter is connected to the third signal terminal; the anode of the fifth diode is connected to the second signal terminal, and its cathode is connected to the first node; the anode of the sixth diode is connected to the third node, and its cathode is connected to the third signal terminal; the emitter of the fourth PNP transistor is connected to the third signal terminal, its base is connected to the first node, and its collector is connected to the third node; the collector of the fourth NPN transistor is connected to the first node, its base is connected to the third node, and its emitter is connected to the second signal terminal; the anode of the seventh diode is connected to the third signal terminal, and its cathode is connected to the first node; the anode of the eighth diode is connected to the third node, and its cathode is connected to the second signal terminal. The first node is connected to the third node.

[0014] In one exemplary embodiment of this disclosure, the electrostatic protection circuit further includes a ninth diode, the anode of which is connected to the first node and the cathode of which is connected to the second node.

[0015] In one exemplary embodiment of this disclosure, the electrostatic protection circuit further includes a ninth diode and a tenth diode, wherein the anode of the ninth diode is connected to the first node and the cathode is connected to the second node; the anode of the tenth diode is connected to the first node and the cathode is connected to the third node.

[0016] According to one aspect of this disclosure, a chip is provided that includes the electrostatic discharge protection structure described above.

[0017] In one exemplary embodiment of this disclosure, the chip includes a high-level power supply terminal, a low-level power supply terminal, and a signal transmission terminal; the first signal terminal of the electrostatic protection structure is connected to the low-level power supply terminal, the second signal terminal of the electrostatic protection structure is connected to the signal transmission terminal, and the third signal terminal of the electrostatic protection structure is connected to the high-level power supply terminal.

[0018] According to one aspect of this disclosure, a chip is provided that includes the electrostatic discharge protection circuit described above.

[0019] In one exemplary embodiment of this disclosure, the chip includes a high-level power supply terminal, a low-level power supply terminal, and a signal transmission terminal; the first signal terminal of the electrostatic discharge (ESD) protection circuit is connected to the low-level power supply terminal, the second signal terminal of the ESD protection circuit is connected to the signal transmission terminal, and the third signal terminal of the ESD protection circuit is connected to the high-level power supply terminal.

[0020] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0021] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0022] Figure 1 This is a schematic diagram of an exemplary embodiment of the electrostatic discharge protection circuit disclosed herein;

[0023] Figure 2 This is a schematic diagram of another exemplary embodiment of the electrostatic discharge protection circuit disclosed herein;

[0024] Figure 3 This is a schematic diagram of another exemplary embodiment of the electrostatic discharge protection circuit disclosed herein;

[0025] Figure 4 This is a schematic diagram of another exemplary embodiment of the electrostatic discharge protection circuit disclosed herein;

[0026] Figure 5 This is a top view of an exemplary embodiment of the electrostatic protection structure disclosed herein;

[0027] Figure 6 for Figure 5 The electrostatic protection structure shown is a cross-sectional view along the dashed line AA.

[0028] Figure 7 A top view of another exemplary embodiment of the electrostatic protection structure disclosed herein;

[0029] Figure 8 for Figure 7 The electrostatic protection structure shown is a cross-sectional view along the dashed line AA.

[0030] Figure 9 A top view of another exemplary embodiment of the electrostatic protection structure disclosed herein;

[0031] Figure 10 for Figure 9The electrostatic protection structure shown is a cross-sectional view along the dashed line AA.

[0032] Figure 11 A top view of another exemplary embodiment of the electrostatic protection structure disclosed herein;

[0033] Figure 12 for Figure 11 The electrostatic protection structure shown is a cross-sectional view along the dashed line AA.

[0034] Figure 13 A top view of another exemplary embodiment of the electrostatic protection structure disclosed herein;

[0035] Figure 14 for Figure 13 The electrostatic protection structure shown is a cross-sectional view along the dashed line AA.

[0036] Figure 15 This is a schematic diagram of the structure of an exemplary embodiment of the present chip. Detailed Implementation

[0037] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0038] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the icon's arrangement is flipped so that it is upside down, the component described as "up" will become the component described as "down." Other relative terms such as "high," "low," "top," "bottom," "left," and "right" also have similar meanings. When a structure is "up" of another structure, it may mean that the structure is integrally located on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0039] The terms “a,” “one,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended meaning of inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0040] This exemplary embodiment first provides an electrostatic discharge protection circuit, such as Figure 1The diagram shown is a schematic representation of an exemplary embodiment of the electrostatic discharge (ESD) protection circuit of this disclosure. The ESD protection circuit may include: a first signal terminal V1, a second signal terminal V2, a first PNP transistor QN1, a first NPN transistor QP1, a first diode D1, a second diode D2, a second PNP transistor QN2, a second NPN transistor QP2, a third diode D3, and a fourth diode D4. The emitter of the first PNP transistor QN1 is connected to the first signal terminal V1, the base is connected to the first node N1, and the collector is connected to the second node N2; the collector of the first NPN transistor QP1 is connected to the first node N1, the base is connected to the second node N2, and the emitter is connected to the second signal terminal V2; the anode of the first diode D1 is connected to the first signal terminal V1, and the cathode is connected to the first node N1; the anode of the second diode D2 is connected to the second node N2, and the cathode is connected to the second signal terminal V2; the emitter of the second PNP transistor QN2 is connected to the second signal terminal V2, the base is connected to the first node N1, and the collector is connected to the second node N2; the collector of the second NPN transistor QP2 is connected to the first node N1, the base is connected to the second node N2, and the emitter is connected to the first signal terminal V1; the anode of the third diode D3 is connected to the second signal terminal V2, and the cathode is connected to the first node N1; the anode of the fourth diode D4 is connected to the second node N2, and the cathode is connected to the first signal terminal V1. The first node N1 and the second node N2 are connected together.

[0041] In this exemplary embodiment, when static electricity exists on the first signal terminal V1 and the potential difference between the first signal terminal V1 and the second signal terminal V2 is greater than a threshold, the first diode D1 and the second diode D2 can be turned on first. Due to the voltage drop of the first diode D1, a potential difference is generated between the first signal terminal V1 and the first node N1. Under the influence of this potential difference, the first PNP transistor QN1 is turned on. Simultaneously, due to the voltage drop of the second diode D2, a potential difference is generated between the second node N2 and the second signal terminal V2. Under the influence of this potential difference, the first NPN transistor QP1 is turned on. The turned-on first PNP transistor QN1 and first NPN transistor QP1 form a positive feedback circuit, thereby enabling the electrostatic discharge protection circuit to quickly release the static electricity on the first signal terminal V1 to the second signal terminal V2. Similarly, when static electricity exists on the second signal terminal V2, and the potential difference between the second signal terminal V2 and the first signal terminal V1 is greater than the threshold, the third diode D3 and the fourth diode D4 can conduct first. Due to the voltage drop of the third diode D3, a potential difference will be generated between the second signal terminal V2 and the first node N1. Under the influence of this potential difference, the second PNP transistor QN2 conducts. Simultaneously, due to the voltage drop of the fourth diode D4, a potential difference will be generated between the second node N2 and the first signal terminal V1. Under the influence of this potential difference, the second NPN transistor QP2 conducts. The conducting second PNP transistor QN2 and the second NPN transistor QP2 form a positive feedback circuit, thus enabling the electrostatic discharge protection circuit to quickly release the static electricity on the second signal terminal V2 to the first signal terminal V1. On the one hand, the electrostatic discharge protection circuit provided in this exemplary embodiment can realize bidirectional electrostatic discharge of the first signal terminal V1 and the second signal terminal V2; on the other hand, after the diode in the electrostatic discharge protection circuit is turned on first, it can assist in triggering the transistor to turn on to achieve rapid discharge. Since the diode requires a low turn-on voltage, the electrostatic discharge protection circuit also has a small trigger voltage and a fast trigger speed.

[0042] like Figure 2The diagram shown is a structural schematic of another exemplary embodiment of the electrostatic discharge (ESD) protection circuit of this disclosure. The ESD protection circuit may further include: a third signal terminal V3, a fourth PNP transistor QN4, a fourth NPN transistor QP4, a seventh diode D7, an eighth diode D8, a third PNP transistor QN3, a third NPN transistor QP3, a fifth diode D5, and a sixth diode D6. The emitter of the fourth PNP transistor QN4 is connected to the third signal terminal V3, the base is connected to the first node N1, and the collector is connected to the third node N3; the collector of the fourth NPN transistor QP4 is connected to the first node N1, the base is connected to the third node N3, and the emitter is connected to the second signal terminal V2; the anode of the seventh diode D7 is connected to the third signal terminal V3, and the cathode is connected to the first node N1; the anode of the eighth diode D8 is connected to the third node N3, and the cathode is connected to the second signal terminal V2; the emitter of the third PNP transistor QN3 is connected to the second signal terminal V2, the base is connected to the first node N1, and the collector is connected to the third node N3; the collector of the third NPN transistor QP3 is connected to the first node N1, the base is connected to the third node N3, and the emitter is connected to the third signal terminal V3; the anode of the fifth diode D5 is connected to the second signal terminal V2, and the cathode is connected to the first node N1; the anode of the sixth diode D6 is connected to the third node N3, and the cathode is connected to the third signal terminal V3.

[0043] In this exemplary embodiment, when static electricity exists on the second signal terminal V2 and the potential difference between the second signal terminal V2 and the third signal terminal V3 is greater than a threshold, the fifth diode D5 and the sixth diode D6 can conduct first. Due to the voltage drop of the fifth diode D5, a potential difference is generated between the second signal terminal V2 and the first node N1. Under the influence of this potential difference, the third PNP transistor QN3 conducts. Simultaneously, due to the voltage drop of the sixth diode D6, a potential difference is generated between the third node N3 and the third signal terminal V3. Under the influence of this potential difference, the third NPN transistor QP3 conducts. The conducting third PNP transistor QN3 and the third NPN transistor QP3 form a positive feedback circuit, thereby enabling the electrostatic discharge protection circuit to quickly release the static electricity on the second signal terminal V2 to the third signal terminal V3. Similarly, when static electricity exists on the third signal terminal V3, and the potential difference between the third signal terminal V3 and the second signal terminal V2 is greater than the threshold, the seventh diode D7 and the eighth diode D8 can conduct first. Due to the voltage drop of the seventh diode D7, a potential difference will be generated between the third signal terminal V3 and the first node N1. Under the influence of this potential difference, the fourth PNP transistor QN4 conducts. Simultaneously, due to the voltage drop of the eighth diode D8, a potential difference will be generated between the third node N3 and the second signal terminal V2. Under the influence of this potential difference, the fourth NPN transistor QP4 conducts. The conducting fourth PNP transistor QN4 and fourth NPN transistor QP4 form a positive feedback circuit, thus enabling the electrostatic discharge protection circuit to quickly release the static electricity on the third signal terminal V3 to the second signal terminal V2. On the one hand, the electrostatic discharge protection circuit provided in this exemplary embodiment can realize bidirectional electrostatic discharge of the third signal terminal V3 and the second signal terminal V2; on the other hand, after the diode in the electrostatic discharge protection circuit is turned on first, it can assist in triggering the transistor to turn on to achieve rapid discharge. Since the diode requires a low turn-on voltage, the electrostatic discharge protection circuit also has a small trigger voltage.

[0044] like Figure 3 The diagram shown is a structural schematic of another exemplary embodiment of the electrostatic discharge (ESD) protection circuit of this disclosure. The ESD protection circuit provided in this exemplary embodiment is similar to... Figure 1 Compared to the electrostatic protection circuit shown, Figure 3 The electrostatic discharge (ESD) protection circuit shown may further include: a ninth diode D9, with its anode connected to the first node N1 and its cathode connected to the second node N2. The ninth diode D9, along with the first diode D1 and the second diode D2, are connected in series between the first signal terminal V1 and the second signal terminal V2. The ninth diode D9, along with the third diode D3 and the fourth diode D4, are also connected in series between the first signal terminal V1 and the second signal terminal V2. Compared to... Figure 1 The electrostatic discharge protection circuit shown has the following characteristics: Figure 3 The electrostatic discharge (ESD) protection circuit shown includes a ninth diode, D9. A higher voltage is required between the first signal terminal V1 and the second signal terminal V2 to conduct the ninth diode D9, the first diode D1, and the second diode D2, or to conduct the ninth diode D9, the third diode D3, and the fourth diode D4. Therefore, this ESD protection circuit can have a higher trigger voltage and a higher sustaining voltage. Simultaneously, the ninth diode D9 can also reduce the leakage current between the first signal terminal V1 and the second signal terminal V2.

[0045] like Figure 4 The diagram shown is a structural schematic of another exemplary embodiment of the electrostatic discharge (ESD) protection circuit of this disclosure. The ESD protection circuit provided in this exemplary embodiment is similar to... Figure 2 Compared to the electrostatic discharge (ESD) protection circuit shown, the ESD protection circuit provided in this exemplary embodiment may further include: a ninth diode D9 and a tenth diode D10, wherein the anode of the ninth diode D9 is connected to the first node N1 and the cathode is connected to the second node; the anode of the tenth diode D10 is connected to the first node N1 and the cathode is connected to the third node. Similarly, Figure 4 The electrostatic protection circuit shown is compared to Figure 2 The electrostatic discharge protection circuit shown can have a larger trigger voltage and a larger sustaining voltage. At the same time, there can be a smaller leakage current between the first signal terminal V1 and the second signal terminal V2, and there can be a smaller leakage current between the second signal terminal V2 and the third signal terminal V3.

[0046] This exemplary embodiment also provides an electrostatic protection structure, such as Figure 5 , 6 As shown, Figure 5 This is a top view of an exemplary embodiment of the electrostatic protection structure disclosed herein. Figure 6 for Figure 5The diagram shows a cross-sectional view of the electrostatic discharge (ESD) protection structure along the dashed line AA. The ESD protection structure may include: a semiconductor substrate Sub, a first N-type well NW1, a second N-type well NW2, a first P-type well PW1, a first P-type doped portion P1, a first N-type doped portion N1, a second N-type doped portion N2, a second P-type doped portion P2, a third N-type doped portion N3, a third P-type doped portion P3, and a fourth N-type doped portion N4. A first N-type well NW1 is located within the semiconductor substrate Sub; a second N-type well NW2 is located within the semiconductor substrate Sub; a first P-type well PW1 is located within the semiconductor substrate Sub, and is situated between the first N-type well NW1 and the second N-type well NW2; a first P-type doped portion P1 is located within the first P-type well PW1; a first N-type doped portion N1 is located within the first P-type well PW1; a second N-type doped portion N2 is located within the first P-type well PW1, and is situated on the side of the first P-type doped portion P1 furthest from the first N-type doped portion N1; a second P-type doped portion P2 is located within the first N-type well NW1; a third N-type doped portion N3 is located within the first P-type well NW1. The third P-type doped part P3 is located within the second N-type well NW1 and on the side of the second P-type doped part P2 away from the first P-type well PW1; the fourth N-type doped part N4 is located within the second N-type well NW2 and on the side of the third P-type doped part P3 away from the first P-type well PW1; wherein the third N-type doped part N3, the first P-type doped part P1, and the fourth N-type doped part N4 are electrically connected, the second P-type doped part P2 and the second N-type doped part N2 are connected to the first signal terminal V1 of the electrostatic protection structure, and the first N-type doped part N1 and the third P-type doped part P3 are connected to the second signal terminal V2 of the electrostatic protection structure.

[0047] In this exemplary embodiment, the doping concentration of the doped wells (e.g., the first P-type well, the first N-type well, and the second N-type well) can be less than the doping concentration of the doped portions (e.g., the first P-type doped portion P1, the first N-type doped portion N1, the second N-type doped portion N2, the second P-type doped portion P2, the third N-type doped portion N3, the third P-type doped portion P3, and the fourth N-type doped portion N4). The semiconductor substrate can be a P-type semiconductor substrate. It should be understood that in other exemplary embodiments, the semiconductor substrate can be an N-type semiconductor substrate. The third N-type doped portion N3, the first P-type doped portion P1, and the fourth N-type doped portion N4 can be connected by conductive lines, the second P-type doped portion P2 and the second N-type doped portion N2 can be connected to the first signal terminal V1 of the electrostatic protection structure by conductive lines, and the first N-type doped portion N1 and the third P-type doped portion P3 can be connected to the second signal terminal V2 of the electrostatic protection structure by conductive lines.

[0048] Figure 5 The electrostatic protection structure shown can be formed Figure 1The electrostatic discharge (ESD) protection circuit is shown. The second P-type doped portion P2 forms the emitter of the first PNP transistor QN1, the first N-type well NW1 forms the base of the first PNP transistor QN1, and the first P-type well PW1 forms the collector of the first PNP transistor QN1. The first N-type doped portion N1 forms the emitter of the first NPN transistor QP1, the first P-type well PW1 forms the base of the first NPN transistor QP1, and the first N-type well NW1 forms the collector of the first NPN transistor QP1. The second P-type doped portion P2 forms the anode of the first diode D1, and the third N-type doped portion N3 forms the cathode of the first diode D1. The first P-type doped portion P1 forms the anode of the second diode D2, and the first N-type doped portion N1 forms the cathode of the second diode D2. The third P-type doped portion P3 forms the emitter of the second PNP transistor QN2, the second N-type well NW2 forms the base of the second PNP transistor QN2, and the first P-type well PW1 forms the collector of the second PNP transistor QN2. The second N-type doped portion N2 forms the emitter of the second NPN transistor QP2, the first P-type well PW1 forms the base of the second NPN transistor QP2, and the second N-type well NW2 forms the collector of the second NPN transistor QP2. The third P-type doped portion P3 forms the anode of the third diode D3, and the fourth N-type doped portion N4 forms the cathode of the third diode D3. The first P-type doped portion P1 forms the anode of the fourth diode D4, and the second N-type doped portion N2 forms the cathode of the fourth diode D4.

[0049] In this exemplary embodiment, the first P-type doped portion in the electrostatic discharge (ESD) protection structure can be reused as the anode of the second diode D2 and the fourth diode D2, the first P-type well PW1 can be reused as the collector of the first PNP transistor QN1 and the collector of the second PNP transistor QN2, and can also be reused as the base of the first NPN transistor QP1 and the base of the second NPN transistor QP2. Therefore, this ESD protection structure can have a smaller layout area.

[0050] like Figure 6 As shown, the first N-type well NW1 can also have its own resistance R1, the first P-type well PW1 can also have its own resistances R2 and R3, and the second N-type well NW2 can also have its own resistance R4.

[0051] like Figure 7 , 8 As shown, Figure 7 This is a top view of another exemplary embodiment of the electrostatic protection structure disclosed herein. Figure 8 for Figure 7 The diagram shows a cross-sectional view of the electrostatic protection structure along the dashed line AA. Figure 7The electrostatic protection structure shown can be formed Figure 3 The electrostatic discharge protection circuit shown is an example of this. Figure 7 The electrostatic protection structure shown is compared to Figure 5 The electrostatic discharge (ESD) protection structure shown includes a ninth diode, D9. The cathode of the ninth diode D9 is connected to the first P-type doped portion P1, and the anode is connected to the third N-type doped portion N3 and the fourth N-type doped portion N4. The function of the ninth diode D9 has been explained in detail above and will not be repeated here.

[0052] like Figure 9 , 10 As shown, Figure 9 This is a top view of another exemplary embodiment of the electrostatic protection structure disclosed herein. Figure 10 for Figure 9 The diagram shows a cross-sectional view of the electrostatic protection structure along the dashed line AA. The electrostatic protection structure may further include: a second P-type well PW2, a third N-type well NW3, a fourth P-type doped portion P4, a fifth N-type doped portion N5, a sixth N-type doped portion N6, a fifth P-type doped portion P5, a seventh N-type doped portion N7, and a sixth P-type doped portion P6. The second P-type well PW2 is located within the semiconductor substrate Sub, and is located on the side of the second N-type well NW2 away from the first P-type well PW1; the third N-type well NW3 is located within the semiconductor substrate Sub, and is located on the side of the second P-type well PW2 away from the second N-type well NW2; the fourth P-type doped portion P4 is located within the second P-type well PW2; the fifth N-type doped portion N5 is located within the second P-type well PW2, and is located on the side of the fourth P-type doped portion P4 facing the second N-type well NW2; the sixth N-type doped portion N6 is located within the second P-type well PW2, and is located on the side of the fourth P-type doped portion P4 away from the second N-type well NW2; the fifth P-type doped portion P5 is located within the third N-type well NW3; the seventh N-type doped portion... Part N7 is located within the third N-type well NW3 and on the side of the fifth P-type doped part P5 away from the second P-type well PW2; the sixth P-type doped part P6 is located within the second N-type doped well and on the side of the fourth N-type doped part N4 away from the third P-type doped part P3; wherein, the third N-type doped part N3, the first P-type doped part P1, the fourth N-type doped part N4, the fourth P-type doped part P4, and the seventh N-type doped part N7 are electrically connected, the first N-type doped part N1, the third P-type doped part P3, the sixth P-type doped part P6, and the sixth N-type doped part N6 are connected to the second signal terminal V2 of the electrostatic protection structure, and the fifth P-type doped part P5 and the fifth N-type doped part N5 are connected to the third signal terminal V3 of the electrostatic protection structure.

[0053] Figure 9 The electrostatic protection structure shown can be formed Figure 2The electrostatic discharge (ESD) protection circuit is shown. Among them, as shown... Figure 10 As shown, the sixth P-type doped portion P6 forms the emitter of the third PNP transistor QN3, the second N-type well NW2 forms the base of the third PNP transistor QN3, and the second P-type well PW2 forms the collector of the third PNP transistor QN3. The fifth N-type doped portion N5 forms the emitter of the third NPN transistor QP3, the second P-type well PW2 forms the base of the third NPN transistor QP3, and the second N-type well NW2 forms the collector of the third NPN transistor QP3. The sixth P-type doped portion P6 forms the anode of the fifth diode D5, and the fourth N-type doped portion N4 forms the cathode of the fifth diode D5. The fourth P-type doped portion P4 forms the anode of the sixth diode D6, and the fifth N-type doped portion N5 forms the cathode of the sixth diode D6. The fifth P-type doped portion P5 forms the emitter of the fourth PNP transistor QN4, the third N-type well NW3 forms the base of the fourth PNP transistor QN4, and the second P-type well PW2 forms the collector of the fourth PNP transistor QN4. The sixth N-type doped portion N6 forms the emitter of the fourth NPN transistor QP4, the second P-type well PW2 forms the base of the fourth NPN transistor QP4, and the third N-type well NW3 forms the collector of the fourth NPN transistor QP4. The fifth P-type doped portion P5 forms the anode of the seventh diode D7, and the seventh N-type doped portion N7 forms the cathode of the seventh diode D7. The fourth P-type doped portion P4 forms the anode of the eighth diode D8, and the sixth N-type doped portion N6 forms the cathode of the eighth diode D8.

[0054] In this exemplary embodiment, the fourth P-type doped portion in the electrostatic discharge (ESD) protection structure can be reused as the anode of the sixth diode D6 and the eighth diode D8; the second P-type well PW2 can be reused as the collector of the third PNP transistor QN3 and the fourth PNP transistor QN4, and also as the base of the third NPN transistor QP3 and the fourth NPN transistor QP4. The fourth N-type doped portion N4 is also reused as the cathode of the third diode D3 and the fifth diode D5. Therefore, this ESD protection structure can have a smaller layout area.

[0055] like Figure 10As shown, the second N-type well NW2 may also have its own resistance R5, the second P-type well PW2 may have its own resistances R6 and R7, and the third N-type well NW3 may have its own resistance R8. In this exemplary embodiment, the third N-type doped part N3, the first P-type doped part P1, the fourth N-type doped part N4, the fourth P-type doped part P4, and the seventh N-type doped part N7 can be electrically connected by wires; the second P-type doped part P2 and the second N-type doped part N2 are connected to the first signal terminal V1 of the electrostatic protection structure by conductive lines; the first N-type doped part N1, the third P-type doped part P3, the sixth P-type doped part P6, and the sixth N-type doped part N6 can be connected to the second signal terminal V2 of the electrostatic protection structure by conductive lines; the fifth P-type doped part P5 and the fifth N-type doped part N5 can be connected to the third signal terminal V3 of the electrostatic protection structure by conductive lines.

[0056] like Figure 11 , 12 As shown, Figure 11 This is a top view of another exemplary embodiment of the electrostatic protection structure disclosed herein. Figure 12 for Figure 11 The diagram shows a cross-sectional view of the electrostatic protection structure along the dashed line AA. Figure 11 The electrostatic protection structure shown can be formed Figure 4 The electrostatic discharge protection circuit shown is an example of this. Figure 11 The electrostatic protection structure shown is compared to Figure 9 The electrostatic discharge (ESD) protection structure shown includes a ninth diode, D9, and a tenth diode, D10. The cathode of the ninth diode, D9, is connected to the first P-type doped portion, P1, and the anode is connected to the third N-type doped portion, N3, the fourth N-type doped portion, N4, and the seventh N-type doped portion, N7. The cathode of the tenth diode, D10, is connected to the fourth P-type doped portion, P4, and the anode is connected to the third N-type doped portion, N3, the fourth N-type doped portion, N4, and the seventh N-type doped portion, N7. The functions of the ninth diode, D9, and the tenth diode, D10, have been explained in detail above and will not be repeated here.

[0057] like Figure 13 , 14 As shown, Figure 13 This is a top view of another exemplary embodiment of the electrostatic protection structure disclosed herein. Figure 14 for Figure 13 The diagram shows a cross-sectional view of the electrostatic protection structure along the dashed line AA. Figure 13 The electrostatic protection structure shown is compared to Figure 11 The electrostatic protection structure shown is as follows. Figure 13The electrostatic discharge (ESD) protection structure also includes an N-type deep well (DNW) located within the semiconductor substrate Sub. The first P-type well PW1, the second P-type well PW2, the first N-type well NW1, the second N-type well NW2, and the third N-type well NW3 are all located within the N-type deep well (DNW). The N-type deep well (DNW) provides noise shielding for the components in the ESD protection structure and prevents leakage current from these components to the P-type semiconductor substrate.

[0058] It should be noted that, in this exemplary embodiment, the doped portions located in the same doped well can be arranged at intervals with any relative positional relationship.

[0059] This exemplary embodiment also provides a chip that includes the above-described electrostatic discharge (ESD) protection junction circuit. For example... Figure 15 The diagram shown is a structural schematic of an exemplary embodiment of the present chip. The chip includes a high-level power supply terminal VDD, a low-level power supply terminal VSS, a signal transmission terminal I / O, and internal circuitry 2. The first signal terminal V1 of the electrostatic discharge (ESD) protection circuit 3 is connected to the low-level power supply terminal VSS, the second signal terminal V2 of the ESD protection circuit 3 is connected to the signal transmission terminal I / O, and the third signal terminal V3 of the ESD protection circuit 3 is connected to the high-level power supply terminal VDD. This chip can be any chip, such as a memory chip. The signal transmission terminal can be a signal input terminal or a signal output terminal.

[0060] This exemplary embodiment also provides a chip including the electrostatic discharge (ESD) protection structure described above. The chip includes a high-level power supply terminal, a low-level power supply terminal, and a signal transmission terminal; a first signal terminal of the ESD protection structure is connected to the low-level power supply terminal, a second signal terminal of the ESD protection structure is connected to the signal transmission terminal, and a third signal terminal of the ESD protection structure is connected to the high-level power supply terminal.

[0061] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the generality of this disclosure and include, but are not disclosed herein, common knowledge or customary techniques in the art. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0062] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.

Claims

1. An electrostatic protection structure, characterized in that, The electrostatic protection structure includes: Semiconductor substrate; A first N-type well is located within the semiconductor substrate; A second N-type well is located within the semiconductor substrate; The first P-type well is located within the semiconductor substrate and between the first N-type well and the second N-type well; The first P-type doped portion is located within the first P-type well; The first N-type doped portion is located within the first P-type well; The second N-type doped portion is located inside the first P-type well and is spaced apart from the first P-type doped portion and the first N-type doped portion; The second P-type doped portion is located within the first N-type well; The third N-type doped portion is located within the first N-type well and is spaced apart from the second P-type doped portion; The third P-type doped portion is located within the second N-type well; The fourth N-type doped portion is located within the second N-type well and is spaced apart from the third P-type doped portion; The third N-type doped portion, the first P-type doped portion, and the fourth N-type doped portion are electrically connected; the second P-type doped portion and the second N-type doped portion are connected to the first signal terminal of the electrostatic protection structure; and the first N-type doped portion and the third P-type doped portion are connected to the second signal terminal of the electrostatic protection structure.

2. The electrostatic protection structure according to claim 1, characterized in that, The electrostatic protection structure also includes: The second P-type well is located within the semiconductor substrate and on the side of the second N-type well away from the first P-type well; The third N-type well is located within the semiconductor substrate and on the side of the second P-type well away from the second N-type well; The fourth P-type doped portion is located within the second P-type well; The fifth N-type doped section is located within the second P-type well and is spaced apart from the fourth P-type doped section; The sixth N-type doped section is located within the second P-type well and is spaced apart from the fourth P-type doped section and the fifth N-type doped section; The fifth P-type doped region is located within the third N-type well; The seventh N-type doped section is located within the third N-type well and is spaced apart from the fifth P-type doped section; The sixth P-type doped portion is located within the second N-type well and is spaced apart from the fourth N-type doped portion and the third P-type doped portion; The third N-type doped portion, the first P-type doped portion, the fourth N-type doped portion, the fourth P-type doped portion, and the seventh N-type doped portion are electrically connected. The first N-type doped portion, the third P-type doped portion, the sixth P-type doped portion, and the sixth N-type doped portion are connected to the second signal terminal of the electrostatic protection structure. The fifth P-type doped portion and the fifth N-type doped portion are connected to the third signal terminal of the electrostatic protection structure.

3. The electrostatic protection structure according to claim 1, characterized in that, The electrostatic protection structure also includes: The ninth diode has its cathode connected to the first P-type doped section and its anode connected to the third and fourth N-type doped sections.

4. The electrostatic protection structure according to claim 2, characterized in that, The electrostatic protection structure also includes: The ninth diode has its cathode connected to the first P-type doped section and its anode connected to the third, fourth, and seventh N-type doped sections. The tenth diode has its cathode connected to the fourth P-type doped section and its anode connected to the third N-type doped section, the fourth N-type doped section, and the seventh N-type doped section.

5. The electrostatic protection structure according to claim 2, characterized in that, The semiconductor substrate is a P-type semiconductor substrate.

6. The electrostatic protection structure according to claim 5, characterized in that, The electrostatic protection structure also includes: An N-type deep well is located within the semiconductor substrate, and the first P-type well, the second P-type well, the first N-type well, the second N-type well, and the third N-type well are all located within the N-type deep well.

7. The electrostatic protection structure according to claim 2, characterized in that, The third N-type doped region, the first P-type doped region, the fourth N-type doped region, the fourth P-type doped region, and the seventh N-type doped region are electrically connected by wires. The second P-type doped portion and the second N-type doped portion are connected to the first signal terminal of the electrostatic protection structure via conductive lines; The first N-type doped portion, the third P-type doped portion, the sixth P-type doped portion, and the sixth N-type doped portion are connected to the second signal terminal of the electrostatic protection structure via conductive lines; The fifth P-type doped part and the fifth N-type doped part are connected to the third signal terminal of the electrostatic protection structure via conductive lines.

8. An electrostatic discharge protection circuit, characterized in that, The electrostatic protection circuit includes: First signal terminal; Second signal terminal; The first PNP transistor has its emitter connected to the first signal terminal, its base connected to the first node, and its collector connected to the second node. The first NPN transistor has its collector connected to the first node, its base connected to the second node, and its emitter connected to the second signal terminal. The first diode has its anode connected to the first signal terminal and its cathode connected to the first node. The second diode has its anode connected to the second node and its cathode connected to the second signal terminal. The second PNP transistor has its emitter connected to the second signal terminal, its base connected to the first node, and its collector connected to the second node. The second NPN transistor has its collector connected to the first node, its base connected to the second node, and its emitter connected to the first signal terminal. The third diode has its anode connected to the second signal terminal and its cathode connected to the first node. The fourth diode has its anode connected to the second node and its cathode connected to the first signal terminal. The first node and the second node are connected.

9. The electrostatic discharge protection circuit according to claim 8, characterized in that, The electrostatic protection circuit also includes: Third signal terminal; The third PNP transistor has its emitter connected to the second signal terminal, its base connected to the first node, and its collector connected to the third node. The third NPN transistor has its collector connected to the first node, its base connected to the third node, and its emitter connected to the third signal terminal. The fifth diode has its anode connected to the second signal terminal and its cathode connected to the first node; The sixth diode has its anode connected to the third node and its cathode connected to the third signal terminal. The fourth PNP transistor has its emitter connected to the third signal terminal, its base connected to the first node, and its collector connected to the third node. The fourth NPN transistor has its collector connected to the first node, its base connected to the third node, and its emitter connected to the second signal terminal. The seventh diode has its anode connected to the third signal terminal and its cathode connected to the first node. The eighth diode has its anode connected to the third node and its cathode connected to the second signal terminal; wherein the first node is connected to the third node.

10. The electrostatic discharge protection circuit according to claim 8, characterized in that, The electrostatic protection circuit also includes: The ninth diode has its anode connected to the first node and its cathode connected to the second node.

11. The electrostatic discharge protection circuit according to claim 9, characterized in that, The electrostatic protection circuit also includes: The ninth diode has its anode connected to the first node and its cathode connected to the second node. The tenth diode has its anode connected to the first node and its cathode connected to the third node.

12. A chip, characterized in that, Includes the electrostatic protection structure as described in any one of claims 1-7.

13. The chip according to claim 12, characterized in that, The chip includes a high-level power supply terminal, a low-level power supply terminal, and a signal transmission terminal; The first signal terminal of the electrostatic protection structure is connected to the low-level power supply terminal, the second signal terminal of the electrostatic protection structure is connected to the signal transmission terminal, and the third signal terminal of the electrostatic protection structure is connected to the high-level power supply terminal.

14. A chip, characterized in that, Includes the electrostatic discharge protection circuit as described in any one of claims 8-11.

15. The chip according to claim 14, characterized in that, The chip includes a high-level power supply terminal, a low-level power supply terminal, and a signal transmission terminal; The first signal terminal of the electrostatic discharge protection circuit is connected to the low-level power supply terminal, the second signal terminal of the electrostatic discharge protection circuit is connected to the signal transmission terminal, and the third signal terminal of the electrostatic discharge protection circuit is connected to the high-level power supply terminal.

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