Semiconductor structure and method of forming the same
By adjusting the height difference of the isolation structure during the fabrication of non-volatile memory and using an etching process to remove excess sidewall material, the problem of slow device speed was solved, and product yield and device performance were improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SEMICON MFG INT (SHANGHAI) CORP
- Filing Date
- 2021-01-07
- Publication Date
- 2026-07-21
AI Technical Summary
During the fabrication of non-volatile memory, the top surface of the isolation structure of the logic region is higher than the surface of the semiconductor substrate, making it difficult to remove the sidewall material formed after floating gate etching, which affects device speed and product yield.
By forming a specific height difference of the isolation structure on the semiconductor substrate, the height difference between the top surface of the isolation structure and the surface of the semiconductor substrate is ensured to be in the range of -400 angstroms to 400 angstroms. Excess sidewall material is removed by dry or wet etching process to form offset sidewalls to improve the thickness uniformity of the logic region gate structure.
It significantly improves device operating speed and product yield, reduces residual material on logic area sidewalls, and increases the coverage area of active regions.
Smart Images
Figure CN114743977B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology
[0002] Non-volatile memory (NVM) has been widely used in personal computers and electronic devices because it allows for multiple data storage, retrieval, and erasure operations, and the stored data will not be lost after power is turned off. However, there are still many problems in the manufacturing process of non-volatile memory, resulting in a low yield.
[0003] Because the top surface of the isolation structure in the logic region is higher than the surface of the semiconductor substrate, there is a significant step height between the isolation structure and the semiconductor substrate. After polyetching, when sidewalls are formed on both sides of the control gate in the flash memory region, sidewall material is also deposited on the surface of the isolation structure in the logic region and at the step height. The sidewall material at the step height is difficult to etch. When the gate structure is formed in the logic region, the residual sidewall material at the step height reduces the effective width of the active region, resulting in slower device speeds and lower product yield. Summary of the Invention
[0004] The technical problem addressed by this application is the slow device speed and low product yield.
[0005] To address the aforementioned technical problems, this application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, the semiconductor substrate including a first region and a second region, wherein a floating gate dielectric layer and a floating gate layer are sequentially formed on the surfaces of the semiconductor substrate in the first region and the second region, wherein an isolation structure is formed in the semiconductor substrate, the floating gate dielectric layer, and the floating gate layer in the first region, and a discrete control gate structure is formed on the surface of the floating gate layer in the second region; forming a first sidewall on the sidewall of the control gate structure, and forming dielectric layers on the surfaces of the floating gate layers on both sides of the first sidewall and on the surfaces of the floating gate layer and the isolation structure in the first region; removing a portion of the corresponding first sidewall and the dielectric layer on the side where the corresponding first sidewall is located, forming an offset sidewall on the sidewall of the control gate structure; removing the dielectric layer and a portion of the isolation structure in the first region and the remaining dielectric layer in the second region, such that there is a specific height difference between the top surface of the isolation structure and the surface of the semiconductor substrate.
[0006] In some embodiments of this application, the specific height difference is -400 angstroms to 400 angstroms.
[0007] In some embodiments of this application, the process of forming the first sidewall and the dielectric layer includes: sequentially forming a first sidewall material layer and a second sidewall material layer on the surface of the floating gate layer and the isolation structure in the first region and the second region, as well as on the surface and sidewall of the control gate structure; etching the second sidewall material layer so that the remaining second sidewall material layer only covers the first sidewall material layer of the control gate structure sidewall; forming a third sidewall material layer on the exposed surface of the first sidewall material layer and the remaining second sidewall material layer; etching the third sidewall material layer so that the remaining third sidewall material layer only covers the second sidewall material layer of the control gate structure sidewall; wherein the first sidewall material layer, the second sidewall material layer and the third sidewall material layer of the control gate structure sidewall constitute the first sidewall, and the exposed first sidewall material layer serves as the dielectric layer.
[0008] In some embodiments of this application, the thickness of the third sidewall material layer is 50 angstroms to 1000 angstroms.
[0009] In some embodiments of this application, after forming the first sidewall and the dielectric layer, a threshold voltage layer is further formed in the semiconductor substrate between the respective first sidewalls. The process of forming the threshold voltage layer includes: forming a mask over the first region and the second region, the mask exposing the respective first sidewall and the surface of the dielectric layer between the respective first sidewalls; and forming the threshold voltage layer using an ion implantation process with the mask as a mask.
[0010] In some embodiments of this application, the process of forming the offset sidewall includes: using the mask as a mask, etching the third sidewall material layer in the corresponding first sidewall to make the thickness of the first sidewalls on both sides of the control gate structure different, forming the offset sidewall, and etching the dielectric layer on the side where the corresponding first sidewall is located.
[0011] In some embodiments of this application, the process for removing the dielectric layer and part of the isolation structure in the first region and the remaining dielectric layer in the second region is a maskless dry etching process or a wet etching process.
[0012] In some embodiments of this application, the method for forming the semiconductor structure further includes: etching the floating gate layers of the first region and the second region, such that the floating gate layer of the second region and the sidewall of the offset sidewall are coplanar.
[0013] In some embodiments of this application, the method for forming the semiconductor structure further includes forming a second sidewall on the sidewalls of the floating gate layer and the offset sidewall.
[0014] In some embodiments of this application, the first region is a logical region and the second region is a flash memory region.
[0015] This application also provides a semiconductor structure, comprising: a semiconductor substrate, the semiconductor substrate including a first region and a second region, wherein a floating gate dielectric layer is formed on the surface of the semiconductor substrate in the first region and the second region; an isolation structure located in the semiconductor substrate and the floating gate dielectric layer in the first region, wherein the height difference between the top surface of the isolation structure and the surface of the semiconductor substrate is greater than 0 angstroms and not more than 400 angstroms; a floating gate layer, discretely located on the surface of the floating gate dielectric layer in the second region; a control gate structure located on the surface of the floating gate layer; and an offset sidewall located on the sidewall of the control gate structure, wherein the offset sidewall and the sidewall of the floating gate layer are coplanar.
[0016] This application also provides another semiconductor structure, comprising: a semiconductor substrate, the semiconductor substrate including a first region and a second region, wherein a floating gate dielectric layer is formed on the surface of the semiconductor substrate in the first region and the second region; an isolation structure located in the semiconductor substrate in the first region, wherein the height difference between the top surface of the isolation structure and the surface of the semiconductor substrate is -400 angstroms to 0 angstroms; a floating gate layer, discretely located on the surface of the floating gate dielectric layer in the second region; a control gate structure located on the surface of the floating gate layer; and an offset sidewall located on the sidewall of the control gate structure, wherein the offset sidewall and the sidewall of the floating gate layer are coplanar.
[0017] In some embodiments of this application, the control gate structure includes a control gate dielectric layer, a control gate layer, and a mask layer stacked sequentially.
[0018] In some embodiments of this application, the semiconductor structure further includes a second sidewall located on the sidewall of the floating gate layer and the offset sidewall.
[0019] The technical solution of this application reduces the height of the isolation structure, so that the height difference between the top surface of the isolation structure and the surface of the semiconductor substrate is within a specific range, specifically, between -400 angstroms and 400 angstroms. This allows subsequent processes to reduce or avoid the residue of sidewall material in the logic region when forming the second sidewall in the flash memory region, improves the thickness uniformity of the gate structure in the logic region, increases the coverage area of the gate structure on the active region, and thus significantly improves the operating speed of the device and greatly improves the product yield. Attached Figure Description
[0020] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale. Wherein:
[0021] Figures 1 to 3 This is a schematic diagram of the structural steps in a method for forming a non-volatile memory.
[0022] Figures 4 to 14 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of this application;
[0023] Figure 15 This is a schematic diagram of another semiconductor structure according to an embodiment of this application. Detailed Implementation
[0024] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.
[0025] refer to Figure 1 A non-volatile memory includes a semiconductor substrate 10, which includes a logic region 11 and a flash memory region 12. A dielectric layer 30 is formed on the surface of the semiconductor substrate 10 of the logic region 11 and the flash memory region 12. Shallow trench isolation structures 20 are formed on the surfaces of the semiconductor substrate 10 and the dielectric layer 30 in the logic region 11. The top surface of the shallow trench isolation structure 20 is significantly higher than the surface of the dielectric layer 30, and the height difference between the top surface of the shallow trench isolation structure 20 and the surface of the semiconductor substrate 10 exceeds 500 angstroms. A plurality of discrete control gate structures 40 are formed on the surface of the dielectric layer 30 of the flash memory region 12.
[0026] refer to Figure 2 Sidewall material 51 is deposited on the surface of the dielectric layer 30, the sidewalls and surfaces of the control gate structure 40, and the sidewalls and surfaces of the shallow trench isolation structure 20 above the dielectric layer 30.
[0027] refer to Figure 3The sidewall material 51 is etched, leaving only the sidewall material of the control gate structure 40 to form the sidewall 52. However, since the top surface of the shallow trench isolation structure 20 is much higher than the surface of the dielectric layer 30, a high step is formed between the shallow trench isolation structure 20 and the dielectric layer 30. The sidewall material 51 located at the high step is difficult to completely remove during the etching process and remains on the sidewall of the high step.
[0028] When the gate structure 60 is formed in the logic region, the residual sidewall material covers part of the surface of the dielectric layer 30, which reduces the coverage area of the gate structure on the active region, making the effective width of the active region smaller and causing the device speed to slow down.
[0029] Based on this, the technical solution of this application reduces the height of the isolation structure, so that the height difference between the top surface of the isolation structure and the surface of the semiconductor substrate is within a reasonable range. After the etching process for forming the sidewalls is completed, the residual material of the logic region sidewalls can be reduced or avoided, thereby maximizing the coverage area of the gate structure on the active region and improving the operating speed of the device.
[0030] The technical solution of this application will be described in detail below with reference to the embodiments and accompanying drawings.
[0031] The method for forming a semiconductor structure according to embodiments of this application includes:
[0032] Step S1, provide a semiconductor substrate, the semiconductor substrate including a first region and a second region, a floating gate dielectric layer and a floating gate layer are sequentially formed on the surface of the semiconductor substrate in the first region and the second region, wherein an isolation structure is formed in the semiconductor substrate, the floating gate dielectric layer and the floating gate layer in the first region, and a discrete control gate structure is formed on the surface of the floating gate layer in the second region.
[0033] Step S2: First sidewalls are formed on both sides of the control gate structure, and dielectric layers are formed on the surface of the floating gate layer on both sides of the first sidewalls and on the surface of the floating gate layer and the isolation structure in the first region.
[0034] Step S3: Remove a portion of the corresponding first sidewall and the dielectric layer on the side where the corresponding first sidewall is located to form an offset sidewall on the sidewall of the control gate structure.
[0035] Step S4: Remove the dielectric layer and part of the isolation structure in the first region and the remaining dielectric layer in the second region, so that there is a specific height difference between the top surface of the isolation structure and the surface of the semiconductor substrate.
[0036] refer to Figure 4A semiconductor substrate 100 is provided. The semiconductor substrate 100 can be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc. As an example, in this embodiment, the semiconductor substrate 100 is made of single-crystal silicon. The semiconductor substrate 100 includes a first region 110 and a second region 120. The first region 110 and the second region 120 have different semiconductor structures depending on the required performance. In this embodiment, the first region 110 serves as a logic region, and the second region 120 serves as a flash memory region.
[0037] A floating gate dielectric layer and a floating gate layer are sequentially formed on the semiconductor substrate surfaces of the first region and the second region. An isolation structure is formed in the semiconductor substrate, the floating gate dielectric layer and the floating gate layer in the first region. A dielectric layer is formed on the surface of the floating gate layer and the isolation structure. A discrete control gate structure is formed on the surface of the dielectric layer in the second region.
[0038] Specifically, please refer to Figure 4 A floating gate dielectric layer 200 and a floating gate layer 300 are sequentially deposited on the surfaces of the semiconductor substrate 100 in the first region 110 and the second region 120. The material of the floating gate dielectric layer 200 may include oxides, such as SiO2, SiON, and other similar oxides including perovskite oxides, which are conventional dielectrics. The material of the floating gate layer 300 may include polycrystalline silicon. The floating gate dielectric layer 200 can be formed by deposition processes such as thermal oxidation, chemical vapor deposition (CVD), or oxynitriding, and the floating gate layer 300 can be formed by processes such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition.
[0039] refer to Figure 5An isolation structure 400 is formed in the semiconductor substrate 100, floating gate dielectric layer 200, and floating gate layer 300 in the first region 110. The isolation structure 400 may be a shallow trench isolation structure. The process of forming the isolation structure 400 may include: coating photoresist on the surface of the floating gate layer 300 in the first region 110 and the second region 120; exposing and developing the photoresist to transfer a predefined pattern onto the photoresist; then etching using the remaining photoresist as a mask, sequentially etching the floating gate layer 300, floating gate dielectric layer 200, and semiconductor substrate 100 not covered by the photoresist to form trenches, the bottom of which is located in the semiconductor substrate 100; next, filling the trenches, depositing an isolation material layer, preferably an oxide layer, within the trenches and on the floating gate layer 300. In some embodiments, an oxide layer is formed in the trench and on the floating gate layer 300 using an HDP (high-density plasma) deposition process. The oxide layer is preferably made of silicon dioxide, and the oxide layer is formed using HDP-CVD (high-density plasma chemical vapor deposition). The isolation material layer is planarized so that its surface is coplanar with the surface of the floating gate layer 300. Specifically, a barrier layer can be formed on the surface of the floating gate layer 300 first, then planarized so that the surface of the isolation material layer is coplanar with the surface of the floating gate layer 300, and the barrier layer is removed by wet etching to form the isolation structure 400.
[0040] The top surface of the isolation structure 400 is higher than the surface of the floating gate dielectric layer 200, and the height difference between the top surface of the isolation structure 400 and the surface of the semiconductor substrate 100 is not less than 500 angstroms. When the height difference is not less than 500 angstroms, after the floating gate layer 300 is removed in a subsequent process, a very high step will be generated between the isolation structure 400 and the floating gate dielectric layer 200. As a result, when the second sidewall is formed, the sidewall of the step will have residual sidewall material, and the residual sidewall material will reduce the effective width of the active region.
[0041] In actual processes, isolation structures are also formed in the semiconductor substrate, floating gate dielectric layer, and floating gate layer of the second region 120. However, when the dielectric layer is removed in subsequent processes, part of the isolation structure of the second region 120 is also removed, which reduces the height of the isolation structure of the second region 120. Therefore, the isolation structure of the second region 120 will not have the problem of reducing the effective width of the active region due to residual sidewall material. Therefore, the embodiments of this application only improve the isolation structure of the first region 110.
[0042] Then, discrete control gate structures are formed on the surface of the floating gate layer 300 in the second region 120.
[0043] refer to Figure 6A control gate dielectric layer 610 and a control gate layer 620 are sequentially formed on the surface of the floating gate layer 300, and the formation process can be a conventional deposition process. The material of the control gate dielectric layer 610 may include at least one of silicon oxide, silicon oxynitride, silicon-rich oxide, and silicon nitride. The thickness of the control gate dielectric layer 610 may be from 10 angstroms to 160 angstroms, and the control gate dielectric layer 610 may be a single-layer structure or a multi-layer structure. For example, the control gate dielectric layer 610 may include an oxide layer, a nitride layer, and an oxide layer (i.e., an ONO structure) stacked sequentially, wherein the thickness of the bottom oxide layer may be 55 angstroms, and the thickness of the middle nitride layer and the top oxide layer may be 50 angstroms. The control gate layer 620 may be formed using a chemical vapor deposition process. The material of the control gate layer 620 may include polysilicon, and the thickness of the control gate layer 620 may be from 500 angstroms to 700 angstroms, for example, 650 angstroms.
[0044] A mask layer is formed on the surface of the control gate layer 620, which serves to protect the control gate layer 620. The mask layer can be a single-layer or multi-layer structure. For example, the mask layer includes a first mask layer 630 located on the surface of the control gate layer 620 and a second mask layer 640 located on the surface of the first mask layer 630. The material of the first mask layer 630 may include tetraethyl orthosilicate (TEOS), and the material of the second mask layer 640 may include silicon nitride. Tetraethyl orthosilicate (TEOS) can buffer the stress between silicon nitride and polysilicon. In other embodiments, other mask materials may also be used.
[0045] refer to Figure 7 A dry etching process is used to etch a portion of the second mask layer 640, the first mask layer 630, the control gate layer 620, and the control gate dielectric layer 610 in the first region 110 and the second region 120, thereby forming a discrete control gate structure 600 on the surface of the floating gate layer 300 in the second region 120. That is, the control gate structure 600 includes the control gate dielectric layer 610, the control gate layer 620, and the mask layers (the first mask layer 630 and the second mask layer 640) stacked sequentially.
[0046] refer to Figure 8A first sidewall 650 is formed on the sidewall of the control gate structure 600. The first sidewall 650 can be a single-layer structure or a multi-layer structure. In this embodiment, the first sidewall 650 is an ONO structure, that is, an oxide layer / nitride layer / oxide layer, such as a silicon oxide / silicon nitride / silicon oxide structure. The process for forming the ONO structure may include: depositing a first sidewall material layer 651 on the surface of the floating gate layer 300 and the isolation structure 400 in the first region 110, the surface of the floating gate layer 300 and the second mask layer 640 in the second region 120, and the sidewalls of the second mask layer 640, the first mask layer 630, the control gate layer 620, and the control gate dielectric layer 610. The first sidewall material layer 651 is, for example, a silicon oxide layer. A second sidewall material layer is formed on the surface of the first sidewall material layer 651. The second sidewall material layer is, for example, a silicon nitride layer. The process for forming the first sidewall material layer 651 and the second sidewall material layer may be a conventional deposition process such as chemical vapor deposition or physical vapor deposition. Then, the second sidewall material layer on the surfaces of the floating gate layer 300 and isolation structure 400 in the first region 110, the floating gate layer 300 in the second region 120, and the second mask layer 640 is etched away. An ON structure is formed on the sidewalls of the second mask layer 640, the first mask layer 630, the control gate layer 620, and the control gate dielectric layer 610, while retaining the first sidewall material layer 651 on the surfaces of the floating gate layer 300 and isolation structure 400 in the first region 110 and the floating gate layer 300 in the second region 120. The first sidewall material layer 651 serves two purposes: firstly, it acts as a barrier layer for ion implantation to prevent tunneling during subsequent ion implantation to form a threshold voltage layer; secondly, it protects the floating gate layer 300 during subsequent etching processes. Then, a third sidewall material layer is formed on the surface of the first sidewall material layer 651 of the first region 110, the surface of the first sidewall material layer 651 of the second region 120, the surface of the second mask layer 640, and the sidewall of the ON structure. The third sidewall material layer is, for example, a silicon oxide layer. Finally, the surface of the first sidewall material layer 651 of the first region 110, the surface of the first sidewall material layer 651 of the second region 120, and the surface of the third sidewall material layer of the second mask layer 640 are etched away, leaving only the first sidewall material layer 651 of the ON structure sidewall. Finally, the first sidewall 650 of the ONO structure is formed on the sidewalls of the second mask layer 640, the first mask layer 630, the control gate layer 620, and the control gate dielectric layer 610. That is, the first sidewall 650 includes the first sidewall material layer 651, the second sidewall material layer, and the third sidewall material layer, while the first sidewall material layer 651 formed on the surface of the floating gate layer 300 on both sides of the first sidewall 650 and the surface of the floating gate layer 300 and the isolation structure 400 of the first region 110 serves as the dielectric layer.
[0047] In this embodiment, the thickness of the third sidewall material layer, the outermost layer of the ONO structure located on the first sidewall 650, is crucial and needs to be determined in conjunction with subsequent processes. The thickness of the third sidewall material layer is preferably 50–1000 angstroms; the specific reasons will be explained in detail in subsequent processes.
[0048] refer to Figure 9 A threshold voltage layer 800 is formed in the semiconductor substrate between the corresponding first sidewalls 650. The specific semiconductor substrates between which the first sidewalls 650 are formed with the threshold voltage layer 800 need to be determined based on the actual situation; the figure is only an example. The process of forming the threshold voltage layer 800 may include: forming a mask 700 above the first region 110 and the second region 120, the mask 700 exposing the region where the threshold voltage layer 800 is to be formed, that is, the mask 700 exposing the corresponding first sidewalls 650 and the surface of the dielectric layer 651 between the corresponding first sidewalls 650. Using the mask 700 as a mask, the threshold voltage layer 800 is formed in the semiconductor substrate 100 by an ion implantation process.
[0049] Next, please refer to Figure 10 The process involves removing a portion of the corresponding first sidewall 650 and the dielectric layer 651 on the side where the corresponding first sidewall 650 is located, thereby forming an offset sidewall 660 on the sidewall of the control gate structure 600. The process of forming the offset sidewall 660 includes: using the mask plate 700 as a mask, etching the third sidewall material layer in the corresponding first sidewall 650 to create a difference in thickness between the first sidewalls 650 on both sides of the control gate structure 600, thus forming the offset sidewall 660; simultaneously, etching the dielectric layer 651 on the side where the corresponding first sidewall 650 is located. The etching process for the third sidewall material layer and the dielectric layer 651 can be a wet etching process. In this embodiment, the etching of the third sidewall material layer, the dielectric layer 651, and the formation of the threshold voltage layer 800 all utilize the same mask plate 700, eliminating one masking process and reducing costs.
[0050] refer to Figure 11 The dielectric layer 651 and part of the isolation structure 400 in the first region 110 and the remaining dielectric layer 651 in the second region 120 are removed, so that there is a specific height difference Δh between the top surface of the isolation structure 400 and the surface of the semiconductor substrate 100. In this embodiment, the mask 700 is removed, and the dielectric layer 651 and the isolation structure 400 are etched using a maskless blank etching method, avoiding the use of a mask layer or photoresist layer and reducing costs. Dry etching or wet etching processes can be used during etching.
[0051] In some embodiments of this application, a dry etching process is used to etch the dielectric layer 651 and the isolation structure 400. This dry etching process includes, but is not limited to, reactive ion etching (RIE), ion beam etching, plasma etching, or laser cutting. If plasma etching is used, the etching gas can be a fluorine-based gas. Specifically, dry etching is achieved using a low-frequency energy plasma gas that generates low pressure and high density. It is important to note that the gas flow rate and time during dry etching must be strictly controlled. As an example, the flow rate of the etching gas used in plasma etching can range from 5 cubic centimeters per minute (sccm) to 150 cubic centimeters per minute (sccm), and the pressure in the reaction chamber can range from 50 millitors (mTorr) to 500 millitors (mTorr). The etching gas used in dry etching can be hydrogen bromide, carbon tetrafluoride, or nitrogen trifluoride, and additional gases such as nitrogen, helium, or oxygen can also be introduced. In some other embodiments of this application, a wet etching process can also be used. The etching solvent for this wet etching process is not specifically required. It should be noted that while wet etching the remaining dielectric layer 651 of the second region 120, a small portion of the third sidewall material layer offset from the sidewall 660 may also be etched. If a wet etching process is used, the thickness of the third sidewall material layer needs to be slightly larger. Therefore, as mentioned above, when forming the third sidewall material layer, it is necessary to increase its thickness, for example, to 50 angstroms to 1000 angstroms.
[0052] When etching the isolation structure 400, special attention needs to be paid to controlling the etching stop position, as this position directly affects the effective width of the active region. In this embodiment, the height difference Δh between the top surface of the isolation structure 400 and the surface of the semiconductor substrate 100 is controlled within a specific range. This ensures that when the second sidewall is etched in subsequent processes, the first region 110 will not have excessive residual sidewall material, effectively mitigating the problem of slower device speeds due to a smaller effective width of the active region. After removing part of the isolation structure 400, the device performance is optimal when the height difference Δh between the top surface of the isolation structure 400 and the surface of the semiconductor substrate 100 is between -400 angstroms and 400 angstroms. In other words, the top surface of the isolation structure 400 can be higher than the surface of the semiconductor substrate 100, and the height difference Δh does not exceed 400 angstroms. For example, the height difference Δh is 20 angstroms, 50 angstroms, 70 angstroms, 80 angstroms, 90 angstroms, 100 angstroms, 200 angstroms, 300 angstroms, 400 angstroms, etc. Or the top surface of the isolation structure 400 can be coplanar with the surface of the semiconductor substrate 100, in which case the height difference Δh is 0. Or the top surface of the isolation structure 400 can be lower than the surface of the semiconductor substrate 100, and the height difference Δh does not exceed 400 angstroms. For example, the height difference Δh is 20 angstroms, 50 angstroms, 70 angstroms, 80 angstroms, 90 angstroms, 100 angstroms, 200 angstroms, 300 angstroms, 400 angstroms, etc.
[0053] By reducing the height of the isolation structure 400 in this embodiment, the subsequent process can avoid forming sidewall material that is difficult to remove in the first region when forming the second sidewall. The gate structure formed on this basis has better thickness uniformity, retains the effective width of the active region to the maximum extent, and improves the device speed.
[0054] The following description uses an example where the top surface of the isolation structure 400 is higher than the surface of the semiconductor substrate 100, and the height difference Δh does not exceed 400 angstroms.
[0055] refer to Figure 12 After removing the dielectric layer 651 and part of the isolation structure 400 in the first region 110 and the remaining dielectric layer 651 in the second region 120, the process further includes: etching the floating gate layer 300 in the first region 110 and the second region 120, so that the floating gate layer 300 in the second region 120 and the sidewall of the offset sidewall 660 are coplanar, providing space for the subsequent formation of the gate structure. The process for removing the floating gate layer 300 can be a dry etching process or a wet etching process.
[0056] Before forming the gate structure, a second sidewall needs to be formed on the sidewall of the control gate structure 600 and the floating gate layer 300. The second sidewall can protect the floating gate layer and prevent subsequent processes from damaging the floating gate layer.
[0057] refer to Figure 13 A sidewall material layer 900 is formed on the sidewall of the offset sidewall 660, the surface of the control gate structure 600, the sidewall of the floating gate layer 300, the surface of the isolation structure 400, and the surface of the exposed floating gate dielectric layer 200. If the top surface of the isolation structure 400 is higher than the surface of the floating gate dielectric layer 200, a sidewall material layer 900 is also formed on the sidewall of the higher isolation structure 400. The material of the sidewall material layer 900 is preferably silicon nitride. Methods for forming the sidewall material layer 900 include, but are not limited to, chemical vapor deposition and physical vapor deposition methods; any method suitable for forming the sidewall material layer in this embodiment can be used.
[0058] refer to Figure 14 The control gate structure 600, the exposed floating gate dielectric layer 200, the surface of the isolation structure 400, and the sidewall material layer 900 are etched to form a second sidewall 910 on the offset sidewall 660 and the sidewall of the floating gate layer 300. A dry etching process can be used to etch the sidewall material layer 900 to form the second sidewall 910. The second sidewall 910 can avoid damage to the floating gate layer 300 and ensure the width of the floating gate layer 300. Because the height of the isolation structure 400 is reduced before the sidewall material layer 900 is deposited in this embodiment, the step between the isolation structure 400 and the floating gate dielectric layer 200 is made gentler. In other embodiments of this application, the top surface of the isolation structure 400 and the floating gate dielectric layer 200 can be made coplanar, or the top surface of the isolation structure 400 can be made lower than the surface of the semiconductor substrate 100 to eliminate the step, thereby reducing or avoiding the presence of residual sidewall material layer 900, and making the subsequently formed gate structure have better thickness uniformity. Based on the prior art, the effective area of the active region is significantly increased, and the device speed is greatly improved.
[0059] Continue to refer to Figure 14This application also provides a semiconductor structure, including: a semiconductor substrate 100, the semiconductor substrate 100 including a first region 110 and a second region 120, wherein a floating gate dielectric layer 200 is formed on the surface of the semiconductor substrate 100 in the first region 110 and the second region 120; an isolation structure 400 located in the semiconductor substrate 100 and the floating gate dielectric layer 200 in the first region 110, wherein the height difference Δh between the top surface of the isolation structure 400 and the surface of the semiconductor substrate 100 is greater than 0 angstroms and does not exceed 400 angstroms; a floating gate layer 300, discretely located on the surface of the floating gate dielectric layer 200 in the second region 120; a control gate structure 600 located on the surface of the floating gate layer 300; and an offset sidewall 660 located on the sidewall of the control gate structure 600, wherein the offset sidewall 660 and the sidewall of the floating gate layer 300 are coplanar.
[0060] In some embodiments, the semiconductor structure further includes a second sidewall 910 located on the sidewalls of the floating gate layer 300 and the offset sidewall 660.
[0061] In some embodiments, the control gate structure 600 includes a control gate dielectric layer 610, a control gate layer 620, and a mask layer stacked sequentially, wherein the mask layer may include a first mask layer 630 and a second mask layer 640.
[0062] refer to Figure 15 This application also provides another semiconductor structure, including: a semiconductor substrate 100, the semiconductor substrate 100 including a first region 110 and a second region 120, wherein a floating gate dielectric layer 200 is formed on the surface of the semiconductor substrate 100 in the first region 110 and the second region 120; an isolation structure 400 located in the semiconductor substrate 100 and the floating gate dielectric layer 200 in the first region 110, and the height difference between the top surface of the isolation structure 400 and the surface of the semiconductor substrate 100 is -400 angstroms to 0 angstroms; a floating gate layer 300, discretely located on the surface of the floating gate dielectric layer 200 in the second region 120; a control gate structure 600 located on the surface of the floating gate layer 300; and an offset sidewall 660 located on the sidewall of the control gate structure 600, wherein the offset sidewall 660 and the sidewall of the floating gate layer 300 are coplanar.
[0063] In some embodiments, the semiconductor structure further includes a second sidewall 910 located on the sidewalls of the floating gate layer 300 and the offset sidewall 660.
[0064] In some embodiments, the control gate structure 600 includes a control gate dielectric layer 610, a control gate layer 620, and a mask layer stacked sequentially, wherein the mask layer may include a first mask layer 630 and a second mask layer 640.
[0065] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.
[0066] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.
[0067] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," when used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.
[0068] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.
[0069] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate including a first region and a second region, wherein a floating gate dielectric layer and a floating gate layer are sequentially formed on the surface of the semiconductor substrate in the first region and the second region, wherein an isolation structure is formed in the semiconductor substrate, the floating gate dielectric layer and the floating gate layer in the first region, and a discrete control gate structure is formed on the surface of the floating gate layer in the second region. A first sidewall is formed on the sidewall of the control gate structure, and a dielectric layer is formed on the surface of the floating gate layer on both sides of the first sidewall and on the surface of the floating gate layer and the isolation structure in the first region; Remove a portion of the corresponding first sidewall and the dielectric layer on the side where the corresponding first sidewall is located to form an offset sidewall on the sidewall of the control grid structure; Remove the dielectric layer and part of the isolation structure in the first region and the remaining dielectric layer in the second region, so that there is a specific height difference between the top surface of the isolation structure and the surface of the semiconductor substrate, the height difference being greater than 0 angstroms and not exceeding 400 angstroms.
2. The method for forming a semiconductor structure according to claim 1, characterized in that, The process of forming the first sidewall and the medium layer includes: A first sidewall material layer and a second sidewall material layer are sequentially formed on the floating grid layer in the first region and the second region, the surface of the isolation structure, and the surface and sidewall of the control grid structure. The second sidewall material layer is etched so that the remaining second sidewall material layer only covers the first sidewall material layer of the control grid structure sidewall; A third sidewall material layer is formed on the surface of the exposed first sidewall material layer and the remaining second sidewall material layer; The third sidewall material layer is etched so that the remaining third sidewall material layer only covers the second sidewall material layer of the control gate structure sidewall; The first sidewall consists of a first sidewall material layer, a second sidewall material layer, and a third sidewall material layer, and the exposed first sidewall material layer serves as the medium layer.
3. The method for forming a semiconductor structure according to claim 2, characterized in that, The thickness of the third sidewall material layer is 50 angstroms to 1000 angstroms.
4. The method for forming a semiconductor structure according to claim 2, characterized in that, After forming the first sidewall and the dielectric layer, the process further includes forming a threshold voltage layer in the semiconductor substrate between the respective first sidewalls. The process for forming the threshold voltage layer includes: A mask is formed above the first region and the second region, the mask exposing the respective first sidewall and the surface of the dielectric layer between the respective first sidewall; Using the mask as a mask, the critical voltage layer is formed by ion implantation.
5. The method for forming a semiconductor structure according to claim 4, characterized in that, The process of forming the offset sidewall includes: using the mask plate as a mask, etching the third sidewall material layer in the corresponding first sidewall to make the thickness of the first sidewalls on both sides of the control gate structure different, forming the offset sidewall, and etching the dielectric layer on the side where the corresponding first sidewall is located.
6. The method for forming a semiconductor structure according to claim 1, characterized in that, The process for removing the dielectric layer and part of the isolation structure in the first region and the remaining dielectric layer in the second region is a maskless dry etching process or a wet etching process.
7. The method for forming a semiconductor structure according to claim 1, characterized in that, Also includes: The floating grid layers of the first region and the second region are etched so that the floating grid layer of the second region and the sidewall of the offset sidewall are coplanar.
8. The method for forming a semiconductor structure according to claim 7, characterized in that, Also includes: A second sidewall is formed on the sidewalls of the floating grid layer and the offset sidewall.
9. The method for forming a semiconductor structure according to claim 1, characterized in that, The first area is a logical area, and the second area is a flash memory area.
10. A semiconductor structure, characterized in that, include: A semiconductor substrate, the semiconductor substrate including a first region and a second region, wherein a floating gate dielectric layer is formed on the surface of the semiconductor substrate in the first region and the second region; An isolation structure is located in the semiconductor substrate and floating gate dielectric layer in the first region, and the height difference between the top surface of the isolation structure and the surface of the semiconductor substrate is greater than 0 angstroms and does not exceed 400 angstroms; The floating gate layer is discretely located on the surface of the floating gate dielectric layer in the second region; A control gate structure is located on the surface of the floating gate layer; An offset sidewall is located on the sidewall of the control grid structure, and the outer surface of the offset sidewall is coplanar with the sidewall of the floating grid layer.
11. A semiconductor structure, characterized in that, include: A semiconductor substrate, the semiconductor substrate including a first region and a second region, wherein a floating gate dielectric layer is formed on the surface of the semiconductor substrate in the first region and the second region; An isolation structure is located in the semiconductor substrate of the first region, and the height difference between the top surface of the isolation structure and the surface of the semiconductor substrate is greater than 0 angstroms and not more than 400 angstroms; The floating gate layer is discretely located on the surface of the floating gate dielectric layer in the second region; A control gate structure is located on the surface of the floating gate layer; An offset sidewall is located on the sidewall of the control grid structure, and the outer surface of the offset sidewall is coplanar with the sidewall of the floating grid layer.
12. The semiconductor structure according to claim 10 or 11, characterized in that, The control gate structure includes a control gate dielectric layer, a control gate layer, and a mask layer stacked sequentially.
13. The semiconductor structure according to claim 10 or 11, characterized in that, It also includes a second sidewall, located on the sidewall of the floating grid layer and the offset sidewall.