Memory structure and method of forming the same

Abstract

A memory structure and a method for forming the same, the memory structure comprising: a substrate; a plurality of composite structures located on the substrate and separated from each other, a first opening between adjacent composite structures, the composite structure comprising a first conductive structure, a floating gate structure located on both sides of the first conductive structure, an erase gate structure located on the floating gate structure, a first isolation structure located on the erase gate structure, a second isolation structure, and a third isolation structure, the second isolation structure being located between the first conductive structure and the floating gate structure, the erase gate structure and the first isolation structure, the third isolation structure being located on the sidewalls of the first isolation structure, the erase gate structure and the floating gate structure, and the inner wall of the first opening exposing the sidewalls of the third isolation structure and the surface of the substrate; a plurality of independent source doping regions located in the substrate, the source doping regions being in contact with the bottom surfaces of the first conductive structure and the floating gate structure; and a word line structure located in the first opening. Thus, the performance and integration of the memory structure are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a memory structure and a forming method thereof. Background Art

[0002] Flash memory has become a hot topic in non-volatile memory research due to its convenience, high storage density, and good reliability. Since the first flash memory came out in the 1980s, with the development of technology and the demand for storage in various electronic products, flash memory has been widely used in mobile and communication devices such as mobile phones, notebooks, PDAs, and USB flash drives.

[0003] Flash memory is a non-volatile memory. Its operating principle is to control the switch of the gate channel by changing the critical voltage of the transistor or memory cell to achieve the purpose of storing data, so that the data stored in the memory will not disappear due to power outage. Nowadays, flash memory has occupied most of the market share of non-volatile semiconductor memory and has become the fastest growing non-volatile semiconductor memory. The flash memory with the most widespread application is the split-gate structure.

[0004] However, the performance and reliability of the flash memory in the prior art still need to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a memory structure and a forming method thereof, so as to improve the performance and integration of the flash memory.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a memory structure, including: a substrate; a plurality of composite structures located on the substrate and separated from each other, a first opening being provided between adjacent composite structures, the composite structure including a first conductive structure, a floating gate structure located on both sides of the first conductive structure, an erase gate structure located on the floating gate structure, a first isolation structure located on the erase gate structure, a second isolation structure, and a third isolation structure, the second isolation structure being located between the first conductive structure and the floating gate structure, the erase gate structure and the first isolation structure, the third isolation structure being located on the side walls of the first isolation structure, the erase gate structure and the floating gate structure, and the inner wall surface of the first opening exposes the side walls of the third isolation structure and the surface of the substrate; a plurality of independent source doping regions located in the substrate, the source doping regions being in contact with the bottom surfaces of the first conductive structure and the floating gate structure; and a word line structure located in the first opening.

[0007] Optionally, the floating gate structure includes: a floating gate dielectric layer, and a floating gate located on the floating gate dielectric layer.

[0008] Optionally, the erase gate structure includes: a tunneling dielectric layer, and an erase gate located on the tunneling dielectric layer.

[0009] Optionally, the width of the erase gate is smaller than the width of the floating gate structure.

[0010] Optionally, in a sidewall of the erase gate structure adjacent to the third isolation structure, the sidewall of the erase gate is recessed relative to a sidewall of the tunneling dielectric layer.

[0011] Optionally, the third isolation structure includes: a first side wall located on the side wall surface of the first isolation structure and the erase gate, and a second side wall located on the side wall surface of the first side wall, the tunneling dielectric layer and the floating gate structure, and the first opening exposes the side wall surface of the second side wall.

[0012] Optionally, it also includes: a first protection layer located between the second isolation structure and the first conductive structure.

[0013] Optionally, the material of the first protective layer includes: polysilicon or silicon nitride.

[0014] Optionally, it also includes: a contact layer located on the top surface of the first conductive structure.

[0015] Optionally, it also includes: a second protective layer located on the top surface of the first conductive structure.

[0016] Optionally, the word line structure includes: a word line dielectric film located on the inner wall surface of the first opening, and two word line films respectively located on opposite side wall surfaces of the word line dielectric film, wherein a word line opening is provided between the two word line films, and the word line opening exposes the side wall surfaces of the two word line films and a portion of the surface of the word line dielectric film on the bottom surface of the first opening.

[0017] Optionally, it also includes: a third sidewall spacer located on the sidewall surface of the word line film.

[0018] Optionally, it also includes: an interlayer dielectric layer located on the plurality of composite structures and the word line structure, the surface of the interlayer dielectric layer is higher than the top surface of the composite structure; and a plurality of bit lines located in the interlayer dielectric layer, the bit lines are also located in the word line opening.

[0019] Correspondingly, the technical solution of the present invention also provides a method for forming a memory structure, comprising: providing a substrate; forming a plurality of discrete composite structures on the substrate, wherein a first opening is provided between adjacent composite structures, wherein the composite structure comprises a first conductive structure, a floating gate structure located on both sides of the first conductive structure, an erase gate structure located on the floating gate structure, a first isolation structure located on the erase gate structure, a second isolation structure, and a third isolation structure, wherein the second isolation structure is located between the first conductive structure and the floating gate structure, the erase gate structure and the first isolation structure, and the third isolation structure is located on the side walls of the first isolation structure, the erase gate structure and the floating gate structure, and the inner wall surface of the first opening exposes the side walls of the third isolation structure and the surface of the substrate; in the process of forming the composite structure, forming a plurality of independent source doping regions in the substrate, wherein the source doping regions are in contact with the bottom surfaces of the first conductive structure and the floating gate structure; after forming the composite structure, forming a word line structure in the first opening.

[0020] Optionally, the method for forming the plurality of composite structures includes: forming an initial floating gate layer, an initial erase gate layer located on the initial floating gate layer, and a mask layer located on the initial erase gate layer on the substrate, wherein the mask layer has a plurality of mask openings, and the mask openings expose a portion of the surface of the initial erase gate layer; forming the first isolation structure on the side wall surfaces of the mask openings; using the mask layer and the first isolation structure as masks, etching the initial erase gate layer and the initial floating gate layer until the surface of the substrate is exposed, and forming a third opening in the initial erase gate layer and the initial floating gate layer; forming the second isolation structure on the side wall surfaces of the first isolation structure and the third opening; after forming the second isolation structure, forming the first conductive structure in the mask openings and the third openings, and a second protective layer located on the top surface of the first conductive structure.

[0021] Optionally, the method further includes: forming a first protection layer on the side wall surface of the second isolation structure during the process of forming the second isolation structure.

[0022] Optionally, the method for forming the second isolation structure and the conductive sidewall film includes: forming a second isolation structure material film on the surface of the mask layer, the surface of the first isolation structure, and the inner wall surface of the third opening; forming a first protective material film on the surface of the second isolation structure material film; and etching the first protective material film and the second isolation structure material film using an anisotropic etching process until the top surface of the mask layer and the bottom surface of the third opening are exposed.

[0023] Optionally, in the process of forming the composite structure, a method for forming several independent source doping regions in the substrate includes: before forming the first conductive structure, using the mask layer, the first isolation structure and the second isolation structure as masks, performing ion implantation on the substrate exposed at the bottom of the third opening, and diffusing the injected ions into the substrate below the initial floating gate layer on both sides of the third opening.

[0024] Optionally, the method for forming the plurality of composite structures also includes: after forming the first conductive structure and the second protective layer, removing the mask layer; after removing the mask layer, patterning the initial erase gate layer according to the second protective layer and the first isolation structure to form an erase gate structure; after forming the erase gate structure, patterning the initial floating gate layer according to the second protective layer and the first isolation structure to form a floating gate structure.

[0025] Optionally, the initial erase gate layer includes: an initial tunneling dielectric layer, and an initial erase gate layer located on the initial tunneling dielectric layer; the erase gate structure includes: a tunneling dielectric layer, and an erase gate located on the tunneling dielectric layer.

[0026] Optionally, the third isolation structure includes: a first side wall located on the side wall surface of the first isolation structure and the erase gate; a second side wall located on the side wall surface of the first side wall, the tunneling dielectric layer and the floating gate structure, and the first opening exposes the side wall surface of the second side wall.

[0027] Optionally, the method for forming the third isolation structure includes: forming the first side wall in the process of patterning the initial erase gate layer according to the second protective layer and the first isolation structure to form the erase gate structure; after forming the floating gate structure, forming a second side wall on the side wall surface of the first side wall, the tunneling dielectric layer and the side wall surface of the floating gate structure.

[0028] Optionally, the method of forming an erase gate structure by patterning the initial erase gate layer according to the second protective layer and the first isolation structure includes: using the second protective layer and the first isolation structure as a mask, etching the initial erase gate layer until the surface of the initial tunneling dielectric layer is exposed to form an erase gate; forming a first side wall on the side wall surface of the first isolation structure and the erase gate; using the second protective layer, the first isolation structure, and the first side wall as a mask, etching the initial tunneling dielectric layer until the surface of the initial floating gate layer is exposed to form a tunneling dielectric layer.

[0029] Optionally, after forming the erase gate structure, the initial floating gate layer is patterned according to the second protective layer and the first isolation structure, and the method for forming the floating gate structure includes: using the second protective layer, the first isolation structure, and the first side wall as a mask, and etching the initial floating gate layer until the substrate surface is exposed.

[0030] Optionally, after forming the composite structure, the method for forming a word line structure in the first opening includes: forming a word line dielectric material film on the composite structure and on the inner wall surface of the first opening, the word line dielectric material film located on the inner wall surface of the first opening being the word line dielectric film; forming an initial word line film on the surface of the word line dielectric material film; etching the initial word line film using an anisotropic etching process until the surface of the word line dielectric film at the bottom of the first opening is exposed, forming two word line films on opposite side wall surfaces of the word line dielectric film, a word line opening being provided between the two word line films, the word line opening exposing the side wall surfaces of the two word line films and a portion of the surface of the word line dielectric film on the bottom surface of the first opening.

[0031] Optionally, after forming the word line structure, the method further includes: forming a third spacer on the side wall surface of the word line film.

[0032] Optionally, after forming the word line structure, it also includes: forming an interlayer dielectric layer on the composite structure and the word line structure, the surface of the interlayer dielectric layer is higher than the top surface of the composite structure; forming a plurality of bit lines in the interlayer dielectric layer, and the bit lines are also located in the word line opening.

[0033] Optionally, after forming the word line structure, the method further includes: forming a contact layer on the top surface of the first conductive structure.

[0034] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0035] In the memory structure provided by the prior art of the present invention, the composite structure includes a first conductive structure, a floating gate structure located on both sides of the first conductive structure, an erase gate structure located on the floating gate structure, a first isolation structure located on the erase gate structure, a second isolation structure, and a third isolation structure, wherein the second isolation structure is located between the first conductive structure and the floating gate structure, the erase gate structure and the first isolation structure, and the third isolation structure is located on the sidewalls of the first isolation structure, the erase gate structure and the floating gate structure; a plurality of mutually independent source doping regions in the substrate, the surface of the source doping region is in contact with the bottom surface of the first conductive structure and the floating gate structure; and a word line structure located in the first opening. Therefore, the performance and integration of the memory structure can be improved while taking into account the low reading voltage of the memory structure, the low risk of interference when reading data and the high accuracy of data reading. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a schematic diagram of a cross-sectional structure of a memory structure;

[0037] Figures 2 to 19 It is a schematic cross-sectional structure diagram of each step of a method for forming a memory structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0038] As described in the background art, the performance and reliability of the flash memory in the prior art are relatively poor, which will be described in detail below with reference to the accompanying drawings.

[0039] Figure 1 It is a schematic diagram of the cross-sectional structure of a memory structure.

[0040] Please refer to Figure 1 The memory structure includes: a substrate 100; and a plurality of composite structures located on the substrate 100.

[0041] The composite structure includes: an erase gate structure 210 located on a substrate 100, the erase gate structure 210 including an erase gate oxide layer 211 and an erase gate 212 located on the erase gate oxide layer 211; a floating gate structure 220 located on both sides of the erase gate structure 210; a control gate structure 230 located on the floating gate structure 220; and a word line structure 240 located on both sides of the floating gate structure 220 and the erase gate structure 230, respectively.

[0042] The substrate 100 has a source doping region 110 therein, and the source doping region 110 is located below the erase gate structure 210 .

[0043] The control gate structure 230 is used to couple the voltage to the floating gate structure 220, the erase gate structure 210 is used to erase data, and the word line structure 240 is used to read data. Therefore, the word line structure 240 can be used only to read data, so that the word line structure 240 is not affected by the erase voltage, thereby reducing the read voltage and the risk of interference when reading data is low.

[0044] However, in the above-mentioned memory structure, the erase gate structure 210 is located above the source doping region 110. Therefore, on the one hand, there is an erase gate oxide layer 211 between the source doping region 110 and the erase gate 212, which leads to large parasitic resistance at the source doping region 110 and the erase gate structure 210, resulting in poor performance of the memory structure. On the other hand, it is necessary to form a structure (not shown) for connecting the source doping region 110 under each erase gate structure 210 in the substrate 100 other than under the composite structure to lead out the source doping region 110 under each erase gate structure 210, thereby resulting in poor integration of the memory structure. Therefore, the memory structure of the prior art has poor performance and low integration.

[0045] In order to solve the above technical problems, the technical solution of the present invention provides a memory structure and a method for forming the same, wherein the memory structure comprises: a substrate; a plurality of composite structures located on the substrate and separated from each other, a first opening between adjacent composite structures, the composite structure comprising a first conductive structure, a floating gate structure located on both sides of the first conductive structure, an erase gate structure located on the floating gate structure, a first isolation structure located on the erase gate structure, a second isolation structure, and a third isolation structure, wherein the second isolation structure is located between the first conductive structure and the floating gate structure, the erase gate structure and the first isolation structure, the third isolation structure is located on the sidewalls of the first isolation structure, the erase gate structure and the floating gate structure, and the inner wall of the first opening exposes the sidewalls of the third isolation structure and the surface of the substrate; a plurality of independent source doping regions located in the substrate, the source doping regions contacting the bottom surfaces of the first conductive structure and the floating gate structure; and a word line structure located in the first opening. Therefore, the performance and integration of the memory structure are improved.

[0046] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0047] Figures 2 to 19 It is a schematic cross-sectional structure diagram of each step of a method for forming a memory structure in one embodiment of the present invention.

[0048] Please refer to Figure 2 , providing a substrate 300.

[0049] In this embodiment, the substrate 300 includes a memory cell region I and a logic region II.

[0050] It should be noted that Figure 2 For the convenience of explanation, part of the storage cell area I and part of the logic area II are schematically shown.

[0051] The storage area I is used to form a memory structure, and the logic area II is used to form a logic circuit for performing logic control on the memory structure.

[0052] In this embodiment, the material of the substrate 300 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0053] Next, a plurality of separate composite structures are formed on the substrate 300, and in the process of forming the composite structures, a plurality of independent source doping regions are formed in the substrate 300. For the specific steps of forming the composite structures and the source doping regions, please refer to Figures 3 to 14 .

[0054] Please refer to Figure 3 An initial floating gate layer 310, an initial erase gate layer 320 located on the initial floating gate layer 310, and a mask layer 330 located on the initial erase gate layer 320 are formed on the substrate 300, wherein the mask layer 330 has a plurality of mask openings 331, and the mask openings 331 expose a portion of the surface of the initial erase gate layer 320.

[0055] In this embodiment, the initial floating gate layer 310 includes: an initial floating gate dielectric layer 311 and an initial floating gate layer 312 located on the surface of the initial floating gate structure layer 311 .

[0056] The initial floating gate layer 310 provides materials for the subsequent formation of a floating gate structure. Specifically, the initial floating gate dielectric layer 311 provides materials for the subsequent formation of a floating gate dielectric layer, and the initial floating gate layer 312 provides materials for the subsequent formation of a floating gate.

[0057] In this embodiment, the material of the initial floating gate dielectric layer 311 includes silicon oxide.

[0058] In this embodiment, the material of the initial floating gate layer 312 includes polysilicon.

[0059] In this embodiment, the method for forming the initial floating gate layer 310 includes: depositing an initial floating gate dielectric layer 311 on the surface of the substrate 300 ; and depositing an initial floating gate layer 312 on the surface of the initial floating gate dielectric layer 311 .

[0060] In this embodiment, the initial erase gate layer 320 includes an initial tunneling dielectric layer 321 and an initial erase gate layer 322 located on the initial tunneling dielectric layer 321 .

[0061] The initial erase gate layer 320 provides materials for the subsequent formation of an erase gate structure. Specifically, the initial tunnel dielectric layer 321 provides materials for the subsequent formation of a tunnel dielectric layer, and the initial erase gate layer 322 provides materials for the subsequent formation of an erase gate.

[0062] In this embodiment, the material of the initial tunneling dielectric layer 321 includes silicon oxide.

[0063] In this embodiment, the material of the initial erase gate layer 322 includes polysilicon.

[0064] In this embodiment, the method for forming the initial erase gate layer 320 includes: depositing an initial tunneling dielectric layer 321 on the surface of the initial floating gate layer 310 ; and depositing an initial erase gate layer 322 on the surface of the initial tunneling dielectric layer 321 .

[0065] In this embodiment, the material of the mask layer 330 includes photoresist. In addition, the method of forming the mask layer 330 includes: forming a photoresist material layer (not shown) on the surface of the initial erase gate layer 320; exposing and developing the photoresist material layer to form the mask layer 330.

[0066] In other embodiments, the mask layer includes: a hard mask layer, and a photoresist layer located on the surface of the hard mask layer. Since the mask layer includes the hard mask layer, the stability of pattern transfer can be improved. Specifically, the method for forming the mask layer includes: forming a hard mask material layer on the surface of the initial erase gate layer 320; forming a photoresist material layer on the surface of the hard mask material layer; exposing and developing the photoresist material layer to form a photoresist layer, wherein the photoresist layer exposes a portion of the surface of the hard mask material layer; using the photoresist layer as a mask, etching the hard mask material layer until the initial erase gate layer 320 is exposed to form the hard mask layer. Specifically, the material of the hard mask layer includes silicon nitride.

[0067] In this embodiment, based on the fact that the substrate 300 includes a memory cell region I and a logic region II, the plurality of mask openings 331 are located in the mask layer 330 on the memory cell region I.

[0068] Please refer to Figure 4 A first isolation structure 340 is formed on the sidewall surface of the mask opening 331 .

[0069] In this embodiment, the method for forming the first isolation structure 340 includes: depositing a first isolation structure material film (not shown) on the exposed surface of the initial erase gate layer 320 and the surface of the mask layer 330; and etching the first isolation structure material film using an anisotropic etching process until the surface of the initial erase gate layer 320 and the top surface of the mask layer 330 are exposed.

[0070] In this embodiment, the process of etching the first isolation structure material film includes: a plasma etching process.

[0071] In this embodiment, the material of the first isolation structure 340 is a dielectric material.

[0072] In this embodiment, the material of the first isolation structure 340 includes silicon oxide.

[0073] Please refer to Figure 5 , using the mask layer 330 and the first isolation structure 340 as masks, the initial erase gate layer 320 and the initial floating gate layer 310 are etched until the surface of the substrate 300 is exposed, and a third opening 332 is formed in the initial erase gate layer 320 and the initial floating gate layer 310 on the storage cell area I.

[0074] In this embodiment, the process of etching the initial erase gate layer 320 and the initial floating gate layer 310 includes: at least one of a dry etching process and a wet etching process.

[0075] Please refer to Figure 6 , a second isolation structure 350 is formed on the sidewalls of the first isolation structure 340 and the third opening 332 .

[0076] In this embodiment, the mask opening 331 and the third opening 332 after the second isolation structure 350 is formed provide space for the subsequent formation of the first conductive structure.

[0077] In this embodiment, the second isolation structure 350 is also located on a portion of the bottom surface of the third opening 332 .

[0078] In this embodiment, the material of the second isolation structure 350 includes silicon oxide.

[0079] In this embodiment, during the process of forming the second isolation structure 350 , a first protection layer 351 is formed on the sidewall surface of the second isolation structure 350 .

[0080] In this embodiment, the method for forming the second isolation structure 350 and the first protective layer 351 includes: depositing a second isolation structure material film (not shown) on the surface of the mask layer 330, the surface of the first isolation structure 340, and the inner wall surface of the third opening 332; depositing a first protective material film (not shown) on the surface of the second isolation structure material film; and etching the first protective material film and the second isolation structure using an anisotropic etching process until the top surface of the mask layer 330 and the bottom surface of the third opening 332 are exposed.

[0081] Since the first protective material film is formed on the surface of the second isolation structure material film, when the first protective material film and the second isolation structure material film are etched using an anisotropic etching process, the second isolation structure material film on the side wall of the first isolation structure 340 can be protected by the first protective material film, thereby reducing or avoiding the loss of the second isolation structure material film on the side wall of the first isolation structure 340 when etching the second isolation structure material film. As a result, a second isolation structure 350 with a more accurate film thickness is formed, further improving the performance of the memory structure.

[0082] In this embodiment, the material of the first protection layer 351 is the same as the material of the first conductive structure formed subsequently, so as to ensure the stability of the conductive performance and further reduce the parasitic resistance.

[0083] Specifically, the material of the first protection layer 351 includes polysilicon.

[0084] In some other embodiments, the material of the first conductive layer includes silicon nitride.

[0085] In some other embodiments, the first protective layer is not formed. Specifically, the second isolation structure is formed only on the sidewalls of the first isolation structure 340 and the third opening 332. In addition, the method for forming the second isolation structure includes: depositing a second isolation structure material film on the surface of the mask layer 330, the surface of the first isolation structure 340, and the inner wall surface of the third opening 332; and etching the first protective material film using an anisotropic etching process until the top surface of the mask layer 330 and the bottom surface of the third opening 332 are exposed.

[0086] Please refer to Figure 7 , a plurality of mutually independent source doping regions 360 are formed in the substrate 300 of the memory cell region I.

[0087] The surface of the source doping region 360 is connected to the first conductive structure 370 (such as Fig.14 As shown) and the floating gate structure 410 (as shown Fig.14 A bottom contact is formed (as shown) to achieve voltage coupling to the floating gate structure 410.

[0088] In this embodiment, the method for forming the source doping region 360 includes: using the mask layer 330, the first isolation structure 340 and the second isolation structure 350 as masks, performing ion implantation on the substrate 300 exposed at the bottom of the third opening 332, and diffusing the implanted ions into the substrate 300 below the initial floating gate layer 310 on both sides of the third opening 332.

[0089] Since the implanted ions diffuse into the substrate 300 below the initial floating gate layer 310 on both sides of the third opening 332, the source doping region 360 can be connected to the first conductive structure 370 (such as Fig.14 ) on both sides of the floating gate structure 410 (as shown Fig.14 A bottom contact is provided (as shown) to achieve coupling of voltage to the floating gate structure 410.

[0090] Furthermore, since the substrate 300 exposed at the bottom of the third opening 332 is ion-implanted using the mask layer 330, the first isolation structure 340 and the second isolation structure 350 as masks to form the source doping region 360, the source doping region 360 can be formed in a self-aligned manner based on the mask layer 330, thereby reducing the number of photolithography patterns in the formation process of the memory structure (no need to use a separate photolithography pattern to form the source doping region 360), and simplifying the formation process of the memory structure.

[0091] Please refer to Figure 8 After forming the source doping region 360 , a first conductive structure 370 and a second protective layer 371 located on a top surface of the first conductive structure 370 are formed in the mask opening 331 and the third opening 332 .

[0092] In this embodiment, the material of the first conductive structure 370 includes polysilicon.

[0093] In this embodiment, the material of the second protection layer 371 includes silicon oxide.

[0094] The second protection layer 371 is used to protect the first conductive structure 370 to reduce the risk of oxidation of the first conductive structure 370 in subsequent formation steps and to improve the performance and reliability of the formed memory structure.

[0095] In addition, on the one hand, the second protective layer 371 is also used as a mask for the subsequent patterning of the initial erase gate layer 320 and the initial floating gate layer 310; on the other hand, the second protective layer 371 can also separate the material of the word line structure from the first conductive structure 370 in the subsequent process of forming the word line structure, and serve as the stop position of the etching step when etching the material of the word line structure. Thus, not only can the source doping region 360 be formed in a self-aligned manner, but also the erase gate structure, floating gate structure and bit line structure can be formed in a self-aligned manner. Thus, the formation process of the memory structure is further simplified.

[0096] In this embodiment, the method for forming the first conductive structure 370 and the second protective layer 371 includes: forming a first conductive structure material layer (not shown) in the mask opening 331, in the third opening 332, and on the mask layer 330, wherein the surface of the first conductive structure material layer is higher than the top surface of the mask layer 330; planarizing the first conductive structure material layer until the top surface of the mask layer 330 is exposed to form an initial first conductive structure (not shown); and oxidizing the surface layer of the top surface of the initial first conductive structure to form the first conductive structure 370 and the second protective layer 371 located on the top surface of the first conductive structure 370.

[0097] Please refer to Fig. 9 After forming the first conductive structure 370 and the second protective layer 371 , the mask layer 330 is removed.

[0098] In this embodiment, the process of removing the mask layer 330 includes an ashing process.

[0099] In other embodiments, the process of removing the mask layer 330 includes a wet cleaning process. Specifically, the agent used in the wet cleaning process includes phosphoric acid.

[0100] Next, the initial erase gate layer 320 is patterned based on the second protection layer 371 and the first isolation structure 340 to form an erase gate structure.

[0101] In this embodiment, during the process of patterning the initial erase gate layer 320 based on the second protection layer 371 and the first isolation structure 340 , a first spacer for constituting the third isolation structure is formed.

[0102] For specific steps of forming the erase gate structure and the first sidewall, please refer to Figures 10 to 12 .

[0103] Please refer to Fig.10 , using the second protection layer 371 and the first isolation structure 340 as masks, the initial erase gate layer 322 is etched until the surface of the initial tunneling dielectric layer 321 is exposed to form an erase gate 422 .

[0104] In this embodiment, the erase gate 422 is made of polysilicon.

[0105] In this embodiment, the process of etching the initial erase gate layer 322 includes: at least one of a dry etching process and a wet etching process.

[0106] Please refer to Fig.11 , a first spacer 381 is formed on the sidewall surfaces of the first isolation structure 340 and the erase gate 422 .

[0107] In this embodiment, the first sidewall 381 is used to form a third isolation structure 380 (such as Fig.14 As a result, the spacing between the first conductive structure 370 and the subsequently formed word line structure is increased, thereby further reducing the risk of short circuit between the first conductive structure 370 and the word line structure and improving the reliability of the memory structure.

[0108] In addition, the first spacer 381 is also used as a part of a mask when patterning the initial floating gate layer 310 to form a floating gate structure. Therefore, the first spacer 381 can increase the floating gate structure 410 (such as Fig.13 The width W2 (as shown in Fig.13 As shown in ), while forming an erase gate 422 with a small width W1, a floating gate structure 410 with a large width W2 is formed to further reduce the voltage coupled to the erase gate 422, thereby further reducing the erase voltage to better improve the performance of the memory structure.

[0109] In addition, the first spacer 381 can protect the sidewall surface of the erase gate 422 during the subsequent etching process of patterning the initial tunneling dielectric layer 321 and the initial floating gate layer 310, so as to reduce damage to the erase gate 422. Thus, the performance of the memory structure is further improved.

[0110] In this embodiment, the method for forming the first sidewall 381 includes: depositing a first sidewall material film (not shown) on the surface of the second protective layer 371, the surface of the first isolation structure 340, the sidewall surface of the erase gate 422, and the surface of the initial tunneling dielectric layer 321; and etching the first sidewall material film using an anisotropic etching process until the surface of the second protective layer 371, the top surface of the first isolation structure 340, and the surface of the initial tunneling dielectric layer 321 are exposed.

[0111] In this embodiment, the anisotropic etching process includes a plasma etching process.

[0112] The material of the first sidewall spacer 381 includes a dielectric material.

[0113] In this embodiment, the material of the first sidewall spacer 381 includes silicon oxide.

[0114] Please refer to Fig.12 , using the second protection layer 371, the first isolation structure 340, and the first sidewall 381 as masks, the initial tunneling dielectric layer 321 is etched until the surface of the initial floating gate layer 310 is exposed to form a tunneling dielectric layer 421, so as to form an erase gate structure 420 on both sides of the first conductive structure 370.

[0115] In this embodiment, the erase gate structure 420 includes a tunnel dielectric layer 421 and an erase gate 422 located on the tunnel dielectric layer 421 .

[0116] In this embodiment, the material of the tunnel dielectric layer 421 includes silicon oxide.

[0117] In this embodiment, the width of the tunnel dielectric layer 421 is greater than the width of the erase gate 422 .

[0118] Specifically, in the sidewall of the erase gate structure 420 adjacent to the first sidewall 381 , the sidewall of the erase gate 422 is recessed relative to the sidewall of the tunnel dielectric layer 421 .

[0119] Specifically, the width of the tunnel dielectric layer 421 is equal to the width W2 (eg Fig.13 ).

[0120] In this embodiment, the process of etching the initial tunneling dielectric layer 321 includes at least one of a dry etching process and a wet etching process.

[0121] Please refer to Fig.13 After forming the erase gate structure 420 , the initial floating gate layer 310 is patterned according to the second protection layer 371 and the first isolation structure 340 , and a floating gate structure 410 is formed on both sides of the first conductive structure 370 .

[0122] In this embodiment, after the erase gate structure 420 is formed, the initial floating gate layer 310 is patterned according to the second protective layer 371 and the first isolation structure 340, and the method for forming the floating gate structure 410 includes: using the second protective layer 371, the first isolation structure 340, and the first side wall 381 as a mask, etching the initial floating gate layer 310 until the surface of the substrate 300 is exposed to form the floating gate structure 410.

[0123] In this embodiment, the floating gate structure 410 includes a floating gate dielectric layer 411 and a floating gate 412 located on the floating gate dielectric layer 411 .

[0124] In this embodiment, the material of the floating gate dielectric layer 411 includes silicon oxide.

[0125] In this embodiment, the material of the floating gate 412 includes polysilicon.

[0126] In this embodiment, the width W2 of the floating gate structure 410 is greater than the width W1 of the erase gate 422 .

[0127] Please refer to Fig.14After forming the floating gate structure 410, a second sidewall spacer 382 is formed on the sidewall surface of the first sidewall spacer 381, the sidewall surface of the tunneling dielectric layer 421, and the sidewall surface of the floating gate structure 410 to form a third isolation structure 380 on the sidewall surfaces of the first isolation structure 340, the erase gate structure 420, and the floating gate structure 410.

[0128] Specifically, in this embodiment, the third isolation structure 380 includes: a first side wall 381 located on the side wall surface of the first isolation structure 340 and the erase gate 422; and a second side wall 382 located on the side wall surface of the first side wall 381, the tunneling dielectric layer 421 and the floating gate structure 410.

[0129] The second spacer 382 is made of a dielectric material.

[0130] In this embodiment, the material of the second sidewall spacer 382 includes silicon oxide.

[0131] In this embodiment, the method for forming the second sidewall 382 on the sidewall surface of the first sidewall 381, the sidewall surface of the tunneling dielectric layer 421, and the sidewall surface of the floating gate structure 410 includes: depositing a second sidewall material film (not shown) on the surface of the second protective layer 371, the top surface of the first isolation structure 340, the surface of the first sidewall 381, the sidewall surface of the tunneling dielectric layer 421, the sidewall surface of the floating gate structure 410, and the exposed surface of the substrate 300; and etching the second sidewall material film using an anisotropic etching process until the surface of the second protective layer 371, the top surface of the first isolation structure 340, the top surface of the first sidewall 381, and the surface of the substrate 300 are exposed.

[0132] Thus, a plurality of separate composite structures 400 are formed on the substrate 300 of the memory cell region I, and a first opening 333 is provided between adjacent composite structures 400 .

[0133] The composite structure 400 includes: a first conductive structure 370; a floating gate structure 410 located on both sides of the first conductive structure 370; an erase gate structure 420 located on the floating gate structure 410; a first isolation structure 340 located on the erase gate structure 420; a second isolation structure 350, wherein the second isolation structure 350 is located between the first conductive structure 370 and the floating gate structure 410, the erase gate structure 420 and the first isolation structure 340; and a third isolation structure 380, wherein the third isolation structure 380 is located on the side walls of the first isolation structure 340, the erase gate structure 420 and the floating gate structure 410, and the inner wall of the first opening 333 exposes the side walls of the third isolation structure 420 and the surface of the substrate 300.

[0134] Specifically, the first opening 333 in this embodiment exposes the sidewall surface of the second sidewall 382 .

[0135] Next, after the composite structure 400 is formed, a word line structure is formed in the first opening 333 .

[0136] In this embodiment, during the process of forming the word line structure, a plurality of logic gate structures are formed on the logic region II.

[0137] For the specific steps of forming word line structure and several logic gate structures, please refer to Figures 15 to 17 .

[0138] Please refer to Fig.15 A word line dielectric material film 431 is formed on the composite structure 400 , the inner wall surface of the first opening 333 and the surface of the substrate 300 in the logic area II; and an initial word line film 432 is formed on the surface of the word line dielectric material film 431 .

[0139] The word line dielectric material film 431 located on the inner wall surface of the first opening 333 is a word line dielectric film 431 a .

[0140] In this embodiment, the material of the word line dielectric film 431 a includes silicon oxide.

[0141] In the present embodiment, the process of forming the word line dielectric material film 431 includes a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0142] The initial word line film 432 is used to provide material for subsequent formation of a word line film.

[0143] In this embodiment, the material of the initial word line film 432 includes polysilicon.

[0144] In the present embodiment, the formation process of the initial word line film 432 includes a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0145] Please continue to refer to Fig.15 After the initial word line film 432 is formed, a logic mask layer 440 is formed on the initial word line film 432 on the memory cell region I, and the logic mask layer 440 exposes the initial word line film 432 on the logic region II.

[0146] The logic mask layer 440 is used to protect the structures formed in and on the memory cell region I during the subsequent process of forming a plurality of logic gate structures on the logic region II.

[0147] In this embodiment, the material of the logic mask layer 440 includes photoresist.

[0148] Please continue to refer to Fig.15 , using the logic mask layer 440 as a mask, the initial word line film 432 and the word line dielectric material film 431 exposed on the logic region II are etched until the surface of the substrate 300 of the logic region II is exposed.

[0149] Please refer to Fig.16 , a plurality of logic gate structures 500 are formed on the surface of the exposed logic region II.

[0150] In this embodiment, a plurality of logic gate structures 500 are used to form a plurality of high-voltage MOS transistors and a plurality of low-voltage MOS transistors.

[0151] In addition, for ease of explanation, Fig.16 Only one logic gate structure 500 is schematically shown.

[0152] In this embodiment, after forming a plurality of logic gate structures 500 , the logic mask layer 440 is removed.

[0153] Please refer to Fig.17 After forming a plurality of logic gate structures 500 , a storage mask layer 450 is formed on the logic region II, and the storage mask layer 450 exposes the initial word line film 432 on the memory cell region I.

[0154] The storage mask layer 450 is used to protect the substrate 300 of the logic region II and a plurality of logic gate structures 500 on the logic region II during the subsequent etching process of the initial word line film.

[0155] In this embodiment, the material of the storage mask layer 450 includes photoresist.

[0156] Please continue to refer to Fig.17 After forming the storage mask layer 450, the initial word line film 432 is etched by an anisotropic etching process until the surface of the second protection layer 371 and the surface of the word line dielectric film 431a at the bottom of the first opening 333 are exposed, and two word line films 433 are formed on opposite side walls of the word line dielectric film 431a, with a word line opening 434 between the two word line films 433, and the word line opening 434 exposes the side walls of the two word line films 433 and the bottom surface of the word line dielectric film 431a.

[0157] Thus, a word line structure 430 is formed in the first opening 333 .

[0158] In this embodiment, the word line structure 430 includes: a word line dielectric film 431a located on the inner wall surface of the first opening 333, and two word line films 433 respectively located on the opposite side wall surfaces of the word line dielectric film 431a, and a word line opening 434 is provided between the two word line films 433, and the word line opening 434 exposes the side wall surfaces of the two word line films 433 and a portion of the surface of the word line dielectric film 431a on the bottom surface of the first opening 333.

[0159] In this embodiment, the material of the word line film 433 includes polysilicon.

[0160] In this embodiment, the anisotropic etching process for etching the initial word line film 432 includes a plasma etching process.

[0161] In this embodiment, after the word line structure 430 is formed, the storage mask layer 450 is removed.

[0162] In other embodiments, the substrate does not include a logic region, and no logic gate structure is formed. Therefore, after forming the initial word line film, the initial word line film is directly etched using an anisotropic etching process until the surface of the word line dielectric film at the bottom of the first opening is exposed, and two word line films are formed on opposite sidewalls of the word line dielectric film.

[0163] Next, please refer to Fig.18 A third spacer 460 is formed on the sidewall surface of the word line film 433 .

[0164] By forming the third spacer 460 on the sidewall surface of the word line film 433 , the risk of short circuit between the subsequently formed bit line structure and the word line film 433 can be further reduced, thereby better improving the reliability of the memory structure.

[0165] In this embodiment, the material of the third spacer 460 includes a dielectric material. Specifically, the material of the third spacer 460 includes silicon oxide.

[0166] In other embodiments, the third spacer is not formed.

[0167] In this embodiment, while forming the third spacer 460 , a fourth spacer 510 is formed on the sidewall surface of the logic gate structure 500 .

[0168] In other embodiments, the fourth sidewall spacer is not formed.

[0169] In this embodiment, the method for forming the third sidewall 460 and the fourth sidewall 510 includes: forming a third sidewall material film (not shown) on the surfaces of the composite structure 400, the second protective layer 371, the word line structure 430, and the logic gate structure 500; and etching the third sidewall material film using an anisotropic etching process until the top surface of the composite structure 400, the surface of the second protective layer 371, the bottom surface of the word line opening 434, and the top surface of the logic gate structure 500 are exposed.

[0170] Please refer to Fig.19 , a contact layer 480 is formed on the top surface of the first conductive structure 370 using a SAB process.

[0171] By forming the contact layer 480 on the top surface of the first conductive structure 370 , the conductive performance of the memory structure can be further improved, thereby further improving the performance of the memory structure.

[0172] Preferably, the contact layer 480 is also formed on the top surface of the word line film 433 , the surface of the substrate 300 between the two word line films 433 , the top surface of the logic gate structure 500 , and the surface of the substrate 300 on both sides of the logic gate structure 500 .

[0173] In this embodiment, the material of the contact layer 480 includes metal silicide.

[0174] In other embodiments, no contact layer is formed.

[0175] Next, please continue to refer to Fig.19 An interlayer dielectric layer 520 is formed on the composite structure 400 and the word line structure, and the surface of the interlayer dielectric layer 520 is higher than the top surface of the composite structure 400; a plurality of bit lines 530 are formed in the interlayer dielectric layer 520, and the bit lines 530 are also located in the word line opening 434.

[0176] In this embodiment, the bottom surface of the bit line 530 is in contact with the contact layer 480 on the surface of the substrate 300 between the two word line films 433 .

[0177] In other embodiments, no contact layer is formed on the surface of the substrate 300 between the two word line films 433 , and the bit line contacts the surface of the substrate between the two word line films.

[0178] In this embodiment, while forming the bit line 530 , a second conductive structure 541 is formed in the interlayer dielectric layer 520 . The second conductive structure 541 is located on the first conductive structure 370 , and the second conductive structure 541 is in contact with the contact layer 480 located on the top surface of the first conductive structure 370 .

[0179] In this embodiment, while forming the bit line 530, a third conductive structure 542 is formed in the interlayer dielectric layer 520 on the storage cell area I, and the third conductive structure 542 is located on the word line film 433, and the third conductive structure 542 is in contact with the contact layer 480 located on the top surface of the word line film 433.

[0180] In this embodiment, while forming the bit line 530, a fourth conductive structure 543 and a fifth conductive structure 544 are formed in the interlayer dielectric layer 520 on the logic region II, the fourth conductive structure 543 is located on the logic gate structure 500, and the fourth conductive structure 543 is in contact with the contact layer 480 located on the top surface of the logic gate structure 500, and the fifth conductive structure 544 is in contact with the contact layer 480 on the surface of the substrate 300 located on both sides of the logic gate structure 500.

[0181] Accordingly, an embodiment of the present invention further provides a memory structure formed by the above method, please continue to refer to Fig.18 The memory structure includes: a substrate 300; a plurality of composite structures 400 located on the substrate 300 and separated from each other, and a first opening 333 (such as Fig.14 As shown in ), the composite structure 400 includes a first conductive structure 370, a floating gate structure 410 located on both sides of the first conductive structure 370, an erase gate structure 420 located on the floating gate structure 410, a first isolation structure 340 located on the erase gate structure 420, a second isolation structure 350, and a third isolation structure 380, wherein the second isolation structure 350 is located between the first conductive structure 370 and the floating gate structure 410, the erase gate structure 420 and the first isolation structure 340, the third isolation structure 380 is located on the sidewalls of the first isolation structure 340, the erase gate structure 420 and the floating gate structure 410, and the inner wall of the first opening 333 exposes the sidewalls of the third isolation structure 380 and the surface of the substrate 300; a plurality of independent source doping regions 360 located in the substrate 300, the source doping regions 360 are in contact with the bottom surfaces of the first conductive structure 370 and the floating gate structure 410; and a word line structure 430 located in the first opening 333.

[0182] Specifically, since the composite structure 400 includes the first conductive structure 370 and the floating gate structure 410 located on both sides of the first conductive structure 370, and a plurality of independent source doping regions 360 are located in the substrate 300, and the source doping regions 360 are in contact with the first conductive structure 370 and the bottom surface of the floating gate structure 410, the voltage is coupled to the floating gate structure 410. Moreover, since the composite structure 400 includes the floating gate structure 410 located on both sides of the first conductive structure 370, the erase gate structure 420 located on the floating gate structure 410, and the memory structure further includes the word line structure 430 located in the first opening 333, the memory structure erases data based on the erase gate structure 420, so that the word line structure 430 can be used only for data reading, so that the read voltage of the memory structure is low, and the risk of interference when reading data is low, and the data reading accuracy is high.

[0183] On this basis, on the one hand, in the memory structure, since the erase gate structure 420 of the composite structure 400 is located on the floating gate structure 410, a placement space is provided for the first conductive structure 370, so that the first conductive structure 370 can be located between the split gates (i.e., the floating gate structure 410 and the erase gate structure 420 on both sides), and contact (connect) with the source doped region 360 in the lower substrate 300 between the split gates to directly lead out the source doped region 360, and thus, the parasitic resistance at the source doped region 360 and the first conductive structure 370 above it is low, so that the performance of the memory structure is improved. On the other hand, since the source doping region 360 can be directly led out through the first conductive structure 370, the multiple source doping regions 360 can be independent of each other (that is, each source doping region 360 can be isolated), and each source doping region 360 can be located only in the substrate 300 below the first conductive structure 370 and the floating gate structure 410, so that there is no need to form a structure for leading out the multiple source doping regions 360 in the substrate 300 other than below the multiple composite structures 400, thereby reducing the extra area occupied by the substrate 300 and improving the integration.

[0184] In summary, while taking into account the low reading voltage of the memory structure, the low risk of interference when reading data, and the high data reading accuracy, the performance and integration of the memory structure are improved.

[0185] In addition, since the several source doping regions 360 can be independent of each other (that is, each source doping region 360 can be isolated), and each source doping region 360 can be located only in the substrate 300 below the first conductive structure 370 and the floating gate structure 410, the pattern of the source doping region 360 is simple, and the several source doping regions 360 can be formed in a self-alignment manner, thereby simplifying the formation process of the memory structure.

[0186] In this embodiment, the substrate 300 includes a memory cell region I and a logic region II.

[0187] The storage area I is used to form a memory structure, and the logic area II is used to form a logic circuit for performing logic control on the memory structure.

[0188] Accordingly, in the present embodiment, the composite structure 400 , the first opening 333 and the word line structure 430 are located on the memory cell region I, and the source doping region 360 is located in the memory cell region I.

[0189] In this embodiment, the material of the substrate 300 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0190] In this embodiment, the material of the first conductive structure 370 includes polysilicon.

[0191] In this embodiment, the memory structure further includes: a second protection layer 371 located on the top surface of the first conductive structure 370 .

[0192] In this embodiment, the material of the second protection layer 371 includes silicon oxide.

[0193] In this embodiment, the floating gate structure 410 includes a floating gate dielectric layer 411 and a floating gate 412 located on the floating gate dielectric layer 411 .

[0194] In this embodiment, the material of the floating gate dielectric layer 411 includes silicon oxide.

[0195] In this embodiment, the material of the floating gate 412 includes polysilicon.

[0196] In this embodiment, the erase gate structure 420 includes a tunnel dielectric layer 421 and an erase gate 422 located on the tunnel dielectric layer 421 .

[0197] Specifically, electrons are pulled out through a window between the erasing gate 422 and the floating gate structure 410 to achieve data erasure.

[0198] In this embodiment, the material of the tunnel dielectric layer 421 includes silicon oxide.

[0199] In this embodiment, the erase gate 422 is made of polysilicon.

[0200] In this embodiment, the width W1 of the erase gate 422 is smaller than the width W2 of the floating gate structure 410 .

[0201] In this embodiment, the width of the tunnel dielectric layer 421 is greater than the width W1 of the erase gate 422 (eg, Fig.12 ).

[0202] Specifically, in the sidewall of the erase gate structure 420 adjacent to the third isolation structure 380 , the sidewall of the erase gate 422 is recessed relative to the sidewall of the tunnel dielectric layer 421 .

[0203] Specifically, the width of the tunnel dielectric layer 421 is equal to the width W2 of the floating gate structure 410 .

[0204] In this embodiment, the material of the first isolation structure 340 is a dielectric material.

[0205] Specifically, the material of the first isolation structure 340 includes silicon oxide.

[0206] In this embodiment, the material of the second isolation structure 350 includes silicon oxide.

[0207] In this embodiment, the memory structure further includes: a first protection layer 351 located between the second isolation structure 350 and the first conductive structure 370 .

[0208] In this embodiment, the material of the first protection layer 351 is the same as the material of the first conductive structure formed subsequently, so as to ensure the stability of the conductive performance.

[0209] Specifically, the material of the first protection layer 351 includes polysilicon.

[0210] In some other embodiments, the material of the first conductive layer includes silicon nitride.

[0211] In some other embodiments, there is no first protective layer.

[0212] In this embodiment, the third isolation structure 380 includes a first spacer 381 located on the sidewalls of the first isolation structure 350 and the erase gate 422 .

[0213] The material of the first sidewall spacer 381 includes a dielectric material.

[0214] In this embodiment, the material of the first sidewall spacer 381 includes silicon oxide.

[0215] In this embodiment, the third isolation structure 380 further includes a second sidewall spacer 382 located on the sidewall surfaces of the first sidewall spacer 381 , the tunnel dielectric layer 421 and the floating gate structure 410 , and the first opening 333 exposes the sidewall surface of the second sidewall spacer 382 .

[0216] The second spacer 382 is made of a dielectric material.

[0217] In this embodiment, the material of the second sidewall spacer 382 includes silicon oxide.

[0218] In this embodiment, the word line structure 430 includes: a word line dielectric film 431a located on the inner wall surface of the first opening 333, and two word line films 433 located on opposite side wall surfaces of the word line dielectric film 431a, with a word line opening 434 (such as Fig.17 As shown in FIG. 4 , the word line opening 434 exposes the sidewall surfaces of the two word line films 433 and a portion of the surface of the word line dielectric film 431 a on the bottom surface of the first opening 333 .

[0219] In this embodiment, the material of the word line dielectric film 431 a includes silicon oxide.

[0220] In this embodiment, the material of the word line film 433 includes polysilicon.

[0221] In this embodiment, the memory structure further includes: a third spacer 460 located on the sidewall surface of the word line film 433 .

[0222] In this embodiment, the material of the third spacer 460 includes a dielectric material. Specifically, the material of the third spacer 460 includes silicon oxide.

[0223] In other embodiments, there is no third sidewall.

[0224] In this embodiment, the memory structure further includes: a plurality of logic gate structures 500 located on the logic region II.

[0225] In this embodiment, a plurality of logic gate structures 500 are used to form a plurality of high-voltage MOS transistors and a plurality of low-voltage MOS transistors.

[0226] In other embodiments, the substrate does not include a logic region and does not have a logic gate structure.

[0227] In this embodiment, the memory structure further includes: a fourth spacer 510 located on the sidewall surface of the logic gate structure 500 .

[0228] In other embodiments, there is no fourth sidewall.

[0229] In this embodiment, the memory structure further includes: a contact layer 480 located on the top surface of the first conductive structure 370 .

[0230] Preferably, the contact layer 480 is also located on the top surface of the word line film 433 , the surface of the substrate 300 between the two word line films 433 , the top surface of the logic gate structure 500 , and the surface of the substrate 300 on both sides of the logic gate structure 500 .

[0231] In this embodiment, the material of the contact layer 480 includes metal silicide.

[0232] In other embodiments, there is no contact layer.

[0233] In this embodiment, the memory structure further includes: an interlayer dielectric layer 520 located on the composite structure 400 and the word line structure 430 , and a surface of the interlayer dielectric layer 520 is higher than a top surface of the composite structure 400 .

[0234] In this embodiment, the memory structure further includes: a plurality of bit lines 530 located in the interlayer dielectric layer 520 , and the bit lines 530 are also located in the word line opening 434 .

[0235] In this embodiment, the bottom surface of the bit line 530 contacts the contact layer 480 on the surface of the substrate 300 between the two word line films 433. In other embodiments, there is no contact layer, and the bit line contacts the substrate surface between the two word line films.

[0236] In this embodiment, the memory structure also includes: a second conductive structure 541 located in the interlayer dielectric layer 520, the second conductive structure 541 is also located on the first conductive structure 370, and the second conductive structure 541 is in contact with a contact layer 480 located on the top surface of the first conductive structure 370.

[0237] In this embodiment, the memory structure also includes: a third conductive structure 542 located in the interlayer dielectric layer 520 on the memory cell area I, the third conductive structure 542 is also located on the word line film 433, and the third conductive structure 542 is in contact with the contact layer 480 located on the top surface of the word line film 433.

[0238] In this embodiment, the memory structure also includes: a fourth conductive structure 543 and a fifth conductive structure 544 located in the interlayer dielectric layer 520 on the logic region II, the fourth conductive structure 543 is also located on the logic gate structure 500 and is in contact with the contact layer 480 located on the top surface of the logic gate structure 500, and the fifth conductive structure 544 is in contact with the contact layer 480 on the surface of the substrate 300 located on both sides of the logic gate structure 500.

[0239] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A memory structure, characterized in that: include: substrate; A plurality of composite structures located on the substrate and separated from each other, with a first opening between adjacent composite structures, the composite structures comprising a first conductive structure, floating gate structures located on both sides of the first conductive structure, an erase gate structure located on the floating gate structure, a first isolation structure located on the erase gate structure, a second isolation structure, and a third isolation structure, wherein the second isolation structure is located between the first conductive structure and the floating gate structure, the erase gate structure and the first isolation structure, the third isolation structure is located on sidewalls of the first isolation structure, the erase gate structure and the floating gate structure, and the inner wall of the first opening exposes the sidewalls of the third isolation structure and the surface of the substrate; A plurality of mutually independent source doping regions located in the substrate, wherein the source doping regions are in contact with the first conductive structure and the bottom surface of the floating gate structure; a word line structure located in the first opening; The erase gate structure includes: a tunneling dielectric layer and an erase gate located on the tunneling dielectric layer; in the sidewall of the erase gate structure adjacent to the third isolation structure, the sidewall of the erase gate is recessed relative to the sidewall of the tunneling dielectric layer.

2. The memory structure according to claim 1, characterized in that: The floating gate structure includes a floating gate dielectric layer and a floating gate located on the floating gate dielectric layer.

3. The memory structure according to claim 1, wherein: The width of the erase gate is smaller than the width of the floating gate structure.

4. The memory structure according to claim 1, characterized in that: The third isolation structure includes: a first sidewall located on the sidewall surface of the first isolation structure and the erase gate, and a second sidewall located on the sidewall surface of the first sidewall, the tunnel dielectric layer and the floating gate structure, and the first opening exposes the sidewall surface of the second sidewall.

5. The memory structure according to claim 1, wherein: Also includes: A first protection layer is located between the second isolation structure and the first conductive structure.

6. The memory structure according to claim 5, characterized in that: The material of the first protection layer includes: polysilicon or silicon nitride.

7. The memory structure according to claim 1, characterized in that: Also includes: A contact layer is located on the top surface of the first conductive structure.

8. The memory structure according to claim 1, wherein: Also includes: A second protection layer is located on the top surface of the first conductive structure.

9. The memory structure according to claim 1, characterized in that: The word line structure includes: a word line dielectric film located on the inner wall surface of the first opening, and two word line films respectively located on the opposite side wall surfaces of the word line dielectric film, a word line opening is provided between the two word line films, and the word line opening exposes the side wall surfaces of the two word line films and a portion of the surface of the word line dielectric film on the bottom surface of the first opening.

10. The memory structure according to claim 9, characterized in that: Also includes: A third sidewall spacer is located on the sidewall surface of the word line film.

11. The memory structure according to claim 9, characterized in that: Also includes: An interlayer dielectric layer located on the plurality of composite structures and the word line structure, wherein a surface of the interlayer dielectric layer is higher than a top surface of the composite structure; A plurality of bit lines are located in the interlayer dielectric layer, and the bit lines are also located in the word line openings.

12. A method for forming a memory structure, characterized in that: include: providing a substrate; A plurality of composite structures separated from each other are formed on the substrate, with a first opening between adjacent composite structures, the composite structure comprising a first conductive structure, a floating gate structure located on both sides of the first conductive structure, an erase gate structure located on the floating gate structure, a first isolation structure located on the erase gate structure, a second isolation structure, and a third isolation structure, wherein the second isolation structure is located between the first conductive structure and the floating gate structure, the erase gate structure and the first isolation structure, the third isolation structure is located on sidewalls of the first isolation structure, the erase gate structure and the floating gate structure, and the inner wall of the first opening exposes the sidewalls of the third isolation structure and the surface of the substrate; In the process of forming the composite structure, a plurality of mutually independent source doping regions are formed in the substrate, wherein the source doping regions are in contact with the first conductive structure and the bottom surface of the floating gate structure; After forming the composite structure, forming a word line structure in the first opening; The erase gate structure includes: a tunneling dielectric layer and an erase gate located on the tunneling dielectric layer; in the sidewall of the erase gate structure adjacent to the third isolation structure, the sidewall of the erase gate is recessed relative to the sidewall of the tunneling dielectric layer.

13. The method for forming a memory structure according to claim 12, wherein: The method for forming the plurality of composite structures comprises: forming an initial floating gate layer, an initial erase gate layer located on the initial floating gate layer, and a mask layer located on the initial erase gate layer on the substrate, wherein the mask layer has a plurality of mask openings, and the mask openings expose a portion of the surface of the initial erase gate layer; forming the first isolation structure on the sidewall surface of the mask opening; using the mask layer and the first isolation structure as masks, etching the initial erase gate layer and the initial floating gate layer until the surface of the substrate is exposed, and forming a third opening in the initial erase gate layer and the initial floating gate layer; forming the second isolation structure on the sidewall surface of the first isolation structure and the third opening; after forming the second isolation structure, forming the first conductive structure in the mask opening and the third opening, and a second protective layer located on the top surface of the first conductive structure.

14. The method for forming a memory structure according to claim 13, wherein: Also includes: During the process of forming the second isolation structure, a first protection layer is formed on the sidewall surface of the second isolation structure.

15. The method for forming a memory structure according to claim 14, wherein: The method for forming the second isolation structure and the first protective layer includes: forming a second isolation structure material film on the surface of the mask layer, the surface of the first isolation structure, and the inner wall surface of the third opening; forming a first protective material film on the surface of the second isolation structure material film; and etching the first protective material film and the second isolation structure material film using an anisotropic etching process until the top surface of the mask layer and the bottom surface of the third opening are exposed.

16. The method for forming a memory structure according to claim 13, wherein: In the process of forming the composite structure, the method of forming a plurality of independent source doping regions in the substrate includes: before forming the first conductive structure, using the mask layer, the first isolation structure and the second isolation structure as masks, performing ion implantation on the substrate exposed at the bottom of the third opening, and diffusing the implanted ions into the substrate below the initial floating gate layer on both sides of the third opening.

17. The method for forming a memory structure according to claim 13, wherein: The method for forming the plurality of composite structures also includes: after forming the first conductive structure and the second protective layer, removing the mask layer; after removing the mask layer, patterning the initial erase gate layer according to the second protective layer and the first isolation structure to form an erase gate structure; after forming the erase gate structure, patterning the initial floating gate layer according to the second protective layer and the first isolation structure to form a floating gate structure.

18. The method for forming a memory structure according to claim 17, wherein: The initial erasing gate layer includes: an initial tunneling dielectric layer, and an initial erasing gate layer located on the initial tunneling dielectric layer.

19. The method for forming a memory structure according to claim 18, wherein: The third isolation structure includes: a first sidewall located on the sidewall surface of the first isolation structure and the erase gate; a second sidewall located on the sidewall surface of the first sidewall, the tunneling dielectric layer and the floating gate structure, and the first opening exposes the sidewall surface of the second sidewall.

20. The method for forming a memory structure according to claim 19, wherein: The method for forming the third isolation structure includes: forming the first sidewall in the process of patterning the initial erase gate layer according to the second protective layer and the first isolation structure to form the erase gate structure; after forming the floating gate structure, forming the second sidewall on the sidewall surface of the first sidewall, the tunneling dielectric layer and the sidewall surface of the floating gate structure.

21. The method for forming a memory structure according to claim 20, wherein: The method for forming an erase gate structure by patterning the initial erase gate layer according to the second protective layer and the first isolation structure includes: using the second protective layer and the first isolation structure as masks, etching the initial erase gate layer until the surface of the initial tunneling dielectric layer is exposed to form an erase gate; forming a first side wall on the side wall surface of the first isolation structure and the erase gate; using the second protective layer, the first isolation structure, and the first side wall as masks, etching the initial tunneling dielectric layer until the surface of the initial floating gate layer is exposed to form a tunneling dielectric layer.

22. The method for forming a memory structure according to claim 20, wherein: After forming the erase gate structure, the initial floating gate layer is patterned according to the second protective layer and the first isolation structure. The method for forming the floating gate structure includes: using the second protective layer, the first isolation structure, and the first sidewall as a mask, etching the initial floating gate layer until the substrate surface is exposed.

23. The method for forming a memory structure according to claim 12, wherein: After the composite structure is formed, a method for forming a word line structure in the first opening includes: forming a word line dielectric material film on the composite structure and on the inner wall surface of the first opening, wherein the word line dielectric material film located on the inner wall surface of the first opening is a word line dielectric film; forming an initial word line film on the surface of the word line dielectric material film; etching the initial word line film using an anisotropic etching process until the surface of the word line dielectric film at the bottom of the first opening is exposed, forming two word line films on opposite side wall surfaces of the word line dielectric film, a word line opening is provided between the two word line films, and the word line opening exposes the side wall surfaces of the two word line films and a portion of the surface of the word line dielectric film on the bottom surface of the first opening.

24. The method for forming a memory structure according to claim 23, wherein: After forming the word line structure, the method further includes: forming a third spacer on the side wall surface of the word line film.

25. The method for forming a memory structure according to claim 23, wherein: After forming the word line structure, the method further includes: forming an interlayer dielectric layer on the composite structure and the word line structure, wherein the surface of the interlayer dielectric layer is higher than the top surface of the composite structure; and forming a plurality of bit lines in the interlayer dielectric layer, wherein the bit lines are also located in the word line opening.

26. The method for forming a memory structure according to claim 12, wherein: After forming the word line structure, the method further includes: forming a contact layer on the top surface of the first conductive structure.

Images