Storage modules, devices, and SOI process implementation methods for non-volatile high-speed FPGAs
By employing dual SONOS non-volatile memory cells and P-type body contact isolation in the FPGA, combined with SOI technology, the integration and radiation resistance issues of FPGA devices are solved, achieving high integration and high-speed operation.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 58TH RES INST OF CETC
- Filing Date
- 2022-04-12
- Publication Date
- 2026-06-30
AI Technical Summary
Existing FPGA devices suffer from problems such as difficulty in process integration, high signal transmission impedance, and poor radiation resistance. In particular, floating gate FPGAs are prone to failure in radiation environments.
It employs dual SONOS non-volatile memory cells, with the memory cells sharing a first N-type heavily doped region and isolated by a P-type body contact region. Combined with SOI technology, it simplifies wiring and improves integration and radiation resistance.
It reduces chip area, lowers process costs, improves FPGA operating speed and radiation resistance, simplifies wiring processes, and enhances the performance of logic modules.
Smart Images
Figure CN114743981B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit semiconductor technology, and specifically to a storage module, device, and SOI process implementation method for a non-volatile high-speed FPGA. Background Technology
[0002] With advancements in semiconductor process technology, Field Programmable Gate Array (FPGA) design technology has achieved a leap forward. The charge storage cells forming the memory array are the most crucial part of FPGA design, requiring careful consideration of factors such as process technology, layout area, aspect ratio, read speed, and erase / write current. The use of different types of memory cells to implement programmable functionality has a significant impact on the structure and performance of FPGA devices. Currently, commonly used programming technologies include SRAM programming, antifuse programming, and flash programming. While SRAM-based FPGAs offer high operating speeds, they consume a lot of power, and the information stored in SRAM is lost upon power failure. Floating gate technology is the mainstream technology for flash FPGAs. Based on floating gate technology, Actel has developed three generations of flash architecture FPGA products: ProASIC, ProASIC_Plus, and ProASIC3.
[0003] However, floating-gate FPGAs have inherent limitations: First, floating-gate structures require specialized semiconductor processes and are difficult to integrate. Second, the transmission transistors used to program the signal transmission paths within the FPGA employ high-voltage transistors, introducing significant impedance to signal transmission and reducing signal integrity and drive current. Third, floating-gate devices are prone to charge loss under radiation environments, leading to device failure. A patent search has not yet revealed a waveform recognition method suitable for ultrasonic scanning of stacked chips. Summary of the Invention
[0004] To address the shortcomings of existing technologies, this invention provides a memory module, device, and SOI process implementation method for a non-volatile high-speed FPGA. The memory module employs dual SONOS non-volatile memory cells, which share a first N-type heavily doped region. Furthermore, the memory module uses P-type body contact isolation instead of STI isolation, significantly reducing chip area, increasing FPGA integration density, and lowering process costs. The second N-type heavily doped region is externally connected to a low-voltage switching transistor, which not only simplifies FPGA wiring and the manufacturing process but also shortens the length of metal wiring interconnects between logic modules, improving FPGA operating speed, reducing latency, and ensuring logic module performance.
[0005] This invention is achieved through the following technical solution:
[0006] A non-volatile high-speed FPGA memory module includes a P-type substrate, a buried oxide layer, an STI isolation region, a tunneling dielectric layer, a charge storage layer, a barrier dielectric layer, a first gate oxide layer, a first N-type heavily doped region, a second N-type heavily doped region, a logic heavily doped region, a P-type body region, a logic body region, a P-type body contact region, a polysilicon gate electrode, a body contact metal, and a body contact hole.
[0007] The first N-type heavily doped region, the second N-type heavily doped region, and the P-type body contact region are disposed in the P-type body region; the body contact metal is disposed on the P-type body contact region and connected to the P-type body contact region through the body contact hole; the tunneling dielectric layer is disposed on the upper surface of the P-type body region, the charge storage layer is disposed on the upper surface of the tunneling dielectric layer, the barrier dielectric layer is disposed on the upper surface of the charge storage layer, and the polysilicon gate electrode is disposed on the upper surface of the barrier dielectric layer; the memory module is composed of multiple memory arrays, the memory arrays are composed of multiple memory cells, and the memory cells are composed of two SONOS (silicon-oxide-nitride-oxide-silicon) NMOS transistors. The SONOS NMOS transistors mainly include the tunneling dielectric layer, the charge storage layer, the barrier dielectric layer, the first N-type heavily doped region, the second N-type heavily doped region, the P-type body region, and the P-type body contact region.
[0008] Preferably, adjacent memory cells share the first N-type heavily doped region, which is connected to word lines 71-73. The memory arrays are isolated by P-type body contact regions, and STI isolation regions are not required.
[0009] Preferably, the two SONOS NMOS transistors share the second heavily doped N-type region, which is connected to a low-voltage switching transistor, and the polysilicon gate electrode is connected to bit lines 81-84.
[0010] The present invention also provides the following technical solution: a non-volatile high-speed FPGA device, wherein the FPGA device is integrated on an SOI substrate, and its structure includes a SONOS memory module, a low-voltage switching transistor and a logic module, wherein the memory module is connected to the logic module through the low-voltage switching transistor.
[0011] Preferably, the logic module further includes an integrated dual-gate oxide structure, and the memory module includes a tunneling dielectric layer, a charge storage layer, a barrier dielectric layer, a first heavily doped N-type region, a second heavily doped N-type region, a P-type body region, and a polysilicon gate electrode; the logic module includes a first gate oxide layer, a second gate oxide layer, a logic heavily doped region, a logic body region, and a polysilicon gate electrode; the memory module and the logic module are isolated from each other by an STI isolation region.
[0012] This invention also provides the following technical solution: a method for implementing a non-volatile high-speed FPGA using SOI technology, comprising the following steps:
[0013] Step 1: Create an STI isolation zone;
[0014] Step 2: Form a sacrificial oxide layer on the surface of the silicon wafer, and deposit photoresist on top of the sacrificial oxide layer;
[0015] Step 3: Using photolithography and ion implantation processes, a P-type body contact region is formed in the P-type body region, and photoresist is etched. The implantation dose of the P-type body contact region is 1E13~2E16cm⁻¹. -2 ;
[0016] Step 4: Deposit photoresist, then etch the photoresist and sacrificial oxide layer on the surface of the memory module;
[0017] Step 5: Form a tunneling dielectric layer, a charge storage layer, and a barrier dielectric layer, wherein the total thickness of the tunneling dielectric layer, the charge storage layer, and the barrier dielectric layer is 4 to 40 nm;
[0018] Step 6: Deposit photoresist and etch away the photoresist and sacrificial oxide layer on the surface of the logic module;
[0019] Step 7: Form a first gate oxide layer on the surface of the logic module, wherein the thickness of the first gate oxide layer is 4-20 nm;
[0020] Step 8: Form a polysilicon gate electrode on the upper surface of the barrier dielectric layer and the first gate oxide layer, wherein the sheet resistance of the polysilicon gate electrode is 10 to 40 Ω / □ (ohms / square); etch the polysilicon gate electrode, the barrier dielectric layer, the charge storage layer and the tunnel oxide layer;
[0021] Step 9: Using photolithography and ion implantation processes, form a first heavily doped N-type region and a second heavily doped N-type region in the P-type body region; and form a heavily doped logic region in the logic body region. The implantation dose of the first heavily doped N-type region, the second heavily doped N-type region, and the heavily doped logic region is 1E13~2E16cm. -2 .
[0022] The beneficial effects of this invention are as follows:
[0023] This invention's memory module employs dual SONOS non-volatile memory cells, sharing a first heavily doped N-type region. The module uses P-type body contact isolation instead of STI isolation, significantly reducing chip area, increasing FPGA integration density, and lowering process costs. A low-voltage switching transistor is externally connected to the second heavily doped N-type region, simplifying FPGA wiring and making the process simpler. It also shortens the length of metal wiring connecting logic modules, increasing FPGA operating speed, reducing latency, and ensuring logic module performance. The memory module uses SONOS NMOS transistors, greatly improving the FPGA's radiation resistance because electrons and holes are stored in isolated traps and cannot move freely. The novel FPGA process integrates on an SOI substrate, improving resistance to single-event upsets and latch-up, while the well isolation facilitates substrate biasing. Attached Figure Description
[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0025] Figure 1 This is a schematic diagram of a non-volatile high-speed FPGA memory module provided by the present invention;
[0026] Figure 2 This invention provides a circuit diagram of a non-volatile high-speed FPGA memory module.
[0027] Figure 3 yes Figure 1 A schematic cross-sectional view of storage module 11 taken along 11';
[0028] Figure 4 yes Figure 1 A schematic cross-sectional view of storage module 11 taken along 22';
[0029] Figure 5 yes Figure 1 A schematic cross-sectional view of storage module 11 taken along the 33' section;
[0030] Figure 6 This is a schematic diagram of a non-volatile high-speed FPGA device and memory cell structure provided by the present invention;
[0031] Figure 7 This is a schematic diagram of another non-volatile high-speed FPGA memory module provided by the present invention, wherein the outermost periphery of the memory module 11 does not integrate the P-type body contact area 44;
[0032] Figure 8 This is a schematic diagram of another non-volatile high-speed FPGA memory module provided by the present invention, wherein the memory arrays 61 are isolated by STI isolation regions 22;
[0033] Figure 9 This is a schematic diagram of a non-volatile high-speed FPGA device structure provided by the present invention, wherein the logic module 13 integrates a dual-gate oxide structure;
[0034] Figures 10-17 This invention provides a method for implementing a non-volatile high-speed FPGA using SOI technology, wherein:
[0035] Figure 10 This is a schematic diagram of the formation of STI isolation zone 22;
[0036] Figure 11 This is a schematic diagram of the formation of sacrificial oxide layer 26;
[0037] Figure 12 This is a schematic diagram of the etching of the window of storage module 11;
[0038] Figure 13 This is a schematic diagram showing the formation of the tunneling dielectric layer 23, the charge storage layer 24, and the barrier dielectric layer 25.
[0039] Figure 14 This is a schematic diagram of the corrosion of the sacrificial oxide layer of the logic module;
[0040] Figure 15 This is a schematic diagram of the formation of the first gate oxide layer 27;
[0041] Figure 16 This is a schematic diagram of the formation of the polysilicon gate electrode 51;
[0042] Figure 17 This is a schematic diagram of the formation of a first N-type heavily doped region 31, a second N-type heavily doped region 32, a P-type body contact region 44, and a logic heavily doped region 33 by ion implantation. Detailed Implementation
[0043] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0044] Example 1:
[0045] like Figure 1The diagram shows a storage module of a non-volatile high-speed FPGA provided by the present invention. The storage module 11 is composed of multiple storage arrays 61, including a P-type substrate 41, a buried oxide layer 21, an STI isolation region 22, a tunneling dielectric layer 23, a charge storage layer 24, a barrier dielectric layer 25, a first gate oxide layer 27, a first N-type heavily doped region 31, a second N-type heavily doped region 32, a P-type body region 42, a P-type body contact region 44, a polysilicon gate electrode 51, a body contact metal 52, and a body contact hole 53; the first N-type heavily doped region 41... A doped region 31, a second heavily doped N-type region 32, and a P-type body contact region 44 are disposed in the P-type body region 42; the body contact metal 52 is disposed on the P-type body contact region 44 and is connected to the P-type body contact region 44 through a body contact hole 53; the tunneling dielectric layer 23 is disposed on the upper surface of the P-type body region 42, the charge storage layer 24 is disposed on the upper surface of the tunneling dielectric layer 23, the barrier dielectric layer 25 is disposed on the upper surface of the charge storage layer 24, and the polysilicon gate electrode 51 is disposed on the upper surface of the barrier dielectric layer 25; the SONOS NMOS transistor 63 mainly includes the tunneling dielectric layer 23, the charge storage layer 24, the barrier dielectric layer 25, the first heavily doped N-type region 31, the second heavily doped N-type region 32, the P-type body region 42, and the P-type body contact region 44. Two SONOS NMOS transistors 63 constitute a memory cell 62, and multiple memory cells 62 constitute a memory array 61.
[0046] Adjacent memory cells 62 share a first heavily doped N-type region 31, and the memory arrays 61 are isolated using heavily doped P-type body contact regions 44, eliminating the need for STI isolation regions 22. This effectively reduces chip area, increases the integration density of FPGA devices, and lowers process costs. The compatible process between the memory module 11 and the low-voltage switching transistor 12 not only simplifies the FPGA's metal wiring, making process implementation simpler, but also shortens the interconnect metal wiring length of the logic module 13, reducing FPGA device latency and increasing circuit operating speed. The memory module 11 uses dual SONOS non-volatile NMOS transistors 63. Because electrons and holes are stored in isolated traps and cannot move freely, the FPGA configuration unit of this invention is not affected by single-event upsets. Using SOI technology further improves the FPGA's radiation resistance.
[0047] like Figure 2 The diagram shows a non-volatile high-speed FPGA memory module circuit provided by the present invention. The memory cell 62 is composed of two SONOS NMOS transistors 63. These two NMOS transistors 63 share a second heavily doped N-type region 32, which is connected to a low-voltage switching transistor 12, as shown by the dashed box in the figure. The memory cells 62 share a first heavily doped N-type region 31, which is connected to word lines 71-73. The polysilicon gate electrode 51 is connected to bit lines 81-84.
[0048] like Figure 3 As shown, is Figure 1 The schematic diagram of the memory module cross-section taken at 11' shows that the device is integrated on an SOI substrate, including a P-type substrate 41, a buried oxide layer 21, a P-type body region 42, a first heavily doped N-type region 31, a P-type body contact region 44, and a body contact metal 52. The first heavily doped N-type region 31 and the P-type body contact region 44 are located in the P-type body region 42, with the P-type body contact region 44 located in the middle of the first moderately doped N-type region 31. Two SONOS NMOS transistors share the P-type body contact region 44. The body contact metal 52 is connected to the P-type body contact region 44 through a body contact hole 53. The memory arrays 61 are isolated from each other through the lightly doped P-type body region 42. This method can reduce the chip area and improve the chip integration density.
[0049] like Figure 4 As shown, is Figure 1 The schematic diagram of the memory module taken along the 22' section shows that the device is integrated on an SOI substrate, including a P-type substrate 41, a buried oxide layer 21, a tunneling dielectric layer 23, a charge storage layer 24, a barrier dielectric layer 25, a P-type body region 42, a first N-type heavily doped region 31, a second N-type heavily doped region 32, and a polysilicon gate electrode 51. The two SONOS NMOS transistors 63 of the memory cell 62 share the first N-type heavily doped region 31. The tunneling dielectric layer 23, the charge storage layer 24, the barrier dielectric layer 25, and the polysilicon gate electrode 52 are located on the surface of the P-type body region 42 and are in contact with each other.
[0050] like Figure 5 As shown, Figure 1 The schematic diagram of the cross-section of the memory module 11 taken along the 33' section shows that the device is integrated on the SOI substrate and includes a P-type substrate 41, a buried oxide layer 21, a tunneling dielectric layer 23, a charge storage layer 24, a barrier dielectric layer 25, a P-type body region 42, a polysilicon gate electrode 51, and a P-type body contact region 44. The tunneling dielectric layer 23, the charge storage layer 24, the barrier dielectric layer 25, and the polysilicon gate electrode 52 are located on the surface of the P-type body region 42 and are in contact with each other. The memory arrays 61 are isolated from each other through the P-type body contact regions 44.
[0051] like Figure 6The diagram shows a non-volatile high-speed FPGA device and its memory cell structure according to the present invention. As can be seen from the figure, the novel FPGA device structure includes a SONOS memory module 11, a low-voltage switching transistor 12, and a logic module 13. The memory module 11 is connected to the logic module 13 via the low-voltage switching transistor 12. The dashed box indicates the FPGA's switching unit, which includes a charge storage cell 62 and the low-voltage switching transistor 12. The memory cell 62 is composed of two SONOS NMOS transistors 63, which share a common drain and are connected to the gate electrode of the low-voltage switching transistor 12.
[0052] Comparative Example 2:
[0053] like Figure 7 The diagram shows another non-volatile high-speed FPGA memory module provided by the present invention, wherein the outermost periphery of the memory module 11 does not integrate a P-type body contact region 44. The memory module 11 is integrated on an SOI substrate and includes a P-type substrate 41, a buried oxide layer 21, an STI isolation region 22, a tunneling dielectric layer 23, a charge storage layer 24, a barrier dielectric layer 25, a first gate oxide layer 27, a first heavily doped N-type region 31, a second heavily doped N-type region 32, a P-type body region 42, a P-type body contact region 44, a polysilicon gate electrode 51, a body contact metal 52, and a body contact hole 53. The memory arrays 61 are isolated from each other by the P-type body contact regions 44. The memory module 11 does not form a P-type body contact region 44 along the inner side of the STI isolation region 22, compared to... Figure 1 The structure and radiation resistance have been weakened.
[0054] Comparative Example 3:
[0055] like Figure 8 This is a schematic diagram of another non-volatile high-speed FPGA memory module provided by the present invention, wherein the memory arrays 61 are isolated from each other by STI isolation regions 22. The memory module 11 is integrated on an SOI substrate and includes a P-type substrate 41, a buried oxide layer 21, an STI isolation region 22, a tunneling dielectric layer 23, a charge storage layer 24, a barrier dielectric layer 25, a first gate oxide layer 27, a first heavily doped N-type region 31, a second heavily doped N-type region 32, a P-type body region 42, a P-type body contact region 44, a polysilicon gate electrode 51, a body contact metal 52, and a body contact hole 53; the memory arrays 61 are isolated from each other by the STI isolation region 22. The memory module 11 does not have a P-type body contact region 44 formed along the inner side of the STI isolation region 22, compared to... Figure 2 The structure and radiation resistance have been weakened.
[0056] Example 4:
[0057] like Figure 9The diagram shows a non-volatile high-speed FPGA device structure provided by the present invention, wherein the logic module 13 integrates a dual-gate oxide structure. The device is integrated on an SOI substrate, where 41 is a P-type substrate, 21 is a buried oxide layer, and 22 is an STI isolation region. The storage module 11 includes a tunneling dielectric layer 23, a charge storage layer 24, a barrier dielectric layer 25, a first heavily doped N-type region 31, a second heavily doped N-type region 32, a P-type body region 42, and a polysilicon gate electrode 51; the logic module 13 includes a first gate oxide layer 27, a second gate oxide layer 28, a heavily doped logic region 33, a logic body region 43, and a polysilicon gate electrode 51; the storage module 11 and the logic module 13 are isolated from each other by the STI isolation region 22.
[0058] Example 5:
[0059] Figures 10-17 This invention provides a method for implementing a non-volatile high-speed FPGA using SOI technology, with the following specific steps:
[0060] like Figure 10 As shown, STI isolation regions 22 are formed on the SOI substrate material using photolithography and oxidation processes. The memory module 11 and the logic module 13 are isolated from each other by the STI isolation regions 22. The width of the STI isolation regions is 0.4 to 1.0 μm. In the figure, 41 is a P-type substrate, 42 is a P-type body region, 43 is a logic body region, and 21 is a buried oxide layer.
[0061] like Figure 11 As shown, a sacrificial oxide layer 26 is formed on the surface of the material wafer by oxidation, and then photoresist is deposited on the surface of the sacrificial oxide layer 26. The thickness of the sacrificial oxide layer 26 is 20-30 nm. A P-type body contact region 44 is formed in the P-type body region 42 using an ion implantation process, and the implantation dose of the P-type body contact region 44 is 1E13-2E16 cm⁻¹. -2 .
[0062] like Figure 12 As shown, the photoresist and sacrificial oxide layer 26 on the surface of the memory module 11 are etched. The sacrificial oxide layer 26 on the surface of the logic module 13 serves as an etching barrier layer for subsequent etching processes to prevent silicon corrosion on the surface of the logic module 13 and ensure the performance of the logic module 13.
[0063] like Figure 13 As shown, an oxidation and deposition process is used to form a tunneling dielectric layer 23, a charge storage layer 24, and a barrier dielectric layer 25 on the surface of the device. The total thickness of the tunneling dielectric layer 23, the charge storage layer 24, and the barrier dielectric layer 25 is 4 to 40 nm.
[0064] like Figure 14 As shown, photolithography and etching processes are used to etch away the photoresist and sacrificial oxide layer 26 on the surface of logic module 13.
[0065] like Figure 15 As shown, a first gate oxide layer 27 is formed on the surface of the logic module 13, and the thickness of the first gate oxide layer 27 is 4 to 20 nm.
[0066] like Figure 16 As shown, a polysilicon gate electrode 51 is deposited on the upper surface of the barrier dielectric layer 25 and the first gate oxide layer 27. The sheet resistance of the polysilicon gate electrode 51 is 10 to 40 ohms / square. The polysilicon gate electrode 51, the barrier dielectric layer 25, the charge storage layer 24, and the tunneling dielectric layer 23 are etched.
[0067] like Figure 17 As shown, a first N-type heavily doped region 31 and a second N-type heavily doped region 32 are formed in the P-type body region 42 using photolithography and ion implantation processes; a logic heavily doped region 33 is formed in the logic body region 43. The implantation dose of the first N-type heavily doped region 31, the second N-type heavily doped region 32, and the logic heavily doped region 33 is 1E13~2E16 cm⁻¹. -2 .
[0068] The non-volatile high-speed FPGA of this invention employs dual SONOS memory cells and low-voltage switching transistors as configuration units. The memory cells formed by the dual SONOS NMOS transistors share a first heavily doped N-type region, significantly reducing the chip area. Heavily doped P-type body contacts are used for isolation within the memory module, further reducing the chip area, increasing the FPGA's integration density, and lowering manufacturing costs. The compatible process between the memory module and the low-voltage switching transistors reduces the complexity of FPGA metal wiring, simplifying implementation, shortening the length of logic interconnect metal wiring, reducing signal delay, and increasing FPGA operating speed. The FPGA memory module of this invention uses a SONOS structure, which makes the FPGA configuration units unaffected by single-event upsets. The well isolation of the memory module facilitates substrate biasing, and the SOI process further improves the FPGA's radiation resistance. Moreover, the process implementation is relatively simple, and the FPGA proposed in this invention has excellent process compatibility.
[0069] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A non-volatile high-speed FPGA memory module, characterized in that, It includes a P-type substrate, buried oxide layer, STI isolation region, tunneling dielectric layer, charge storage layer, barrier dielectric layer, first gate oxide layer, first N-type heavily doped region, second N-type heavily doped region, logic heavily doped region, P-type body region, logic body region, P-type body contact region, polysilicon gate electrode, body contact metal and body contact hole; The first N-type heavily doped region, the second N-type heavily doped region, and the P-type body contact region are disposed in the P-type body region; the body contact metal is disposed on the P-type body contact region and connected to the P-type body contact region through the body contact hole; the tunneling dielectric layer is disposed on the upper surface of the P-type body region, the charge storage layer is disposed on the upper surface of the tunneling dielectric layer, the barrier dielectric layer is disposed on the upper surface of the charge storage layer, and the polysilicon gate electrode is disposed on the upper surface of the barrier dielectric layer; The storage module is composed of multiple storage arrays, the storage arrays are composed of multiple storage cells, and the storage cells are composed of two SONOS NMOS transistors. The SONOS NMOS transistors mainly include the tunneling dielectric layer, the charge storage layer, the barrier dielectric layer, the first heavily doped N-type region, the second heavily doped N-type region, the P-type body region, and the P-type body contact region. Adjacent memory cells share the first N-type heavily doped region, which is connected to word lines (71-73). The memory arrays are isolated from each other using P-type body contact regions. The two SONOS NMOS transistors share the second heavily doped N-type region, which is connected to the low-voltage switching transistor. The polysilicon gate electrode is connected to bit lines (81-84).
2. A non-volatile high-speed FPGA device, characterized in that, The FPGA device is integrated on an SOI substrate and its structure includes a SONOS memory module, a low-voltage switching transistor, and a logic module. The memory module is connected to the logic module through the low-voltage switching transistor.
3. A non-volatile high-speed FPGA device according to claim 2, characterized in that, The logic module further includes an integrated dual-gate oxide structure. The memory module includes a tunneling dielectric layer, a charge storage layer, a barrier dielectric layer, a first heavily doped N-type region, a second heavily doped N-type region, a P-type body region, and a polysilicon gate electrode. The logic module includes a first gate oxide layer, a second gate oxide layer, a logic heavily doped region, a logic body region, and a polysilicon gate electrode. The memory module and the logic module are isolated from each other by an STI isolation region.
4. A method for implementing a non-volatile high-speed FPGA using SOI technology, characterized in that, Includes the following steps: Step 1: Create an STI isolation zone; Step 2: Form a sacrificial oxide layer on the surface of the silicon wafer, and deposit photoresist on top of the sacrificial oxide layer; Step 3: Using photolithography and ion implantation processes, a P-type body contact region is formed in the P-type body region, and photoresist is etched. The implantation dose of the P-type body contact region is 1E13~2E16 cm⁻¹. -2 ; Step 4: Deposit photoresist, then etch the photoresist and sacrificial oxide layer on the surface of the memory module; Step 5: Form a tunneling dielectric layer, a charge storage layer, and a barrier dielectric layer, wherein the total thickness of the tunneling dielectric layer, the charge storage layer, and the barrier dielectric layer is 4~40nm; Step 6: Deposit photoresist and etch away the photoresist and sacrificial oxide layer on the surface of the logic module; Step 7: Form a first gate oxide layer on the surface of the logic module, the thickness of the first gate oxide layer being 4~20nm; Step 8: Form a polysilicon gate electrode on the upper surface of the barrier dielectric layer and the first gate oxide layer, wherein the sheet resistance of the polysilicon gate electrode is 10~40Ω / £; etch the polysilicon gate electrode, the barrier dielectric layer, the charge storage layer and the tunnel oxide layer; Step 9: Using photolithography and ion implantation processes, form a first N-type heavily doped region and a second N-type heavily doped region in the P-type body region; and form a logic heavily doped region in the logic body region. The implantation dose of the first N-type heavily doped region, the second N-type heavily doped region, and the logic heavily doped region is 1E13~2E16 cm⁻¹. -2 .