Three-dimensional memory and its fabrication method, storage system, electronic device

Abstract

This disclosure provides a three-dimensional memory and its fabrication method, memory system, and electronic device. It relates to the field of semiconductor chip technology and aims to solve the problem of high risk of channel vias and gate trenches merging. The aforementioned three-dimensional memory includes a stacked structure and a gate trench structure. The stacked structure includes a gate layer and an insulating layer stacked on top of each other, and includes a first side and a second side opposite to each other along the stacking direction; the gate trench structure penetrates the stacked structure along the stacking direction; wherein, the trench width of at least the portion of the gate trench structure near the first side gradually decreases in a direction away from the first side and towards the second side. The aforementioned three-dimensional memory is used for data read and write operations.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a three-dimensional memory and its fabrication method, storage system, and electronic device. Background Technology

[0002] As the feature size of memory cells approaches the lower limit of the process, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach its upper limit, posing a serious challenge to the semiconductor memory industry.

[0003] Three-dimensional memory (such as 3D NADA flash memory) overcomes the above limitations. Specifically, by stacking storage cells in three dimensions to form a multi-layer structure, it increases storage density and its storage capacity is several times higher than that of similar planar memory.

[0004] During the fabrication of 3D memory, as the number of stacked layers increases, the overall thickness also increases. The critical size ratio between the top and bottom of the gate spacer tends to deteriorate, increasing the risk of the channel via merging with the gate spacer. Summary of the Invention

[0005] The embodiments of this disclosure provide a three-dimensional memory and its fabrication method, a memory system, and an electronic device, aiming to solve the problem of high risk of merging of channel vias and gate slots.

[0006] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions:

[0007] On one hand, a three-dimensional memory is provided. The three-dimensional memory includes a stacked structure and a gate trench structure. The stacked structure includes a gate layer and an insulating layer stacked in an overlapping manner, and the stacked structure includes a first side and a second side opposite to each other along the stacking direction; the gate trench structure extends through the stacked structure along the stacking direction; wherein the ratio between the trench width of the gate trench structure near the first side and the trench width of the gate trench structure near the second side is 0.5 to 2.

[0008] The three-dimensional memory provided in the above embodiments of this disclosure, because the ratio of the width of the gate partition structure near the first side to the width of the gate partition structure near the second side is 0.5 to 2, can avoid the ratio of the width of the gate partition structure near the first side to the width of the gate partition structure near the second side (the width of the bottom of the gate and the width of the top of the gate) being too small or too large, thus making the size of the gate partition structure more uniform and reducing the risk of the gate partition structure merging with the channel hole. In this way, it is not necessary to increase the distance between the gate partition structure and the channel hole, ensuring the density along the direction perpendicular to the wall of the gate partition structure, thereby ensuring that the storage density is not reduced.

[0009] In some embodiments, the ratio between the widths of any two slots in the gate spacer structure is 0.8 to 1.2.

[0010] In some embodiments, the gate spacer structure includes opposing first and second wall sections, each of which has a first region and a second region. The second region is closer to the first side than the first region; the width of the gate spacer structure located in the second region decreases in the direction from the first side to the second side. The surface of the first wall section in the second region is a first stepped surface, and the surface of the second wall section in the second region is a second stepped surface; the first and second stepped surfaces are symmetrical.

[0011] In some embodiments, the gate spacer structure includes two opposing trench walls, each trench wall having a third region and a fourth region. The surface of the trench wall in the third region is planar. The trench width of the trench wall in the third region increases in the direction from the first side to the second side, and the surfaces of the two opposing third regions are symmetrical. The fourth region is closer to the first side than the third region, and the surface of the trench wall in the fourth region is planar. The trench width of the trench wall in the fourth region decreases in the direction from the first side to the second side, and the surfaces of the two opposing fourth regions are symmetrical.

[0012] In some embodiments, the gate spacer structure includes a first trench wall and a second trench wall opposite to each other. The surface of the first trench wall is a third stepped surface, and the surface of the second trench wall is a fourth stepped surface, wherein the third and fourth stepped surfaces are symmetrical.

[0013] In some embodiments, the gate trench structure includes two opposing trench walls, the surfaces of which are planar and the surfaces of the two opposing trench walls are symmetrical.

[0014] In some embodiments, the gate spacer structure includes a gate spacer and a filling structure, wherein the gate spacer extends through the stacked structure along the stacking direction, and the filling structure fills the gate spacer.

[0015] On the other hand, a storage system is provided, including a three-dimensional memory and peripheral circuitry. The three-dimensional memory is the same as in any of the above embodiments. The peripheral circuitry is coupled to the three-dimensional memory.

[0016] In another aspect, an electronic device is provided, including a housing and a storage system, wherein the storage system is the storage system of any of the above embodiments, and the storage system is disposed within the housing.

[0017] In another aspect, a method for fabricating a three-dimensional memory is provided, comprising forming a stacked structure on one side of a semiconductor substrate, the stacked structure including alternating layers of sacrificial layers and insulating layers; forming a gate trench penetrating the stacked structure; performing a first etching process on the trench wall of at least the portion of the gate trench close to the semiconductor substrate in a direction away from the semiconductor substrate, such that the trench width of the portion of the gate trench after the first etching process decreases in the direction away from the semiconductor substrate; and replacing the sacrificial layer with gate material through the gate trench to form a gate layer.

[0018] In some embodiments, before etching the trench wall of at least the portion of the gate trench near the semiconductor substrate, the method includes: covering the inner wall of the gate trench with an isolation layer; and covering the surface of the isolation layer away from the inner wall of the gate trench with a protective layer. Etching the trench wall of at least the portion of the gate trench near the semiconductor substrate in a direction away from the semiconductor substrate includes: performing multiple trimming etching cycles on the protective layer, the isolation layer, and the stacked structure in a direction away from the semiconductor substrate; wherein each trimming etching cycle includes trimming the protective layer and, using the trimmed protective layer as a mask, etching the isolation layer and a portion of the stacked structure covered by the isolation layer.

[0019] In some embodiments, performing multiple trimming etching cycles on the protective layer, isolation layer, and stacked structure along a direction away from the semiconductor substrate includes: dividing multiple regions to be etched on the trench wall of the gate trench along a direction perpendicular to the semiconductor substrate; and sequentially performing one trimming etching cycle on the protective layer, isolation layer, and stacked structure in each region to be etched along a direction away from the semiconductor substrate.

[0020] In some embodiments, performing multiple trimming etching cycles on the protective layer, isolation layer, and stacked structure along a direction away from the semiconductor substrate further includes: dividing a non-etchable region on the trench wall of the gate trench along a direction perpendicular to the semiconductor substrate; wherein the non-etchable region is located on the side of the plurality of regions to be etched away from the semiconductor substrate; and performing a trimming etching cycle sequentially on the protective layer, isolation layer, and stacked structure in each region to be etched along a direction away from the semiconductor substrate until the non-etchable region is etched.

[0021] In some embodiments, along a direction away from the semiconductor substrate, a trimming etching cycle is performed sequentially on the protective layer, isolation layer, and stacked structure in each region to be etched until the non-etched region is reached. The method further includes: using a second etching process to remove the non-etched region.

[0022] In some embodiments, removing the non-etched area using a second etching process includes: removing the protective layer of the non-etched area using a gas etching process; and removing the isolation layer of the non-etched area using a wet etching process.

[0023] In some embodiments, the thickness of the isolation layer gradually decreases along the direction close to the semiconductor substrate; the thickness of the protective layer gradually decreases along the direction close to the semiconductor substrate.

[0024] In some embodiments, the material of the isolation layer includes oxide; the material of the protective layer includes polycrystalline silicon.

[0025] It is understood that the beneficial effects of the three-dimensional memory fabrication method, storage system, and electronic device provided in the above embodiments of this disclosure can be referred to the beneficial effects of the three-dimensional memory described above, and will not be repeated here. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0027] Figure 1 This is a schematic diagram of the three-dimensional structure of a three-dimensional memory according to some embodiments;

[0028] Figure 2 for Figure 1 A cross-sectional view of a string of storage cells in a three-dimensional memory along section line AA';

[0029] Figure 3 for Figure 1 The equivalent circuit diagram of a string of storage cells in a three-dimensional memory is shown.

[0030] Figure 4 for Figure 1 The cross-sectional view of the three-dimensional memory shown is along the section line BB'.

[0031] Figure 5 A top view of a three-dimensional memory according to some embodiments;

[0032] Figure 6 A cross-sectional view of a second type of three-dimensional memory according to some embodiments;

[0033] Figure 7 This is a cross-sectional view of a third type of three-dimensional memory according to some embodiments;

[0034] Figure 8 A cross-sectional view of the three-dimensional memory provided in Example 1;

[0035] Figure 9This is a cross-sectional view of the gate spacer provided in Example 1;

[0036] Figure 10 A flowchart illustrating a method for fabricating a three-dimensional memory, as shown in Example 1;

[0037] Figure 11 This is the main view of the stacked structure provided in Example 1;

[0038] Figure 12 A cross-sectional view of the channel holes in the laminated structure provided in Example 1;

[0039] Figure 13 A cross-sectional view of the gate spacer formed on the stacked structure provided in Example 1;

[0040] Figure 14 This is a cross-sectional view of the isolation layer formed in the gate trench provided in Example 1;

[0041] Figure 15 This is a cross-sectional view of the protective layer formed in the gate trench provided in Example 1;

[0042] Figure 16 Here is a flowchart of the first etching process provided in Example 1;

[0043] Figure 17 This is a cross-sectional view showing the division of the etchable and non-etchable areas within the gate trench provided in Example 1.

[0044] Figure 18 This is a cross-sectional view of the area to be etched in the gate spacer provided in Example 1 after the first etching process;

[0045] Figure 19 A cross-sectional view of the protective layer in the area to be etched near the semiconductor substrate within the gate trench provided in Example 1, after being trimmed;

[0046] Figure 20 This is a cross-sectional view of the area to be etched near the semiconductor substrate within the gate trench provided in Example 1 after etching.

[0047] Figure 21 A cross-sectional view of the protective layer in the gate trench, away from the semiconductor substrate, after being trimmed, as provided in Example 1;

[0048] Figure 22 This is a cross-sectional view of the area to be etched away from the semiconductor substrate within the gate trench provided in Example 1 after etching.

[0049] Figure 23 This is a magnified view of a local structure of the area to be etched near the semiconductor substrate, as provided in Example 1.

[0050] Figure 24A cross-sectional view of the non-etched region within the gate trench provided in Example 1 after the protective layer has been removed;

[0051] Figure 25 A cross-sectional view of the non-etched region of the gate trench provided in Example 1 after the isolation layer has been removed;

[0052] Figure 26 This is a cross-sectional view of the sacrificial gap formed within the laminated structure provided in Example 1;

[0053] Figure 27 A cross-sectional view of the stacked structure provided in Example 1;

[0054] Figure 28 This is a cross-sectional view of the gate spacer provided in Example 1 after the filling structure has been completed;

[0055] Figure 29 A cross-sectional view of the three-dimensional memory provided for Example 2;

[0056] Figure 30 A cross-sectional view of the three-dimensional memory provided for Example 3;

[0057] Figure 31 A cross-sectional view of the three-dimensional memory provided for Example 4.

[0058] Reference numerals: 10-3D memory; 100-Semiconductor substrate; 200-Stacked structure; 210-Gate layer; 211-Source select gate; 212-Drain select gate; 213-Word line; 220-Insulating layer; 230-Channel structure; 231-Channel via; 232-Dielectric layer; 234-Channel layer; 240-Memory cell string; 250-Gate trench structure; 251-First trench wall; 252-Second trench wall; 253-First region ; 254-Second region; 2541-First step surface; 2542-Second step surface; 255-Third region; 256-Fourth region; 257-Third step surface; 258-Fourth step surface; 259-Gateway; 260-Memory block; 270-Fill structure; 300-Stacked structure; 310-Sacrificial layer; 311-Sacrificial gap; 400-Isolation layer; 410-Protective layer; 420-Area to be etched; 430-Non-etched area. Detailed Implementation

[0059] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0060] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0061] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0062] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0063] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0064] As used herein, “about,” “close to,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0065] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0066] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0067] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0068] The term "three-dimensional memory" refers to a memory formed by regularly arranged (e.g., array arrangement) strings of memory cell transistors that are generally parallel to each other (referred to herein as "memory cell string 240", e.g., NAND memory cell string 240).

[0069] In one embodiment of this application, a three-dimensional memory 10 and peripheral circuitry coupled to the three-dimensional memory 10 are described. For example... Figure 1 and Figure 2 As shown, the three-dimensional memory 10 includes a semiconductor substrate 100 and a stacked structure 200 formed on the semiconductor substrate 100. The stacked structure 200 includes multiple alternating layers of gate layers 210 and insulating layers 220, having a stepped morphology. The gate layers 210 and insulating layers 220 extend along the XY plane. Along the third direction Z, as... Figure 2As shown, the multilayer gate layer 210 has at least one source select gate 211 and at least one drain select gate 212. For example, when one source select gate 211 and one drain select gate 212 are both provided, the lowermost gate layer 210 in the multilayer gate layer 210 can be constructed as the source select gate 211, the uppermost gate layer 210 in the multilayer gate layer 210 can be constructed as the drain select gate 212, and the gate layer 210 in the middle layer of the multilayer gate layer 210 can be constructed as multiple word lines 213.

[0070] The XY plane is a surface parallel to the semiconductor substrate 100 used to support the stacked structure 200. The Z direction is perpendicular to the XY plane. The storage stacked structure is stacked on the support surface of the semiconductor substrate 100 along the Z direction.

[0071] like Figure 1 As shown, the three-dimensional memory 10 also includes an array of channel structures 230 that extend along the third direction Z through the drain select gate 212, each layer of word lines 213, and the source select gate 211. The portion of the channel structure 230 and each layer of word lines 213 surrounding the channel structure 230 forms a memory cell string 240.

[0072] like Figure 3 As shown, the memory cell string 240 includes multiple transistors connected in series, including a first selection transistor Q1, memory transistors M1 to M4, and a second selection transistor Q2. The memory transistors M1 to M4 are connected in series between the first selection transistor Q1 and the second selection transistor Q2. The gate of the first selection transistor Q1 is electrically connected to the drain selection gate 212, the gate of the second selection transistor Q2 is electrically connected to the source selection gate 211, and the gates of the memory transistors M1 to M4 are electrically connected to word lines 213.

[0073] To achieve block storage of the storage area of ​​the three-dimensional memory 10, such as Figure 1 As shown, the three-dimensional memory 10 also includes a gate partition structure 250 for dividing the stacked structure 200 into a plurality of memory blocks 260. In some examples, the gate partition structure 250 extends through the stacked structure 200 in a third direction Z, and the length of the gate partition structure 250 extends through the memory stacked structure 200 in a first direction X, and the width of the gate partition structure 250 extends in the Y direction, thereby enabling the stacked structure 200 to be divided into a plurality of memory blocks 260.

[0074] During the fabrication of the three-dimensional memory 10, such as Figure 4 As shown, Figure 4 for Figure 1The cross-sectional view of the three-dimensional memory 10 along section line BB' shows that when the channel structure 230 and the gate spacer structure 250 are formed on the stacked structure 200, etching is performed from the upper surface A1 to the lower surface A2 of the stacked structure 200 (i.e., from top to bottom). Therefore, the cross-sections of the formed channel structure 230 and gate spacer structure 250 are such that the width of the top end (near the upper surface A1 of the stacked structure 200) is greater than the width of the bottom end (near the lower surface A2 of the stacked structure 200). Figure 4 The cross-section of the channel structure 230 and the gate spacer structure 250 shown is perpendicular to the upper surface A1 of the stacked structure 200. Thus, as the thickness of the stacked structure 200 along the Z direction continuously increases, to ensure the bottom width D of the gate spacer structure 250 (or channel structure 230) is maintained... down If the process requirements can be met, then when forming the gate spacer structure 250 (or channel structure 230), the top width D of the gate spacer structure 250 (or channel structure 230) shall be... up This will increase, which will cause the gap distance H between the channel structure 230 and the gate partition structure 250 to continuously decrease, thus increasing the risk of the channel structure 230 and the gate partition structure 250 merging.

[0075] The above-mentioned channel structure 230 and gate partition structure 250 being combined means that the channel structure 230 and gate partition structure 250 are interconnected, which may cause leakage risk between two adjacent memory blocks 260, or leakage risk between adjacent bit lines within memory block 260.

[0076] In some embodiments of this application, such as Figure 5 As shown, the risk of merging between the channel structure 230 and the gate spacer structure 250 is generally reduced by increasing the gap distance H between them. However, as mentioned above, ensuring the bottom width D of the gate spacer structure 250 (or channel structure 230) is crucial. down To meet the process requirements, the top width D of the gate trench structure 250 (or channel structure 230) needs to be increased. up Therefore, as Figure 4 As shown, in H and D up When both are increased, the size of multiple storage blocks 260 along the Y direction will increase, which reduces the number of storage blocks 260 that the three-dimensional memory 10 can accommodate along the Y direction within the limited component space, thereby reducing the storage density of the stacked structure 200.

[0077] To address the aforementioned problems, this application provides an electronic device. The electronic device includes a housing and a storage system disposed within the housing. The storage system includes a three-dimensional memory 10 coupled to each other and peripheral circuitry. This electronic device can be any device capable of storing data, such as a mobile phone, desktop computer, tablet computer, laptop computer, or server.

[0078] like Figure 6 As shown, the aforementioned three-dimensional memory 10 may include a semiconductor substrate 100 and a plurality of memory blocks 260, the plurality of memory blocks 260 being located on one side of the semiconductor substrate 100; a gate spacer structure 250 is provided between two adjacent memory blocks 260. Specifically, in the Z direction, at least a portion of the gate spacer structure 250 closest to the semiconductor substrate 100 ( Figure 6 The groove width (shown in the dashed box) decreases in the direction away from the semiconductor substrate 100, for example, D down >D1>D2>D3>D4.

[0079] In this case, in order to form the embodiments provided in this application, as shown in the example Figure 6 The gate spacer structure 250 is shown within the dashed box. During the fabrication of the gate spacer structure 250, an etching process can be used to first form a structure such as... Figure 4 The gate spacer structure 250 shown here has a groove width that gradually increases in the direction away from the semiconductor substrate 100, and the width of the top end meets the design requirements so that the spacing between the channel structure 230 and the gate spacer structure 250 is greater than or equal to Hmin, thereby preventing the channel structure 230 and the gate spacer structure 250 from merging. Here, the spacing Hmin refers to the limit value that ensures the channel structure 230 and the gate spacer structure 250 will not merge. Therefore, even if the thickness of the stacked structure 200 along the Z direction continuously increases, the spacing between the channel structure 230 and the gate spacer structure 250 can still be controlled to be greater than or equal to Hmin through the above process.

[0080] Based on this, since the thickness of the stacked structure 200 along the Z direction continuously increases, the thickness H at the bottom of the gate trench structure 250 (e.g., Figure 4 The area shown (as shown) will be very small, resulting in the bottom of the gate trench structure 250 not meeting the process requirements and failing to adequately isolate the two memory blocks 260 on both sides. Therefore, next, the trench wall of at least the portion of the gate trench structure 250 closest to the semiconductor substrate 100 can be etched to reduce the trench width of the portion of the gate trench structure 250 closest to the semiconductor substrate 100 in the direction away from the semiconductor substrate 100, for example... Figure 6 In the middle, D down>D1>D2>D3>D4. This etches away at least the portion of the gate trench structure 250 closest to the semiconductor substrate 100 to increase the trench width of the portion of the gate trench structure 250 closest to the semiconductor substrate 100, thereby ensuring that the bottom width of the gate trench structure 250 also meets the manufacturing process requirements.

[0081] Therefore, as described above, the three-dimensional memory 10 provided in this application embodiment, when the thickness of the stacked structure 200 along the Z direction continuously increases, does not require increasing the top width of the gate partition structure 250 to ensure that the bottom width of the gate partition structure 250 meets production requirements during the fabrication of the gate partition structure 250. In this way, on the one hand, the bottom dimension of the gate partition structure 250 can meet process requirements without increasing the top dimension, making the contour of the gate partition structure 250 more uniform, thereby reducing the risk of the gate partition structure 250 merging with adjacent channel structures 230.

[0082] On the other hand, since the structure of the three-dimensional memory 10 formed by the above-described fabrication method ensures that the distance between the channel hole 231 and the gate spacer structure 250 is greater than or equal to Hmin, the risk of the gate spacer structure 250 merging with the adjacent channel structure 230 is reduced. Therefore, it is not necessary to increase the gap distance between the gate spacer structure 250 and the adjacent channel structure 230, thus avoiding increasing the distance along the three-dimensional memory 10 device. Figure 5 The dimensions shown in the Y direction save space in the Y direction, which helps to ensure or improve the storage density of multiple storage blocks 260.

[0083] In some embodiments, such as Figure 6 As shown, along the Z direction (perpendicular to the semiconductor substrate 100), the gate trench structure 250 has a bottom width D near the bottom end of the semiconductor substrate 100. down The gate trench structure 250 has a top width D away from the top of the semiconductor substrate 100. up Where 0.5 < D down / D up <2.

[0084] In this way, when D down / D up When the ratio is between 0.5 and 2, the top width D of the gate spacer structure 250 is increased. up and bottom width D down Neither too large nor too small. That is, the distance between the two opposing inner walls within the gate spacer structure 250 is more uniform, thereby reducing the risk of the gate spacer structure 250 merging with the adjacent channel structure 230.

[0085] Building upon this, to further improve the uniformity of the gate spacer structure 250 profile, the ratio between the widths of any two points in the gate spacer structure 250 provided in this application is 0.8 to 1.2. For example, as... Figure 6 As shown, that is, D down D1, D2, D3, D4 and D up The ratio of any two slot widths in the gate spacer structure 250 is within this range. This makes the slot width dimension of the gate spacer structure 250 more uniform, further improving the uniformity of the gate spacer structure 250 profile.

[0086] It should be noted that the slot width of the aforementioned gate spacer structure 250 refers to the width dimension along the Y direction; the ratio between any two slot widths of the aforementioned gate spacer structure 250 refers to the ratio of the slot widths along the Y direction at any two selected points along the Z direction, for example, Figure 6 D shown down D1, D2, D3, D4 and D up Any two of them.

[0087] For example, such as Figure 7 As shown, along the direction away from the semiconductor substrate 100, when the width of the gate spacer structure 250 decreases from the bottom to the top, that is, the entire width of the gate spacer structure 250 decreases along this direction. Simultaneously, the width ratio between any two ends of the gate spacer structure 250, for example, the ratio D of the top width to the bottom width... down / D up If the value approaches 1, the two opposing inner walls within the gate spacer structure 250 will become nearly parallel to each other. Therefore, as the stack thickness increases, the top width of the gate spacer structure 250 does not need to increase continuously, thereby reducing the risk of the gate spacer structure 250 merging with the channel via 231.

[0088] Furthermore, in this case, the top gap between the gate spacer structure 250 and the channel structure 230 is H1, and the bottom gap between the gate spacer structure 250 and the channel structure 230 is H2, both of which satisfy a value greater than or equal to Hmin. This avoids the top slot width of the gate spacer structure 250 increasing with the increase of the stacked structure 200, thereby reducing the risk of the gate spacer structure 250 merging with adjacent channel structures 230.

[0089] It should be noted that the decrease in the width of the gate spacer structure 250 at least in the portion closest to the semiconductor substrate 100 along the direction away from the semiconductor substrate 100 means that, from a macroscopic structural perspective, the width of the gate spacer structure 250 at least in the portion closest to the semiconductor substrate 100 exhibits a decreasing trend. From a microscopic structural perspective, the width of the gate spacer structure 250 may exhibit a completely decreasing trend, or it may exhibit an increasing trend in some areas, but the overall width still exhibits a decreasing trend. Therefore, this application does not impose specific limitations in this regard.

[0090] Furthermore, the statement that the two opposing inner walls of the gate spacer structure 250 are nearly parallel to each other refers to the fact that the two inner walls are approximately parallel from a macroscopic structural perspective. However, from a microscopic structural perspective, the inner walls of the gate spacer structure 250 may have some microscopic protrusions and are not necessarily completely flat surfaces.

[0091] The following detailed description of the specific structure and fabrication method of the three-dimensional memory 10 having the above-described gate trench structure 250 is provided through specific examples.

[0092] Example 1

[0093] In this example, to ensure that the width of the gate spacer structure 250, at least in the portion closest to the semiconductor substrate 100, gradually decreases in the direction away from the semiconductor substrate 100, any sidewall of the gate spacer structure 250 can be divided into two regions. For example, as... Figure 8 The diagram shows a first region 253 and a second region 254. The first region 253 is located on the side away from the semiconductor substrate 100, and the second region 254 is located on the side closer to the semiconductor substrate 100. The portion of the gate spacer structure 250 located in the second region 254 is the portion of the gate spacer structure 250 closer to the semiconductor substrate 100. Therefore, the width of the second region 254 decreases in the direction away from the semiconductor substrate 100.

[0094] Specifically, in some embodiments of this application, such as Figure 9 As shown, the gate trench structure 250 (the internal structure is not filled in the figure) may include opposing first trench walls 251 and second trench walls 252. Either the first trench wall 251 or the second trench wall 252 has a first region 253 and a second region 254. For example, the first trench wall 251 has a first region 253a and a second region 254a, and the second trench wall has a first region 253b and a second region 254b.

[0095] It should be noted that, for ease of explanation, the letters “a” and “b” are added to the identifiers of the first and second regions of the first and second trench walls 251 and 252 for distinction. The letters “a” and “b” are not used to define the structure and position of the first and second regions.

[0096] In addition, such as Figure 9 As shown, the first groove wall 251 has a first step surface 2541 on the surface of the second region 254a, and the second groove wall 252 has a second step surface 2542 on the surface of the second region 254b. The first step surface 2541 and the second step surface 2542 have a symmetrical structure.

[0097] It should be noted that the first step surface 2541 and the second step surface 2542 are symmetrical in that they are symmetrical about the center line containing the midpoint of the width of the gate trench structure 250. This center line is perpendicular to the semiconductor substrate 100.

[0098] Furthermore, either the first step surface 2541 or the second step surface 2542 can include multiple L-surfaces with different heights along the Y direction. Figure 9 Taking an example where each step surface includes two L-faces, the gate slot structure 250 has different slot widths at different step surfaces in the second region 254. For example, Figure 9 In the gate spacer structure 250, a first groove width is provided between the symmetrical L1 and L2 planes, and a second groove width is provided between the symmetrical L3 and L4 planes. The first groove width is greater than the second groove width. This allows the groove width in the second region 254 of the gate spacer structure 250 to decrease along the direction away from the semiconductor substrate 100.

[0099] It should be noted that the symmetry between the first step surface 2541 and the second step surface 2542 should be understood as a macroscopic symmetrical structure, and the first groove width between them is greater than the second groove width, thus achieving a decreasing trend in the groove width between the first step surface 2541 and the second step surface 2542. However, from a microscopic perspective, each step surface may also have some protrusions or depressions, and is not necessarily a completely flat plane. Furthermore, from a microscopic perspective, the distance between the first step surface 2541 and the second step surface 2542, for example, the distance between the two L1 surfaces or the two L2 surfaces, can show a decreasing or increasing trend along the direction away from the semiconductor substrate 100. Additionally, there may be slight dimensional differences between them, meaning that the first step surface 2541 and the second step surface 2542 are approximately symmetrical structures.

[0100] Combination such as Figure 9The structure of the three-dimensional memory 10 shown is illustrated below, and the method for fabricating the three-dimensional memory 10 will be described with examples. This method may include, for example... Figure 10 Steps S1 to S7 are shown below:

[0101] S1. A stacked structure is formed on one side of the semiconductor substrate.

[0102] For example, during the execution of S1 above, such as Figure 11 As shown, a sacrificial layer 310 and an insulating layer 220 are alternately formed along the Z direction on a semiconductor substrate 100. The alternately stacked sacrificial layer 310 and insulating layer 220 constitute the stacked structure 300.

[0103] For example, the method of forming the sacrificial layer 310 and the insulating layer 220 may include thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0104] In the above-mentioned laminated structure 300, the thicknesses of the multiple insulating layers 220 can be the same or different; the thicknesses of the multiple sacrificial layers 310 can be the same or different; the specific settings can be made according to process requirements.

[0105] Furthermore, in the fabrication process of the stacked structure 300, different numbers of stacked layers correspond to different stacking heights. For example, the stacked structure 300 can have 8, 32, 64, or 128 layers. The more layers the stacked structure 300 has, the higher the integration density, and the more memory cells are formed subsequently. The specific number of stacked layers and stacking height of the stacked structure 300 can be designed according to actual storage requirements, and this disclosure does not impose specific limitations on this.

[0106] For example, the material of the insulating layer 220 may include silicon oxide, and the material of the sacrificial layer 310 may include silicon nitride.

[0107] S2. A channel structure 230 is formed on the above-mentioned stacked structure 300.

[0108] like Figure 12 As shown, a channel hole 231 is formed on the surface of the stacked structure 300 away from the semiconductor substrate 100. The channel hole 231 penetrates the stacked structure 300 and extends to the semiconductor substrate 100 layer.

[0109] In some embodiments, the channel hole 231 can be processed using a room temperature (20-80℃) etching process, a low temperature (<-30℃) etching process, a dry etching process, or a wet etching process.

[0110] In some embodiments, a dielectric layer 232 and a channel layer 233 are sequentially deposited on the inner wall of the channel hole 231 to form the aforementioned channel structure 230. The dielectric layer 232 may be a tubular structure, and the channel layer 233 is formed within the tubular dielectric layer 232. The dielectric layer 232 may be formed by sequentially forming a barrier layer, a charge storage layer, and a tunnel insulating layer. For example, the dielectric layer 232 may be formed as a layered structure of oxide-nitride-oxide (ONO).

[0111] S3. A gate spacer 259 is formed on the above-mentioned stacked structure 300.

[0112] like Figure 13 As shown, a gate trench 259 is formed on the surface of the stacked structure 300 away from the semiconductor substrate 100. The gate trench 259 penetrates the stacked structure 300 along the Z direction and extends to the semiconductor substrate 100, and also penetrates the stacked structure 300 along the X direction. At this time, the top width D of the gate trench 259 is... up Greater than the bottom width D down ', and the bottom width D down 'With top width D up The ratio is relatively small.

[0113] In some embodiments, the channel hole 231 can be processed using a room temperature (20-80℃) etching process, a low temperature (<-30℃) etching process, a dry etching process, or a wet etching process.

[0114] Different process methods can be used to form the gate spacer 259 and the channel via 231. Since the gate spacer 259 and the channel via 231 have different structures, different process methods can be used to meet different structural requirements, thereby forming different structures without affecting the structural performance.

[0115] S4. Cover the gate trench 259 with an isolation layer 400 and a protective layer 410, and perform a first etching process on part of the trench wall of the gate trench 259.

[0116] For example, during the execution of S4 above, you can first... Figure 14 As shown, an isolation layer 400 is covered on the inner wall of the gate spacer 259.

[0117] Next, as Figure 15 As shown, a protective layer 410 is covered on the surface of the isolation layer 400 away from the inner wall of the gate trench 259.

[0118] In the steps of covering the inner wall of the gate trench 259 with the isolation layer 400 and the protective layer 410 on the isolation layer 400, thin film deposition processes such as CVD, PVD or ALD can be used.

[0119] Next, a first etching process is performed on the trench wall of at least the portion of the gate trench 259 closest to the semiconductor substrate 100 in a direction away from the semiconductor substrate 100, so that the trench width of the portion of the gate trench 259 that has undergone the first etching process decreases in a direction away from the semiconductor substrate 100.

[0120] The first etching process described above includes performing multiple trimming etching cycles on the protective layer 410, the isolation layer 400, and the memory stack-up structure along a direction away from the semiconductor substrate 100; wherein each trimming etching cycle includes trimming the protective layer 410 (hereinafter referred to as TR) and using the trimmed protective layer 410 as a mask to etch the isolation layer 400 and a portion of the memory block 260 covered by the isolation layer 400 (ET).

[0121] In this way, through multiple trimming etching cycles, a stepped structure can be formed in the second region 254 of the gate spacer 259, and the width of the spacer decreases in the direction away from the semiconductor substrate, thereby increasing the ratio of the bottom width to the top width of the gate spacer 259. This helps to make the dimensions of the gate spacer 259 more uniform.

[0122] In some embodiments, the first etching process described above includes, for example, Figure 16 Steps S41 to S42 shown:

[0123] S41, such as Figure 17 As shown, along a direction perpendicular to the semiconductor substrate 100, a plurality of etchable regions 420 (for example, etchable regions 420a and 420b, i.e., the second region 254 mentioned above) and a non-etchable region 430 (i.e., the first region 253 mentioned above) are divided on the wall of the gate trench 259. The non-etchable region 430 is located on the side of the plurality of etchable regions 420 away from the semiconductor substrate 100.

[0124] It should be noted that the area to be etched refers to the part that needs to undergo a trimming etching cycle, while the non-etched area refers to the part that does not need to undergo a trimming etching cycle.

[0125] S42, such as Figure 18 As shown, along the direction away from the semiconductor substrate 100, the protective layer 410, the isolation layer 400 and the memory block 260 in each area to be etched 420 are sequentially etched once to complete one trimming etching cycle until the non-etched area 430 is reached.

[0126] For example, such as Figure 17 As shown, the gate spacer 259 is divided into two etchable regions 420 and one non-etchable region 430, namely etchable region 420a and etchable region 420b.

[0127] like Figure 19 As shown, the protective layer 410 of the region 420a to be etched near the semiconductor substrate 100 is first trimmed (TR1), that is, the protective layer 410 of the region 420a to be etched is removed, so that the isolation layer 400 of the region 420a to be etched is exposed.

[0128] like Figure 20 As shown, the exposed isolation layer 400 and the memory block 260 covered by the isolation layer 400 are then etched (ET1) using the modified protective layer 410 as a mask, thereby increasing the trench width of the area to be etched 420a. At this time, the bottom of the gate trench is etched to a thickness of N1 (the dashed line in the figure represents the trench wall of the gate trench 259 before etching).

[0129] like Figure 21 As shown, the protective layer 410 of the area to be etched 420b is then trimmed (TR2) to expose the isolation layer 400 of the area to be etched 420b. Figure 24 As shown, then using the modified hard membrane layer as a mask, the exposed isolation layer 400 and the memory block 260 covered by the isolation layer 400 are etched (ET2), and the memory block 260 exposed in the area to be etched 420a is also etched. At this time, the thickness of the gate trench 259 etched again is N2 (the dashed line in the figure represents the trench wall of the gate trench 259 before etching). Wherein, N2 < N1.

[0130] It should be noted that, since the walls of the gate trench 259 are inclined before the finishing etching, N1 and N2 are the etching thicknesses of the ends of the regions 420a and 420b to be etched that are closest to the semiconductor substrate 100.

[0131] like Figure 22 As shown, after two trimming etching cycles, the bottom width D of the area 420a to be etched in the gate trench 259 is... down =N1+D down '。 Among them, D down 'for Figure 13 The bottom width of the gate trench 259 shown is before the first etching process. Since N2 < N1, the width of the etched region 420b near the semiconductor substrate 100 is smaller than the bottom width D of the etched region 420a. downThis allows the bottom width of the gate spacer 259 to increase and decrease in the direction away from the semiconductor substrate 100.

[0132] Specifically, a stepped surface (including the first stepped surface 2541 and the second stepped surface 2542) is formed between the trench wall of the etched region 420a and the trench wall of the etched region 420b. That is, the trench width of the etched region 420a is greater than the trench width of the etched region 420b. As a result, the trench width of the gate spacer 259 after the first etching process tends to decrease.

[0133] In some embodiments, the thickness of the isolation layer 400 decreases in the direction approaching the semiconductor substrate 100; the thickness of the protective layer 410 decreases in the direction approaching the semiconductor substrate 100 (as described above). Figure 15 (As shown). In this way, as Figure 23 As shown, the thickness C2 of the protective layer 410 and the thickness C1 of the isolation layer 400 in the etchable region 420a are the smallest. During the trimming etching, the inner wall region of the gate trench 259 in the etchable region 420a is etched first. Then, when the etchable region 420b is etched, since the thickness of the isolation layer 400 corresponding to the etchable region 420b is reduced, the thickness of the portion of the etchable region 420a that is exposed is reduced. This helps to reduce the thickness difference of the step surface formed between the etchable regions 420a and 420b after the first etching process, thereby making the width ratio of the gate trench 259 closer to 1.

[0134] In some embodiments, the material of the isolation layer 400 may include oxide; the material of the protective layer 410 may include polysilicon.

[0135] S5. Remove the protective layer 410 and isolation layer 400 from the non-etched area 430.

[0136] like Figure 24 As shown, a gas etching process is used to remove the protective layer 410 in the non-etched area 430. For example, HCl or CL2 gas can be used to etch the protective layer 410 to remove the remaining protective layer 410.

[0137] like Figure 25 As shown, a wet etching process is used to remove the isolation layer 400 in the non-etched area 430. For example, HF acid is used to etch the isolation layer 400 in the non-etched area 430 to remove the remaining isolation layer 400.

[0138] Combination Figure 13 and Figure 25 As shown, after two trimming etching cycles, the bottom width D of the gate spacer 259 is... down =N1+D down'。 That is, the bottom width D of the gate spacer 259 down Increase, and at the same time, its top width D up The width D at the bottom of the gate trench 259 after the first etching process remains unchanged. down With top width D up The increased width ratio helps to make the size of the gate spacer 259 more uniform.

[0139] S6. Replace the sacrificial layer 310 to form multiple storage blocks 260.

[0140] like Figure 26 As shown, the sacrificial layer 310 is removed via the gate trench 259 to form a sacrificial gap 311; as Figure 27 As shown, a gate layer 210 is formed in the sacrificial gap 311 using a gate material, thereby forming a plurality of memory blocks 260 with storage function.

[0141] In the step of removing the sacrificial layer 310 via the gate trench 259 to form the sacrificial gap 311, the gate trench 259 can be used as a channel for the etchant, and a wet etching process can be used to remove all the sacrificial layer 310 in the stacked structure 320 to form the sacrificial gap 311.

[0142] In the step of forming the gate layer 210 within the sacrificial gap 311, a thin film deposition process such as CVD, PVD, or ALD can be used to form the gate layer 210 within the sacrificial gap 311. The material of the gate layer 210 can be any one or a combination of conductive materials selected from tungsten, cobalt, copper, aluminum, doped crystalline silicon, or silicides.

[0143] S7. A filling structure 270 is formed in the gate spacer 259 to form the gate spacer structure 250.

[0144] like Figure 28 As shown, a filling structure 270 is filled in the gate spacer 259 to form a gate spacer structure 250.

[0145] For example, the filling structure 270 may include a dielectric material and a conductive material, wherein the conductive material is connected to the semiconductor substrate 100. The dielectric material may be polycrystalline silicon, thereby enabling the isolation of two adjacent memory blocks 260.

[0146] Example 2

[0147] The difference between this example and Example 1 is that, Figure 29 As shown, the two opposing trench walls within the gate spacer structure 250 each have a third region 255 and a fourth region 256. Figure 29(As shown in the dashed box in the middle), the third region 255 is located on the side away from the semiconductor substrate 100, and the fourth region 256 is located on the side closer to the semiconductor substrate 100.

[0148] The surface of the third region 255 of the two opposing trench walls is planar, and the trench width of the trench wall in the third region 255 increases in the direction away from the semiconductor substrate 100, for example, Figure 29 D up >D5. Furthermore, the surfaces of the two opposing third regions 255 have a symmetrical structure.

[0149] The surface of the fourth region 256 of the two opposing trench walls is planar, and the trench width of the trench wall in the fourth region 256 decreases in the direction away from the semiconductor substrate 100, for example, Figure 29 D down >D1>D2>D3>D4. Furthermore, the surfaces of the two opposing fourth regions 256 have a symmetrical structure.

[0150] It should be noted that the surface of the third region 255 and the fourth region 256 being planar should be understood as being planar from a macroscopic structural perspective, and that the groove width of the third region 255 tends to increase along the direction away from the semiconductor substrate 100, while that of the fourth region 256 tends to decrease. However, from a microscopic structural perspective, the surface of the third region 255 and the fourth region 256 can be a step surface with a very small step height, or the surface of the third region 255 and the fourth region 256 can have some protruding or recessed structures.

[0151] For example, in the first etching process step described above, the more areas 420 to be etched that are divided into by the trench wall of the gate spacer structure 250, the more trimming etching cycles are required. In this way, the thickness of the trench wall can be reduced as much as possible for each etching, thereby making the thickness difference between the step surfaces formed by two adjacent areas 420 to be etched smaller. From a macroscopic perspective, the fourth region 256 after the first etching process is approximately planar.

[0152] Since the fourth region 256 of the trench wall is close to a plane, the outline dimensions of the gate trench structure 250 are more uniform, which is conducive to further increasing the ratio of the bottom width to the top width of the gate trench structure 250, making it closer to 1, so as to reduce the risk of the gate trench structure 250 merging with the channel hole 231.

[0153] The other structures and fabrication methods of the three-dimensional memory 10 provided in this example are the same as those in Example 1, therefore, they will not be described again.

[0154] Example 3

[0155] The difference from Example 1 is that, as Figure 30As shown, the inner wall of the gate spacer structure 250 includes a first groove wall 251 and a second groove wall 252. The surface of the first groove wall 251 is a third step surface 257, and the surface of the second groove wall 252 is a fourth step surface 258. The structures of the third step surface 257 and the fourth step surface 258 are symmetrical.

[0156] For example, in step S51 of the fabrication method of Example 1, only multiple etchable regions 420 are defined, and non-etchable regions 430 are not defined. This allows the entire inner wall of the gate trench structure 250 to undergo a trimming etching cycle, forming a stepped surface. This causes the width of the gate trench structure 250 to gradually decrease in the direction away from the semiconductor substrate 100. For example, D down >D1>D2>D up .

[0157] In this way, the gate trench structure 250, which has a top width greater than the bottom width, formed in step S3, can be processed by the first etching process, thereby increasing the bottom width of the gate trench structure 250 and thus improving the ratio of the bottom width to the top width of the gate trench structure 250.

[0158] The other structures and fabrication methods of the three-dimensional memory 10 in this example are the same as those in Example 1, therefore, they will not be described again.

[0159] Example 4

[0160] The difference from Example 3 is that, as Figure 31 As shown, in this example, the first trench wall 251 and the second trench wall 252 of the gate trench structure 250 are both planar. The trench width of the gate trench structure 250 gradually decreases in the direction away from the semiconductor substrate 100, for example, D down >D1>D2>D up Furthermore, the surfaces of the first groove wall 251 and the second groove wall 252 have a symmetrical structure.

[0161] It should be noted that the trench wall of the gate trench structure 250 provided in this example is flat. This should be understood as being flat from a macroscopic structural perspective. However, from a microscopic structural perspective, the surface of the trench wall can be a step surface with a very small step height, or the surfaces of the third region 255 and the fourth region 256 can have some protruding or recessed structures.

[0162] The other structures and fabrication methods of the gate trench structure 250 provided in this example are the same as those in Example 3, therefore, they will not be described again.

[0163] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A three-dimensional memory, characterized in that, include: A stacked structure comprising alternately stacked gate layers and insulating layers, the stacked structure including a first side and a second side opposite to each other along the stacking direction; A gate spacer structure extends through the stacked structure along the stacking direction; wherein the ratio between the width of the gate spacer structure near the first side and the width of the gate spacer structure near the second side is 0.5 to 2. The gate trench structure includes opposing first trench walls and second trench walls, wherein either the first trench wall or the second trench wall has: First area; The second region is closer to the first side relative to the first region; the width of the slot in the second region of the gate trench structure decreases along the direction from the first side to the second side. Wherein, the surface of the first groove wall in the second region is a first stepped surface, and the surface of the second groove wall in the second region is a second stepped surface, and the first stepped surface and the second stepped surface are symmetrical structures.

2. The three-dimensional memory according to claim 1, characterized in that, The ratio between the widths of any two slots in the gate spacer structure is 0.8 to 1.

2.

3. The three-dimensional memory according to claim 1, characterized in that, The gate trench structure includes: A gate spacer extends through the stacked structure along the stacking direction; A filling structure is formed within the gate spacer.

4. A three-dimensional memory, characterized in that, include: A stacked structure comprising alternately stacked gate layers and insulating layers, the stacked structure including a first side and a second side opposite to each other along the stacking direction; A gate spacer structure extends through the stacked structure along the stacking direction; wherein the ratio between the width of the gate spacer structure near the first side and the width of the gate spacer structure near the second side is 0.5 to 2. The gate trench structure includes two opposing trench walls, the trench walls having: In the third region, the groove wall has a planar surface; the groove width of the groove wall in the third region increases in the direction from the first side to the second side, and the surfaces of the two opposite third regions have a symmetrical structure; and... The fourth region is located closer to the first side than the third region, and the surface of the groove wall in the fourth region is planar; the groove width of the groove wall in the fourth region decreases in the direction from the first side to the second side, and the surfaces of the two opposite fourth regions have a symmetrical structure.

5. A three-dimensional memory, characterized in that, include: A stacked structure comprising alternately stacked gate layers and insulating layers, the stacked structure including a first side and a second side opposite to each other along the stacking direction; A gate spacer structure extends through the stacked structure along the stacking direction; wherein the ratio between the width of the gate spacer structure near the first side and the width of the gate spacer structure near the second side is 1 to 2, and the width of the gate spacer structure gradually decreases along the direction from the first side to the second side; the gate spacer structure includes opposing first and second wall sections; the surface of the first wall section is a third step surface, and the surface of the second wall section is a fourth step surface, wherein the third and fourth step surfaces are symmetrical.

6. A three-dimensional memory, characterized in that, include: A stacked structure comprising alternately stacked gate layers and insulating layers, the stacked structure including a first side and a second side opposite to each other along the stacking direction; A gate spacer structure extends through the stacked structure along the stacking direction; wherein the ratio between the width of the gate spacer structure near the first side and the width of the gate spacer structure near the second side is 1 to 2, and the width of the gate spacer structure gradually decreases along the direction from the first side to the second side; the gate spacer structure includes two opposing spacer walls, the surface of the spacer walls is planar, and the surfaces of the two opposing spacer walls are symmetrical.

7. A storage system, characterized in that, include: The three-dimensional memory is the three-dimensional memory as described in any one of claims 1 to 6; The peripheral circuitry is coupled to the three-dimensional memory.

8. An electronic device, characterized in that, include: shell; The storage system, as described in claim 7, is disposed within the housing.

9. A method for manufacturing a three-dimensional memory, characterized in that, The method includes: A stacked structure is formed on one side of a semiconductor substrate, the stacked structure comprising alternating layers of sacrificial layers and insulating layers; A gate spacer is formed through the stacked structure; A first etching process is performed on the trench wall of at least the portion of the gate trench closest to the semiconductor substrate in a direction away from the semiconductor substrate, such that the trench width of the portion of the gate trench that has undergone the first etching process decreases in a direction away from the semiconductor substrate. The gate layer is formed by replacing the sacrificial layer with gate material through the gate trench.

10. The manufacturing method according to claim 9, characterized in that, Prior to performing a first etching process on the trench wall of at least the portion of the gate spacer closest to the semiconductor substrate, the method includes: An isolation layer is applied to the inner wall of the gate spacer. A protective layer is applied to the surface of the isolation layer away from the inner wall of the gate trench. The first etching process for the trench wall of at least the portion closest to the semiconductor substrate in the gate spacer, along a direction away from the semiconductor substrate, includes: Multiple trimming etching cycles are performed on the protective layer, the isolation layer, and the stacked structure in a direction away from the semiconductor substrate; wherein each trimming etching cycle includes trimming the protective layer and using the trimmed protective layer as a mask to etch the isolation layer and a portion of the stacked structure covered by the isolation layer.

11. The manufacturing method according to claim 10, characterized in that, The multiple trimming etching cycles performed along a direction away from the semiconductor substrate on the protective layer, the isolation layer, and the stacked structure include: Along a direction perpendicular to the semiconductor substrate, multiple areas to be etched are defined on the trench wall of the gate spacer. Along a direction away from the semiconductor substrate, the protective layer, the isolation layer, and the stacked structure in each of the areas to be etched are sequentially subjected to one trimming etching cycle.

12. The manufacturing method according to claim 11, characterized in that, The multiple trimming etching cycles performed along a direction away from the semiconductor substrate on the protective layer, the isolation layer, and the stacked structure further include: Along a direction perpendicular to the semiconductor substrate, a non-etchable region is defined on the trench wall of the gate spacer; wherein the non-etchable region is located on the side of the plurality of etchable regions away from the semiconductor substrate; Along the direction away from the semiconductor substrate, the protective layer, the isolation layer, and the stacked structure in each of the areas to be etched are sequentially subjected to one trimming etching cycle until the non-etched area is etched.

13. The manufacturing method according to claim 12, characterized in that, The method further includes performing one trimming etching cycle sequentially on the protective layer, the isolation layer, and the stacked structure in each of the areas to be etched, along a direction away from the semiconductor substrate, until the non-etchable area is reached. Remove the protective layer from the non-etched area; Remove the isolation layer from the non-etched area.

14. The manufacturing method according to any one of claims 10 to 12, characterized in that, The thickness of the isolation layer gradually decreases along the direction close to the semiconductor substrate; the thickness of the protective layer gradually decreases along the direction close to the semiconductor substrate.

15. The manufacturing method according to any one of claims 10 to 12, characterized in that, The material of the isolation layer includes oxides; the material of the protective layer includes polycrystalline silicon.

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