Array substrate, manufacturing method thereof and display panel

Abstract

The application discloses an array substrate, a manufacturing method thereof and a display panel. The array substrate comprises a display area, the display area comprises a first display area and a second display area, the first display area is arranged around the second display area, and the first display area is provided with at least part of functional modules of a gate drive circuit. The array substrate comprises a substrate, a first insulating layer located on the substrate, a plurality of grooves arranged on the first insulating layer at least in the first display area, a metal trace located in the groove, a planarization layer located on a side of the metal trace away from the substrate, and the planarization layer covers the first insulating layer, and a first electrode layer located on a side of the planarization layer away from the substrate. Compared with the prior art, the technical scheme provided by the embodiment of the application can reduce the height difference of the first electrode layer, is beneficial to the planarization of the first electrode layer, and further improves the phenomenon of optical mura.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to an array substrate, its manufacturing method, and a display panel. Background Technology

[0002] With the rapid development of display technology, the requirements for display devices are also increasing, such as ultra-narrow bezels and the need for higher screen-to-body ratios. In order to minimize the footprint of display bezels, manufacturers are working to narrow them.

[0003] Currently, narrow-bezel displays are prone to optical mura during the display process, which seriously affects the display effect. Summary of the Invention

[0004] This invention provides an array substrate, a method for manufacturing the same, and a display panel to reduce optical mura in the display panel, thereby improving the display effect of the ultra-narrow bezel display panel.

[0005] According to one aspect of the present invention, an array substrate is provided, the array substrate including a display area, the display area including a first display area and a second display area, the first display area being disposed around the second display area, the first display area being provided with at least a portion of the functional modules of a gate driving circuit, the array substrate comprising:

[0006] Substrate; a first insulating layer located on the substrate, wherein a plurality of grooves are provided on the first insulating layer at least within the first display area;

[0007] Metal traces are located within the groove;

[0008] A planarization layer is located on the side of the metal trace away from the substrate, and the planarization layer covers the first insulating layer;

[0009] The first electrode layer is located on the side of the planarization layer away from the substrate.

[0010] Optionally, the surface of the metal trace located in the groove on the side away from the substrate is flush with the surface of the first insulating layer on the side away from the substrate, so as to ensure that the first electrode layer formed on the planarization layer has a high flatness.

[0011] Optionally, the depth of the groove is 50%-90% of the thickness of the first insulating layer, which can reduce the thickness of the first insulating layer.

[0012] Optionally, the first electrode layer includes an array of first electrode blocks, each of which corresponds to a sub-pixel;

[0013] Preferably, the array further includes a buffer layer, a semiconductor layer, a second insulating layer, a gate layer, and an interlayer insulating layer stacked sequentially on the side away from the substrate, wherein the first insulating layer is disposed on the side of the interlayer insulating layer away from the substrate; preferably, the first insulating layer is reused as the interlayer insulating layer to reduce the overall thickness of the array substrate.

[0014] Optionally, it also includes a via penetrating the planarization layer, through which the first electrode layer is connected to at least a portion of the metal trace.

[0015] Optionally, the first insulating layer includes an organic film layer and / or an inorganic film layer.

[0016] According to another aspect of the present invention, a method for manufacturing an array substrate is provided, the array substrate including a display area, the display area including a first display area and a second display area, the first display area being disposed around the second display area, and the first display area being provided with at least some functional modules of a gate driving circuit;

[0017] The method for fabricating the array substrate includes:

[0018] Provide substrate;

[0019] A first insulating layer is formed on the substrate;

[0020] At least the first insulating layer located within the first display area is patterned to form a groove on the first insulating layer;

[0021] Metal traces are formed within the groove;

[0022] A planarization layer is formed on the side of the metal trace away from the substrate, and the planarization layer covers the first insulating layer;

[0023] A first electrode layer is formed on the side of the planarization layer away from the substrate.

[0024] Optionally, the step of patterning at least the first insulating layer located within the first display area to form a groove on the first insulating layer includes:

[0025] A photoresist layer is formed on the side of the first insulating layer away from the substrate, and the photoresist layer is exposed.

[0026] Using the exposed photoresist layer as a mask, the first insulating layer is etched to form the groove, and the photoresist layer is removed.

[0027] Optionally, the step of forming a metal trace within the groove includes:

[0028] A metal film layer is formed on the side of the first insulating layer away from the substrate, and the surface of the metal film layer on the side away from the substrate in the groove is flush with the surface of the first insulating layer on the side away from the substrate.

[0029] The metal film layer on the surface of the first insulating layer away from the substrate is etched to form a metal trace within the groove.

[0030] According to another aspect of the present invention, a display panel is provided, comprising an array substrate provided in any embodiment of the present invention or an array substrate prepared by any method of fabricating an array substrate according to the present invention; the display panel further comprises a light-emitting functional layer and a second electrode layer, wherein the light-emitting functional layer is located on the side of the first electrode layer away from the substrate, and the second electrode layer is located on the side of the light-emitting functional layer away from the substrate.

[0031] The technical solution provided by this invention reduces the area occupied by the pixel circuits in the first display area by compressing the pixel circuit size within the first display area while keeping the position of the first electrode layer (i.e., the pixel position) unchanged. Metal traces connect the first electrode layer and the pixel circuits, thereby reducing the area occupied by the pixel circuits in the first display area. This allows at least some functional modules of the gate driving circuit located in the non-display area to be placed in the first display area, reducing the bezel size of the non-display area and achieving an ultra-narrow bezel. Compared to the prior art, the technical solution provided by this invention provides multiple grooves on the first insulating layer located within the first display area, and metal traces within these grooves. The planarization layer and the first electrode layer are sequentially disposed on the side of the metal traces away from the substrate, thereby reducing the height difference of the first electrode layer. This facilitates planarization of the first electrode layer and improves the optical mura phenomenon.

[0032] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a top view of an array substrate in the prior art.

[0035] Figure 2 for Figure 1 A schematic diagram of the cross-sectional structure of the array substrate shown.

[0036] Figure 3 This is a top view of an array substrate provided in an embodiment of the present invention;

[0037] Figure 4 This is a schematic cross-sectional view of an array substrate provided in an embodiment of the present invention;

[0038] Figure 5 A cross-sectional view of another array substrate provided in an embodiment of the present invention;

[0039] Figure 6 for Figure 5 A partially enlarged schematic diagram of the array substrate shown.

[0040] Figure 7 for Figure 5 Another partially enlarged schematic diagram of the array substrate shown;

[0041] Figure 8 for Figure 5 Another partially enlarged schematic diagram of the array substrate shown;

[0042] Figure 9 A cross-sectional view of another array substrate provided in an embodiment of the present invention;

[0043] Figure 10 A flowchart illustrating a method for fabricating an array substrate according to an embodiment of the present invention;

[0044] Figure 11 A flowchart illustrating another method for fabricating an array substrate according to an embodiment of the present invention;

[0045] Figures 12-18 This is a schematic diagram of the structure of the array substrate corresponding to the method for manufacturing the array substrate provided in the embodiments of the present invention;

[0046] Figure 19 This is a cross-sectional structural diagram of a display panel provided in an embodiment of the present invention. Detailed Implementation

[0047] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0048] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0049] As described in the background section, ultra-narrow bezel display devices are prone to optical mura, leading to a reduction in display quality. Through long-term and careful research, the inventors discovered that the cause of this problem lies in the fact that existing technologies typically achieve ultra-narrow bezels by compressing the size of the pixel circuitry around the display area. For example, by keeping the anode position in the display area unchanged, the size of the pixel circuitry around the display area is compressed to make room for the gate drive circuitry in the non-display area. Then, the pixel circuitry is connected to the anode via an array of traces. Because the gate drive circuitry is located in the display area, the size of the non-display area can be reduced, thus achieving an ultra-narrow bezel. Figure 1 This is a top view schematic diagram of an array substrate in the prior art. Figure 2 for Figure 1 The schematic diagram of the cross-sectional structure of the array substrate shown is specifically a schematic diagram of the cross-sectional structure obtained along the cutting line NN', combined with... Figure 1 and Figure 2 The array traces 3 are formed on the substrate 1. An insulating layer 2 is disposed between the anode 4 and the array traces 3. Under normal, uncompressed conditions, the anode 4 and the array traces 3 are usually aligned. However, due to the compression of the pixel circuits in the surrounding area of ​​the display region, the film layer below the anode 4 changes, resulting in mismatch in the pattern matching of each film layer. This causes the film layer below the anode 4 to be uneven, with height differences. In other words, some array traces 3 have an anode 4 above them, while others do not. During the fabrication of the anode 4, it becomes uneven. When light from the external environment shines on the array traces 3 or the anode 4, the light reflection causes differences in the luminous intensity of the anode 4 in different directions (e.g., Figure 2 As shown in the figure, this produces the optical mura phenomenon.

[0050] To address the aforementioned problems, embodiments of the present invention provide an array substrate to improve the optical mura phenomenon in ultra-narrow bezel display devices. Figure 3 This is a top view of an array substrate provided in an embodiment of the present invention. Figure 4 This is a schematic cross-sectional view of an array substrate provided in an embodiment of the present invention, specifically... Figure 3 The cross-sectional structure of the array substrate shown is obtained along the cutting line BB', for reference. Figure 3 and Figure 4 The array substrate provided in this embodiment of the invention includes a display area AA, which includes a first display area AA1 and a second display area AA2. The first display area AA1 is disposed around the second display area AA2. The first display area AA1 is provided with at least some functional modules of a gate driving circuit. The array substrate includes: a substrate 10; a first insulating layer 20 located on the substrate 10, and a plurality of grooves 21 are provided on the first insulating layer 20 located at least within the first display area AA1; a metal trace 40 located within the grooves 21; a planarization layer 30 located on the side of the metal trace 40 away from the substrate 10, and the planarization layer 30 covers the first insulating layer 20; and a first electrode layer 50 located on the side of the planarization layer 30 away from the substrate 10.

[0051] Specifically, the array substrate includes a display area AA and a non-display area NA surrounding the display area AA. Pixel circuits composed of thin-film transistors are disposed within the display area AA to drive light-emitting elements formed on the subsequent substrate 10. The non-display area NA is used to house epitaxial circuits, which are also composed of thin-film transistors and are used to drive the pixel circuits disposed within the display area AA. For example, the epitaxial circuits include gate driving circuits composed of thin-film transistors to provide control signals to the pixel circuits. The display area AA includes a first display area AA1 and a second display area AA2, wherein the first display area AA1 is the peripheral area of ​​the display area AA, surrounding the second display area AA2. To achieve an ultra-narrow bezel, this embodiment reduces the size of the non-display area NA by compressing the pixel circuit size within the first display area AA1, thereby placing at least a portion of the functional modules of the gate driving circuit originally disposed in the non-display area NA within the first display area AA1. The functional modules of the gate driving circuit can be traces or partial transistors of the gate driving circuit, or of course, the entire gate driving circuit.

[0052] like Figure 4As shown (only the film layer within the display area AA is shown), the substrate 10 can be flexible, formed of a flexible insulating material; the substrate 10 can also be rigid, such as a glass substrate. This provides support for the subsequent fabrication of thin-film transistors. A first insulating layer 20 is formed on the substrate 10 to isolate the film layers on both sides of the first insulating layer 20. An array of thin-film transistors (not shown) is also disposed between the first insulating layer 20 and the substrate 10. A metal trace 40 and a first electrode layer 50 are disposed on the side of the first insulating layer 20 away from the substrate 10. A planarization layer 30 is disposed between the metal trace 40 and the first electrode layer 50, serving both planarization and insulation functions. The first electrode layer 50 can be an anode and is disposed within the display area AA. The metal trace 40 can be a power trace or a connection line between film layers or devices.

[0053] Because the pixel circuit size is compressed within the first display area AA1, but the pixel position (i.e., the position of the first electrode layer 50) remains unchanged—that is, the first electrode layer 50 is located within the first display area AA1 and the second display area AA2—the position of the film layer below the first electrode layer 50 (closer to the substrate 10) within the first display area AA1 changes. This means the pixel circuit size within the first display area AA1 is compressed, while the pixel circuit size within the second display area AA2 remains unchanged. Alternatively, in other embodiments, the position of the film layer below the first electrode layer 50 in both the first and second display areas AA1 and AA2 may also change, meaning the pixel circuit size in both areas is compressed. Therefore, when the pixel circuit size within the display area AA is compressed, misalignment occurs between the various film layer patterns, resulting in different film layers below the first electrode layer 50. When the metal trace 40 is formed directly above the first insulating layer 20, a height difference occurs in the film layer below the first electrode layer 50. This results in some metal traces 40 having the first electrode layer 50 above them, while some metal traces 40 do not. Consequently, the flatness of the first electrode layer 50 is poor when it is formed. When ambient light shines on the first electrode layer 50 or the metal trace 40, optical mura is likely to occur.

[0054] In this embodiment, at least a plurality of grooves 21 are provided on the first insulating layer 20 located in the first display area AA1, and the metal trace 40 is disposed in the grooves 21. Compared with the technical solution of directly fabricating the metal trace 40 on the first insulating layer 20, this embodiment can reduce the height difference of the film layer below the first electrode layer 50. When the planarization layer 30 and the first electrode layer 50 are subsequently formed, it is beneficial to ensure the flatness of the first electrode layer 50, thereby effectively solving the optical mura phenomenon caused by the unevenness of the first electrode layer 50.

[0055] It should be noted that the location of the groove 21 on the first insulating layer 20 can be set according to the actual situation. When the pixel circuit size in the first display area AA1 is compressed, a groove can be made only on the first insulating layer 20 in the first display area AA1 to reduce the height difference of the first electrode layer 50 in the first display area AA1. Since the pixel circuit in the second display area AA2 is not compressed, the position of the film pattern below the first electrode layer 50 in the second display area AA2 does not change. Therefore, the first insulating layer 20 located in the second display area AA2 does not need to be grooved, and the height difference between the first display area AA1 and the second display area AA2 can be compensated by adding a planarization layer 30.

[0056] In a preferred embodiment of this invention, the first insulating layer 20 in both the first display area AA1 and the second display area AA2 is provided with a groove 21. Since the metal traces 40 are all located in the groove 21, no matter how the pixel size is compressed, the height difference of the film layer below the first electrode layer 50 can be kept small, thereby reducing the height difference of the first electrode layer 50. When light from the external environment shines on the first electrode layer 50, the light reflected by the first electrode layer 50 can be made more uniform, thereby reducing the difference in light intensity in all directions of the first electrode layer 50, which is beneficial to improving the optical mura phenomenon.

[0057] The technical solution provided by this invention reduces the area occupied by the pixel circuits in the first display area by compressing the pixel circuit size within the first display area while keeping the position of the first electrode layer (i.e., the pixel position) unchanged. Metal traces connect the first electrode layer and the pixel circuits, thereby reducing the area occupied by the pixel circuits in the first display area. This allows at least some functional modules of the gate driving circuit located in the non-display area to be placed in the first display area, reducing the bezel size of the non-display area and achieving an ultra-narrow bezel. Compared to the prior art, the technical solution provided by this invention provides multiple grooves on the first insulating layer located within the first display area, and metal traces within these grooves. The planarization layer and the first electrode layer are sequentially disposed on the side of the metal traces away from the substrate, thereby reducing the height difference of the first electrode layer. This achieves an ultra-narrow bezel and facilitates the planarization of the first electrode layer, thus improving the optical mura phenomenon.

[0058] Optionally, since the groove depth of the groove 21 is related to the thickness of the metal trace 40, and the metal trace 40 is usually thin, by controlling the thickness of the first insulating layer 20, the depth of the groove 21 can be 50%-90% of the thickness of the first insulating layer 20. Specifically, the depth of the groove 21 can be 70%, 80%, or 90% of the thickness of the first insulating layer 20. This allows the first insulating layer 20 to achieve good insulation performance while reducing its thickness, resulting in a thinner overall film thickness of the array substrate, which is beneficial for achieving a thinner and lighter product.

[0059] In this embodiment, the thickness of the metal trace 40 can be less than, greater than, or equal to the depth of the groove 21. That is, the upper surface of the metal trace 40 can be lower than, higher than, or flush with the upper surface of the first insulating layer 20. When the upper surface of the metal trace 40 is lower than or higher than the upper surface of the first insulating layer 20, the surface of the planarization layer 30 near the first electrode layer 50 can be kept horizontal by adding a film layer to ensure the flatness of the first electrode layer 50.

[0060] Continue to refer to Figure 4 Preferably, in this embodiment, the surface of the metal trace 40 located in the groove 21 on the side away from the substrate 10 is flush with the surface of the first insulating layer 20 on the side away from the substrate 10. In other words, all the metal traces 40 are located in the groove 21, and the thickness of the metal traces 40 is the same as the depth of the groove 21. That is, the upper surface of the metal traces 40 and the upper surface of the first insulating layer 20 are on the same horizontal plane. The planarization layer 30 located above the metal traces 40 will not have "bumps", so that the first electrode layer 50 formed on the planarization layer 30 has a high flatness, effectively solving the problem of optical mura caused by the mismatch of the patterns of each film layer due to the height difference of the film layers below the first electrode layer 50.

[0061] Figure 5 This is a schematic cross-sectional view of another array substrate provided in an embodiment of the present invention, with reference to... Figure 5 Based on the above technical solution, optionally, the first electrode layer 50 includes an array of first electrode blocks 501, each first electrode block 501 corresponding to a sub-pixel.

[0062] In this embodiment, the first electrode layer 50 can adopt a three-layer structure, wherein the first and third layers can be metal oxide layers, such as indium tin oxide (ITO), indium zinc oxide (IZO), or aluminum zinc oxide (AZO), and the middle second layer can be a metal layer (such as silver or copper). A plurality of pixel circuits (not shown in the figure) are also disposed on the side of the first electrode layer 50 near the substrate 10. The pixel circuits are connected to the first electrode block 501 and are used to provide driving current and voltage to the first electrode block 501.

[0063] Figure 6 for Figure 5 A partially enlarged schematic diagram of the array substrate shown. Figure 7 for Figure 5 Another partially enlarged schematic diagram of the array substrate shown. Figure 8 for Figure 5 The diagram shows another partially enlarged structural representation of the array substrate, in which... Figures 6-8 The structure shown corresponds to Figure 5 The magnified structure at different locations within the dashed box. In the first display area AA1, when the pixel circuit size is compressed, a difference in size occurs between the metal traces 40 in the first display area AA1 and the metal traces 40 in the uncompressed second display area AA2, causing a mismatch between the first electrode layer 50 and the underlying film pattern. Furthermore, since the first electrode layer 50 is composed of arrayed first electrode blocks 501, there are instances where the metal trace 40 has a first electrode block 501 above it and instances where it does not, or instances where a portion of the same metal trace 40 has a first electrode block 501 above it (e.g.,...). Figure 6-8 (As shown). By slotting a groove 21 in the first insulating layer 20, the metal trace 40 is disposed in the groove 21 within the first display area AA1, and the surface of the metal trace 40 away from the substrate 10 is flush with the surface of the first insulating layer 20 away from the substrate 10. Therefore, the metal trace 40 will not produce "bumps" on the first insulating layer 20. During the subsequent formation of the first electrode layer 50, the flatness of the first electrode layer 50 can be guaranteed. Even if the vertical projection of a certain first electrode block 501 on the substrate 10 overlaps with the vertical projection of the metal trace 40 on the substrate 10, there will be no unevenness in the height of the first electrode blocks 501 at different positions. When light from the external environment shines on the first electrode layer 50 or the metal trace 40, the first electrode layer 50 or the metal trace 40 can uniformly reflect the light, thereby avoiding uneven light intensity above the first electrode layer 50 and improving optical mura.

[0064] Figure 9 This is a schematic cross-sectional view of another array substrate provided in an embodiment of the present invention, with reference to... Figure 9 Based on the above technical solutions, the array substrate provided in the embodiments of the present invention further includes a buffer layer 11, a semiconductor layer 101, a second insulating layer 12, a gate layer 102 and an interlayer insulating layer 13 stacked sequentially on the side away from the substrate 10, and a first insulating layer 20 disposed on the side of the interlayer insulating layer 13 away from the substrate 10.

[0065] Specifically, a buffer layer 11 for protection is formed on one side of the substrate 10, wherein the buffer layer 11 may be a film layer formed by stacking silicon nitride and / or silicon oxide. Then, a semiconductor layer 101 is formed on the side of the buffer layer 11 away from the substrate 10, and the semiconductor layer 101 is made conductive. The semiconductor layer 101, the second insulating layer 12, and the gate layer 102 together form a thin-film transistor, wherein the gate layer 102 is the gate of the thin-film transistor, and the portion of the semiconductor layer 101 not covered by the gate layer 102 forms the source and drain of the thin-film transistor and is led out through the metal trace 40. An interlayer insulating layer 13 is also provided between the gate layer 102 and the first insulating layer 20 for insulating the upper and lower plates of the storage capacitor (not shown). A via is also included in the planarization layer 30 to realize the electrical connection between the first electrode layer 50 and the metal trace 40.

[0066] Continue to refer to Figure 9 Within the first display area AA1, due to the compression of the pixel circuit, the thin-film transistor T1, which should be located below the first first electrode block 501(1), moves to below the second first electrode block 501(2). A metal trace 40 (which can be a trace corresponding to the gate drive circuit) exists below the first first electrode block 501(1). This means the film pattern below the first electrode layer 50 does not match the first electrode layer 50 correctly. However, since the metal trace 40 is located within the groove 21, and the surface of the metal trace 40 away from the substrate 10 is flush with the surface of the first insulating layer 20 away from the substrate 10, the metal trace 40 will not produce a "bump" on the first insulating layer 20. This ensures the flatness of the first electrode layer 50 during subsequent formation. In this embodiment, because the first first electrode block 501(1) and its corresponding thin-film transistor T1 are misaligned, the electrical connection between the thin-film transistor T1 and the first first electrode block 501 can be achieved through a gold wire bonding process, reducing the difficulty of creating holes in the planarization layer 30.

[0067] Furthermore, in this embodiment, the first insulating layer 20 can be the existing interlayer insulating layer 13 on the array substrate. By reusing the first insulating layer 20 as the interlayer insulating layer 13, there is no need to add a new film layer, which helps to reduce the thickness of the array substrate and reduce the difficulty of the process. The first insulating layer 20 can be an organic film layer or an inorganic film layer, or it can be a superposition of organic and inorganic film layers, which can be set according to the actual situation. Specifically, the organic film layer includes an organic adhesive layer, and the inorganic film layer includes at least one of a silicon nitride layer, a silicon oxide layer, or a silicon oxynitride layer.

[0068] It should be noted that the accompanying drawings provided in this embodiment do not show the metal trace 40 in the second display area AA2. In the second display area AA2, the metal trace 40 can be disposed in the groove or directly formed on the second insulating layer 20. This embodiment does not limit this.

[0069] Optionally, embodiments of the present invention also provide a method for manufacturing an array substrate, used to manufacture the array substrate provided in any of the above embodiments. Figure 10 This is a flowchart illustrating a method for fabricating an array substrate according to an embodiment of the present invention, in conjunction with... Figure 3 and Figure 4 The array substrate includes a display area AA, which includes a first display area AA1 and a second display area AA2. The first display area AA1 is disposed around the second display area AA2, and the first display area AA1 is provided with at least some functional modules of a gate driving circuit.

[0070] refer to Figure 10 The method for fabricating an array substrate provided in this embodiment of the invention includes:

[0071] S110 provides a substrate.

[0072] S120, A first insulating layer is formed on the substrate.

[0073] S130, at least the first insulating layer located in the first display area is patterned to form a groove on the first insulating layer.

[0074] S140, Forming metal traces within the groove.

[0075] S150. A planarization layer is formed on the side of the metal trace away from the substrate, and the planarization layer covers the first insulating layer.

[0076] S160. A first electrode layer is formed on the side of the planarization layer away from the substrate.

[0077] The technical solution provided by this invention reduces the area occupied by the pixel circuits in the first display area by compressing the pixel circuit size within the first display area while keeping the position of the first electrode layer (i.e., the pixel position) unchanged. Metal traces connect the first electrode layer and the pixel circuits, thereby reducing the area occupied by the pixel circuits in the first display area. This allows at least some functional modules of the gate driving circuit located in the non-display area to be placed in the first display area, reducing the bezel size of the non-display area and achieving an ultra-narrow bezel. Compared to the prior art, the technical solution provided by this invention provides multiple grooves on the first insulating layer located within the first display area, and metal traces within these grooves. The planarization layer and the first electrode layer are sequentially disposed on the side of the metal traces away from the substrate, thereby reducing the height difference of the first electrode layer. This facilitates planarization of the first electrode layer and improves the optical mura phenomenon.

[0078] Figure 11 The flowchart illustrates another method for fabricating an array substrate according to an embodiment of the present invention. Figures 12-18 This is a schematic diagram of the structure of the array substrate corresponding to the method for fabricating the array substrate provided in the embodiments of the present invention, combined with... Figures 11-18 The method for fabricating the array substrate provided in this embodiment includes:

[0079] S110 provides a substrate.

[0080] like Figure 12 As shown, the substrate 10 can be flexible, formed of a flexible insulating material; the substrate 10 can also be rigid, such as a glass substrate. This provides support for the subsequent fabrication of thin-film transistors.

[0081] S120, A first insulating layer is formed on the substrate.

[0082] like Figure 13 As shown, a first insulating layer 20 is deposited on one side of the substrate 10, wherein the first insulating layer 20 can be an organic film layer and / or an inorganic film layer. In this embodiment, other processes can be performed between the deposition of the first insulating layer 20, such as depositing the film layers corresponding to the thin-film transistor on the substrate 10, which will not be described in detail here.

[0083] S1301. A photoresist layer is formed on the side of the insulating layer away from the substrate, and the photoresist layer is exposed.

[0084] like Figure 14 As shown, the photoresist layer 60 is made of a photosensitive material, and its film thickness can be set according to actual needs. The photoresist layer 60 can be a positive photoresist. The photoresist layer 60 is etched using an exposure and development method to form an etching pattern. In this embodiment of the invention, a halftone mask 100 is used to expose and develop the photoresist layer 60. The halftone mask 100 includes a light-transmitting area and a light-blocking area. The light-transmitting area corresponds to the location of the first insulating layer 20 that needs to be etched. The photoresist layer 60 exposed to light will dissolve in the developing solution, while the photoresist not exposed to light will not dissolve in the developing solution, thereby achieving the etching purpose.

[0085] S1302. Using the exposed photoresist layer as a mask, etch the insulating layer to form a groove, and remove the photoresist layer.

[0086] like Figure 15 As shown, after etching the photoresist layer 60 to form a pattern, the first insulating layer 20 is etched using the exposed photoresist layer 60 as a mask to form a groove 21. The etching depth of the groove 21 can be determined by the thickness of the metal trace 40 to be set. After etching to form the groove 21, the photoresist layer 60 is etched away, resulting in... Figure 16 The array substrate structure shown.

[0087] In this embodiment, the groove 21 is at least provided in the portion of the first insulating layer 20 located within the first display area AA1, and whether the first insulating layer 20 within the second display area AA2 is grooved can be determined according to actual needs.

[0088] S1401, A metal film layer is formed on the side of the first insulating layer away from the substrate, and the surface of the metal film layer in the groove on the side away from the substrate is flush with the surface of the first insulating layer on the side away from the substrate.

[0089] like Figure 17 As shown, a metal film is formed on the side of the first insulating layer 20 where the groove 21 is formed, away from the substrate 10. The material of the metal film can be titanium, molybdenum, copper, aluminum, molybdenum-titanium alloy, or molybdenum-niobium alloy, etc., and it can be formed by sputtering, thermal evaporation, plasma-enhanced chemical vapor deposition, etc. Due to the presence of the groove 21, during the formation of the metal film, part of the metal film will be formed within the groove 21. By controlling the film thickness, the surface of the metal film in the groove 21 on the side away from the substrate 10 is made flush with the surface of the first insulating layer 20 on the side away from the substrate 10.

[0090] S1402, Etch the metal film layer on the surface of the first insulating layer away from the substrate to form a metal trace in the groove.

[0091] like Figure 18 As shown, a photolithography process is used to etch the metal film layer on the surface of the first insulating layer 20 to form the metal trace 40. Specifically, in the first display area AA1, the metal film layer on the surface of the first insulating layer 20 is etched away, thereby forming the metal trace 40 in the groove 21. The surface of the metal trace 40 away from the substrate 10 is flush with the surface of the first insulating layer 20 away from the substrate 10. In the second display area AA2, the metal film layer can be directly etched on the surface of the second insulating layer 20 to form the metal trace 40, or the metal film layer on the surface of the second insulating layer 20 can be etched away to form the metal trace 40 in the groove 21.

[0092] S150. A planarization layer is formed on the side of the metal trace away from the substrate, and the planarization layer covers the first insulating layer.

[0093] Continue to refer to Figure 18 After the metal trace 40 is formed (the metal trace 40 in the second display area AA2 is not shown in the figure), a planarization layer 30 is formed on the side of the metal trace 40 away from the substrate 10, which serves to planarize and insulate.

[0094] S160. A first electrode layer is formed on the side of the planarization layer away from the substrate.

[0095] like Figure 5As shown, after the planarization layer 30 is formed, a first electrode layer 50 is deposited on the side of the planarization layer 30 away from the substrate 10. The first electrode layer 50 can be an anode layer, and the first electrode layer 50 is patterned to form an array of first electrode blocks 501. At least within the first display area AA1, even if there are metal traces 40 below the first electrode blocks 501, there is no height difference in the film layer below the first electrode blocks 501. Therefore, the formed first electrode blocks 501 will also not have a height difference. When light from the external environment shines on the first electrode layer 50, the light reflected by the first electrode layer 50 can be made more uniform, thereby reducing the difference in light intensity in all directions of the first electrode layer 50. This is beneficial to improving the optical mura phenomenon and effectively solves the problem of reduced display effect caused by the periodic mismatch between the metal traces and other film layer patterns due to the compression of pixel circuit size (including trace size).

[0096] Optionally, embodiments of the present invention also provide a display panel, including the array substrate provided in any of the above embodiments. Figure 19 This is a cross-sectional structural diagram of a display panel provided in an embodiment of the present invention, wherein... Figure 19 Only a portion of the film structure in the display area is shown; see reference. Figure 19 The display panel also includes a light-emitting functional layer 80 and a second electrode layer 90. The light-emitting functional layer 80 is located on the side of the first electrode layer 50 away from the substrate 10, and the second electrode layer 90 is located on the side of the light-emitting functional layer 80 away from the substrate 10.

[0097] Specifically, the array substrate also includes a pixel definition layer 70 formed on the side of the first electrode layer 50 away from the substrate 10, used to define multiple pixels. The light-emitting functional layer 80 may consist of only a single film layer, i.e., only a light-emitting material layer, or it may consist of a multilayer structure formed by stacked hole injection layers, hole transport layers, light-emitting material layers, electron transport layers, electron injection layers, etc. Furthermore, the light-emitting functional layer 80 may include a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer, thereby enabling the display of multiple colors. The second electrode layer 90 may be a cathode layer, which provides voltage to the first electrode layer 50 and the second electrode layer 90 through the pixel circuit, driving the light-emitting functional layer 80 to emit light, thereby achieving the display effect.

[0098] Since the display panel provided in this embodiment of the invention includes the array substrate provided in any embodiment of the invention, the display panel also possesses the beneficial effects described in any of the above embodiments. This display panel can be applied to any electronic product with display functionality, including but not limited to the following categories: mobile phones, televisions, laptops, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, automotive displays, medical devices, industrial control equipment, touch interactive terminals, etc. This embodiment of the invention does not impose any special limitations on these categories.

[0099] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0100] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. An array substrate, characterized in that, The array substrate includes a display area, which includes a first display area and a second display area. The first display area is disposed around the second display area. The first display area is provided with at least some functional modules of a gate driving circuit. The array substrate includes: Substrate; A first insulating layer is located on the substrate, and a plurality of grooves are provided on the first insulating layer at least in the first display area; All metal traces are located within the groove; A planarization layer is located on the side of the metal trace away from the substrate, and the planarization layer covers the first insulating layer; The first electrode layer is located on the side of the planarization layer away from the substrate; The first electrode layer includes an array of first electrode blocks, each of which corresponds to a sub-pixel; The vertical projection of the first electrode block on the substrate overlaps with the vertical projection of the metal trace on the substrate, and the surface of the metal trace located in the groove on the side away from the substrate is flush with the surface of the first insulating layer on the side away from the substrate, so that the surface of the first electrode block is flush.

2. The array substrate according to claim 1, characterized in that, The depth of the groove is 50%-90% of the thickness of the first insulating layer.

3. The array substrate according to claim 1, characterized in that, It also includes a buffer layer, a semiconductor layer, a second insulating layer, a gate layer and an interlayer insulating layer stacked sequentially on the side away from the substrate, wherein the first insulating layer is disposed on the side of the interlayer insulating layer away from the substrate.

4. The array substrate according to claim 3, characterized in that, The first insulating layer is reused as the interlayer insulating layer.

5. The array substrate according to claim 1, characterized in that, It also includes vias penetrating the planarization layer, through which the first electrode layer is connected to at least a portion of the metal traces.

6. The array substrate according to claim 1, characterized in that, The first insulating layer includes an organic film layer and / or an inorganic film layer.

7. A method for fabricating an array substrate, used to prepare the array substrate according to any one of claims 1-6, characterized in that, The array substrate includes a display area, which includes a first display area and a second display area. The first display area is disposed around the second display area, and the first display area is provided with at least some functional modules of a gate driving circuit. The method for fabricating the array substrate includes: Provide substrate; A first insulating layer is formed on the substrate; At least the first insulating layer located within the first display area is patterned to form a groove on the first insulating layer; Metal traces are formed within the groove; A planarization layer is formed on the side of the metal trace away from the substrate, and the planarization layer covers the first insulating layer; A first electrode layer is formed on the side of the planarization layer away from the substrate.

8. The method for fabricating an array substrate according to claim 7, characterized in that, The step of patterning at least the first insulating layer located within the first display area to form a groove on the first insulating layer includes: A photoresist layer is formed on the side of the first insulating layer away from the substrate, and the photoresist layer is exposed. Using the exposed photoresist layer as a mask, the first insulating layer is etched to form the groove, and the photoresist layer is removed.

9. The method for fabricating an array substrate according to any one of claims 7, characterized in that, The step of forming the metal trace in the groove includes: A metal film layer is formed on the side of the first insulating layer away from the substrate, and the surface of the metal film layer on the side away from the substrate in the groove is flush with the surface of the first insulating layer on the side away from the substrate. The metal film layer on the surface of the first insulating layer away from the substrate is etched to form a metal trace within the groove.

10. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1-6 or the array substrate prepared by the method of manufacturing the array substrate as described in any one of claims 7-9; The display panel further includes a light-emitting functional layer and a second electrode layer, wherein the light-emitting functional layer is located on the side of the first electrode layer away from the substrate, and the second electrode layer is located on the side of the light-emitting functional layer away from the substrate.

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