Display panel

Abstract

The application provides a display panel, comprising: a substrate comprising a display area and a non-display area; a first transistor disposed in the non-display area, wherein the first transistor comprises an active layer; and a second metal layer comprising a first connection pad, wherein the first transistor is electrically connected to the first connection pad through a first transmission line, and the first connection pad is located outside the active layer; wherein a minimum line width of the first transmission line in a direction is less than a minimum width of the first connection pad in the direction.

Description

[0001] This application is a divisional application, specifically application number 201910951625.9. The parent application number is 201510653771.5, the application date is October 12, 2015, and the title is "Display Panel". Technical Field

[0002] This invention relates to a display panel, and more particularly to a display panel that improves the electrical properties of transistors in the non-display area. Background Technology

[0003] With the continuous advancement of display technology, all display devices are trending towards smaller size, thinner profile, and lighter weight. Therefore, the mainstream display devices on the market have evolved from the previous cathode ray tubes to thin displays, such as liquid crystal displays (LCDs) or organic light-emitting diode (OLED) displays. LCDs and OLEDs have a wide range of applications; most everyday devices such as mobile phones, laptops, cameras, music players, mobile navigation devices, and televisions use these display panels.

[0004] Although liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays are common in the market, especially LCD technology which is quite mature, manufacturers are striving to develop displays with even higher quality as display devices continue to evolve and consumers demand higher display quality. In addition to the thin-film transistor (TFT) structure in the display area, the TFT element structure used in the gate drive circuit area outside the display area is also a factor affecting the overall efficiency of the display device.

[0005] Therefore, even though LCD or OLED displays are already common in the market, improvements are still needed in the gate drive circuit area in the non-display area in order to develop display devices with better display quality to meet consumer needs. Summary of the Invention

[0006] The main objective of this invention is to provide a display panel in which no transparent conductive layer is disposed above the transistor in the gate driving circuit area, so as to avoid the top gate effect and thereby improve the switching and operating characteristics of the transistor.

[0007] The display panel provided by the present invention includes: a substrate comprising a display area and a non-display area; a first transistor disposed in the non-display area, the first transistor comprising an active layer disposed on the substrate; and a transparent conductive layer disposed in the non-display area, wherein the transparent conductive layer comprises an opening disposed above the active layer, and the area of ​​the opening is larger than the area of ​​the active layer.

[0008] In the display panel of the present invention, it is preferable that the opening fully exposes the active layer.

[0009] In the display panel of the present invention, the first transistor further includes a gate electrode disposed on the substrate, wherein the opening includes a first edge and a second edge, the gate electrode includes a third edge and a fourth edge, wherein the first edge and the third edge are located in the extension direction of the width of the channel region of the active layer and the first edge is adjacent to the third edge, and the second edge and the fourth edge are located in the extension direction of the length of the channel region of the active layer and the second edge is adjacent to the fourth edge, wherein the minimum distance between the first edge and the third edge is greater than the minimum distance between the second edge and the fourth edge.

[0010] In the display panel of the present invention, the opening includes a first edge and a second edge, the active layer includes a fifth edge and a sixth edge, wherein the first edge and the fifth edge are located in the direction of extending the width of the channel region of the active layer and the first edge is adjacent to the fifth edge, and the second edge and the sixth edge are located in the direction of extending the length of the channel region of the active layer and the second edge is adjacent to the sixth edge, wherein the minimum distance between the first edge and the fifth edge is greater than the minimum distance between the second edge and the sixth edge.

[0011] In the display panel of the present invention, the first transistor is electrically connected to a first pad via a first transmission line, wherein the line width of the first transmission line is smaller than the width of the first pad.

[0012] In the display panel of the present invention, the display panel may further include a second transistor disposed in the non-display area, the second transistor being electrically connected to a second pad via a second transmission line, wherein the line width of the second transmission line is smaller than the width of the second pad, and wherein the second pad is electrically connected to the first pad.

[0013] In the display panel of the present invention, the first transistor further includes: an insulating layer disposed on the active layer, the insulating layer including a hole; and a first conductive electrode disposed on the insulating layer and electrically connected to the active layer through the hole, wherein the maximum length of the hole in the extension direction of the width of the channel region corresponding to the active layer is greater than the maximum length in the extension direction of the length of the channel region corresponding to the active layer.

[0014] In the display panel of the present invention, the first transistor further includes: a gate electrode disposed on the substrate and the active layer disposed on the gate electrode, the gate electrode including a third edge, and the length direction of the third edge being substantially the same as the extension direction of the channel region of the active layer; an insulating layer disposed on the active layer, the insulating layer including a hole; and a first conductive electrode disposed on the insulating layer and electrically connected to the active layer through the hole; wherein the first conductive electrode located above the hole has a first width, the first conductive electrode located above the third edge has a second width, and the first width is greater than the second width.

[0015] Furthermore, in the display panel of the present invention, the extension direction of the length of the channel region of the active layer is the carrier movement direction of the channel region, and the extension direction of the width of the channel region of the active layer is a direction perpendicular to the carrier movement direction of the channel region.

[0016] Furthermore, in the display panel of the present invention, the active layer comprises a metal oxide.

[0017] In the display panel of the present invention, in the gate driving circuit region of the non-display area, an opening is provided in the transparent conductive layer above the active layer of the transistor, wherein the area of ​​the opening is larger than the area of ​​the active layer, and in particular, the opening completely exposes the active layer; thus, the top-gate effect caused by the transparent conductive layer above the active layer can be avoided, thereby improving the switching and operating characteristics of the transistor in the gate driving circuit region. Furthermore, the carrier transport in the transistor channel region is also affected by the transparent conductive layer above the transistor; therefore, one edge of the opening in the transparent conductive layer is designed to be relatively far from the channel region, with its length direction substantially the same as the carrier movement direction. This avoids the top-gate effect generated between the transparent conductive layer and the active layer from affecting the operation of the channel region, thereby further improving the switching and operating characteristics of the transistor. Attached Figure Description

[0018] Figure 1 This is a cross-sectional schematic diagram of a display panel according to a preferred embodiment of the present invention.

[0019] Figure 2A and 2B This is a top view of the gate driving circuit area of ​​the non-display area of ​​a display panel according to a preferred embodiment of the present invention.

[0020] Figure 2C and 2D This is a partially enlarged view of the gate driving circuit area of ​​the non-display area of ​​a display panel according to a preferred embodiment of the present invention.

[0021] Figure 3 This is a cross-sectional schematic diagram of the first transistor in the non-display area of ​​a display panel according to a preferred embodiment of the present invention.

[0022] Figure 4 This is a cross-sectional schematic diagram of the first and second pads in the non-display area of ​​a display panel according to a preferred embodiment of the present invention.

[0023] Figure 5 This is a top view of the gate driving circuit area of ​​the non-display area of ​​the display panel, which is another preferred embodiment of the present invention.

[0024] Figure 6 This is a cross-sectional schematic diagram of the first transistor in the non-display area of ​​the display panel, which is another preferred embodiment of the present invention.

[0025] Figure 7 This is a top view of the gate driving circuit area of ​​the non-display area of ​​the display panel, which is another preferred embodiment of the present invention.

[0026] Figure 8 This is a schematic diagram of the display device of the present invention.

[0027] [Explanation of Labels in the Attached Image]

[0028] 1-First substrate

[0029] 10-First Transistor

[0030] 101-First Transmission Line

[0031] 102-First joint pad

[0032] 11-Substrate

[0033] 12-Gate electrode

[0034] 121-Third Edge

[0035] 122-Fourth Edge

[0036] 123-Seventh Edge

[0037] 13-Gate insulating layer

[0038] 131, 151 - Holes

[0039] 14, 24 - Active Layer

[0040] 141-The Fifth Edge

[0041] 142-Sixth Edge

[0042] 15-Insulation layer

[0043] 161, 261 - First conductive electrode

[0044] 162, 262 - Second conductive electrode

[0045] 163-Ditch Area

[0046] 17-Protective Layer

[0047] 18-Transparent conductive layer

[0048] 181, 281 - Opening

[0049] 1811 - First Edge

[0050] 1812 - Second Edge

[0051] 1813 - opposite edge

[0052] 2-Second substrate

[0053] 20-Second transistor

[0054] 201-Second Transmission Line

[0055] 202-Second joint pad

[0056] 263-Third conductive electrode

[0057] 3-Tablet PC

[0058] AA -- Display Area

[0059] B - Non-display area

[0060] L1, L2, L3, L4 - Distance

[0061] L5, L6 - Length

[0062] W1, W3 - Line width

[0063] W2, W4 - Width

[0064] W5 - First Width

[0065] W6 - Second Width

[0066] W7 - Third Width

[0067] W8 - Fourth Width

[0068] X, Y - extension direction Detailed Implementation

[0069] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0070] Figure 1This is a cross-sectional schematic diagram of a display panel according to a preferred embodiment of the present invention. The display panel of this embodiment includes: a first substrate 1; a second substrate 2; and a display layer 3 sandwiched between the first substrate 1 and the second substrate 2. The first substrate 1 may be a thin-film transistor substrate with thin-film transistor units (not shown) disposed on it, and the second substrate 2 may be a color filter substrate with a color filter layer (not shown) disposed on it; however, in other embodiments of the present invention, the color filter layer (not shown) may also be disposed on the first substrate 1, in which case the first substrate 1 is a thin-film transistor substrate (color filter on array, COA) integrating a color filter array. Furthermore, the display layer 3 in the display panel of this embodiment may be a liquid crystal layer or an organic light-emitting diode element layer.

[0071] like Figure 1 As shown, the display panel of this embodiment includes a display area AA and a non-display area B; the non-display area B is disposed around the display area AA. Next, the design of the gate drive circuit area on the non-display area B will be described in detail.

[0072] Figure 2A and 2B This is a top view of the gate driving circuit area of ​​the non-display area of ​​a display panel according to a preferred embodiment of the present invention, wherein... Figure 2A and Figure 2B For the same view, and for the convenience of later explanations, Figure 2B It is Figure 2A Remove the section lines in the image; Figure 2C and Figure 2D for Figure 2A and Figure 2B Enlarged view of part of the image; Figure 3 For along Figure 2A A cross-sectional view of a transistor along the A-A' section line; and Figure 4 Then it is along Figure 2A A schematic diagram of the cross-sections of the first and second pads along section line B-B'.

[0073] like Figure 2A , Figure 3 and Figure 4As shown, firstly, a substrate 11 is provided, and a first metal layer including a gate electrode 12 and a second pad 202 is formed on the substrate 11. Then, a gate insulating layer 13 is formed on the first metal layer, wherein the gate insulating layer 13 corresponding to the second pad 202 has a hole 131 to expose a portion of the second pad 202. After forming the gate insulating layer 13, an active layer 14, 24 corresponding to the gate electrode 12 is formed on the gate insulating layer 13 in the region where the first transistor 10 and the second transistor 20 are to be formed. Then, an insulating layer 15 is formed on the active layers 14, 24 and the gate insulating layer 13, and the insulating layer 15 includes a hole 151 to expose a portion of the active layers 14, 24. Next, a second metal layer is formed on the insulating layer 15, including first conductive electrodes 161, 261, second conductive electrodes 162, 262, third conductive electrode 263, and a first pad 102. Adjacent first conductive electrodes 161, 261, 162, 262, and 263 are spaced a predetermined distance to form a channel region 163, and the first conductive electrodes 161, 261, 162, 262, and 263 are electrically connected to the active layers 14, 24. The first pad 102 is electrically connected to the second pad 202. Furthermore, the first conductive electrode 161 serves as a source, and the second conductive electrode 162 serves as a drain. Subsequently, a protective layer 17 is formed on the insulating layer 15 and the second metal layer including the first conductive electrodes 161, 261, the second conductive electrodes 162, 262, the third conductive electrode 263, and the first pad 102. A transparent conductive layer 18 is formed on the protective layer 17, and the transparent conductive layer 18 has an opening 181, 281 corresponding to the active layers 14, 24. After the above steps, the fabrication of the gate driving circuit area in the non-display area of ​​the display panel of this embodiment is completed.

[0074] In this embodiment, the substrate 11 can be made of a substrate material such as glass, plastic, or flexible material; the first metal layer and the second metal layer can be made of conductive materials such as metals, alloys, metal oxides, metal nitrides, or other electrode materials; the gate insulating layer 13, the insulating layer 15, and the protective layer 17 can be made of oxides (e.g., silicon oxide SiO2). x ), nitrides (e.g., silicon nitride SiN) x The insulating layer 14 and 24 may be made of insulating materials such as aluminum oxide or oxynitride; the active layers 14 and 24 may contain metal oxide materials such as IGZO, and the metal may include indium, gallium, zinc, tin, aluminum, or combinations thereof; while the transparent conductive layer 18 may be made of transparent conductive electrode materials such as ITO, IZO, or ITZO. However, in other embodiments of the present invention, the materials of the aforementioned elements are not limited to these.

[0075] like Figure 1 , Figure 2A and Figure 3 As shown, the display panel obtained in this embodiment includes: a substrate 11, comprising a display area AA and a non-display area B; a first transistor 10 disposed in the non-display area B, the first transistor 10 including an active layer 14 disposed on the substrate 1; and a transparent conductive layer 18 disposed in the non-display area B, wherein the transparent conductive layer 18 includes an opening 181 disposed above the active layer 14, and the area of ​​the opening 181 is larger than the area of ​​the active layer 14. Furthermore, the display panel of this embodiment also includes: a second transistor 20 disposed on the non-display area B, and including an active layer 24; wherein the transparent conductive layer 18 includes an opening 281 disposed above the active layer 24, and the area of ​​the opening 281 is also larger than the area of ​​the active layer 24. In particular, the openings 181 and 281 of the transparent conductive layer 18 completely expose the active layers 14 and 24, respectively. Here, the transparent conductive layer 18 of the non-display area B and the common electrode layer (not shown in the figure) of the display area AA are the same layer, so that the potential of the common electrode layer (not shown in the figure) is the ground potential.

[0076] In the display panel of this embodiment, in the gate driving circuit area of ​​the non-display area B, an opening 181, 281 is provided on the transparent conductive layer 18 above the active layers 14, 24 of the first transistor 10 and the second transistor 20, respectively. The area of ​​the opening 181, 281 is larger than the area of ​​the active layers 14, 24. In particular, the opening 181, 281 can completely expose the active layers 14, 24. In this way, the top gate effect can be avoided due to the transparent conductive layer 18 above the active layers 14, 24, thereby improving the switching and operating characteristics of the first transistor 10 and the second transistor 20 in the gate driving circuit area.

[0077] In this embodiment, the first transistor 10 and the second transistor 20 have similar designs, except that the first transistor 10 includes two conductive electrodes (first conductive electrode 161 and second conductive electrode 162), while the second transistor 20 includes five conductive electrodes (first conductive electrode 261, second conductive electrode 262, and three third conductive electrodes 263). However, in other embodiments of the present invention, the number of conductive electrodes on the first transistor 10 and the second transistor 20 is not limited to the following. Figure 2AAs shown, it is sufficient that the first transistor 10 and the second transistor 20 each include at least two conductive electrodes serving as source and drain. Furthermore, in this embodiment and other embodiments of the present invention, unless otherwise specified, the second transistor 20 has similar structural features to the first transistor 10, and the relationship between the active layers 14, 24 and the openings 181, 281 of the transparent conductive layer 18 is also similar in both the first transistor 10 and the second transistor 20. Therefore, in this embodiment, since the first transistor 10 and the second transistor 20 have similar structural features, only the first transistor 10 is used as an example for explanation.

[0078] like Figures 2A to 2C As shown, where, Figure 2C for Figure 2A and Figure 2B A magnified view of the first transistor 10 in the non-display area of ​​the display panel in this embodiment shows that the first transistor 10 includes a gate electrode 12 disposed on the substrate 11 (e.g., ...). Figure 3 As shown, the opening 181 includes a first edge 1811 and a second edge 1812, and the gate electrode 12 includes a third edge 121 and a fourth edge 122. The first edge 1811 and the third edge 121 are located in the extension direction Y of the width of the channel region 163 of the active layer 14, and the first edge 1811 is adjacent to the third edge 121. The second edge 1812 and the fourth edge 122 are located in the extension direction X of the length of the channel region 163 of the active layer 14, and the second edge 1812 is adjacent to the fourth edge 122. The minimum distance L1 between the first edge 1811 and the third edge 121 is greater than the minimum distance L2 between the second edge 1812 and the fourth edge 122. In this embodiment, the "extension direction X of the length of the channel region 163 of the active layer 14" is the carrier movement direction of the channel region 163, while the "extension direction Y of the width of the channel region 163 of the active layer 14" is a direction perpendicular to the carrier movement direction of the channel region 163.

[0079] In addition, such as Figures 2A to 2C As shown, in the non-display area of ​​the display panel in this embodiment, the active layer 14 includes a fifth edge 141 and a sixth edge 142. The fifth edge 141 is located in the extension direction Y of the width of the channel region 163 of the active layer 14 and is adjacent to the first edge 1811. The sixth edge 142 is located in the extension direction X of the length of the channel region 163 of the active layer 14 and is adjacent to the second edge 1812. The minimum distance L3 between the first edge 1811 and the fifth edge 141 is greater than the minimum distance L4 between the second edge 1812 and the sixth edge 142.

[0080] In this embodiment, the carrier transfer in the channel region 163 of the first transistor 10 is affected by the transparent conductive layer 18 above the first transistor 10 (e.g., Figure 3 (As shown) has an impact; therefore, the transparent conductive layer 18 (as shown) Figure 3 The first edge 1811 of the opening 181 (as shown) is designed to be relatively far from the channel region 163, wherein the length direction of the first edge 1811 is substantially the same as the carrier movement direction. More specifically, in this embodiment, the minimum distance L1 between the first edge 1811 of the opening 181 and the third edge 121 of the gate electrode 12 is designed to be greater than the minimum distance L2 between the second edge 1812 of the opening 181 and the fourth edge 122 of the gate electrode 12; and the minimum distance L3 between the first edge 1811 of the opening 181 and the fifth edge 141 of the active layer 14 is designed to be greater than the minimum distance L4 between the second edge 1812 of the opening 181 and the sixth edge 142 of the active layer 14. In this way, the transparent conductive layer 18 (such as...) can be made more transparent. Figure 3 The spacing between the transparent conductive layer 18 (as shown) and the channel region 163 is increased to avoid the transparent conductive layer 18 (as shown) from being damaged by the increased spacing between the transparent conductive layer 18 and the channel region 163. Figure 3 (As shown) being too close to the channel region 163 would affect electron transmission within the channel region 163, and prevent the transparent conductive layer 18 (as shown) from being too close to the channel region 163, thus affecting electron transmission within the channel region 163, and preventing the transparent conductive layer 18 (as shown) from being too close to the channel region 163. Figure 3 The top-gate effect generated between the active layer 14 and the transparent conductive layer 18 (as shown) affects the operation of the channel region 163, thereby further improving the switching and operating characteristics of the first transistor 10. Here, only the transparent conductive layer 18 (as shown) is used. Figure 3 The first edge 1811 of the opening 181 (as shown) will be explained, and the relationship between the opposite edge 1813 and the gate electrode 12 and the active layer 14 is the same as that of the first edge 1811, so it will not be described again here.

[0081] like Figures 2A to 2C As shown, the length direction of the third edge 121 of the gate electrode 12 in the first transistor 10 is substantially the same as the extension direction X of the channel region 163 of the active layer 14, that is, the length direction of the third edge 121 is parallel to the extension direction X of the channel region 163 or the angle between them is less than 5 degrees; the insulating layer 15 (such as Figure 3 (As shown) is disposed on the active layer 14 and includes a hole 151; and the first conductive electrode 161 is disposed on the insulating layer 15 (as shown). Figure 3As shown, the active layer 14 is electrically connected to the gate electrode 12 via a hole 151. The first conductive electrode 161 located at the third edge 121 of the gate electrode 12 has a recessed structure compared to the first conductive electrode 161 at the hole 151. More specifically, the first conductive electrode 161 above the hole 151 has a first width W5, and the first conductive electrode 161 above the third edge 121 has a second width W6, with the first width W5 being greater than the second width W6. The second conductive electrode 262 does not have a recessed design.

[0082] When the first conductive electrode 161 at the third edge 121 of the gate electrode 12 has a concave structure, since the first conductive electrode 161 is simultaneously connected to the signal transmission line for signal input and output, its overlap with the gate electrode 12 is designed to include at least one notch to reduce the resistive-capacitive load (RC loading) of the first conductive electrode 161 in transmitting signals. As for the second conductive electrode 262, since it is not simultaneously connected to the signal transmission line for signal input and output, its overlap with the gate electrode 12 is not designed with a notch; however, the present invention is not limited to this. When the second conductive electrode 262 is also simultaneously connected to the signal transmission line for signal input and output, its overlap with the gate electrode 12 preferably also includes a notch.

[0083] like Figure 2A , Figure 2B and Figure 2D As shown, where, Figure 2D for Figure 2A and Figure 2B The enlarged view shows a portion of the regions of the first pad 102 and the second pad 202. The first transistor 10 is electrically connected to the first pad 102 via a first transmission line 101, where the linewidth W1 of the first transmission line 101 is smaller than the width W2 of the first pad 102. Similarly, the second transistor 20 is electrically connected to the second pad 202 via a second transmission line 201, where the linewidth W3 of the second transmission line 201 is smaller than the width W4 of the second pad 202. Here, the second pad 202 is electrically connected to the first pad 102. Figure 2B and Figure 4 As shown, since the first pad 102 and the second pad 202 are electrically connected through the hole 131, in order to form the hole 131, the widths W2 and W4 of the first pad 102 and the second pad 202 are designed to be greater than the line widths W1 and W3 of the first transmission line 101 and the second transmission line 201, respectively.

[0084] In addition, such as Figures 2A to 2C As shown, the insulating layer 15 disposed on the active layer 14 (such as...) Figure 3The diagram shows a hole 151, through which a first conductive electrode 261 and a second conductive electrode 262 disposed on an insulating layer 15 are electrically connected to the active layer 14. The maximum length L5 of the hole 151 in the Y direction extending from the width of the channel region 163 of the active layer 14 is greater than the maximum length L6 in the X direction extending from the length of the channel region 163 of the active layer 14. More specifically, the maximum length L5 of the hole 151 perpendicular to the carrier transport direction is greater than the maximum length L6 parallel to the carrier transport direction. Therefore, the carrier transport distance can be shortened, and the area capable of transmitting carriers can be increased, thereby improving the electron transport efficiency of the active layer 14.

[0085] Figure 5 This is a top view of the gate driving circuit area of ​​the non-display area of ​​the display panel according to another preferred embodiment of the present invention; and Figure 6 For along Figure 5 A cross-sectional view of the transistor along the A-A' section line. The display panel of this embodiment is the same as the aforementioned display panel, except that the display panel of this embodiment does not include the insulating layer 15 and the hole 151.

[0086] Figure 7 This is a top view of the gate driving circuit area of ​​the non-display area of ​​the display panel according to another preferred embodiment of the present invention, and the transparent conductive layer and its holes are not shown here. The display panel of this embodiment is the same as the aforementioned display panel, except that both the first conductive electrode 161 and the second conductive electrode 162 are simultaneously connected to the signal transmission lines for signal input and output, so the overlap between them and the gate electrode 12 is designed to include at least one notch. More specifically, the first conductive electrode 161 located above the hole 151 has a first width W5, the first conductive electrode 161 located above the third edge 121 has a second width W6, and the first width W5 is greater than the second width W6; while the second conductive electrode 162 located above the hole 151 has a third width W7, and the first conductive electrode 161 located above the seventh edge 123 (which is disposed opposite to the third edge 121) has a fourth width W8, and the third width W7 is greater than the fourth width W8.

[0087] In this invention, the display panel obtained in the foregoing embodiments can be applied to liquid crystal display panels or organic light-emitting diode display panels. Furthermore, the display panel obtained in the foregoing embodiments can also be used in conjunction with a touch panel to form a touch display device. Simultaneously, the display panel or touch display device obtained in the foregoing embodiments of this invention can be applied to any electronic device known in this art that requires a display screen, such as... Figure 8 On the tablet computer 3 shown, or on other electronic devices that need to display images, such as monitors, mobile phones, laptops, cameras, camcorders, music players, mobile navigation devices, televisions, etc.

[0088] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A display panel, characterized in that, Include: A substrate comprising a display area and a non-display area; A first transistor is disposed in the non-display area, wherein the first transistor includes an active layer; A second metal layer includes a first pad, wherein the first transistor is electrically connected to the first pad via a first transmission line, and the first pad is located outside the active layer. A second pad, overlapping the first pad; A second transistor is disposed in the non-display area, wherein the second transistor is electrically connected to the second pad via a second transmission line; and An insulating layer is disposed between the first pad and the second pad and includes a hole, wherein the first pad and the second pad are electrically connected through the hole; The minimum linewidth of the first transmission line along a certain direction is less than the minimum width of the first pad along that direction.

2. The display panel according to claim 1, characterized in that, The minimum linewidth is located between the active layer and the first pad.

3. The display panel according to claim 1, characterized in that, The first transmission line has different line widths on both sides adjacent to the first pad.

4. The display panel according to claim 1, characterized in that, The first transistor further includes at least three conductive electrodes.

5. The display panel according to claim 4, characterized in that, At least one of the at least three conductive electrodes has a concave structure.

6. The display panel according to claim 1, characterized in that, The display panel further includes a first metal layer, an insulating layer disposed between the first metal layer and the second metal layer, and the second metal layer is electrically connected to the first metal layer through the hole.

7. The display panel according to claim 1, characterized in that, The display panel also includes a first metal layer, and the first metal layer includes the second pad.

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