Semiconductor device

Abstract

The present disclosure relates to a semiconductor device including: a semiconductor substrate including an impurity region; and a wiring layer including: a first wiring connected to the impurity region; a second wiring; and a first hollow region, wherein the first hollow region is provided between the first wiring and the second wiring.

Description

[0001] This application is a divisional application of patent application No. 201680015741.4, filed on March 17, 2016, entitled "Solid-State Image Capture Element and Electronic Device". Technical Field

[0002] This disclosure relates to a solid-state image capture element and an electronic device, and more particularly to a solid-state image capture element and electronic device capable of reducing capacitance by using a hollow region. Background Technology

[0003] In complementary metal-oxide-semiconductor (CMOS) image sensors, as pixel miniaturization continues, the aperture area of ​​photodiodes decreases, and sensitivity declines. Furthermore, the size of pixel transistors shrinks, and random noise worsens. Consequently, the signal-to-noise ratio (S / N) decreases, and image quality deteriorates.

[0004] Therefore, it has been proposed to improve the signal-to-noise ratio by reducing the parasitic capacitance of floating diffusion (FD) and improving the charge-to-voltage conversion efficiency.

[0005] The parasitic capacitances of the FD include the diffusion capacitance of the FD, the capacitance connected to the gate electrode of the amplifying transistor through the FD wiring, the capacitance of the FD wiring itself, and any other capacitances. The diffusion capacitance of the FD can be reduced by decreasing the concentration of N-type impurities in the FD. However, in this case, there is a concern about contact failure.

[0006] The gate capacitance of an amplifying transistor can be reduced by decreasing its size. However, when the size of the amplifying transistor is reduced, random noise is exacerbated.

[0007] Furthermore, the capacitance of the FD wiring can be reduced to some extent by designing the wiring layout. However, because the FD needs to be connected to the amplifying transistor, and in a pixel-based shared system, this wiring layout is limited. Therefore, reducing the capacitance of the FD wiring through wiring layout design is difficult.

[0008] Therefore, a method has been proposed to reduce the capacitance of FD wiring by making the entire periphery of the wiring layer a low dielectric constant film (e.g., refer to PTL 1).

[0009] [List of Citations]

[0010] [Patent Literature]

[0011] [PTL 1]

[0012] JP 2009-231501A Summary of the Invention

[0013] [Technical Issues]

[0014] As a method to reduce capacitance, it is desirable to use a method different from that described in PTL 1.

[0015] This disclosure takes such a scenario into account and makes it possible to reduce capacitance by using a hollow region.

[0016] [Solution to the problem]

[0017] According to one aspect of this disclosure, a solid-state image capture element is such that at least a portion of the region between the FD wiring connected to the floating diffusion node and wiring other than the FD wiring is a hollow region.

[0018] An electronic device according to one aspect of the present disclosure corresponds to a solid-state image capture element of that aspect of the present disclosure.

[0019] According to one aspect of this disclosure, at least a portion of the area between the FD wiring connected to the floating diffusion node and wiring other than the FD wiring is a hollow area.

[0020] [Beneficial Effects of the Invention]

[0021] According to one aspect of this disclosure, capacitance can be reduced. Furthermore, according to one aspect of this disclosure, capacitance can be reduced by using a hollow region.

[0022] The beneficial effects described in this disclosure are not necessarily limited and can be any of the effects described in this disclosure. Attached Figure Description

[0023] [ Figure 1 ]

[0024] Figure 1 This is a schematic diagram illustrating a configuration example of a CMOS image sensor as a solid-state image capture element according to a first embodiment of the present disclosure.

[0025] [ Figure 2 ]

[0026] Figure 2 To show in Figure 1 A schematic diagram of a circuit configuration example for one pixel in a two-dimensional arrangement of pixels in a pixel region.

[0027] [ Figure 3 ]

[0028] Figure 3 This is a schematic diagram illustrating a first structural example of a CMOS image sensor.

[0029] [ Figure 4]

[0030] Figure 4 This is a schematic diagram illustrating a second structural example of a CMOS image sensor.

[0031] [ Figure 5 ]

[0032] Figure 5 This is a schematic diagram illustrating a third structural example of a CMOS image sensor.

[0033] [ Figure 6 ]

[0034] Figure 6 This is a schematic diagram illustrating a fourth structural example of a CMOS image sensor.

[0035] [ Figure 7 ]

[0036] Figure 7 This is a schematic diagram illustrating an example of the circuit configuration of pixels in a CMOS image sensor according to a second embodiment of the present disclosure.

[0037] [ Figure 8 ]

[0038] Figure 8 This is a view illustrating an example of the layout of various parts of a CMOS image sensor according to a third embodiment.

[0039] [ Figure 9 ]

[0040] Figure 9 From the perspective of the wiring layer Figure 8 A plan view of the first structural instance of the pixel region in the image.

[0041] [ Figure 10 ]

[0042] Figure 10 Including along Figure 9 The sectional view obtained by cutting along A-A' and along Figure 9 A sectional view obtained by cutting along line B'.

[0043] [ Figure 11 ]

[0044] Figure 11 For the purpose of illustrating manufacturing Figure 9 and Figure 10 A schematic diagram of the method for using a semiconductor substrate.

[0045] [ Figure 12 ]

[0046] Figure 12 For the purpose of illustrating manufacturing Figure 9 and Figure 10 A schematic diagram of the method for using a semiconductor substrate.

[0047] [ Figure 13 ]

[0048] Figure 13 For the purpose of illustrating manufacturing Figure 9 and Figure 10 A schematic diagram of the method for using a semiconductor substrate.

[0049] [ Figure 14 ]

[0050] Figure 14 For the purpose of illustrating manufacturing Figure 9 and Figure 10 A schematic diagram of the method for using a semiconductor substrate.

[0051] [ Figure 15 ]

[0052] Figure 15 For along Figure 9 A-A' cut Figure 8 A cross-sectional view of a second structural instance in the middle pixel region.

[0053] [ Figure 16 ]

[0054] Figure 16 For the purpose of illustrating manufacturing Figure 15 A schematic diagram of the method for using a semiconductor substrate.

[0055] [ Figure 17 ]

[0056] Figure 17 For the purpose of illustrating manufacturing Figure 15 A schematic diagram of the method for using a semiconductor substrate.

[0057] [ Figure 18 ]

[0058] Figure 18 For the purpose of illustrating manufacturing Figure 15 A schematic diagram of the method for using a semiconductor substrate.

[0059] [ Figure 19 ]

[0060] Figure 19 For the purpose of illustrating manufacturing Figure 15 A schematic diagram of the method for using a semiconductor substrate.

[0061] [ Figure 20 ]

[0062] Figure 20 For along Figure 9 A-A' cut Figure 8A cross-sectional view of another second structural instance in the middle pixel region.

[0063] [ Figure 21 ]

[0064] Figure 21 For along Figure 9 A-A' cut Figure 8 A cross-sectional view of the third structural instance in the middle pixel region.

[0065] [ Figure 22 ]

[0066] Figure 22 For the purpose of illustrating manufacturing Figure 21 A schematic diagram of the method for using a semiconductor substrate.

[0067] [ Figure 23 ]

[0068] Figure 23 For the purpose of illustrating manufacturing Figure 21 A schematic diagram of the method for using a semiconductor substrate.

[0069] [ Figure 24 ]

[0070] Figure 24 This is a schematic diagram illustrating other structural examples of the hollow region between the FD wiring and the semiconductor substrate.

[0071] [ Figure 25 ]

[0072] Figure 25 For the purpose of illustrating manufacturing Figure 8 A schematic diagram of the first method using a CMOS image sensor.

[0073] [ Figure 26 ]

[0074] Figure 26 For the purpose of illustrating manufacturing Figure 8 A schematic diagram of the first method using a CMOS image sensor.

[0075] [ Figure 27 ]

[0076] Figure 27 For the purpose of illustrating manufacturing Figure 8 A schematic diagram of the first method using a CMOS image sensor.

[0077] [ Figure 28 ]

[0078] Figure 28 For the purpose of illustrating manufacturing Figure 8 A schematic diagram of a second method using a CMOS image sensor.

[0079] [ Figure 29 ]

[0080] Figure 29 For the purpose of illustrating manufacturing Figure 8 A schematic diagram of a second method using a CMOS image sensor.

[0081] [ Figure 30 ]

[0082] Figure 30 For the purpose of illustrating manufacturing Figure 8 A schematic diagram of a second method using a CMOS image sensor.

[0083] [ Figure 31 ]

[0084] Figure 31 For the purpose of illustrating manufacturing Figure 8 A schematic diagram of a second method using a CMOS image sensor.

[0085] [ Figure 32 ]

[0086] Figure 32 This is a schematic diagram illustrating other structural examples of the hollow region surrounding a through-silicon via (TSV).

[0087] [ Figure 33 ]

[0088] Figure 33 This is a plan view illustrating the arrangement of the hollow regions in the CMOS image sensor according to the fourth embodiment.

[0089] [ Figure 34 ]

[0090] Figure 34 To show Figure 33 Schematic diagram of other shapes of the hollow area around the FD wiring.

[0091] [ Figure 35 ]

[0092] Figure 35 A plan view showing an example of the shape of the hollow region formed around the TSV.

[0093] [ Figure 36 ]

[0094] Figure 36 A block diagram illustrating a configuration example of an image capture device as an electronic device according to this disclosure.

[0095] [ Figure 37 ]

[0096] Figure 37This is a schematic diagram illustrating an example of the use of the aforementioned CMOS image sensor. Detailed Implementation

[0097] The following describes a mode for implementing the present invention (hereinafter referred to as an embodiment). This description will be performed in the following order.

[0098] 1. First implementation method: CMOS image sensor ( Figures 1 to 6 )

[0099] 2. Second implementation method: CMOS image sensor ( Figure 7 )

[0100] 3. Third implementation method: CMOS image sensor ( Figures 8 to 32 )

[0101] 4. Fourth implementation method: CMOS image sensor ( Figures 33 to 35 )

[0102] 5. Fifth implementation method: Electronic device ( Figure 36 )

[0103] 6. Examples of using CMOS image sensors ( Figure 37 )

[0104] <First Implementation Method>

[0105] (Configuration example of a CMOS image sensor according to the first embodiment)

[0106] Figure 1 This is a schematic diagram illustrating a configuration example of a CMOS image sensor as a solid-state image capture element according to a first embodiment of the present disclosure.

[0107] The CMOS image sensor 50 includes a pixel region 51, a pixel driving line 52, a vertical signal line 53, a vertical driving unit 54, a column processor 55, a horizontal driving unit 56, a system controller 57, a signal processor 58, and a memory unit 59, all of which are formed on a semiconductor substrate (chip) (such as a silicon substrate) not shown.

[0108] The pixel region 51 of the CMOS image sensor 50 includes pixels arranged in a two-dimensional array. Each pixel has a photoelectric conversion element that generates a charge corresponding to the amount of incident light, and these charges are accumulated within the photoelectric conversion element, enabling the CMOS image sensor 50 to capture an image. Further, in the pixel region 51, for pixels presenting an array shape, a pixel driving line 52 is formed for each row, and a vertical signal line 53 is formed for each column.

[0109] The vertical drive unit 54 includes a shift register, an address decoder, or any other unit, and drives each pixel of the pixel region 51 row by row. One end of the pixel drive line 52 is connected to an output terminal (not shown) corresponding to each row of the vertical drive unit 54. Although the detailed configuration of the vertical drive unit 54 is not shown, the vertical drive unit 54 has two scanning systems: a readout scanning system and a clear scanning system.

[0110] The readout scanning system sequentially selects rows to read pixel signals from each pixel on a row-by-row basis and outputs the selected signals from an output terminal connected to the pixel drive line 52 of the selected row. In this arrangement, the pixels of the row selected by the readout scanning system are read as pixel signals, which are electrical signals representing the charge accumulated in the photoelectric conversion element. The readout scanning system provides the pixel signals to the vertical signal line 53.

[0111] The clearing scan system activates a reset signal output from the pixel drive line 52 connected to each row to clear (reset) unwanted charges from the photoelectric conversion elements. Through scanning by the clearing scan system, a so-called electronic shutter operation is performed sequentially for each row. In this case, the electronic shutter operation discards the charge from the photoelectric conversion elements and begins a new exposure (initiating charge accumulation).

[0112] Column processor 55 includes signal processing circuitry for each column of pixel region 51. Each signal processing circuitry of column processor 55 performs signal processing, such as analog-to-digital (A / D) conversion, on the pixel signal output from each pixel of the selected row via vertical signal line 53. After this signal processing, column processor 55 temporarily stores these pixel signals.

[0113] The horizontal drive unit 56 includes a shift register, an address decoder, or any other unit, and sequentially selects the signal processing circuitry of the column processor 55. Based on the selective scanning of the horizontal drive unit 56, the pixel signals processed by each signal processing circuitry of the column processor 55 are sequentially output to the signal processor 58.

[0114] System controller 57 includes a timing generator or any other unit that generates various timing signals. Based on the timing signals generated by the timing generator, system controller 57 controls vertical drive unit 54, column processor 55, and horizontal drive unit 56.

[0115] The signal processor 58 performs various signal processing operations on the pixel signals output from the column processor 55. During this process, when necessary, the signal processor 58 stores intermediate results of the signal processing in the memory unit 59 and references the memory unit 59 when needed. After the signal processing, the signal processor 58 outputs the pixel signals.

[0116] Memory cell 59 includes dynamic random access memory (DRAM) or static random access memory (SRAM).

[0117] (Example of circuit configuration for a pixel)

[0118] Figure 2 To show in Figure 1 A schematic diagram of a circuit configuration example for one pixel in a two-dimensional arrangement of pixels in a pixel region.

[0119] Pixel 90 has a photodiode 91, a transmission transistor 92, an FD 93, a reset transistor 94, an amplification transistor 95, and a selection transistor 96 as photoelectric conversion elements.

[0120] The photodiode 91 generates and accumulates charge based on the amount of light received. The anode terminal of the photodiode 91 is grounded, and it has a cathode terminal connected to the FD 93 via the transfer transistor 92.

[0121] The gate terminal of the transmission transistor 92 is connected to a line in the pixel drive line 52 formed for the pixel 90 to provide a transmission signal. When turned on by the transmission signal, the transmission transistor 92 reads out the charge generated by the photodiode 91 and transfers the charge to the FD 93.

[0122] FD 93 retains the charge read from photodiode 91. The gate terminal of reset transistor 94 is connected to a line in pixel drive line 52 formed for pixel 90 to provide a reset signal. When turned on by this reset signal, reset transistor 94 discharges the charge accumulated in FD 93 to power supply 97 at potential VDD and resets the potential of FD 93.

[0123] The gate terminal of the amplifying transistor 95 is connected to the FD 93, and the amplifying transistor 95 outputs a pixel signal corresponding to the potential of the FD 93 by using the power supply 97.

[0124] The gate terminal of the select transistor 96 is connected to a line in the pixel drive line 52 formed for the pixel 90 to provide a select signal. When activated by the select signal, the select transistor 96 provides the pixel signal output from the amplifying transistor 95 via the vertical signal line 53. Figure 1 The column processor 55.

[0125] FD 93 can be shared among multiple pixels 90.

[0126] (First structural example of a CMOS image sensor)

[0127] Figure 3 This is a schematic diagram illustrating a first structural example of a CMOS image sensor 50.

[0128] like Figure 3 As shown, the CMOS image sensor 50 includes a wiring layer 112 stacked on a semiconductor substrate 111, such as a silicon substrate. The wiring layer 112 includes, for example, five wiring layers 121 to 125.

[0129] On the semiconductor substrate 111, a photodiode 91, an FD 93, a power supply 97, etc., are formed. A transmission transistor 92 is formed between the photodiode 91 and the FD 93 on the semiconductor substrate 111. An amplifying transistor 95 is connected to the power supply 97. Furthermore, a vertical signal line 53 is formed in the wiring layer 124.

[0130] Amplifying transistor 95 is connected to FD wiring 132 formed in wiring layer 122 via via 131 formed in wiring layer 121. Simultaneously, FD 93 is connected to FD wiring 132 via via 131 formed in wiring layer 121. In this arrangement, amplifying transistor 95 and FD 93 are connected via via 131 and FD wiring 132.

[0131] Through a via 131 formed in wiring layer 121, power supply 97 is connected to wiring 133 formed in wiring layer 122. Through a via 131 formed in wiring layer 121, transmission transistor 92 is connected to TRG wiring 134 formed in wiring layer 122.

[0132] In the regions of wiring layers 121 to 125 where no wiring is formed, an interlayer film 130, such as a SiO film, is formed. However, in Figure 3 In this example, the area surrounding FD wiring 132 (including the entire area between FD wiring 132 and adjacent wiring 133, and between FD wiring 132 and adjacent TRG wiring 134, which are formed within wiring layers 122 outside of FD wiring 132) is a hollow area 135. FD wiring 132 is in contact with the hollow area 135.

[0133] When the wiring interlayer film 130 is a SiO film, the dielectric constant of the hollow region (air) 135 is 1 / 4 of that of the wiring interlayer film 130. Therefore, by forming the hollow region 135, the capacitance of the FD wiring 132 is reduced to about 1 / 4 of the capacitance of the FD wiring 132 when the hollow region 135 is not formed.

[0134] Furthermore, because the interlayer membrane 130 is formed in the area outside the hollow region 135 in the wiring layer 122, it has higher mechanical strength compared to the case where the interlayer membrane 130 is not formed in the entire wiring layer 122.

[0135] (Second structural example of a CMOS image sensor)

[0136] Figure 4 This is a schematic diagram illustrating a second structural example of a CMOS image sensor 50.

[0137] exist Figure 4 In the configuration shown, for the purpose of... Figure 3 Components that are identical to those in the drawing are labeled with the same reference numerals. Where appropriate, repeated descriptions are omitted.

[0138] Figure 4 The structure of the CMOS image sensor 50 in the middle and Figure 3 The difference in the structure is that it forms hollow regions 201 to 206, rather than hollow region 135.

[0139] exist Figure 4 In the example, hollow regions 201 to 206 are formed in the area surrounding FD wiring 132 (including the entire area between FD wiring 132 and wiring 133 and between FD wiring 132 and TRG wiring 134) to avoid contact with FD wiring 132, wiring 133 and TRG wiring 134.

[0140] (A third structural example of a CMOS image sensor)

[0141] Figure 5 This is a schematic diagram illustrating a third structural example of a CMOS image sensor 50.

[0142] exist Figure 5 In the configuration shown, for the purpose of... Figure 3 Components that are identical to those in the drawing are labeled with the same reference numerals. Where appropriate, repeated descriptions are omitted.

[0143] Figure 5 The structure of the CMOS image sensor 50 in the middle and Figure 3 The difference in the structure is that it forms a hollow region 221 instead of a hollow region 135.

[0144] exist Figure 5 In the example, the area around FD wiring 132 (including only the area between FD wiring 132 and wiring 133, excluding the entire area between FD wiring 132 and wiring 133 and between FD wiring and TRG wiring 134) is a hollow area 221.

[0145] That is, because FD wiring 132 processes analog signals, it is less resistant to noise compared to wiring that processes digital signals, such as vertical signal line 53. Therefore, it is desirable to reduce the capacitance between wiring 133 and wiring 132, which becomes a noise source due to their connection to power supply 97. However, in some cases, it is better to maintain the capacitance between TRG wiring 134 and FD wiring 132.

[0146] Therefore, in Figure 5 In this example, the area surrounding the FD wiring (including only the area between FD wiring 132 and adjacent wiring 133, and the area between FD wiring 132 and adjacent TRG wiring 134) is designated as a hollow area 221. That is, within the areas between FD wiring 132 and adjacent wiring 133, and between FD wiring 132 and adjacent TRG wiring 134, the area excluding the area between FD wiring 132 and TRG wiring 134 becomes the hollow area 221.

[0147] As a result, noise propagation through the capacitance between FD wiring 132 and wiring 133, which becomes a noise source, can be suppressed. Furthermore, the capacitance between TRG wiring 134 and FD wiring 132 can be maintained.

[0148] like Figure 5 As shown, the hollow region 221 may or may not be in contact with FD wiring 132 and wiring 133.

[0149] (A fourth structural example of a CMOS image sensor)

[0150] Figure 6 This is a schematic diagram illustrating a fourth structural example of a CMOS image sensor 50.

[0151] exist Figure 6 In the configuration shown, for the purpose of... Figure 3 Components that are identical to those in the drawing are labeled with the same reference numerals. Where appropriate, repeated descriptions are omitted.

[0152] Figure 6 The structure of the CMOS image sensor 50 in the middle and Figure 3 The difference in the structure is that, in addition to the hollow region 135, a hollow region 241 is also formed.

[0153] exist Figure 6 In this example, the entire area surrounding the vertical signal line 53 is a hollow region 241.

[0154] That is, when the number of vertical signal lines 53 is large, high-speed driving is possible, but the wiring density increases, and the capacitance of the vertical signal lines 53 increases. As a result, the response deteriorates, the variation in pixel signals increases, and the image quality of the captured image deteriorates. Therefore, in Figure 6 In this example, the entire area surrounding the vertical signal line 53 is designated as a hollow region 241. This arrangement reduces the capacitance of the vertical signal line 53. Consequently, the image quality of the captured image can be improved by suppressing pixel signal variations during high-speed driving.

[0155] exist Figure 6 In this example, although the entire area around the vertical signal line 53 is a hollow region 241, only a portion of the area around the vertical signal line 53 can be a hollow region 241. Furthermore, hollow regions 201 to 206 or hollow region 221 can be formed instead of hollow region 135.

[0156] Furthermore, such as Figure 6 As shown, the hollow region 241 may or may not be in contact with the wiring of the adjacent vertical signal line 53.

[0157] As described above, in the CMOS image sensor 50, at least a portion of the regions between FD wiring 132 and wiring 133, and between FD wiring 132 and TRG wiring 134, is a hollow region 135 (201 to 206, or 221). Therefore, the capacitance of FD wiring 132 can be reduced, and the charge-to-voltage conversion efficiency can be improved without changing the wiring layout.

[0158] Furthermore, because no changes to the wiring layout are required, any system can be used as a system that shares the pixels of the CMOS image sensor 50.

[0159] In the regions of wiring layers 121 to 125, a low dielectric constant film, rather than the interlayer film 130, may be formed, unlike the wiring and the hollow regions 135 (201 to 206, 221 and / or 241).

[0160] <Second Implementation Method>

[0161] (Example of the circuit configuration of pixels in a CMOS image sensor according to the second embodiment)

[0162] Apart from the circuit configuration of each pixel arranged in two dimensions in pixel region 51 and the operation of the clearing scanning system, the configuration of the CMOS image sensor as a solid-state image capture element according to the second embodiment of this disclosure is as follows: Figure 1 The CMOS image sensors shown are configured identically. Therefore, the following will only describe the circuit configuration for each pixel and the operation of the clearing scanning system. This will be achieved through the use of... Figure 1The reference numerals in the figures describe the configuration elements of pixels that differ from those of CMOS image sensors.

[0163] Figure 7 This is a schematic diagram illustrating an example of the circuit configuration of pixels in a CMOS image sensor according to a second embodiment of the present disclosure.

[0164] exist Figure 7 In the configuration shown, for the purpose of... Figure 3 Components that are identical to those in the drawing are labeled with the same reference numerals. Where appropriate, repeated descriptions are omitted.

[0165] Figure 7 The circuit configuration of pixel 300 is different Figure 2 The circuit configuration of pixel 90 in the image is characterized by the use of FD301 and 302 instead of FD93, and the use of reset transistors 303 and 304 instead of reset transistor FD94. By switching between the on and off states of reset transistor 304 in pixel 300, the imaging mode can be switched between a high charge-to-voltage conversion efficiency mode and a low charge-to-voltage conversion efficiency mode.

[0166] Specifically, in pixel 300, the gate terminal of amplifying transistor 95 is connected to FD301. Between power supply 97 and FD301, reset transistor 303 and reset transistor 304 are connected in series via FD302.

[0167] Different lines in the corresponding row of pixel drive lines 52 are connected to the gate terminals of reset transistor 303 and reset transistor 304. Different reset signals are provided to these gate terminals via different lines. The reset signal to be provided to reset transistor 303 is activated by the clear scan system of vertical drive unit 54 to clear unwanted charge from photodiode 91.

[0168] When the image capture mode is in low charge-to-voltage conversion efficiency mode, the reset signal to be supplied to the reset transistor 304 is always kept on by the clear scan system. Therefore, in this case, when the reset signal supplied to the reset transistor 303 is turned on, the potential of FD301 becomes the potential VDD of the power supply 97, and the capacitance of the FD of pixel 300 becomes only the capacitance of FD301. Thus, the charge-to-voltage conversion efficiency is increased.

[0169] On the other hand, when the image capture mode is a low charge-to-voltage conversion efficiency mode, the reset signal to be supplied to the reset transistor 304 is always kept off by the clear scan system. Therefore, in this case, when the reset signal to be supplied to the reset transistor 303 is turned on, the potential of FD302 becomes the potential VDD of the power supply 97, and the capacitance of the FD of pixel 300 becomes the sum of the capacitances of FD301 and FD302. Consequently, the charge-to-voltage conversion efficiency decreases.

[0170] In the pixel 300 configured as described above, the ratio of the charge-voltage conversion efficiency in the high charge-voltage conversion efficiency mode to the charge-voltage conversion efficiency in the low charge-voltage conversion efficiency mode (hereinafter referred to as the mode ratio) is determined based on the ratio of the capacitance of FD301 to the sum of the capacitances of FD301 and FD302. The capacitances of FD301 and FD302 contribute to the capacitance of the FD wiring connected to FD301 (not shown) and the capacitance of the FD wiring connected to FD302 (not shown), respectively.

[0171] Therefore, in pixel 300, in order to obtain the desired mode ratio, a hollow region similar to the hollow region 135 (201 to 206 or 221) is formed around the FD line connected to FD301 in one of the two FD lines that are self-connected to FD301 and FD302.

[0172] That is, as described above, by forming a hollow region around the FD wiring, the capacitance of the FD wiring can be reduced compared to the case where no hollow region is formed. Therefore, a hollow region is formed such that the capacitance of the FD wiring connected to FD301 becomes the capacitance of the FD wiring corresponding to the capacitance of FD301, which is determined based on the capacitance of FD302 and the desired mode ratio.

[0173] The hollow area can be formed only around the FD wiring connected to FD302, or it can be formed around the two FD wirings connected to FD301 and FD302. Furthermore, FD301 and FD302 can be shared among multiple pixels 300.

[0174] As described above, in the CMOS image sensor according to the second embodiment, two FDs, FD301 and FD302, are formed. FD wiring is connected to FD301 and FD302. A hollow region is formed around at least one of these FD wirings. With this arrangement, the capacitance of the FD wiring with a hollow region around it is reduced compared to the capacitance of the FD wiring without a hollow region around it. As a result, the mode ratio can be set to a desired ratio.

[0175] On the other hand, when the hollow area is not formed around the FD wiring connecting FD301 and FD302, the mode ratio needs to be adjusted through wiring layout. However, when the number of pixels is 300, the freedom of wiring layout is low. Furthermore, based on a shared system with 300 pixels, there are restrictions on wiring layout. Therefore, adjusting the mode ratio through wiring layout is difficult.

[0176] <Third Implementation Method>

[0177] (Layout example of the various parts of a CMOS image sensor)

[0178] The configuration of the CMOS image sensor as a solid-state image capture element according to the third embodiment of this disclosure and Figure 1 The configuration of the CMOS image sensor 50 shown is the same. Therefore, a description of this configuration is omitted. Furthermore, in the following figures, components that are identical to those in the CMOS image sensor 50 are labeled with the same reference numerals. Where appropriate, repeated descriptions are omitted.

[0179] Figure 8 This is a view showing an example of the layout of the various parts of a CMOS image sensor according to a third embodiment.

[0180] according to Figure 8 The CMOS image sensor 320 has a semiconductor substrate 321 stacked on a semiconductor substrate 322. A pixel region 51 is formed on the semiconductor substrate 321, and control circuitry 331 and logic circuitry 332 are formed on the semiconductor substrate 322. One or more wiring layers are stacked on each of the semiconductor substrates 321 and 322. The semiconductor substrate 321 is stacked on the semiconductor substrate 322, such that the wiring layers are bonded together.

[0181] For example, control circuit 331 includes a vertical drive unit 54, a column processor 55, a horizontal drive unit 56, and a system controller 57. For example, logic circuit 332 includes a signal processor 58 and a memory unit 59.

[0182] In this case, the semiconductor substrate of the CMOS image sensor 320 has two layers, but it can be one, three, or more. Furthermore, a control circuit 331 can be formed on the semiconductor substrate 321 on which the pixel region 51 is disposed.

[0183] (First structural example of semiconductor substrate 321)

[0184] Figure 9 From the perspective of the wiring layer Figure 8 A plan view of the first structural instance of pixel region 51 in the image. Figure 10 Including along Figure 9 The sectional view obtained by cutting along A-A' and along Figure 9 A sectional view obtained by cutting along line B'. For ease of explanation, Figure 9 The semiconductor substrate 321 and only the bottommost wiring layer are shown. Figure 10 The semiconductor substrate 321 and only the two bottommost wiring layers are shown.

[0185] like Figure 9 and 10 As shown, in the CMOS image sensor 320, two adjacent pixels 90 in the horizontal direction share FD93. Figure 10 As shown, in the wiring layer 351 at the bottom of the pixel region 51, an FD wiring 361 is formed, which is used to connect the source of the reset transistor 94 between the FD 93 and the gate of the amplification transistor 95.

[0186] like Figure 10 As shown, FD wiring 361 is connected to FD93 through via 361A, to the source of reset transistor 94 formed on semiconductor substrate 321 through via 361B, and to the gate of amplification transistor 95 through via 361C.

[0187] Furthermore, such as Figure 9 As shown, the gate of the transmission transistor 92 is connected to a TRG line 362, which is a line configuring the pixel drive line 52. Further, as... Figure 10 As shown, various wirings 363 are formed in wiring layer 352 on wiring layer 351.

[0188] like Figure 9 and 10 In wiring layer 351, between FD wiring 361 and other wirings not shown, multiple (in) Figure 10 The example in the text is four) hollow regions (air gaps) 364A. Furthermore, multiple ( ) are formed between the FD wiring 361 with different potentials and the semiconductor substrate 321. Figure 10 In the example, this is 6) hollow region 364B. Further, multiple hollow regions 364C are formed in the region above the FD wiring 361 of the wiring layer 352.

[0189] As described above, hollow regions 364A to 364C are formed between the FD wiring 361 and other wirings or electrodes of the semiconductor substrate 321. This arrangement reduces the dielectric constant between the FD wiring 361 and other wirings or electrodes, and also reduces the capacitance of the FD wiring 361. As a result, the charge-to-voltage conversion efficiency is improved.

[0190] Furthermore, the hollow area formed between the FD wiring and other wirings is configured not by a single hollow area but by multiple hollow areas 364A. Therefore, even if the capacitance of the FD wiring 361 is reduced by increasing the distance between the FD wiring 361 and other wirings, the size of a single hollow area can be reduced. As a result, this hollow area can be easily formed.

[0191] In wiring layers 351 and 352, an insulating film 353 (interlayer film) such as a SiO film is formed in regions where FD wiring 361, TRG wiring 362, wiring 363, hollow regions 364A to 364C, and transistors such as transmission transistor 92 are not formed. In the third embodiment, the material of the insulating film 353 is silicon dioxide, but it is not limited to this material.

[0192] As described above, an insulating film 353 exists between the hollow regions 364A and 364C. Because the hollow regions 364A and 364C are supported by the insulating film 353, the capacitance of the FD wiring 361 can be reduced compared to the case where the hollow regions 364A and 364C are supported by a conductor.

[0193] (Method Description of a First Structural Example of Manufacturing Semiconductor Substrate 321)

[0194] Figures 11 to 14 To illustrate a method for manufacturing a semiconductor substrate 321, a schematic diagram is shown of a semiconductor substrate 321 on which are stacked... Figure 9 and Figure 10 Wiring layers 351 and 352 in the middle.

[0195] First of all, Figure 11 In the first process, photodiodes 91 and FD 93, as well as transistors (such as transmission transistor 92, reset transistor 94, and amplification transistor 95) for configuring pixels 90 are formed on semiconductor substrate 321. Afterward, an insulating film 353 is formed on semiconductor substrate 321.

[0196] exist Figure 11 In the second process, a photoresist pattern is formed on the insulating film 353 by coating a photoresist 381 in an area other than the area corresponding to the hollow region between the FD wiring 361 and the semiconductor substrate 321. Then, the insulating film 353 is etched using this photoresist pattern. As a result, the insulating film 353 is removed from the area where the photoresist 381 was never formed (i.e., the area corresponding to the hollow region 364B). The size of the hollow region 364B can be controlled by modifying the photoresist pattern.

[0197] exist Figure 12In the third process, the photoresist pattern is stripped, and an insulating film 353 is formed using a weak-coverage film deposition method. As a result, a hollow region 364B is formed between the FD wiring 361 and the semiconductor substrate 321. Figure 12 In the fourth process, wiring 361 and vias 361A to 361C are formed in insulating film 353 by damascus method, so that FD93 is connected to the source of reset transistor 94 and the gate of amplification transistor 95.

[0198] exist Figure 13 In the fifth process, a photoresist pattern is formed on the insulating film 353 by applying photoresist 381 to the area outside the region corresponding to the hollow region 364A between the FD wiring 361 and other wirings not shown in the wiring layer 351 (where the FD wiring 361 is formed). The insulating film 353 is then etched using this photoresist pattern. As a result, the insulating film 353 is removed from the region where the photoresist 381 was never formed (i.e., the region corresponding to the hollow region 364A).

[0199] exist Figure 13 In the sixth process, the photoresist pattern is stripped, and an insulating film 353 is formed using a weak-coverage film deposition method. As a result, a hollow region 364A is formed. Figure 14 In the seventh process, wiring 363 of wiring layer 352 is formed by the Damascus method.

[0200] exist Figure 14 In the eighth process, firstly, with... Figure 11 The second processing in Figure 12 The third processing in, and Figure 13 The fifth and sixth processes in the process form a hollow area 364C above the FD wiring 361 in a similar manner.

[0201] Specifically, a photoresist pattern is formed on the insulating film 353 by coating a photoresist 381 in an area other than the area corresponding to the hollow region 364C above the FD wiring 361. Then, the insulating film 353 is etched using this photoresist pattern. As a result, the insulating film 353 is removed from the area corresponding to the hollow region 364C. Afterward, the photoresist pattern is stripped, and the insulating film 353 is formed using a weak-coverage film deposition method.

[0202] Figure 11 In the second processing, Figure 13 The fifth process, and Figure 14 The thickness (length in the direction perpendicular to the semiconductor substrate 321) of the insulating film 353 to be etched in the eighth process, i.e. the thickness of each hollow region 364A to 364C, is less than a few tenths of a micrometer.

[0203] As described above, because the insulating film 353 above the hollow regions 364A to 364C is formed by a weak-coverage film-forming method, it is possible to form the insulating film 353 above the hollow regions 364A to 364C while maintaining the cavity of the hollow regions 364A to 364C. The mass of the insulating film 353 below the hollow regions 364A to 364C can be the same as or different from the mass of the insulating film 353 above the hollow regions 364A to 364C.

[0204] (Second structural example of semiconductor substrate 321)

[0205] Figure 15 For along Figure 9 A-A' cut Figure 8 A cross-sectional view of a second structural example of the pixel region 51 of the semiconductor substrate 321. For ease of explanation, Figure 15 The semiconductor substrate 321 and only the two bottommost wiring layers are shown.

[0206] exist Figure 15 In the configuration shown, for the purpose of... Figure 10 Components that are identical to those in the drawing are labeled with the same reference numerals. Where appropriate, repeated descriptions are omitted.

[0207] Figure 15 The configuration of the semiconductor substrate 321 on which wiring layers 351 and 352 are stacked is different. Figure 10 The configuration in this case involves forming a barrier membrane 401 to contact the bottom surface of the FD wiring 361 and the hollow region 364A.

[0208] The barrier film 401 is a film such as a SiOC film, used to prevent etching of the insulating film 353 when the FD wiring 361 is formed by the Damascus method.

[0209] (Method description of a second structural example of manufacturing semiconductor substrate 321)

[0210] Figures 16 to 19 To illustrate the manufacturing process, stacked on top of it Figure 15 A schematic diagram of the method of the semiconductor substrate 321 of wiring layer 351 and wiring layer 362.

[0211] First, proceed Figure 11 and 12 The first to third processes are performed, forming a hollow region 364B between the FD wiring 361 and the semiconductor substrate 321. Next, in... Figures 16 to 18 In the first to sixth processes, FD wiring 361 and through holes 361A to 361C are formed by the Damascus method.

[0212] That is, in Figure 16In the first process, an insulating film 353 is formed on a semiconductor substrate 321 on which a hollow region 364B is formed. Then, the insulating film 353 is planarized.

[0213] exist Figure 16 In the second process, a barrier film 401 is formed on the insulating film 353. Figure 17 In the third process, an insulating film 353 with a predetermined thickness is (stacked) on the barrier film 401.

[0214] exist Figure 17 In the fourth process, the areas corresponding to the vias 361A to 361C of the insulating film 353 below the barrier film 401 are etched, and the areas corresponding to the FD wiring 361 of the insulating film 353 above the barrier film 401 are also etched. Etching of the insulating film 353 above the barrier film 401 is prevented by the barrier film 401. That is, the bottom surface of the etched area of ​​the insulating film 353 above the barrier film 401 is in contact with the upper surface of the barrier film 401.

[0215] exist Figure 18 In the fifth process, a copper (Cu) film 402 is formed on the uppermost insulating film 353. Figure 18 In the sixth process, unnecessary copper 402 located above the insulating film 353 is removed. As a result, FD wiring 361 and vias 361A to 361C are formed.

[0216] Next, in Figure 19 In the seventh process, a photoresist pattern is formed on the insulating film 353 by applying photoresist 381 to the area outside the region corresponding to the hollow region 364A between the FD wiring 361 and other wirings not shown in the wiring layer 351 (where the FD wiring 361 is formed). The insulating film 353 is then etched using this photoresist pattern to prevent etching by the barrier film 401. As a result, the insulating film 353 is removed from the region where the photoresist 381 was never formed (i.e., the region corresponding to the hollow region 364A).

[0217] After that, proceed Figure 13 and Figure 14 The sixth to eighth processes in the process form hollow regions 364A and 364C.

[0218] With the above arrangement, the bottom surface of all hollow regions 364A is in contact with the upper surface of the barrier film 401. That is, the bottom surfaces of all hollow regions 364A are positioned in the same thickness direction. Therefore, the variation in the depth (length in the direction perpendicular to the semiconductor substrate) of the hollow regions 364A is reduced. As a result, the variation in the capacitance of the FD wiring 361 is reduced.

[0219] exist Figure 19In the seventh process, after the etching of the insulating film 353 is prevented by the blocking film 401, further etching can be performed, such as... Figure 20 As shown in the image.

[0220] (Third structural example of semiconductor substrate 321)

[0221] Figure 21 For along Figure 9 A-A' cut Figure 8 A cross-sectional view of a third structural example of pixel region 51 of semiconductor substrate 321. For ease of explanation, Figure 21 The semiconductor substrate 321 and only the two bottommost wiring layers are shown.

[0222] exist Figure 21 In the configuration shown, for the purpose of... Figure 10 Components that are identical to those in the drawing are labeled with the same reference numerals. Where appropriate, repeated descriptions are omitted.

[0223] Figure 21 The configuration of the semiconductor substrate 321 on which wiring layers 351 and 352 are stacked is different. Figure 10 The configuration is such that the lower parts of four consecutive hollow regions 364A are connected together, and the insulating film around the upper part of the hollow region 364A is an insulating film 421, the material of which is different from the material of the insulating film 353.

[0224] For example, the material of insulating film 421 is SiN.

[0225] (Method description of a third structural example of manufacturing semiconductor substrate 321)

[0226] Figure 22 and 23 To illustrate the manufacturing process, stacked on top of it Figure 21 A schematic diagram of the method for wiring layer 351 and wiring layer 352.

[0227] First, proceed Figure 11 and 12 The first to third processes are performed, forming a hollow region 364B between the FD wiring 361 and the semiconductor substrate 321. Next, in... Figure 22 In the first process, an insulating film 421 is formed on the insulating film 353. Then, FD wiring 361 and through holes 361A to 361C are formed in the insulating film 353 and the insulating film 421 to make contact with FD93 by the damascus method.

[0228] Next, in Figure 22 In the second process, a photoresist pattern is formed on the insulating film 421 by coating a photoresist 381 in an area other than the area corresponding to the hollow region 364A.

[0229] Subsequently, insulating film 353 and insulating film 421 are etched using the photoresist pattern. As a result, insulating film 353 and insulating film 421 are removed from the area where photoresist 381 is not formed (i.e., the area corresponding to hollow region 364A).

[0230] exist Figure 23 In the third process, isotropic etching of insulating films 353 and 421 is performed under the condition that the etching rate of insulating film 353 becomes greater than that of insulating film 421. As a result, only insulating film 353 is etched, and the lower parts of the four hollow regions 364A are connected together.

[0231] exist Figure 23 In the fourth process, the photoresist pattern is stripped, and an insulating film 353 is formed using a weak-coverage film deposition method. In this case, although the lower portion of the hollow region 364A has a large size and the upper portion has a small size, the hollow region 364A closes before the material of the insulating film 353 reaches the lower portion. As a result, the cavity of the hollow region 364A is preserved. Afterwards, [further processing is performed]. Figure 14 The seventh and eighth processes in the process form a hollow region 364C.

[0232] like Figure 24 As shown, in a manner similar to that applied to hollow region 364A, an insulating film 421 can be formed around the upper portion of hollow region 364B, and the lower portions of hollow regions 364B can be connected together. Further, the lower portion of each of hollow regions 364A to 364C can be larger than the upper portion of each of hollow regions 364A to 364C, and the lower portions of hollow regions 364A to 364C are not connected together.

[0233] (The first method for manufacturing CMOS image sensors)

[0234] Figures 25 to 27 For the purpose of illustrating manufacturing Figure 8 A schematic diagram of a first method using a CMOS image sensor 320 is shown. By using... Figures 11 to 14 The semiconductor substrate 321 manufactured by the method described herein is bonded to the semiconductor substrate 322 to manufacture a CMOS image sensor 320.

[0235] In passing Figures 11 to 14 After fabricating a semiconductor substrate 321 on which wiring layers 351 and 352 are stacked, the wiring layer 431 is further stacked on the semiconductor substrate 321. Then, in... Figure 25In the first process, a photoresist pattern is formed on the insulating film 353 of the wiring layer 352 by coating photoresist 381 around the area outside the pixel region 51 where the TSV 452 will be formed. Then, the insulating film 353 is etched using this photoresist pattern. With this arrangement, the insulating film 353 is removed from the areas where the photoresist 381 is not formed (i.e., the area around the region where the TSV 452 will be formed).

[0236] exist Figure 25 In the second process, the photoresist pattern is stripped, and an insulating film 353 is formed by a weak-coverage film deposition method. As a result, a hollow region 432 is formed in the area surrounding the region where the TSV 452 (connection portion) will be formed.

[0237] exist Figure 26 In the third process, semiconductor substrate 321 and semiconductor substrate 322 are bonded together.

[0238] Specifically, in Figure 26 In one example, four wiring layers 441 to 444, in which various wirings 440 are formed, are stacked on a semiconductor substrate 322. An insulating film 445 is formed in the regions in which the wirings 440 and the like are not formed in the wiring layers 441 to 444.

[0239] The wiring 440 of the uppermost wiring layer 444 is made of aluminum (Al), for example. Unlike the wiring 440 of the uppermost wiring layers 441 to 443, which are made of copper (Cu), the wiring 440 of the uppermost wiring layers 441 to 443 are made of copper (Cu). The semiconductor substrate 321 is bonded to the semiconductor substrate 322 such that the uppermost wiring layer 431 of the semiconductor substrate 321 is bonded to the uppermost wiring layer 444 of the semiconductor substrate 322.

[0240] After semiconductor substrates 321 and 322 are bonded together, an insulating film 451 is formed on the surface of the wiring layer 351 on which semiconductor substrates 321 are stacked. Further, color filters, on-chip lenses, etc. (not shown), are formed in the region corresponding to the pixel region 51 on the surface of the wiring layer 351 on which semiconductor substrates 321 are stacked. Further, after bonding, semiconductor substrates 321 and 322 are thinned. With this arrangement, a CMOS image sensor 320 is formed at a desired thickness.

[0241] Next, in Figure 27 In the fourth process, the regions of insulating film 451, semiconductor substrate 321, insulating film 353, and insulating film 445 in which TSV 452 is formed are etched, and TSV 452 is formed. TSV 452 is connected to wiring 440 of wiring layer 444 and wiring 363 of wiring layer 351, so that semiconductor substrate 321 and semiconductor substrate 322 are electrically connected to each other.

[0242] (A second method for manufacturing CMOS image sensors)

[0243] Figures 28 to 31 For the purpose of illustrating manufacturing Figure 8 A schematic diagram of a second method of a CMOS image sensor 320, wherein the sensor uses... Figures 11 to 14 The semiconductor substrate 321 is manufactured by bonding semiconductor substrate 322 together with the semiconductor substrate 321 manufactured by the method described in the article.

[0244] In passing Figures 11 to 14 After fabricating a semiconductor substrate 321 on which wiring layers 351 and 352 are stacked, the manufacturing method further stacks wiring layer 431. Then, in... Figure 28 In the first process, semiconductor substrate 321 and semiconductor substrate 322 are bonded together, such that the uppermost wiring layer 352 of semiconductor substrate 321 and the uppermost wiring layer 442 of semiconductor substrate 322 are bonded together.

[0245] After semiconductor substrates 321 and 322 are bonded together, an insulating film 451 is formed on the surface of the wiring layer 351 on which semiconductor substrates 321 are stacked. Further, color filters, on-chip lenses, etc. (not shown), are formed in the region corresponding to the pixel region 51 on the surface of the wiring layer 351 on which semiconductor substrates 321 are stacked. Further, after bonding, semiconductor substrates 321 and 322 are thinned. With this arrangement, a CMOS image sensor 320 is formed at a desired thickness.

[0246] exist Figure 29 In the second process, a photoresist pattern is formed on the insulating film 451 by applying photoresist 381 to the area surrounding the region in the non-pixel region 51 where the TSV 452 will be formed. Then, the semiconductor substrate 321, the insulating film 451, and the insulating film 353 are etched using this photoresist pattern. With this arrangement, the semiconductor substrate 321, the insulating film 451, and the insulating film 353 are removed from the areas where the photoresist 381 is not formed (i.e., the areas surrounding the regions where the TSV 452 will be formed).

[0247] exist Figure 30 In the third process, the photoresist pattern is stripped, and an insulating film 451 is formed by a weak-coverage film deposition method. As a result, a hollow region 432 penetrating the semiconductor substrate 321 is formed in the region surrounding the area where the TSV 452 is to be formed.

[0248] exist Figure 31In the fourth process, the regions of insulating film 451, semiconductor substrate 321, insulating film 353, and insulating film 445 in which TSV 452 will be formed are etched, and TSV 452 is formed.

[0249] like Figure 32 As shown, in the third process, when forming the insulating film 451, the insulating film 451 can be buried in the hollow region 432 in the semiconductor substrate 321. Further, the TSV 452 can connect the wiring 440 of the wiring layer 444 to the wiring 363 of the wiring layer 351 through one or two vias.

[0250] As described above, by forming a hollow region 432 around the TSV 452, the capacitance between the TSV 452 and the potential portion (e.g., GND) of the semiconductor substrate 321 can be reduced.

[0251] In the third embodiment, the number of hollow regions 364A to 364C and hollow region 432 can be any number equal to or greater than 1. Hollow regions 364A to 364C and hollow region 432 can have any shape in which an insulating film is not formed by a weakly covered film-forming method.

[0252] <Fourth Implementation Method>

[0253] (Instructions for the arrangement of hollow areas within a pixel region)

[0254] Except that the CMOS image sensor in the fourth embodiment has an FD 93 shared between 2 (horizontal) × 2 (vertical) pixels 90 and the arrangement and shape of the hollow regions 364A to 364C and the hollow region 432 are different, the configuration and structure of the CMOS image sensor as a solid-state image capture element according to the fourth embodiment of this disclosure are the same as the configuration and structure of the CMOS image sensor 320.

[0255] Therefore, the following description only covers the arrangement and shape of hollow regions 364A to 364C and hollow region 432. Furthermore, in the following figures, components identical to those in the CMOS image sensor 320 will be labeled with the same reference numerals. Where appropriate, repeated descriptions will be omitted.

[0256] Figure 33 This is a plan view used to illustrate the arrangement of the hollow regions in the pixel region 51 of the CMOS image sensor according to the fourth embodiment. Figure 33 This is a plan view of the pixel region 51 of the semiconductor substrate 321 on which wiring layers 351, 352, and 431 are stacked, as viewed from the side where wiring layer 431 is located.

[0257] Figure 33In the diagram, only semiconductor substrate 321 and wiring layer 351 are shown, and Figure 33 B in the diagram only shows the semiconductor substrate 321 and the wiring layer 431.

[0258] like Figure 33 As shown in Figure A, in the CMOS image sensor according to the fourth embodiment, a hollow region 472 is formed between the FD wiring 361 and other wirings such as wiring 471 in the same wiring layer 351. This arrangement reduces the dielectric constant between the FD wiring 361 and other wirings in the wiring layer 351. As a result, the charge-to-voltage conversion efficiency is improved.

[0259] Furthermore, such as Figure 33 As shown in Figure B, in wiring layer 431, a hollow region 474 is formed between the vertical signal line 53 and other wirings such as wiring 473 in the same wiring layer 431. This arrangement reduces the dielectric constant between the vertical signal line 53 and other wirings in wiring layer 431, and also reduces the capacitance of the vertical signal line 53. As a result, delays in pixel signal readout can be prevented.

[0260] exist Figure 33 In Example A, two hollow regions 472 are formed between FD wiring 361 and other wirings. The number of hollow regions 472 can be any number equal to or greater than one. Similarly, the number of hollow regions 474 formed between vertical signal line 53 and other wirings can be any number equal to or greater than one.

[0261] exist Figure 33 In this example, when viewed from above the wiring layer 431, each of the hollow regions 472 and 474 appears rectangular (strip-shaped). However, each of the hollow regions 472 and 474 can have any shape.

[0262] (Example of the shape of a hollow region within a pixel area)

[0263] Figure 34 The plan view of the pixel region 51 of the semiconductor substrate 321 on which the wiring layer 352 is stacked is shown from the side where the wiring layer 351 is located, which shows other examples of the shape of the hollow region 472.

[0264] like Figure 34 As shown in A, when viewed from above the wiring layer 351, each of the hollow regions 472 can be circular (hole-shaped), or for example... Figure 34 As shown in B, it can be in the form of a mesh (net shape).

[0265] Although not shown, each of the hollow regions 474 may have the same shape as the hollow region 472.

[0266] (Example of hollow region shape in non-pixel region)

[0267] Figure 35 This is a plan view of the CMOS image sensor according to the fourth embodiment, viewed from above the insulating film 451, showing an example of the shape of each hollow region 432 formed around the TSV 452 of the pixel region 51, which is not a CMOS image sensor.

[0268] like Figure 35 As shown in A, when viewed from above the insulating film 451, each hollow region 432 can appear as a rectangular ring, or for example... Figure 35 As shown in B, it can be in a circular ring shape. Further, as... Figure 35 As shown in C, each hollow region 432 can be linear (strip-shaped).

[0269] exist Figure 35 In the examples of A and C, the number of hollow regions 432 formed around TSV 452 is two, and in Figure 35 The number of instances of B in the diagram is one. However, the number of hollow regions 432 is not limited to these numbers and can be any number.

[0270] The shapes of hollow regions 432, 472, and 474 are not limited to... Figure 34 and Figure 35 The shape shown is provided that the hollow region has such a shape that the insulating film is not formed by a weakly covered film-forming method.

[0271] Furthermore, in the fourth embodiment, hollow regions can be formed in the lower and upper portions of the FD wiring 361 in a manner similar to that in the third embodiment.

[0272] Furthermore, in the third embodiment, a hollow region can be formed around the vertical signal line 53 in a manner similar to that in the fourth embodiment. In the third and fourth embodiments, the region where the hollow region is formed can be formed around wirings other than FD wiring 361 and vertical signal line 53, around which it is desirable to reduce their capacitance.

[0273] In the third and fourth embodiments, a hollow region may be formed in the semiconductor substrate 322.

[0274] <Fifth Implementation Method>

[0275] (A configuration example of an image capture device according to one implementation)

[0276] Figure 36A block diagram illustrating a configuration example of an image capture device as an electronic device according to one embodiment of the present disclosure.

[0277] Figure 36 The image capture device 1000 is a camera, digital still camera, etc. The image capture device 1000 includes a lens assembly 1001, a solid-state image capture element 1002, a digital signal processing (DSP) circuit 1003, a frame memory 1004, a display unit 1005, a recording unit 1006, an operation unit 1007, and a power supply unit 1008. The DSP circuit 1003, frame memory 1004, display unit 1005, recording unit 1006, operation unit 1007, and power supply unit 1008 are interconnected via a bus 1009.

[0278] Lens assembly 1001 captures light (image light) incident from the subject and forms an image on the image capture surface of solid-state image capture element 1002. Solid-state image capture element 1002 includes the aforementioned CMOS image sensor. Solid-state image capture element 1002 converts the number (in pixels) of incident light that forms the image on the image capture surface through lens assembly 1001 into electrical signals and provides these electrical signals to DSP circuit 1003 as pixel signals.

[0279] The DSP circuit 1003 performs predetermined image processing on the pixel signal provided from the solid-state image capture element 1002, provides the processed image signal in frames to the frame memory 1004, and temporarily stores the image signal in the frame memory 1004.

[0280] Display unit 1005 includes, for example, a flat panel display device (such as a liquid crystal panel or an organic electroluminescent (EL) panel) and displays images based on pixel signals stored temporarily in frame memory 1004 in units of frames.

[0281] The recording unit 1006 includes a digital multifunction disc (DVD), flash memory, etc., which reads pixel signals in units of frames that are temporarily stored in the frame memory 1004 and records the pixel signals.

[0282] Under user operation, the operation unit 1007 issues operation commands for various functions of the image capture device 1000. The power supply unit 1008 appropriately supplies power to the DSP circuit 1003, frame memory 1004, display unit 1005, recording unit 1006, and operation unit 1007.

[0283] Electronic devices using this technology can be those that use a CMOS image sensor in their image capture unit (photoelectric conversion unit). Besides the image capture device 1000, this technology can be applied to portable terminal devices with image capture capabilities and copiers that use a CMOS image sensor in their image reading unit.

[0284] (Examples of using CMOS image sensors)

[0285] Figure 37 A schematic diagram illustrating an example of the use of the CMOS image sensor described above.

[0286] For example, as described above, the CMOS image sensor can be used in various situations, such as for sensing visible light, infrared light, ultraviolet light, and X-ray light.

[0287] - A device provided for capturing images for viewing, such as a digital camera, and mobile devices with camera functionality.

[0288] - An apparatus provided for use in traffic, such as onboard sensors for taking pictures of the front, rear, surroundings and interior of a vehicle for safe driving such as automatic stopping and for identifying driver status, surveillance cameras for monitoring vehicles and roads in motion, and distance measurement sensors for measuring distances between vehicles.

[0289] - A device provided for use in household appliances such as televisions, refrigerators, and air conditioners, for taking pictures of a user's posture in order to operate the household appliances based on that posture.

[0290] - A device provided for medical and healthcare purposes, such as an endoscope and apparatus for angiography by receiving infrared light.

[0291] - A type of device provided for security purposes, such as surveillance cameras for crime prevention and cameras for personnel authentication.

[0292] - A device provided for cosmetic purposes, such as a skin measurement device that captures images of the skin and a microscope that captures images of the scalp.

[0293] - A device provided for use in sports, such as action cameras and wearable cameras for sports applications.

[0294] - A type of equipment provided for agriculture, such as cameras used to monitor the condition of fields and crops.

[0295] The effects described in this specification are illustrative and not limited. Other effects may exist.

[0296] Furthermore, the embodiments of this disclosure are not intended to be limited to the embodiments described above, and various modifications are possible without departing from the scope of this disclosure.

[0297] This disclosure can also be applied to charge-coupled device (CCD) image sensors, and is not limited to CMOS image sensors.

[0298] This publication can also be configured as follows. (1)

[0300] A solid-state image capture element wherein at least a portion of the region between the floating diffusion wiring connected to the floating diffusion node and wiring other than the floating diffusion wiring is a hollow region. (2)

[0302] According to the solid-state image capture element of (1), wherein the floating diffusion wiring is in contact with the hollow region. (3)

[0304] According to the solid-state image capture element of (1), wherein the floating diffusion wiring is not in contact with the hollow region. (4)

[0306] According to one of (1) to (3) above, the solid-state image capture element, wherein the hollow region is the region between the floating diffusion wiring and the wiring other than the floating diffusion wiring, and the region other than the region between the floating diffusion wiring and the TRG wiring connected to the transmission transistor. (5)

[0308] According to one of the solid-state image capture elements (1) to (4) above, at least a portion of the area around the vertical signal line is a hollow region. (6)

[0310] According to one of the solid-state image capture elements (1) to (5) above, wherein the floating diffusion wiring is one of a plurality of floating diffusion wirings that are self-grounded to a plurality of floating diffusion nodes. (7)

[0312] According to the solid-state image capture element of (1) above, the number of hollow regions is multiple. (8)

[0314] According to the solid-state image capture element of (1) or (7) above, an insulating film is formed in the region other than the hollow region in the region between the floating diffusion wiring and the wiring other than the floating diffusion wiring. (9)

[0316] According to the solid-state image capturing element of (8) above, the materials of the insulating film formed around the upper part of the hollow region and the materials of the insulating film formed around the lower part of the hollow region are different. (10)

[0318] According to the solid-state image capture element of (9) above, the lower part of the hollow region has a larger size than the upper part. (11)

[0320] According to the solid-state image capture element of (10) above, there are multiple hollow regions, and the lower parts of the multiple hollow regions are connected together, and their upper parts are connected together. (12)

[0322] According to one of (1) and (7) to (11) above, a solid-state image capture element wherein at least a portion of the region between the floating diffusion wiring and the semiconductor substrate in contact with the floating diffusion wiring is a hollow region. (13)

[0324] According to one of (1) and (7) to (11) above, the solid-state image capture element includes:

[0325] A first semiconductor substrate on which the floating diffused wiring, the wiring other than the floating diffused wiring, and a wiring layer forming the hollow region therein are stacked;

[0326] A second semiconductor substrate, which is bonded to the first semiconductor substrate; and

[0327] The connection portion electrically connects the first semiconductor substrate to the second semiconductor substrate, wherein a hollow region is formed around the connection portion of the wiring layer. (14)

[0329] According to the solid-state image capture element of (13) above, the hollow region formed around the connection portion of the wiring layer penetrates the first semiconductor substrate. (15)

[0331] An electronic device, comprising:

[0332] A solid-state image capture element, wherein at least a portion of the region between the floating diffusion wiring connected to the floating diffusion node and wiring other than the floating diffusion wiring is a hollow region. (16)

[0334] A solid-state image capture element, comprising:

[0335] First semiconductor substrate;

[0336] A second semiconductor substrate, which is bonded to the first semiconductor substrate; and

[0337] The connection portion electrically connects the first semiconductor substrate to the second semiconductor substrate, wherein a hollow region is formed around the connection portion of the wiring layer stacked on the first semiconductor substrate.

[0338] [List of Reference Symbols]

[0339] 50 CMOS image sensor, 53 vertical signal line, 92 transmission transistor, 93FD, 132FD wiring, 133 wiring, 134TRG wiring, 135, 201 to 206, 221, 241 hollow regions, 301, 302FD, 320 CMOS image sensor, 321, 322 semiconductor substrate, 351, 352 wiring layer, 353 insulating film, 361FD wiring, 364A to 364C hollow regions, 421 insulating film, 432 hollow region, 452TSV, 1000 image capture device, 1002 solid-state image capture element.

Claims

1. A semiconductor device, comprising: Semiconductor substrate; as well as A wiring layer disposed on the semiconductor substrate, and comprising: First wiring; Second wiring; A first hollow region, wherein the first hollow region is located between the first wiring and the second wiring, and the first wiring does not contact the first hollow region; and The second hollow region, wherein the second wiring is located between the first hollow region and the second hollow region, and The first wiring, the first hollow area, the second wiring, and the second hollow area are arranged sequentially in the first direction.

2. The semiconductor device according to claim 1, wherein In the cross-sectional view, no wiring is provided above the first hollow region and the second hollow region.

3. The semiconductor device according to claim 1 or 2, wherein The first wiring and the second wiring are disposed in the same wiring layer and arranged in parallel in the first direction, wherein, in a cross-sectional view, the dimension of the first hollow region in a second direction perpendicular to the first direction is greater than the dimensions of the first wiring and the second wiring in the second direction.

4. The semiconductor device according to claim 1, wherein The second wiring does not contact either the first hollow region or the second hollow region.

5. The semiconductor device according to claim 1, wherein The first direction is the horizontal direction.

6. The semiconductor device according to claim 1, wherein The wiring layer further includes a third wiring, and the second hollow region is located between the second wiring and the third wiring.

7. The semiconductor device according to claim 1 or 2, wherein The first hollow region includes a portion of the region between the first wiring and the second wiring.

8. The semiconductor device according to claim 1 or 2, further comprising: A first film comprising silicon oxide disposed in the wiring layer, wherein the first film is disposed between the first wiring and the first hollow region.

Images