Display substrate and display device

Abstract

The embodiments of the present disclosure provide a display substrate and a display device, wherein the display substrate comprises: a base substrate and a first blocking structure, a second blocking structure, a second planarization layer and a light-emitting device arranged on the base substrate; wherein the base substrate comprises a display area and a non-display area located around the display area; the first blocking structure and the second blocking structure are both located in the non-display area, and the second blocking structure is located on a side of the first blocking structure away from the display area; the first blocking structure comprises at least one first blocking wall, and the second blocking structure comprises at least one second blocking wall; the second planarization layer is located in the display area; the first electrode of the light-emitting device is located on a side of the second planarization layer away from the base substrate and is in contact with the second planarization layer; the surface of the first blocking wall away from the base substrate is higher than the surface of the second blocking wall away from the base substrate, and the surface of the first blocking wall away from the base substrate is lower than the surface of the second planarization layer away from the base substrate.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) devices are electroluminescent devices based on organic semiconductor materials. With the rapid development of the OLED display industry, the requirements for the luminous efficiency of OLED devices are getting higher and higher. Summary of the invention

[0003] Embodiments of the present disclosure provide a display substrate and a display device.

[0004] In a first aspect, an embodiment of the present disclosure provides a display substrate, comprising: a base substrate, and a first blocking structure, a second blocking structure, a second planarization layer, and a light-emitting device arranged on the base substrate; wherein:

[0005] The base substrate comprises a display area and a non-display area located around the display area;

[0006] The first blocking structure and the second blocking structure are both located in the non-display area, and the second blocking structure is located on a side of the first blocking structure away from the display area; the first blocking structure includes at least one first blocking wall, and the second blocking structure includes at least one second blocking wall;

[0007] The second planarization layer is located in the display area;

[0008] The light emitting device comprises a stacked first electrode, a light emitting functional layer and a second electrode, wherein the first electrode is located on a side of the second planarization layer away from the base substrate and in contact with the second planarization layer;

[0009] A surface of the first barrier wall away from the base substrate is higher than a surface of the second barrier wall away from the base substrate, and a surface of the first barrier wall away from the base substrate is lower than a surface of the second planarization layer away from the base substrate.

[0010] In some embodiments, the display substrate further comprises a third blocking structure disposed on the base substrate, the third blocking structure comprising at least one third blocking wall;

[0011] The third blocking structure is located in the non-display area, and the second blocking structure is located on a side of the third blocking structure close to the display area;

[0012] A surface of the third barrier wall away from the substrate is higher than a surface of the second barrier wall away from the substrate.

[0013] In some embodiments, a ratio of a height of the first blocking structure to a height of the third blocking structure is between 0.9 and 1.1.

[0014] In some embodiments, the first barrier wall includes n first film layers stacked together, the second barrier wall includes m second film layers stacked together, and the third barrier wall includes n third film layers stacked together, wherein m and n are both positive integers, and n>m;

[0015] The display substrate further comprises:

[0016] A first planarization layer, a first passivation layer, and a second passivation layer are located between the second planarization layer and the base substrate, and the first planarization layer, the first passivation layer, and the second passivation layer are sequentially arranged in a direction away from the base substrate;

[0017] A switching electrode, wherein the switching electrode is located between the first passivation layer and the second passivation layer;

[0018] A thin film transistor, wherein the thin film transistor is located between the first planarization layer and the base substrate, and the switching electrode and the source and drain of the thin film transistor are connected through a via hole penetrating the first planarization layer and the first passivation layer;

[0019] The first planarization layer, the first passivation layer, the second passivation layer, the switching electrode and the thin film transistor are all located in the display area;

[0020] The n first film layers are respectively arranged on the same layer as the source and drain of the thin film transistor, the first planarization layer, the first passivation layer, the switching electrode, and the second passivation layer; the m second film layers are respectively arranged on the same layer as the source and drain of the thin film transistor, the first passivation layer, the switching electrode, and the second passivation layer; the n third film layers are respectively arranged on the same layer as the source and drain of the thin film transistor, the first planarization layer, the first passivation layer, the switching electrode, and the second passivation layer;

[0021] A first film layer in the first barrier wall that is disposed in the same layer as the first planarization layer is connected to the first planarization layer.

[0022] In some embodiments, the film layer disposed on the same layer as the switching electrode in the first barrier wall, the second barrier wall, and the third barrier wall, and the film layer disposed on the same layer as the source and drain of the thin film transistor in the second barrier wall, all have a first side surface close to the display area and a second side surface away from the display area, and grooves are formed on the first side surface and the second side surface.

[0023] In some embodiments, the first barrier wall includes n first film layers stacked together, the second barrier wall includes m second film layers stacked together, and the third barrier wall includes n third film layers stacked together, wherein m and n are both positive integers, and n>m;

[0024] The display substrate further comprises:

[0025] A first planarization layer, a first passivation layer, and a second passivation layer are located between the second planarization layer and the base substrate, and the first planarization layer, the first passivation layer, and the second passivation layer are sequentially arranged in a direction away from the base substrate;

[0026] A switching electrode, wherein the switching electrode is located between the first passivation layer and the second passivation layer;

[0027] A thin film transistor, wherein the thin film transistor is located between the first planarization layer and the base substrate, and the switching electrode and the source and drain of the thin film transistor are connected through a via hole penetrating the first planarization layer and the first passivation layer;

[0028] The first planarization layer, the first passivation layer, the second passivation layer, the switching electrode and the thin film transistor are all located in the display area;

[0029] The n first film layers are respectively arranged on the same layer as the source and drain of the thin film transistor, the first passivation layer, the switching electrode, the second passivation layer, and the second planarization layer; the m second film layers are respectively arranged on the same layer as the source and drain of the thin film transistor, the first passivation layer, the switching electrode, and the second passivation layer; the n third film layers are respectively arranged on the same layer as the source and drain of the thin film transistor, the first passivation layer, the switching electrode, the second passivation layer, and the second planarization layer;

[0030] The film layer in the first barrier wall disposed in the same layer as the second planarization layer is connected to the second planarization layer.

[0031] In some embodiments, the film layers in the second barrier wall, which are respectively arranged in the same layers as the switching electrode and the source and drain of the thin film transistor, have a third side surface close to the display area and a fourth side surface away from the display area, and grooves are formed on the third side surface and the fourth side surface.

[0032] In some embodiments, the first blocking structure includes a plurality of first blocking walls arranged at intervals, and the plurality of first blocking walls are arranged in sequence along a direction close to the display area;

[0033] The second blocking structure includes a plurality of second blocking walls arranged at intervals, and the plurality of second blocking walls are arranged in sequence along a direction close to the display area;

[0034] The third barrier structure includes a plurality of third barrier walls that are spaced apart from each other, and the plurality of third barrier walls are sequentially arranged in a direction close to the display area.

[0035] In some embodiments, the ratio of the width of the first blocking structure and the third blocking structure to the width of the second blocking structure is between 0.8 and 1.2;

[0036] A first gap is formed between the first blocking structure and the second blocking structure, a second gap is formed between the second blocking structure and the third blocking structure, and the first gap and the second gap have the same width.

[0037] In a second aspect, an embodiment of the present disclosure provides a display device, comprising the display substrate described in the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:

[0039] Figure 1 It is a schematic diagram of the planar structure of a special-shaped display substrate;

[0040] Figure 2 A schematic structural diagram of a display substrate provided in an embodiment of the present disclosure;

[0041] Figure 3 A schematic structural diagram of another display substrate provided in an embodiment of the present disclosure;

[0042] Figure 4 A schematic structural diagram of another display substrate provided in an embodiment of the present disclosure;

[0043] Figure 5 A schematic structural diagram of a blocking structure provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0044] The specific implementation of the present disclosure is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described herein is only used to illustrate and explain the present disclosure, and is not used to limit the present disclosure.

[0045] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0046] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not represent any order, quantity or importance, but are only used to distinguish different components. Similarly, "including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0047] The "same-layer arrangement" in the embodiments of the present disclosure means that multiple structures are formed by the same material layer through a composition process, so these structures are in the same layer in terms of stacking relationship; but this does not mean that the distances between these structures and the substrate must be the same.

[0048] In the field of OLED display, in order to meet the product design of the display substrate, in some products, the plane shape of the display substrate can be designed to be a special shape different from a rectangle. Figure 1 is a schematic diagram of a planar structure of a special-shaped display substrate, such as Figure 1 As shown, the display substrate can be designed as a D-shaped special-shaped structure. During the use of the special-shaped display substrate, it is easy to be physically squeezed and collided, and the risk of cracks is high. The display effect of the display substrate with cracks will be affected, affecting the product yield. Therefore, in the non-display area around the display area of ​​the display substrate, in addition to leaving space for the binding area a, a barrier wall b needs to be set to achieve the packaging effect of the display substrate.

[0049] A thin film transistor, a passivation layer, a planarization layer, a light-emitting device and a pixel defining layer are arranged in the display area of ​​the display substrate, wherein the passivation layer is located on a side of the thin film transistor away from the base substrate, the planarization layer is located on a side of the passivation layer away from the base substrate, the first electrode of the light-emitting device is located between the pixel defining layer and the planarization layer, and the first electrode is connected to the source and drain of the thin film transistor through a via hole penetrating the passivation layer and the planarization layer, a plurality of accommodating portions are formed on the pixel defining layer, and a portion of the first electrode is exposed by the accommodating portion.

[0050] In the process of preparing the display substrate, in order to simplify the preparation process, the film layer in the barrier wall b in the non-display area is arranged in the same layer as some film layers in the display area. For example, the barrier wall b includes a first film layer, a second film layer and a third film layer arranged in sequence away from the base substrate, the first film layer is arranged in the same layer as the source and drain of the thin film transistor, the second film layer is arranged in the same layer as the passivation layer, and the third film layer is arranged in the same layer as the planarization layer. However, since the display area is also provided with structures such as the gate and active layer of the thin film transistor, after the planarization layer is manufactured, a step difference will be formed between the film layer structure in the display area and the film layer structure of the barrier wall.

[0051] The material of the pixel definition layer includes an organic material. When preparing the pixel definition layer, a spraying device can be used along the Figure 1 In the X direction of the spray coating, the colloid is coated on the display area, and the colloid is cured, and then the cured colloid is patterned to form a pixel definition layer. However, due to the operational limitations of the spray coating equipment, when there is a large step difference between the film layer structure in the display area of ​​the display substrate and the film layer structure of the barrier wall in the non-display area, the colloid is prone to large-area loss in the area close to the non-display area, resulting in loss of the formed pixel definition layer, thereby affecting the product yield of the display substrate.

[0052] In order to solve at least one of the above technical problems, the embodiment of the present disclosure provides a display substrate, which reduces the step difference between the upper surface of the barrier wall and the upper surface of the planarization layer to avoid large-area loss of the colloid forming the pixel defining layer during the spraying process, thereby improving the product yield of the display substrate. The upper surface of a structure refers to the surface of the structure away from the base substrate.

[0053] Figure 2 A schematic diagram of the structure of a display substrate provided in an embodiment of the present disclosure is shown in FIG. Figure 2 As shown, the display substrate includes: a base substrate 1, a first barrier structure RIB10, a second barrier structure RIB20, a second planarization layer PLN2 and a light emitting device 2. The first barrier structure RIB10 may include at least one first barrier wall RIB1, and the second barrier structure RIB20 may include at least one second barrier wall RIB2.

[0054] The base substrate 1 includes a display area AA and a non-display area NA located around the display area AA; the first blocking structure RIB10 and the second blocking structure RIB20 are both located in the non-display area NA, the second blocking structure RIB20 is located on the side of the first blocking structure RIB10 away from the display area AA, the first blocking structure RIB10 includes at least one first blocking wall RIB1, and the second blocking structure RIB20 includes at least one second blocking wall RIB2. The second planarization layer PLN2 is located in the display area AA.

[0055] The light-emitting device 2 includes a first electrode 21, a light-emitting functional layer 22 and a second electrode 23 located on the side of the second planarization layer PLN2 away from the base substrate 1, and the first electrode 21, the light-emitting functional layer 22 and the second electrode 23 are arranged in sequence along a direction away from the second planarization layer PLN2, and the first electrode 21 is in contact with the second planarization layer PLN2.

[0056] The surface of the first barrier wall RIB1 away from the base substrate 1 is higher than the surface of the second barrier wall RIB2 away from the base substrate 1 , and the surface of the first barrier wall RIB1 away from the base substrate 1 is lower than the surface of the second planarization layer PLN2 away from the base substrate 1 .

[0057] It should be noted that Figure 2 Only the display substrate structure in which the first barrier structure RIB10 includes a first barrier wall RIB1 and the second barrier structure RIB20 includes a second barrier wall RIB2 is shown. Also, in the present disclosure, a certain surface A is "higher" than another surface B, which means that the distance from the surface A to the substrate 1 is greater than the distance from the surface B to the substrate 1; a certain surface C is "lower" than another surface D, which means that the distance from the surface C to the substrate 1 is less than the distance from the surface D to the substrate 1.

[0058] In addition, the display substrate also includes a pixel defining layer PDL arranged in the display area AA, which is located on the side of the second planarization layer PLN2 away from the base substrate 1 and includes a plurality of accommodating portions. The first electrode 21 is located between the pixel defining layer PDL and the second planarization layer PLN2, and a portion of the first electrode 21 is exposed by the accommodating portion. In addition, the above-mentioned light-emitting functional layer 22 may include: a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer and an electron injection layer stacked in sequence. In one example, the first electrode 21 may be an anode, and the second electrode 23 may be a cathode. Optionally, the first electrode 21 is a reflective electrode made of a metal material, and the second electrode 23 is a transparent electrode made of a transparent conductive material (for example, indium tin oxide). The second electrodes 23 of multiple light-emitting devices 2 may be formed into an integrated structure.

[0059] The display substrate provided by the embodiment of the present disclosure has a surface of the first barrier wall RIB1 away from the base substrate 1 that is higher than the surface of the second barrier wall RIB2 away from the base substrate 1 and lower than the surface of the second planarization layer PLN2 away from the base substrate 1, so that a step structure is formed among the second planarization layer PLN2, the first barrier wall RIB1 and the second barrier wall RIB2 to buffer the large-size step difference between the second planarization layer PLN2 and the second barrier wall RIB2, avoid large-area missing of the colloid forming the pixel defining layer in the area close to the non-display area, and improve the product yield of the display substrate.

[0060] In some embodiments, Figure 2 As shown, the display substrate further includes a third blocking structure RIB30 disposed on the base substrate 1, which includes at least one third blocking wall RIB3; the third blocking structure RIB30 is located in the non-display area NA, and the second blocking structure RIB20 is located on a side of the third blocking structure RIB30 close to the display area AA.

[0061] It should be noted that Figure 2 Only the display substrate structure in which the third barrier structure RIB30 includes one third barrier wall RIB3 is shown.

[0062] Usually, the display substrate is not prepared and formed separately, but each film layer is formed in sequence in each substrate area of ​​a large-size substrate motherboard to form a display substrate motherboard, and then the display substrate motherboard is cut along the redundant area between the substrate areas to form multiple display substrates. Among them, while each film layer is formed in each substrate area of ​​the substrate motherboard, a corresponding redundant film layer is also formed in the redundant area synchronously. For example, while the second planarization layer is formed in the substrate area, a redundant planarization layer is also formed in the redundant area. The height of the redundant planarization layer is substantially the same as that of the upper surface of the second planarization layer. When forming the pixel defining layer, the colloid is coated on each substrate area along the preset direction. If the step difference between the upper surface of the third barrier wall RIB3 and the upper surface of the redundant planarization layer is large, the redundant area will also have a lack of glue coating, which can easily cause false alarms of the production equipment and affect production efficiency.

[0063] To prevent this phenomenon, in the embodiment of the present disclosure, the surface of the third barrier wall RIB3 away from the base substrate 1 is higher than the surface of the second barrier wall RIB2 away from the base substrate 1, so as to buffer the step difference between the second barrier wall RIB2 and the redundant area, thereby avoiding the problem of reduced production efficiency caused by the lack of glue coating in the redundant area.

[0064] In some embodiments, the ratio of the height of the first barrier structure RIB1 to the height of the third barrier structure RIB3 is between 0.9 and 1.1. The height of the first barrier structure RIB1 refers to the distance between the surface of the first barrier wall RIB1 away from the substrate substrate 1 and the substrate substrate 1, and the height of the third barrier structure RIB3 refers to the distance between the surface of the third barrier wall RIB3 away from the substrate substrate 1 and the substrate substrate 1. For example, the height of the first barrier structure RIB1 is equal to the height of the third barrier structure RIB3.

[0065] In some embodiments, Figure 2As shown, the first barrier wall RIB1 includes n film layers stacked together, and each film layer in the first barrier wall RIB1 is recorded as a first film layer. The second barrier wall RIB2 includes m film layers stacked together, and each film layer in the second barrier wall RIB2 is recorded as a second film layer. The third barrier wall RIB3 includes n film layers stacked together, and each film layer in the third barrier wall RIB3 is recorded as a third film layer, wherein m and n are both positive integers, and n>m. By setting different numbers of film layer structures, a step difference between the first barrier wall RIB1 / the third barrier wall RIB3 and the second barrier wall RIB2 is formed.

[0066] Each second film layer is disposed on the same layer as a first film layer, and each second film layer is disposed on the same layer as a third film layer. Figure 2 As shown, the n first film layers in the first barrier wall RIB1 are respectively a1, a2, a3, a4, and a5, the m second film layers in the second barrier wall RIB2 are respectively b1, b2, b3, and b4, and the n third film layers in the third barrier wall RIB3 are respectively c1, c2, c3, c4, and c5, among which a1, b1, and c1 are arranged in the same layer; a2, b2, and c3 are arranged in the same layer; a3, b3, and c3 are arranged in the same layer; and a4, b4, and c4 are arranged in the same layer, thereby simplifying the manufacturing process of the display substrate.

[0067] In some embodiments, Figure 2 As shown, the display substrate also includes a first planarization layer PLN1, a first passivation layer PVX1 and a second passivation layer PVX2, a switching electrode 3, and a thin film transistor 4. The thin film transistor 4 includes a first electrode 41, a second electrode 42, an active layer 43 and a gate 44, wherein one of the first electrode 41 and the second electrode 42 is a source electrode, and the other is a drain electrode.

[0068] The first planarization layer PLN1, the first passivation layer PVX1 and the second passivation layer PVX2 are all located between the second planarization layer PLN2 and the base substrate 1, and the first planarization layer PLN1, the first passivation layer PVX1 and the second passivation layer PVX2 are arranged in sequence in a direction away from the base substrate 1. The switching electrode 3 is located between the first passivation layer PVX1 and the second passivation layer PVX2. The thin film transistor 4 is located between the first planarization layer PLN1 and the base substrate 1, and the switching electrode 3 and the first pole 41 of the thin film transistor are connected through a via hole penetrating the first planarization layer PLN1 and the first passivation layer PVX1. The first planarization layer PLN1, the first passivation layer PVX1 and the second passivation layer PVX2, the switching electrode 3 and the thin film transistor 4 are all located in the display area AA.

[0069] In some embodiments, the m second film layers are respectively arranged in the same layer with the source and drain of the thin film transistor, the first passivation layer PVX1, the transfer electrode 3, and the second passivation layer PVX2. The n first film layers are respectively arranged in the same layer with the source and drain of the thin film transistor, the first planarization layer PLN1, the first passivation layer PVX1, the transfer electrode 3, and the second passivation layer PVX2. The n third film layers are respectively arranged in the same layer with the source and drain of the thin film transistor, the first planarization layer PLN1, the first passivation layer PVX1, the transfer electrode 3, and the second passivation layer PVX2.

[0070] It should be noted that the source and drain of the thin film transistor are arranged in the same layer. In the present disclosure, “arranged in the same layer as the source and drain of the thin film transistor” means that they are arranged in the same layer as the source and drain of the thin film transistor.

[0071] Specifically, Figure 2 As shown, in the first barrier wall RIB1, a1 is arranged in the same layer as the source and drain of the thin film transistor, a2 is arranged in the same layer as the first passivation layer PVX1, a3 is arranged in the same layer as the switching electrode 3, a4 is arranged in the same layer as the second passivation layer PVX2, and a5 is arranged in the same layer as the first planarization layer PLN1; in the second barrier wall RIB2, b1 is arranged in the same layer as the source and drain of the thin film transistor, b2 is arranged in the same layer as the first passivation layer PVX1, b3 is arranged in the same layer as the switching electrode 3, and b4 is arranged in the same layer as the second passivation layer PVX2; in the third barrier wall RIB3, c1 is arranged in the same layer as the source and drain of the thin film transistor, c2 is arranged in the same layer as the first passivation layer PVX1, c3 is arranged in the same layer as the switching electrode 3, c4 is arranged in the same layer as the second passivation layer PVX2, and c5 is arranged in the same layer as the first planarization layer PLN1. By adding a film layer arranged on the same layer as the first flat layer on the first barrier wall RIB1 and the third barrier wall RIB3, a difference in the number of film layers is formed with the second barrier wall RIB2, so that the first barrier wall RIB1 and the third barrier wall RIB3 have a height difference with the second barrier wall RIB2.

[0072] The materials of the above-mentioned first planarization layer PLN1 and the second planarization layer PLN2 may include organic insulating materials, for example, organic insulating materials include polyimide, epoxy resin, acrylic, polyester, photoresist, polyacrylate, polyamide, siloxane and other resin materials, etc., and the present disclosure does not limit this.

[0073] The surfaces of the first planarization layer and the second planarization layer are substantially flat, thereby effectively avoiding color deviation, light leakage and the like caused by uneven film layers.

[0074] In some embodiments, Figure 2As shown, the first film layer arranged on the same layer as the first planarization layer PLN1 in the first barrier wall RIB1 is connected to the first planarization layer PLN1 as an integrated structure. Therefore, there is no need to etch and remove the first planarization layer PLN1 at the gap between the display area AA and the barrier wall, thereby simplifying the manufacturing process of the display substrate.

[0075] In some embodiments, a first gap is formed between the first barrier structure RIB10 and the second barrier structure RIB20 , and a second gap is formed between the second barrier structure RIB20 and the third barrier structure RIB30 . The widths of the first gap and the second gap are equal to facilitate manufacturing process.

[0076] When the first barrier structure RIB10 includes a plurality of first barrier walls RIB1, a gap is formed between two adjacent first barrier walls RIB1; when the second barrier structure RIB20 includes a plurality of second barrier walls RIB2, a gap is formed between two adjacent second barrier walls RIB2; when the third barrier structure RIB30 includes a plurality of third barrier walls RIB3, a gap is formed between two adjacent third barrier walls RIB3, thereby extending the path for external water vapor to invade the display area and improving the protection effect on the display area. The gap between each adjacent first barrier walls RIB1, the gap between each adjacent second barrier walls RIB2, and the gap between each adjacent third barrier walls RIB3 can be equal to the width of the first gap or the second gap, so as to facilitate the process.

[0077] It should be noted that the width of each slit refers to the size of the slit in the direction from the first barrier wall RIB1 to the second barrier wall RIB2. In addition, the equal widths of two slits in the present disclosure means that the difference in width between the two slits is less than 10% of the width of any slit.

[0078] In some embodiments, Figure 2 As shown in the figure, taking the example that each barrier structure includes only one barrier wall, the film layer arranged in the same layer as the switching electrode 3 in the first barrier wall RIB1, the second barrier wall RIB2 and the third barrier wall RIB3, and the film layer arranged in the same layer as the source and drain of the thin film transistor in the second barrier wall RIB2, all have a first side surface close to the display area AA and a second side surface away from the display area AA, and grooves are formed on the first side surface and the second side surface, that is, grooves are formed on both sides of the a3, b1, b3 and c3 film layers, which are used to block external water vapor and prevent water vapor from corroding the film layers in the display substrate, so as to achieve the packaging effect of the display substrate.

[0079] It should also be noted that if Figure 2As shown, the film layers a3, b3, c3 disposed in the same layer as the switching electrode 3 in the blocking structure, and the film layers a1, b1, c1 disposed in the same layer as the source and drain of the thin film transistor, can be made of a multilayer composed of metal, such as a Ti / Al / Ti stack. In one example, a dry etching process is used to etch the Ti / Al / Ti stack. Since Al is more active than Ti, that is, Al has poorer corrosion resistance than Ti, the etching rate of Al is greater than that of Ti. In the same time, the volume of Al etched away is larger than that of Ti, thereby forming a side groove.

[0080] Figure 3 FIG. 1 is a schematic diagram of another display substrate provided in an embodiment of the present disclosure. Also, each blocking structure includes only one blocking wall as an example. In other embodiments, for example Figure 3 As shown, n first film layers are respectively arranged on the same layer with the source and drain of the thin film transistor, the first passivation layer PVX1, the switching electrode 3, the second passivation layer PVX2, and the second planarization layer PLN2; n third film layers are respectively arranged on the same layer with the source and drain of the thin film transistor, the first passivation layer PVX1, the switching electrode 3, the second passivation layer PVX2, and the second planarization layer PLN2.

[0081] Specifically, Figure 3 As shown, the n first film layers in the first barrier wall RIB1 are respectively a1, a2, a3, a4, and a6, wherein a1 is arranged in the same layer as the source and drain of the thin film transistor, a2 is arranged in the same layer as the first passivation layer PVX1, a3 is arranged in the same layer as the switching electrode 3, a4 is arranged in the same layer as the second passivation layer PVX2, and a6 is arranged in the same layer as the second planarization layer PLN2; the m second film layers in the second barrier wall RIB2 are respectively b1, b2, b3, and b4, wherein b1 is arranged in the same layer as the source and drain of the thin film transistor, The first barrier wall RIB1 and the third barrier wall RIB3 are provided with a layer, b2 is provided with a layer in the same layer as the first passivation layer PVX1, b3 is provided with a layer in the same layer as the switching electrode 3, and b4 is provided with a layer in the same layer as the second passivation layer PVX2; the n third film layers in the third barrier wall RIB3 are c1, c2, c3, c4, and c6, wherein c1 is provided with a layer in the same layer as the source and drain of the thin film transistor, c2 is provided with a layer in the same layer as the first passivation layer PVX1, c3 is provided with a layer in the same layer as the switching electrode 3, c4 is provided with a layer in the same layer as the second passivation layer PVX2, and c6 is provided with a layer in the same layer as the second planarization layer PLN2. By adding a film layer provided with a layer in the same layer as the second planarization layer PLN2 on the first barrier wall RIB1 and the third barrier wall RIB3, a difference in the number of film layers with the second barrier wall RIB2 is formed, so that the first barrier wall RIB1 and the third barrier wall RIB3 both form a height difference with the second barrier wall RIB2.

[0082] It should be noted that if Figure 3As shown, the film layer a6 arranged on the same layer as the second planarizing layer PLN2 in the first barrier wall RIB1 is connected to the second planarizing layer PLN2 as an integral structure, the film layer a4 arranged on the same layer as the second passivation layer PVX2 in the first barrier wall RIB1 is connected to the second passivation layer PVX2 as an integral structure, and the film layer a2 arranged on the same layer as the first passivation layer PVX1 in the first barrier wall RIB1 is connected to the first passivation layer PVX1 as an integral structure. That is to say, the gap between the display area AA and the blocking structure is filled with the first passivation layer PVX1, the second passivation layer PVX2 and the second planarizing layer PLN2 in sequence in the direction away from the base substrate. There is no need to etch and remove the materials in the above-mentioned gaps, thereby simplifying the manufacturing process of the display substrate.

[0083] In some embodiments, when the first barrier structure RIB10 , the second barrier structure RIB20 , and the third barrier structure RIB30 each include a plurality of barrier walls, a gap is formed between two adjacent barrier walls.

[0084] In some embodiments, Figure 3 As shown in the figure, each barrier structure includes only one barrier wall, and gaps are formed between the first barrier wall RIB1 and the second barrier wall RIB2, and between the second barrier wall RIB2 and the third barrier wall RIB3; the film layers in the second barrier wall RIB2, which are respectively arranged in the same layer as the switching electrode 3 and the source and drain of the thin film transistor, have a third side surface close to the display area AA and a fourth side surface away from the display area AA, and grooves are formed on the third side surface and the fourth side surface. That is, grooves are formed on the b1 and b3 film layers of the second barrier wall RIB2 to block external water vapor, prevent water vapor from corroding the film layers in the display substrate, and achieve the packaging effect of the display substrate.

[0085] In some embodiments, Figure 2 , 3 As shown, taking the thin film transistor 4 as a top-gate thin film transistor 4 as an example, the gate 44 is located on the side of the active layer 43 away from the substrate 1, and the first pole 41 and the second pole 42 are located on the side of the gate 44 away from the substrate 1. The material of the active layer 43 may include, for example, inorganic semiconductor materials (for example, polycrystalline silicon, amorphous silicon, etc.), organic semiconductor materials, and oxide semiconductor materials. The active layer 43 includes a channel portion and a first connecting portion and a second connecting portion located on both sides of the channel portion, the first connecting portion is connected to the first pole 41 of the thin film transistor, and the second connecting portion is connected to the second pole 42 of the thin film transistor. Both the first connecting portion and the second connecting portion may be doped with impurities (for example, N-type impurities or P-type impurities) with a higher impurity concentration than that of the channel portion. The channel portion is directly opposite to the gate 44 of the thin film transistor. When the voltage signal loaded on the gate 44 reaches a certain value, a carrier path is formed in the channel portion, so that the second pole 42 and the first pole 41 of the thin film transistor are turned on.

[0086] like Figure 2 , 3 As shown, the display substrate further includes: a buffer layer BUF, a first gate insulating layer GI1, a second gate insulating layer GI2 and an interlayer insulating layer ILD. The buffer layer BUF is located between the base substrate 1 and the thin film transistor 4, and is used to prevent or reduce the diffusion of metal atoms and / or impurities from the base substrate 1 into the active layer 43 of the thin film transistor. The buffer layer BUF may include an inorganic material such as silicon oxide, silicon nitride and / or silicon oxynitride, and may be formed as a multilayer or a single layer.

[0087] The first gate insulating layer GI1 is located between the active layer 43 and the gate electrode 44 of the thin film transistor; the second gate insulating layer GI2 and the interlayer insulating layer ILD are located between the gate electrode 44 and the second electrode 42 of the thin film transistor, and the interlayer insulating layer ILD is located on the side of the second gate insulating layer GI2 away from the substrate 1. The materials of the first gate insulating layer GI1, the second gate insulating layer GI2 and the interlayer insulating layer ILD may include silicon compounds or metal oxides, and may be formed into a single layer or multiple layers, which is not limited in the embodiments of the present disclosure.

[0088] The buffer layer BUF, the first gate insulating layer GI1, the second gate insulating layer GI2 and the interlayer insulating layer ILD all extend from the display area AA to the non-display area NA, and the first blocking structure RIB1, the second blocking structure RIB2 and the third blocking structure RIB3 are all located on the side of the interlayer insulating layer ILD away from the base substrate 1.

[0089] The gate electrode layer is arranged on a side of the first gate insulating layer GI1 away from the substrate 1. The gate electrode layer includes the gate 44 of each thin film transistor and the first electrode plate of the capacitor. The material of the gate electrode layer may include, for example, metal, metal alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. For example, the gate electrode layer may include gold, gold alloy, silver, silver alloy, aluminum, aluminum alloy, aluminum nitride, tungsten, tungsten nitride, copper, copper alloy, nickel, chromium, chromium nitride, molybdenum, molybdenum alloy, titanium, titanium nitride, platinum, tantalum, tantalum nitride, neodymium, scandium, strontium ruthenium oxide, zinc oxide, tin oxide, indium oxide, gallium oxide, indium tin oxide, indium zinc oxide, etc. The gate electrode layer may have a single layer or multiple layers.

[0090] Figure 4 FIG. 1 is a schematic diagram of another structure of a display substrate provided in an embodiment of the present disclosure. Also, taking the example that each blocking structure includes only one blocking wall, in some embodiments, such as Figure 4 As shown, the second electrode plate 45 of the capacitor is arranged on the side of the second gate insulating layer GI2 away from the base substrate 1 and connected to the second electrode 42 of the thin film transistor. Its material can be the same as that of the first electrode plate, which will not be repeated here.

[0091] In some embodiments, the first barrier structure RIB10 includes a plurality of first barrier walls RIB1 arranged at intervals, and the plurality of first barrier walls RIB1 are arranged in sequence along the direction close to the display area; the second barrier structure RIB20 includes a plurality of second barrier walls RIB2 arranged at intervals, and the plurality of second barrier walls RIB2 are arranged in sequence along the direction close to the display area; the third barrier structure RIB30 includes a plurality of third barrier walls RIB3 arranged at intervals, and the plurality of third barrier walls RIB3 are arranged in sequence along the direction close to the display area. The function of the barrier structure in the display substrate is to isolate water vapor to protect the various film layers in the display substrate from corrosion. By arranging a plurality of barrier walls in each barrier structure, the protection effect of the various film layers in the display area is improved.

[0092] In some embodiments, the ratio of the width of the first barrier structure RIB10 and the third barrier structure RIB30 to the width of the second barrier structure RIB20 is between 0.8 and 1.2. For example, the first barrier structure RIB10 may include 10 first barrier walls RIB1, the third barrier structure RIB30 may include 10 third barrier walls RIB3, and the second barrier structure RIB2 may also include 10 second barrier walls RIB2, so that the ratio of the width of the first barrier structure RIB10 and the third barrier structure RIB30 to the width of the second barrier structure RIB20 is 1:1.

[0093] Taking the example of adding a film layer disposed on the same layer as the second planarization layer PLN2 to the first blocking structure RIB10 and the third blocking structure RIB30, the embodiment of the present disclosure provides a specific structure of a blocking structure. Figure 5 This is a schematic diagram of a barrier structure provided by an embodiment of the present disclosure. In some embodiments, the widths of the first barrier structure RIB10 and the third barrier structure RIB30 may be the same or different, and the widths of the first barrier structure RIB10, the second barrier structure RIB20 and the third barrier structure RIB30 may be the same or different. Figure 5 As shown, the first barrier structure RIB10 includes q1 first barrier walls RIB1, the second barrier structure RIB20 includes q2 second barrier walls RIB2, and the third barrier structure RIB30 includes q3 third barrier walls RIB3, and a gap is formed between two adjacent barrier walls. The above q1, q2 and q3 are all integers greater than 1, and q1, q2 and q3 can be equal or unequal, which is not limited in the embodiments of the present disclosure. For example, the widths of the three barrier structures are the same, and q1, q2 and q3 are all 10. By providing the first barrier structure RIB10, the second barrier structure RIB20 and the third barrier structure RIB30 with a plurality of barrier walls, the path for external water vapor to enter the display area of ​​the display substrate can be extended, thereby improving the protection effect of the structure in the display area.

[0094] It should also be noted that the film layers arranged on the same layer as the second planarization layer PLN2 in the multiple first barrier walls RIB1 in the first blocking structure RIB10 can be arranged at intervals or connected as an integrated structure, and the film layers arranged on the same layer as the second planarization layer PLN2 in the multiple third barrier walls RIB3 in the third blocking structure RIB30 can be arranged at intervals or connected as an integrated structure, and the embodiments of the present disclosure are not limited to this.

[0095] The embodiment of the present disclosure also provides a display device, comprising the above-mentioned display substrate.

[0096] The above-mentioned display device can be: electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator and any other product or component with display function, which is not limited in the present disclosure.

[0097] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A display substrate, characterized in that: include: A base substrate and a first blocking structure, a second blocking structure, a second planarization layer and a light emitting device arranged on the base substrate; wherein, The base substrate comprises a display area and a non-display area located around the display area; The first blocking structure and the second blocking structure are both located in the non-display area, and the second blocking structure is located on a side of the first blocking structure away from the display area; The first blocking structure includes at least one first blocking wall, and the second blocking structure includes at least one second blocking wall; The second planarization layer is located in the display area; The light emitting device comprises a stacked first electrode, a light emitting functional layer and a second electrode, wherein the first electrode is located on a side of the second planarization layer away from the base substrate and in contact with the second planarization layer; A surface of the first barrier wall away from the base substrate is higher than a surface of the second barrier wall away from the base substrate, and a surface of the first barrier wall away from the base substrate is lower than a surface of the second planarization layer away from the base substrate.

2. The display substrate according to claim 1, characterized in that: The display substrate further comprises a third blocking structure disposed on the base substrate, wherein the third blocking structure comprises at least one third blocking wall; The third blocking structure is located in the non-display area, and the second blocking structure is located on a side of the third blocking structure close to the display area; A surface of the third barrier wall away from the substrate is higher than a surface of the second barrier wall away from the substrate.

3. The display substrate according to claim 2, characterized in that: The ratio of the height of the first blocking structure to the height of the third blocking structure is between 0.9 and 1.

1.

4. The display substrate according to claim 2, characterized in that: The first barrier wall comprises n first film layers stacked together, the second barrier wall comprises m second film layers stacked together, and the third barrier wall comprises n third film layers stacked together, wherein m and n are both positive integers, and n>m; The display substrate further comprises: A first planarization layer, a first passivation layer, and a second passivation layer are located between the second planarization layer and the base substrate, and the first planarization layer, the first passivation layer, and the second passivation layer are sequentially arranged in a direction away from the base substrate; A switching electrode, wherein the switching electrode is located between the first passivation layer and the second passivation layer; A thin film transistor, wherein the thin film transistor is located between the first planarization layer and the base substrate, and the switching electrode and the source and drain of the thin film transistor are connected through a via hole penetrating the first planarization layer and the first passivation layer; The first planarization layer, the first passivation layer, the second passivation layer, the switching electrode and the thin film transistor are all located in the display area; The n first film layers are respectively arranged on the same layer as the source and drain of the thin film transistor, the first planarization layer, the first passivation layer, the switching electrode, and the second passivation layer; the m second film layers are respectively arranged on the same layer as the source and drain of the thin film transistor, the first passivation layer, the switching electrode, and the second passivation layer; the n third film layers are respectively arranged on the same layer as the source and drain of the thin film transistor, the first planarization layer, the first passivation layer, the switching electrode, and the second passivation layer; A first film layer in the first barrier wall that is disposed in the same layer as the first planarization layer is connected to the first planarization layer.

5. The display substrate according to claim 4, characterized in that: The film layer in the first barrier wall, the second barrier wall and the third barrier wall which is arranged on the same layer as the switching electrode, and the film layer in the second barrier wall which is arranged on the same layer as the source and drain of the thin film transistor, all have a first side surface close to the display area and a second side surface away from the display area, and grooves are formed on the first side surface and the second side surface.

6. The display substrate according to claim 2, characterized in that: The first barrier wall comprises n first film layers stacked together, the second barrier wall comprises m second film layers stacked together, and the third barrier wall comprises n third film layers stacked together, wherein m and n are both positive integers, and n>m; The display substrate further comprises: A first planarization layer, a first passivation layer, and a second passivation layer are located between the second planarization layer and the base substrate, and the first planarization layer, the first passivation layer, and the second passivation layer are sequentially arranged in a direction away from the base substrate; A switching electrode, wherein the switching electrode is located between the first passivation layer and the second passivation layer; A thin film transistor, wherein the thin film transistor is located between the first planarization layer and the base substrate, and the switching electrode and the source and drain of the thin film transistor are connected through a via hole penetrating the first planarization layer and the first passivation layer; The first planarization layer, the first passivation layer, the second passivation layer, the switching electrode and the thin film transistor are all located in the display area; The n first film layers are respectively arranged on the same layer as the source and drain of the thin film transistor, the first passivation layer, the switching electrode, the second passivation layer, and the second planarization layer; the m second film layers are respectively arranged on the same layer as the source and drain of the thin film transistor, the first passivation layer, the switching electrode, and the second passivation layer; the n third film layers are respectively arranged on the same layer as the source and drain of the thin film transistor, the first passivation layer, the switching electrode, the second passivation layer, and the second planarization layer; The film layer in the first barrier wall disposed in the same layer as the second planarization layer is connected to the second planarization layer.

7. The display substrate according to claim 6, characterized in that: The film layers in the second barrier wall which are respectively arranged in the same layer as the switching electrode and the source and drain of the thin film transistor have a third side surface close to the display area and a fourth side surface away from the display area, and grooves are formed on the third side surface and the fourth side surface.

8. The display substrate according to any one of claims 2 to 7, characterized in that: The first blocking structure includes a plurality of first blocking walls arranged at intervals, and the plurality of first blocking walls are arranged in sequence along a direction close to the display area; The second blocking structure includes a plurality of second blocking walls arranged at intervals, and the plurality of second blocking walls are arranged in sequence along a direction close to the display area; The third barrier structure includes a plurality of third barrier walls that are spaced apart from each other, and the plurality of third barrier walls are sequentially arranged in a direction close to the display area.

9. The display substrate according to any one of claims 2 to 7, characterized in that: The ratios of the widths of the first blocking structure and the third blocking structure to the width of the second blocking structure are both between 0.8 and 1.2; A first gap is formed between the first blocking structure and the second blocking structure, a second gap is formed between the second blocking structure and the third blocking structure, and the first gap and the second gap have the same width.

10. A display device, characterized in that: A display substrate comprising any one of claims 1 to 9.

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