silicon oxynitride gradient design

Abstract

Embodiments of this disclosure generally relate to methods and apparatus for using low-temperature polysilicon (LTPS) thin-film transistors in liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays.

Description

[0001] This application is a divisional application of the invention patent application filed on June 15, 2016, with application number 201680023536.2 and title "Silicon Oxide Gradient Concept". background Technical Field

[0003] Embodiments of this disclosure generally relate to methods and apparatus for using low-temperature polysilicon (LTPS) thin-film transistors in liquid crystal displays and organic light-emitting diode displays. Background Technology

[0005] Due to the inherent temperature limitations of using large glass panels, low-temperature polycrystalline silicon (LTPS) is crucial for display technology. Thin-film transistors (TFTs) manufactured using LTPS exhibit improved semiconductor properties, enabling the formation of displays with higher resolutions. Therefore, LTPS TFTs offer the potential to improve electronic devices such as liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays.

[0006] With advancements in liquid crystal displays (LCDs) and organic light-emitting diode (OLED) technologies, the demand for higher resolutions has arisen. The interlayer transmittance of low-temperature polycrystalline silicon (LTPS) thin-film transistors (LTPS) is a significant obstacle to improving resolution. In particular, when adjacent layers have different refractive indices, the transmittance decreases, limiting resolution. One approach to improving resolution is to enhance the interlayer transmittance of LTPS.

[0007] Therefore, there is a need for improved light transmittance in low-temperature polycrystalline silicon thin-film transistors. Summary of the Invention

[0008] The embodiments described herein generally relate to liquid crystal displays and organic light-emitting diode devices with low-temperature polycrystalline silicon technology, including an inner layer with a matching refractive index for improved light transmittance.

[0009] More specifically, the embodiments described herein relate to a liquid crystal display or organic light-emitting diode device having two double layers disposed on a substrate. Each double layer includes a first inorganic layer having a first refractive index; a second inorganic layer having a second refractive index; and a transition stack structure disposed between the first and second inorganic layers. The first refractive index is less than the second refractive index. The transition stack structure includes at least a third and a fourth inorganic layer. In the transition stack structure, the third inorganic layer is disposed on the first inorganic layer and has a third refractive index; the fourth inorganic layer is disposed on the third inorganic layer and has a fourth refractive index. The third refractive index is greater than the first refractive index and less than the fourth refractive index. The fourth refractive index is greater than the third refractive index and less than the second refractive index. Liquid crystal layers are disposed on the two double layers.

[0010] The embodiments described herein also relate to liquid crystal displays or organic light-emitting diode devices having a gate insulator double layer and an interlayer dielectric layer disposed on a glass substrate. The gate insulator double layer includes a first inorganic layer having a first refractive index; a second inorganic layer having a second refractive index; and a transition stack structure disposed between the first and second inorganic layers. The first refractive index is less than the second refractive index. The transition stack structure includes at least a third and a fourth inorganic layer. The third inorganic layer is disposed on the first inorganic layer and has a third refractive index. The fourth inorganic layer is disposed on the third inorganic layer and has a fourth refractive index. The third refractive index is greater than the first refractive index and less than the fourth refractive index. The fourth refractive index is greater than the third refractive index and less than the second refractive index. The interlayer dielectric layer is disposed on the gate insulator double layer. The interlayer dielectric layer includes a fifth inorganic layer having a fifth refractive index; a sixth inorganic layer having a sixth refractive index; and a transition stack structure disposed between the fifth and sixth inorganic layers. The fifth refractive index is less than the sixth refractive index. The transition stack structure includes at least a seventh and an eighth inorganic layer. The seventh inorganic layer is disposed on the fifth inorganic layer and has the seventh refractive index. The eighth inorganic layer is disposed on the seventh inorganic layer and has the eighth refractive index. The seventh refractive index is greater than the fifth refractive index and less than the eighth refractive index. The eighth refractive index is greater than the seventh refractive index and less than the sixth refractive index. The liquid crystal layer is disposed on the interlayer dielectric layer. Attached Figure Description

[0011] To gain a more detailed understanding of the features described above in this disclosure, reference can be made to embodiments that provide a more specific description of the disclosure briefly outlined above, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only typical embodiments of the invention and should not be construed as limiting the scope of this disclosure, as other equally effective embodiments are permissible.

[0012] Figure 1 This is a cross-sectional schematic diagram of a plasma processing system according to one embodiment.

[0013] Figure 2 This is a cross-sectional schematic diagram of a thin-film transistor device according to one embodiment.

[0014] Figure 3A This is a detailed cross-sectional schematic diagram of a thin-film transistor device according to another embodiment.

[0015] Figure 3B This is a detailed cross-sectional schematic diagram of a thin-film transistor device according to another embodiment.

[0016] Figure 4 This is a cross-sectional schematic diagram of a thin-film transistor device according to another embodiment.

[0017] Figure 5 This is a detailed cross-sectional schematic diagram of a thin-film transistor device according to another embodiment.

[0018] Figure 6 This is a block diagram illustrating a method for manufacturing a thin-film transistor device according to one embodiment.

[0019] Figure 7A It is a graph that plots the typical energy dispersion n value of a silicon nitride layer over a wavelength range.

[0020] Figure 7B It is a graph showing the typical energy dispersion n value of a silicon oxide layer over a wavelength range.

[0021] Figure 8A It is a graph that plots the typical energy dispersion k-values ​​of a silicon nitride layer over a wavelength range.

[0022] Figure 8B This is a graph illustrating typical energy dispersion k values ​​of a silicon oxide layer over a wavelength range.

[0023] To aid understanding, the same reference numerals are used as much as possible to indicate common elements in the figures. It should be understood that, unless further described, elements and features of one embodiment may be advantageously incorporated into other embodiments. Detailed Implementation

[0024] The embodiments described herein generally provide methods and apparatus for using low-temperature polysilicon (LTPS) thin-film transistors in liquid crystal displays and organic light-emitting diode displays. In the following description, reference will be made to a plasma-enhanced chemical vapor deposition (PECVD) chamber; however, it should be understood that the embodiments described herein can also be implemented in other chambers (including, to name only, high-density plasma (HDP) deposition, physical vapor deposition (PVD) chambers, etching chambers, semiconductor processing chambers, solar cell processing chambers, and organic light-emitting display (OLED) processing chambers). Suitable chambers that can be used are available from AKT America, Inc. (a subsidiary of Applied Materials, Inc.) of Santa Clara, California. It should be understood that the embodiments discussed herein can also be implemented in chambers available from other manufacturers.

[0025] Figure 1 This is a cross-sectional schematic diagram of a plasma processing system 100 according to one embodiment. The plasma processing system 100 is configured to process a large-area substrate 101, using plasma to form structures and devices on the large-area substrate 101 for use in the manufacture of liquid crystal displays, flat panel displays, organic light-emitting diodes, or photovoltaic cells for solar cell arrays. The substrate 101 may be a sheet of a polymer from metal, plastic, organic materials, silicon, glass, quartz, or other suitable materials. The structure may be a thin-film transistor that may include multiple sequential deposition and masking steps. Other structures may include a pn junction forming a diode for a photovoltaic cell.

[0026] like Figure 1As shown, the plasma processing system 100 generally includes a chamber body 102. The chamber body 102 includes a bottom 117a and sidewalls 117b that at least partially define a processing space 111. A substrate support 104 is disposed in the processing space 111. The substrate support 104 is adapted to support a substrate 101 on a top surface during processing. The substrate support 104 is coupled to an actuator 138. The actuator 138 is adapted to move the substrate support at least vertically to assist in the transfer of the substrate 101 and / or adjust the distance D between the substrate 101 and the nozzle assembly 103. One or more lifting pins 110a-110d may extend through the substrate support 104.

[0027] Nozzle assembly 103 is configured to supply process gas to process space 111 from process gas source 122. Plasma processing system 100 also includes exhaust system 118, which is configured to provide negative pressure to process space 111.

[0028] During processing, one or more processing gases flow from gas source 122 through nozzle assembly 103 to processing space 111. Radio frequency (RF) power is applied by RF power supply 105 to generate plasma 108a from the processing gases. Plasma 108a is generated between nozzle assembly 103 and substrate support 104 for processing substrate 101. RF power supply 105 can also be used to maintain the energized gas species or further energize clean gas supplied by remote plasma source 107.

[0029] Figure 2 It is possible Figure 1 A cross-sectional schematic diagram of a thin-film transistor device manufactured by the equipment. Figure 6 Provide demonstrations, for example Figure 2 Block diagram 600 of a method for manufacturing a thin-film transistor according to the illustrated embodiment. A substrate 210 (typically glass) is provided. A buffer layer 220 is disposed on the glass substrate (see reference). Figure 6 (See block 610). The buffer layer 220 may include a barrier oxide (e.g., an inorganic material such as silicon oxide (SiO) or silicon nitride (SiN), or any material suitable for blocking sodium or other materials from the glass substrate). A gate interface and interlayer dielectric 230 are disposed over the buffer layer 220 (see reference). Figure 6 (Blocks 620 and 630). The gate interface and interlayer dielectric 230 may further include one or more inorganic layers. A photoacrylic layer 240 is disposed on the interlayer dielectric 230 (see reference). Figure 6(Box 640). An indium-tin-oxide (ITO) layer 250 is disposed on top of the photopolymer acrylic layer 240 (see reference). Figure 6 (See box 650). Silicon nitride layer 260 is disposed on indium tin oxide layer 250 (see reference). Figure 6 (Box 660). Another indium tin oxide layer 270 may be disposed on all or part of the silicon nitride layer 260 (see reference). Figure 6 (Box 670). A polyimide layer 280 is disposed on the exposed portions (if any) of the silicon nitride layer 260 and the indium tin oxide layer 260 (see reference). Figure 6 (The frame 680). The top layer of the stacked structure is the liquid crystal layer 290 (please refer to...). Figure 6 (The box is 690).

[0030] The gate interface layer and interlayer dielectric 230 may respectively include, for example, Figure 2 The close-up shows two layers. The gate interface layer may include an inorganic layer. For example, the gate interface layer may include a silicon oxide layer 232 and a silicon nitride layer 234. Similarly, the interlayer dielectric may include a silicon oxide layer 236 and a silicon nitride layer 238. Figure 7A As shown, the refractive index (n) of silicon nitride ranges from approximately 1.8 to 2.0, for example, 1.9. Figure 7B As shown, the refractive index of silicon oxide ranges from 1.4 to 1.48, for example, 1.46. The difference in refractive index between the silicon oxide layer and the silicon nitride layer is significant enough to cause some reflection at the interface between the silicon oxide layer 232 and the silicon nitride layer 234. Since these layers extend above the pixel electrode layer, the reflection will interfere with the light transmittance. Similarly, as Figure 8A and Figure 8BAs shown, within a wavelength range, the extinction coefficient (k) of silicon nitride differs from that of silicon oxide. This difference in extinction coefficients leads to attenuation of light as it passes through the medium. This attenuation causes interference with the light transmittance. Therefore, for the gate interface, an additional layer or set of layers may be disposed between silicon oxide layer 232 and silicon nitride layer 234. This additional layer or set of layers is a transition layer 233. Similarly, for the interlayer dielectric, an additional layer or set of layers may be disposed between silicon oxide layer 236 and silicon nitride layer 238. This additional layer or set of layers is a transition layer 237. The transition layers 233 and 237 are composed of one or a set of layers of silicon oxide, silicon nitride, and silicon oxynitride (SiON) in a gradually varying manner, providing a refractive index between that of silicon oxide and silicon nitride. The transition layers 233 and 237 may include at least two sublayers with varying oxygen and nitrogen contents, such that the refractive index difference between the silicon oxide layer 232 and the silicon nitride layer 234, and between the silicon oxide layer 236 and the silicon nitride layer 238, gradually changes. By reducing or gradually changing the refractive index difference, reflection is also reduced and light transmittance is enhanced.

[0031] For example, Figure 3A One implementation of a transition layer to reduce reflections is shown. Figure 3A In the process, the silicon oxide sublayer 236 of the interlayer dielectric is separated from the silicon nitride sublayer 238 of the interlayer dielectric by the transition layer 237 (e.g., Figure 2 (As shown). In Figure 3A In this process, the transition layer 237 may include at least two sublayers 237A and 237B. The interlayer dielectric transition sublayers 237A and 237B may include both silicon oxide and silicon nitride. However, the interlayer dielectric transition sublayer 237A disposed on the interlayer dielectric silicon oxide layer 236 may have a higher concentration of silicon oxide and a lower concentration of silicon nitride. Similarly, the interlayer dielectric transition sublayer 237B disposed above the interlayer dielectric transition sublayer 237A and below the interlayer dielectric silicon nitride sublayer 238 may have a lower concentration of silicon oxide and a higher concentration of silicon nitride. The concentrations of silicon oxide and silicon nitride in the transition sublayers can be controlled by controlling the flow rates of silicon oxide and silicon nitride entering the processing chamber 100 during deposition. Although Figure 3A The embodiment shown only has two interlayer dielectric transition sublayers, but more interlayer dielectric transition layers are also possible. The levels of silicon oxide and silicon nitride are adjusted such that the silicon oxide concentration in each transition layer gradually decreases, while the silicon nitride concentration in each transition layer gradually increases in successive layers. By gradually changing the concentrations of silicon oxide and silicon nitride, the difference in refractive index is minimized, resulting in improved light transmittance.

[0032] Figure 3B A similar implementation showing details of a thin-film transistor with a gate interface layer. Figure 3B In the process, the silicon oxide sublayer 232 of the gate interface is separated from the silicon nitride sublayer 234 of the gate interface by the transition layer 233 (e.g., Figure 2 (As shown). In Figure 3B In this process, transition layer 233 may include at least two sublayers 233A and 233B. Gate interface transition sublayers 233A and 233B may include both silicon oxide and silicon nitride. However, the gate interface transition sublayer 233A, disposed above the interlayer dielectric silicon oxide layer 232, may have a higher concentration of silicon oxide and a lower concentration of silicon nitride. Similarly, the interlayer dielectric transition sublayer 233B, disposed above the interlayer dielectric transition sublayer 233A and below the interlayer dielectric silicon nitride sublayer 234, may have a lower silicon oxide concentration and a higher silicon nitride concentration. The concentrations of silicon oxide and silicon nitride in the transition sublayers can be controlled by controlling the flow rates of silicon oxide and silicon nitride entering the processing chamber 100 during deposition. Although Figure 3B The implementation shown herein only depicts two gate interface transition layers, but more gate interface transition layers are also possible. The content of silicon oxide and silicon nitride is adjusted such that the silicon oxide concentration in each transition layer gradually decreases, while the silicon nitride concentration in each transition layer gradually increases in successive layers. By gradually changing the concentrations of silicon oxide and silicon nitride, the difference in refractive index is minimized, resulting in improved light transmittance.

[0033] Figure 4 exhibit Figure 2 Another embodiment of the low-temperature polycrystalline silicon thin-film transistor is shown. Figure 4 In this configuration, buffer layer 220 may include two sublayers 222 and 224. Buffer sublayers 222 and 224 may include inorganic layers. For example, buffer sublayer 222 may include silicon nitride, and buffer sublayer 224 may include silicon oxide. The difference in refractive index between silicon oxide and silicon nitride in the gate interface and interlayer dielectric may cause reflection interference. To reduce reflection, one or more transition layers 223 may be disposed between silicon oxide layer 222 and silicon nitride layer 224.

[0034] Figure 5The illustration shows one embodiment in which a buffer transition layer 223 includes at least two transition sublayers. A buffer transition sublayer 223A (including silicon nitride) is disposed above a buffer sublayer 222. Buffer transition sublayer 223A may include both silicon oxide and silicon nitride, but the concentration of silicon nitride is higher than that of silicon oxide. A buffer transition sublayer 223B is disposed above buffer transition sublayer 223A and below buffer sublayer 224. Buffer transition sublayer 223B may include both silicon oxide and silicon nitride, but the concentration of silicon oxide is higher than that of silicon nitride. Furthermore, the concentrations of silicon oxide and silicon nitride in the sublayers are controlled by controlling the flow rates of silicon oxide and silicon nitride entering the processing chamber during deposition. The use of transition sublayers reduces the refractive index difference between the individual sublayers, reduces reflection interference, and improves light transmittance.

[0035] As discussed above, the refractive index difference between silicon nitride and silicon oxide deposited by chemical vapor deposition can limit the interlayer transmittance above the pixel electrode, leading to performance degradation. To mitigate this effect, transition layers are disposed between the silicon oxide and silicon nitride layers. These transition layers reduce the change in interlayer refractive index, thereby resulting in reduced reflection interference and improved transmittance at a limited cost.

[0036] Although the present disclosure has been described above with reference to embodiments, other and further embodiments may be devised without departing from the basic scope of the invention, the scope of which is determined by the following claims.

Claims

1. A transistor for controlling pixel electrodes, comprising: The first interlayer dielectric layer includes silicon oxide; A second interlayer dielectric layer, the second interlayer dielectric layer comprising silicon nitride; and A transition layer is formed on the first interlayer dielectric layer. The transition layer includes a first interlayer dielectric transition sublayer disposed on the first interlayer dielectric layer and a second interlayer dielectric transition sublayer disposed on the first interlayer dielectric transition sublayer and below the second interlayer dielectric layer. The first interlayer dielectric transition sublayer and the second interlayer dielectric transition sublayer include both silicon oxide and silicon nitride. The first interlayer dielectric transition sublayer has a higher silicon oxide concentration and a lower silicon nitride concentration, and the second interlayer dielectric transition sublayer has a lower silicon oxide concentration and a higher silicon nitride concentration. The pixel electrode is formed on the first interlayer dielectric layer, the transition layer, and the second interlayer dielectric layer.

2. The transistor for controlling pixel electrodes as claimed in claim 1, wherein the first interlayer dielectric layer has a first refractive index and the second interlayer dielectric layer has a second refractive index.

3. The transistor for controlling pixel electrodes as claimed in claim 2, wherein the first interlayer dielectric transition sublayer has a third refractive index and the second interlayer dielectric transition sublayer has a fourth refractive index.

4. The transistor for controlling a pixel electrode as claimed in claim 3, wherein the first refractive index is less than the second refractive index.

5. The transistor for controlling a pixel electrode as claimed in claim 4, wherein the third refractive index is greater than the first refractive index and less than the fourth refractive index, and the fourth refractive index is greater than the third refractive index and less than the second refractive index.

6. The transistor for controlling pixel electrodes as claimed in claim 1, further comprising a substrate, wherein the first interlayer dielectric layer and the second interlayer dielectric layer are disposed on the substrate.

7. The transistor for controlling pixel electrodes as claimed in claim 6, further comprising a buffer layer disposed on the substrate and below the first interlayer dielectric layer.

8. The transistor for controlling pixel electrodes as claimed in claim 7, wherein the buffer layer further comprises: The first buffer sublayer comprises silicon nitride; The second buffer sublayer includes silicon oxide and is formed on top of the first buffer sublayer; and A transition stack structure is disposed between the first buffer sublayer and the second buffer sublayer, the transition stack structure including at least a first buffer transition sublayer adjacent to the first buffer sublayer and a second buffer transition sublayer adjacent to the second buffer sublayer.

9. The transistor for controlling pixel electrodes as claimed in claim 1, further comprising an optical acrylic layer disposed on the second interlayer dielectric layer.

10. The transistor for controlling a pixel electrode as claimed in claim 9, further comprising a first indium tin oxide layer disposed on the photoacrylic layer.

11. The transistor for controlling a pixel electrode as claimed in claim 10, further comprising a silicon nitride layer disposed on the first indium tin oxide layer.

12. The transistor for controlling a pixel electrode as claimed in claim 11, further comprising a second indium tin oxide layer, the second indium tin oxide layer being disposed at least partially over the silicon nitride layer.

13. The transistor for controlling a pixel electrode as claimed in claim 12, further comprising a polyimide layer disposed over the silicon nitride layer and the second indium tin oxide layer.

14. The transistor for controlling pixel electrodes as claimed in claim 13, further comprising a liquid crystal layer disposed on the polyimide layer.

15. A thin-film transistor, comprising: substrate; A buffer layer disposed on the substrate, the buffer layer comprising an inorganic material; A first interlayer dielectric layer is disposed on the substrate, and the first interlayer dielectric layer includes silicon oxide. A second interlayer dielectric layer is disposed above the first interlayer dielectric layer, and the second interlayer dielectric layer includes silicon nitride; and A transition layer is formed above the first interlayer dielectric layer and below the second interlayer dielectric layer. The transition layer includes a first interlayer dielectric transition sublayer disposed above the first interlayer dielectric layer and a second interlayer dielectric transition sublayer disposed above the first interlayer dielectric transition sublayer and below the second interlayer dielectric layer. The first interlayer dielectric transition sublayer and the second interlayer dielectric transition sublayer include both silicon oxide and silicon nitride. The first interlayer dielectric transition sublayer has a higher silicon oxide concentration and a lower silicon nitride concentration, and the second interlayer dielectric transition sublayer has a lower silicon oxide concentration and a higher silicon nitride concentration.

16. The thin-film transistor of claim 15, wherein the first interlayer dielectric layer has a first refractive index and the second interlayer dielectric layer has a second refractive index.

17. The thin-film transistor of claim 16, wherein the first interlayer dielectric transition sublayer has a third refractive index and the second interlayer dielectric transition sublayer has a fourth refractive index.

18. The thin-film transistor of claim 17, wherein the first refractive index is less than the second refractive index.

19. The thin-film transistor of claim 18, wherein the third refractive index is greater than the first refractive index and less than the fourth refractive index, and the fourth refractive index is greater than the third refractive index and less than the second refractive index.

20. A thin-film transistor, comprising: substrate; A buffer layer disposed on the substrate, the buffer layer comprising an inorganic material; and Two double layers, said two double layers being disposed on the substrate, each double layer comprising: A first interlayer dielectric layer is disposed on the substrate, and the first interlayer dielectric layer includes silicon oxide. A second interlayer dielectric layer is disposed above the first interlayer dielectric layer, and the second interlayer dielectric layer includes silicon nitride; and A transition layer is formed above the first interlayer dielectric layer and below the second interlayer dielectric layer. The transition layer includes a first interlayer dielectric transition sublayer disposed above the first interlayer dielectric layer and a second interlayer dielectric transition sublayer disposed above the first interlayer dielectric transition sublayer and below the second interlayer dielectric layer. The first interlayer dielectric transition sublayer and the second interlayer dielectric transition sublayer include both silicon oxide and silicon nitride. The first interlayer dielectric transition sublayer has a higher silicon oxide concentration and a lower silicon nitride concentration, and the second interlayer dielectric transition sublayer has a lower silicon oxide concentration and a higher silicon nitride concentration.

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