Micro light emitting diode chip and preparation method thereof

Abstract

This disclosure provides a miniature light-emitting diode (LED) chip and its fabrication method, belonging to the field of optoelectronic manufacturing technology. The miniature LED chip includes: a substrate, a light-emitting structure, a first solder block, a second solder block, and a scattering layer; the light-emitting structure is located on the surface of the substrate, the scattering layer is located on the surface of the light-emitting structure away from the substrate, and both the first and second solder blocks are located on the surface of the scattering layer away from the substrate, respectively connected to two electrodes of the light-emitting structure; the scattering layer includes an insulating layer and multiple reflective protrusions, the insulating layer is located on the surface of the light-emitting structure away from the substrate, and the multiple reflective protrusions are spaced apart on the surface of the insulating layer away from the substrate. Embodiments of this disclosure can increase the proportion of lateral light from the chip and reduce the proportion of vertical light, thereby improving the lateral light emission intensity of the chip.

Description

Technical Field

[0001] The present disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a micro light emitting diode chip and a preparation method thereof. Background Art

[0002] Micro Light Emitting Diode (Micro LED) refers to an ultra-small light-emitting diode with a side length of 10μm to 100μm. Micro LEDs are small in size and can be arranged more densely to greatly improve resolution. They also have self-luminous properties and have the characteristics of high brightness, high contrast, high responsiveness and power saving.

[0003] In the related art, a micro light emitting diode chip generally includes a substrate, an epitaxial structure, a first electrode, a second electrode, a distributed Bragg reflector (DBR) layer, a first solder block and a second solder block, the epitaxial structure is stacked on one surface of the substrate, the first electrode and the second electrode are located on the other surface of the epitaxial structure, and the first electrode and the second electrode are respectively connected to the n-type layer and the p-type layer in the epitaxial structure, the DBR layer is located on the first electrode and the second electrode, the first solder block and the second solder block are located on the BDR layer, and the first solder block and the second solder block are respectively connected to the two electrodes.

[0004] Since the DBR layer has good reflective effect, the chip has strong luminous intensity in the direction perpendicular to the substrate, while the light from the side of the chip is weak, resulting in high light intensity in the center area of ​​the chip, but weak light intensity in the surrounding area of ​​the chip, which affects the luminous effect. Summary of the invention

[0005] The embodiment of the present disclosure provides a micro light emitting diode chip and a method for manufacturing the same, which can increase the proportion of lateral light of the chip and reduce the proportion of light in the vertical direction, so as to increase the lateral light intensity of the chip. The technical solution is as follows:

[0006] On the one hand, an embodiment of the present disclosure provides a micro-light-emitting diode chip, which includes: a substrate, a light-emitting structure, a first solder point block, a second solder point block and a scattering layer; the light-emitting structure is located on the surface of the substrate, the scattering layer is located on the surface of the light-emitting structure away from the substrate, the first solder point block and the second solder point block are both located on the surface of the scattering layer away from the substrate, and the first solder point block and the second solder point block are respectively connected to two electrodes of the light-emitting structure; the scattering layer includes an insulating layer and a plurality of reflective protrusions, the insulating layer is located on the surface of the light-emitting structure away from the substrate, and the plurality of reflective protrusions are arranged at intervals on the surface of the insulating layer away from the substrate.

[0007] Optionally, the reflective protrusion includes a first bump and a second bump sequentially stacked on the insulating layer, and an orthographic projection of the second bump on the substrate is located within an orthographic projection of the first bump on the substrate.

[0008] Optionally, the first bump and the second bump each include a plurality of silicon oxide layers and a plurality of titanium oxide layers that are alternately stacked.

[0009] Optionally, a thickness of the second bump is greater than a thickness of the first bump.

[0010] Optionally, the thickness of the first bump is 2.8 μm to 3.2 μm, and the thickness of the second bump is 4.8 μm to 5.2 μm.

[0011] Optionally, the first bump and the second bump are both cylinders, and the first bump and the second bump are coaxial.

[0012] Optionally, a scattering film is provided on the surface of the reflective protrusion, the scattering film covers the surface of the first protrusion and the surface of the second protrusion, the scattering film is filled with titanium oxide particles, and the distribution density of the titanium oxide particles located on the surface of the first protrusion is less than the distribution density of the titanium oxide particles located on the surface of the second protrusion.

[0013] Optionally, the scattering film is a silicon oxide film.

[0014] On the other hand, an embodiment of the present disclosure also provides a method for preparing a micro light-emitting diode chip, the method comprising: providing a substrate; forming a light-emitting structure on the substrate; forming a scattering layer on a surface of the light-emitting structure away from the substrate, the scattering layer comprising an insulating layer and a plurality of reflective protrusions, the insulating layer being located on a surface of the light-emitting structure away from the substrate, and a plurality of the reflective protrusions being arranged at intervals on the surface of the insulating layer away from the substrate; making a first soldering point block and a second soldering point block on a surface of the scattering layer away from the substrate, the first soldering point block and the second soldering point block being respectively connected to two electrodes of the light-emitting structure.

[0015] Optionally, forming a scattering layer on the surface of the light-emitting structure away from the substrate includes: depositing the insulating layer on the surface of the light-emitting structure; making a plurality of the reflective protrusions on the surface of the insulating layer, the reflective protrusions including a first protrusion and a second protrusion stacked in sequence on the insulating layer, the orthographic projection of the second protrusion on the substrate being located within the orthographic projection of the first protrusion on the substrate; making a scattering film on the surface of the reflective protrusion, the scattering film covering the surface of the first protrusion and the surface of the second protrusion, the scattering film being filled with titanium oxide particles, the distribution density of the titanium oxide particles located on the surface of the first protrusion being less than the distribution density of the titanium oxide particles located on the surface of the second protrusion.

[0016] The beneficial effects brought by the technical solution provided by the embodiments of the present disclosure include at least:

[0017] In the micro light emitting diode provided by the embodiment of the present disclosure, a light emitting structure is provided on a substrate, a scattering layer is provided on the surface of the light emitting structure away from the substrate, a first solder point block and a second solder point block are arranged at intervals on the scattering layer, and are respectively connected to two electrodes in the light emitting structure, so that by energizing the two solder point blocks, the light emitting structure can be controlled to emit light. The scattering layer includes an insulating layer and a plurality of reflective protrusions, the insulating layer is on the surface of the light emitting structure, and the plurality of reflective protrusions are arranged on the surface of the insulating layer and arranged at intervals, that is, gaps are reserved between the reflective protrusions. Compared with the related art, designing the DBR layer as a discontinuous thin film with gaps can reduce the area of ​​light reflection by the DBR layer, thereby reducing the light output in the direction perpendicular to the substrate; and the light incident on the gap between the reflective protrusions will also be reflected at the side wall of the reflective protrusion, thereby guiding the light to be emitted to the side of the chip, thereby enhancing the lateral light output of the chip. In this way, by setting the DBR layer to multiple non-continuous reflective protrusions and utilizing the gaps between the reflective protrusions to perform non-uniform processing on the light, the side light output of the chip is increased, the light intensity in the central area of ​​the chip is reduced, the light intensity problem in the surrounding area of ​​the chip is improved, and the luminous effect is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 is a schematic structural diagram of a micro light emitting diode chip provided by an embodiment of the present disclosure;

[0020] Figure 2 is a schematic structural diagram of a scattering layer provided by an embodiment of the present disclosure;

[0021] Figure 3 is a top view of a micro light emitting diode chip provided by an embodiment of the present disclosure;

[0022] Figure 4 is a schematic structural diagram of a reflective protrusion provided by an embodiment of the present disclosure;

[0023] Figure 5 is a top view of a reflective protrusion provided by an embodiment of the present disclosure;

[0024] Figure 6 is a schematic structural diagram of a reflective protrusion provided by an embodiment of the present disclosure;

[0025] Figure 7 is a schematic diagram of a first welding point block provided by an embodiment of the present disclosure;

[0026] Figure 8 is a flow chart of a method for preparing a micro light emitting diode chip provided by an embodiment of the present disclosure;

[0027] Fig. 9 is a diagram of a preparation state of a micro light emitting diode chip provided by an embodiment of the present disclosure;

[0028] Fig.10 This is a diagram of the preparation state of a micro light emitting diode chip provided in an embodiment of the present disclosure.

[0029] The descriptions of the marks in the figure are as follows:

[0030] 10. Substrate;

[0031] 20. Light emitting structure; 21. First semiconductor layer; 22. Multi-quantum well layer; 23. Second semiconductor layer; 24. First electrode; 25. Second electrode;

[0032] 31, first solder joint block; 32, second solder joint block; 301, first Ti layer; 302, first Al layer; 303, second Ti layer; 304, second Al layer; 305, Au layer;

[0033] 40, scattering layer; 41, insulating layer; 42, reflective protrusion; 421, first protrusion; 422, second protrusion; 43, scattering film; 431, first part; 432, second part;

[0034] 50. groove; 51. first via hole; 52. second via hole; 53. protective layer. DETAILED DESCRIPTION

[0035] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0036] Figure 1 Schematic diagram of the structure of a micro light emitting diode chip provided by the embodiment of the present disclosure. Figure 1 As shown, the micro light emitting diode chip includes: a substrate 10 , a light emitting structure 20 , a first soldering point block 31 , a second soldering point block 32 and a scattering layer 40 .

[0037] like Figure 1 As shown, the light emitting structure 20 is located on the surface of the substrate 10, the scattering layer 40 is located on the surface of the light emitting structure 20 away from the substrate 10, the first soldering point block 31 and the second soldering point block 32 are both located on the surface of the scattering layer 40 away from the substrate 10, and the first soldering point block 31 and the second soldering point block 32 are respectively connected to the two electrodes of the light emitting structure 20.

[0038] Figure 2 FIG. 4 is a schematic diagram of the structure of a scattering layer 40 provided in an embodiment of the present disclosure. Figure 2 As shown, the scattering layer 40 includes an insulating layer 41 and a plurality of reflective protrusions 42 . The insulating layer 41 is located on the surface of the light emitting structure 20 away from the substrate 10 , and the plurality of reflective protrusions 42 are arranged at intervals on the surface of the insulating layer 41 away from the substrate 10 .

[0039] In the micro light emitting diode provided by the embodiment of the present disclosure, a light emitting structure 20 is provided on a substrate 10, a scattering layer 40 is provided on the surface of the light emitting structure 20 away from the substrate 10, a first solder point block 31 and a second solder point block 32 are arranged on the scattering layer 40 at intervals, and are respectively connected to two electrodes in the light emitting structure 20, so that the light emitting structure 20 can be controlled to emit light by energizing the two solder point blocks. The scattering layer 40 includes an insulating layer 41 and a plurality of reflective protrusions 42, the insulating layer 41 is on the surface of the light emitting structure 20, and the plurality of reflective protrusions 42 are arranged on the surface of the insulating layer 41 and arranged at intervals, that is, gaps are reserved between the reflective protrusions 42. Compared with the related art, the DBR layer is designed as a discontinuous film with gaps, which can reduce the area of ​​light reflection by the DBR layer, thereby reducing the light output in the direction perpendicular to the substrate 10; and the light incident on the gaps between the reflective protrusions 42 will also be reflected at the side walls of the reflective protrusions 42, thereby guiding the light to be emitted to the side of the chip, thereby enhancing the lateral light output of the chip. In this way, by setting the DBR layer to multiple non-continuous reflective protrusions 42, the gaps between the reflective protrusions 42 are used to perform non-uniform processing on the light, thereby improving the side light output of the chip, reducing the light intensity in the central area of ​​the chip, improving the light intensity problem in the surrounding area of ​​the chip, and improving the luminous effect.

[0040] Alternatively, if Figure 1 As shown, the light emitting structure 20 includes: a first semiconductor layer 21 , a multi-quantum well layer 22 , a second semiconductor layer 23 , a scattering layer 40 , a first electrode 24 and a second electrode 25 .

[0041] like Figure 1As shown, the first semiconductor layer 21, the multi-quantum well layer 22 and the second semiconductor layer 23 are stacked in sequence on the substrate 10, the second electrode 25 is located on the surface of the second semiconductor layer 23, the surface of the second semiconductor layer 23 has a groove 50 exposing the first semiconductor layer 21, the first electrode 24 is located on the surface of the first semiconductor layer 21, and the first electrode 24 is located on the bottom of the groove 50.

[0042] The scattering layer 40 at least covers the surfaces of the first semiconductor layer 21 , the first electrode 24 , the groove 50 , the second semiconductor layer 23 , and the second electrode 25 .

[0043] A first semiconductor layer 21, a multi-quantum well layer 22, and a second semiconductor layer 23 are sequentially stacked on a substrate 10, wherein a second electrode 25 is arranged on the surface of the second semiconductor layer 23, and the surface of the second semiconductor layer 23 has a groove 50 exposing the first semiconductor layer 21, that is, part of the second semiconductor layer 23 and the multi-quantum well layer 22 are removed through the groove 50, so that the first electrode 24 is directly arranged on the surface of the first semiconductor layer 21 through the groove 50, so that the overall thickness of the epitaxial structure is thinned.

[0044] like Figure 1 As shown, the surface of the scattering layer 40 has a first via hole 51 exposing the first electrode 24, the first solder block 31 extends to the first via hole 51 and is connected to the first electrode 24, the surface of the scattering layer 40 has a second via hole 52 exposing the second electrode 25, the second solder block 32 extends to the second via hole 52 and is connected to the second electrode 25.

[0045] The first solder point block 31 is covered on the first via hole 51 so that the first solder point block 31 can be connected to the first electrode 24 through the first via hole 51, thereby facilitating the electrical connection of the first electrode 24; the second solder point block 32 is covered on the second via hole 52 so that the second solder point block 32 can be connected to the second electrode 25 through the second via hole 52, thereby facilitating the electrical connection of the second electrode 25.

[0046] For example, Figure 3 FIG. 1 is a top view of a micro light emitting diode chip provided by an embodiment of the present disclosure. Figure 3 As shown, the first soldering point block 31 and the second soldering point block 32 are both rectangular blocks, which increase the area and facilitate conduction. In addition, on the surface of the scattering layer, the first soldering point block 31 and the second soldering point block 32 are distributed at intervals.

[0047] In the embodiment of the present disclosure, one of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is an n-type layer.

[0048] As an example, the first semiconductor layer 21 is an n-type layer, and the first electrode 24 is an n-type electrode. The second semiconductor layer 23 is a p-type layer, and the second electrode 25 is a p-type electrode.

[0049] Optionally, the substrate 10 is a sapphire substrate. The sapphire substrate has a relatively high light transmittance, that is, the substrate is a transparent substrate. In addition, the sapphire material is relatively hard and has relatively stable chemical properties, so that the red light emitting diode has good light emitting effect and stability.

[0050] Optionally, the first semiconductor layer 21 is an n-type GaN layer, and the thickness of the n-type GaN layer may be 0.5 μm to 3 μm.

[0051] Optionally, the multi-quantum well layer 22 includes alternately grown InGaN quantum well layers and GaN quantum barrier layers, wherein the multi-quantum well layer 22 may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0052] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 22 includes five periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0053] Optionally, the thickness of the multi-quantum well layer 22 may be 150 nm to 200 nm.

[0054] Optionally, the second semiconductor layer 23 is an indium-doped p-type GaN layer. The thickness of the p-type GaN layer may be 0.5 μm to 3 μm.

[0055] Alternatively, if Figure 1 As shown, after the first soldering point block 31 and the second soldering point block 32 are formed, a protective layer 53 may be formed on the surface of the scattering layer 40 , and the protective layer 53 extends from the surface of the scattering layer 40 to the substrate 10 .

[0056] For example, in the embodiment of the present disclosure, the protective layer 53 may be a silicon oxide film, and the thickness of the silicon oxide film is 2000 angstroms.

[0057] It should be noted that after the protective layer 53 is grown on the surface of the scattering layer 40 , a through hole exposing the solder joint block can be etched on the surface of the protective layer 53 using a photolithography technique to facilitate electrical connection.

[0058] Figure 4 4 is a schematic diagram of the structure of a reflective protrusion 42 provided in an embodiment of the present disclosure. Figure 1 , 4 As shown, the reflective protrusion 42 includes a first protrusion 421 and a second protrusion 422 sequentially stacked on the insulating layer 41 , and the orthographic projection of the second protrusion 422 on the substrate 10 is located within the orthographic projection of the first protrusion 421 on the substrate 10 .

[0059] By setting the reflective protrusion 42 as two stacked protrusions to form a stepped protrusion structure, when the light is incident on the first protrusion 421 and emitted from the first protrusion 421 to the second protrusion 422, since the size of the second protrusion 422 is smaller, the reflection of the light by the reflective protrusion 42 in the direction perpendicular to the substrate 10 can be further reduced, thereby enhancing the side light output ratio of the chip.

[0060] Optionally, the first bump 421 and the second bump 422 both include a plurality of silicon oxide layers and a plurality of titanium oxide layers that are alternately stacked, and the thickness of the second bump 422 is greater than the thickness of the first bump 421 .

[0061] Since the cross-sectional area of ​​the second bump 422 is smaller than the cross-sectional area of ​​the first bump 421, the side area of ​​the second bump 422 is also relatively small. By setting a second bump 422 with a larger thickness to increase the side area of ​​the second bump 422, it is ensured that the second bump 422 also has a large enough side for reflecting light, thereby further improving the problem of excessive light intensity in the middle area of ​​the chip and poor light intensity in the edge area.

[0062] Exemplarily, the thickness of the first bump 421 is 2.8 μm to 3.2 μm, and the thickness of the second bump 422 is 4.8 μm to 5.2 μm. As an example, the thickness of the first bump 421 is 3 μm, and the thickness of the second bump 422 is 5 μm.

[0063] Figure 5 FIG. 4 is a top view of a reflective protrusion 42 provided in an embodiment of the present disclosure. Figure 4 , 5 As shown, the first bump 421 and the second bump 422 are both cylindrical, and the first bump 421 and the second bump 422 are coaxial.

[0064] In this way, the first bump 421 and the second bump 422 can form a stepped columnar structure. When light is incident on the first bump 421 and emitted from the first bump 421 to the second bump 422, since the second bump 422 is smaller in size, the reflection of light by the reflective protrusion 42 in the direction perpendicular to the substrate 10 can be further reduced, thereby enhancing the side light output ratio of the chip.

[0065] Exemplarily, the diameter of the first bump 421 is 10 μm to 15 μm, and the diameter of the second bump 422 is 5 μm to 8 μm. As an example, the diameter of the first bump 421 is 10 μm, and the diameter of the second bump 422 is 5 μm.

[0066] Figure 6 4 is a schematic diagram of the structure of a reflective protrusion 42 provided in an embodiment of the present disclosure. Figure 6As shown, a scattering film 43 is provided on the surface of the reflective protrusion 42, and the scattering film 43 covers the surface of the first protrusion 421 and the surface of the second protrusion 422. The scattering film 43 is filled with titanium oxide particles, and the distribution density of the titanium oxide particles located on the surface of the first protrusion 421 is less than the distribution density of the titanium oxide particles located on the surface of the second protrusion 422.

[0067] In the embodiment of the present disclosure, the distribution density of titanium oxide particles may refer to the number of titanium oxide particles in a unit volume. A higher distribution density indicates that the number of titanium oxide particles in a unit volume is greater in the region.

[0068] For example, Figure 6 As shown, the scattering film 43 also includes a first part 431 and a second part 432, the first part 431 is located on the surface of the first bump 421, and the second part 432 is located on the surface of the second bump 422, and the distribution density of the titanium oxide particles filled in the first part 431 is less than the distribution density of the titanium oxide particles filled in the second part 432.

[0069] In this way, more scattering particles are arranged in the middle area of ​​the reflective protrusion 42 in the scattering film 43, while fewer scattering particles are arranged in the edge area of ​​the reflective protrusion 42. This can fully scatter the light in the direction perpendicular to the substrate 10, allowing more light to be emitted from the side of the chip, and can also avoid excessive brightness drop in the direction perpendicular to the substrate 10, thereby ensuring the luminous effect.

[0070] As an example, in the embodiment of the present disclosure, the scattering film 43 is a silicon oxide film, that is, the scattering film 43 is a film layer structure made of silicon oxide.

[0071] Figure 7 FIG. 3 is a schematic diagram of a first solder joint block 31 provided in an embodiment of the present disclosure. Figure 7 As shown, the first soldering point block 31 and the second soldering point block 32 each include a first Ti layer 301 , a first Al layer 302 , a second Ti layer 303 , a second Al layer 304 and an Au layer 305 sequentially stacked on the surface of the light emitting structure 20 .

[0072] Exemplarily, in the first solder joint block 31 and the second solder joint block 32, the thickness of the first Ti layer 301 is 100 angstroms to 300 angstroms, the thickness of the first Al layer 302 is 8000 angstroms to 12000 angstroms, the thickness of the second Ti layer 303 is 100 angstroms to 300 angstroms, the thickness of the second Al layer 304 is 8000 angstroms to 12000 angstroms, and the thickness of the Au layer 305 is 2000 angstroms to 4000 angstroms.

[0073] As an example, in the first solder joint block 31 and the second solder joint block 32, the thickness of the first Ti layer 301 is 200 angstroms, the thickness of the first Al layer 302 is 10,000 angstroms, the thickness of the second Ti layer 303 is 200 angstroms, the thickness of the second Al layer 304 is 10,000 angstroms, and the thickness of the Au layer 305 is 3,000 angstroms.

[0074] Figure 8 is a flow chart of a method for preparing a micro light emitting diode chip provided by an embodiment of the present disclosure. Figure 1 The micro light emitting diode chip shown. Figure 8 As shown, the preparation method comprises:

[0075] S11: providing a substrate 10.

[0076] S12 : forming a light emitting structure 20 on the substrate 10 .

[0077] S13 : forming a scattering layer 40 on a surface of the light emitting structure 20 away from the substrate 10 .

[0078] The scattering layer 40 includes an insulating layer 41 and a plurality of reflective protrusions 42 . The insulating layer 41 is located on a surface of the light emitting structure 20 away from the substrate 10 . The plurality of reflective protrusions 42 are arranged at intervals on the surface of the insulating layer 41 away from the substrate 10 .

[0079] S14 : manufacturing a first soldering point block 31 and a second soldering point block 32 on the surface of the scattering layer 40 away from the substrate 10 .

[0080] The first soldering point block 31 and the second soldering point block 32 are respectively connected to two electrodes of the light emitting structure 20 .

[0081] In the micro light-emitting diode prepared by the preparation method, a light-emitting structure 20 is provided on the substrate 10, and a scattering layer 40 is provided on the surface of the light-emitting structure 20 away from the substrate 10, and a first solder point block 31 and a second solder point block 32 are arranged on the scattering layer 40 at intervals, and are respectively connected to two electrodes in the light-emitting structure 20, so that the light-emitting structure 20 can be controlled to emit light by energizing the two solder point blocks. The scattering layer 40 includes an insulating layer 41 and a plurality of reflective protrusions 42, the insulating layer 41 is on the surface of the light-emitting structure 20, and the plurality of reflective protrusions 42 are arranged on the surface of the insulating layer 41 and arranged at intervals, that is, gaps are reserved between the reflective protrusions 42. Compared with the related art, the DBR layer is designed as a discontinuous film with gaps, which can reduce the area of ​​light reflection by the DBR layer, thereby reducing the light output in the direction perpendicular to the substrate 10; and the light incident on the gap between the reflective protrusions 42 will also be reflected at the side wall of the reflective protrusion 42, thereby guiding the light to be emitted to the side of the chip, thereby enhancing the lateral light output of the chip. In this way, by setting the DBR layer to multiple non-continuous reflective protrusions 42, the gaps between the reflective protrusions 42 are used to perform non-uniform processing on the light, thereby improving the side light output of the chip, reducing the light intensity in the central area of ​​the chip, improving the light intensity problem in the surrounding area of ​​the chip, and improving the luminous effect.

[0082] Optionally, the substrate 10 is a sapphire substrate 10. The sapphire substrate 10 has a relatively high light transmittance, that is, the substrate 10 is a transparent substrate 10. In addition, the sapphire material is relatively hard and has relatively stable chemical properties, so that the red light emitting diode has good light emitting effect and stability.

[0083] In step S11, the sapphire substrate 10 may be pre-treated by placing the sapphire substrate 10 in a MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber and baking the sapphire substrate 10 for 12 to 18 minutes. As an example, in the embodiment of the present disclosure, the sapphire substrate 10 is baked for 15 minutes.

[0084] Specifically, the baking temperature may be 1000° C. to 1200° C., and the pressure in the MOCVD reaction chamber during baking may be 100 mbar to 200 mbar.

[0085] Step S11 may also include growing a dry etching mask on the sapphire substrate 10 and etching a pattern on the mask using a photolithography process.

[0086] The light emitting structure 20 grown in step S12 includes a first semiconductor layer 21 , a multi-quantum well layer 22 , a second semiconductor layer 23 , a first electrode 24 and a second electrode 25 .

[0087] like Fig. 9As shown, the process of growing the light emitting structure 20 may include: first, growing a first semiconductor layer 21 , a multi-quantum well layer 22 , and a second semiconductor layer 23 in sequence on the substrate 10 .

[0088] For example, the first semiconductor layer 21 is an n-type GaN layer, and the thickness of the n-type GaN layer may be 0.5 μm to 3 μm.

[0089] The multi-quantum well layer 22 includes alternately grown InGaN quantum well layers and GaN quantum barrier layers. The multi-quantum well layer 22 may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0090] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 22 includes five periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0091] Optionally, the thickness of the multi-quantum well layer 22 may be 150 nm to 200 nm.

[0092] The second semiconductor layer 23 is an indium-doped p-type GaN layer, and the thickness of the p-type GaN layer may be 0.5 μm to 3 μm.

[0093] In step S12 , after the second semiconductor layer 23 is grown, a groove 50 is etched on the surface of the second semiconductor layer 23 to expose the first semiconductor layer 21 .

[0094] Specifically, it may include: removing a part of the second semiconductor layer by dry etching, and etching until the first semiconductor layer 21 is exposed. The etching depth is 1 μm to 2 μm, for example, etching 1.5 μm.

[0095] After etching to form the groove 50, an indium tin oxide (ITO) layer can be formed on the surface of the second semiconductor layer 23 and the bottom of the groove 50. This is achieved by using photoresist protection, and wet etching is performed after the photolithography pattern is completed. The solution can be a hydrochloric acid solution.

[0096] After the ITO layer is manufactured, a first electrode 24 may be formed on the ITO layer on the first semiconductor layer 21 , and a second electrode 25 may be formed on the second semiconductor layer 23 .

[0097] In step S12 , forming the first electrode 24 and the second electrode 25 may include: processing the first electrode 24 and the second electrode 25 respectively by negative resist stripping.

[0098] like Fig. 9 As shown, the second electrode 25 is located on the surface of the second semiconductor layer 23 , and the first electrode 24 is located on the bottom surface of the groove 50 .

[0099] The first electrode 24 and the second electrode 25 are both evaporated with chromium as the base material.

[0100] Exemplarily, the thickness of chromium is controlled within 100 angstroms to prevent affecting the brightness.

[0101] In step S13, the manufacturing of the scattering layer 40 includes the following steps:

[0102] In the first step, an insulating layer 41 is deposited on the surface of the light emitting structure 20 .

[0103] Specifically, the method may include depositing a silicon oxide film with a thickness of 3000 angstroms to 7000 angstroms to form an insulating layer 41 covering the second semiconductor layer 23 , the second electrode 25 , the first semiconductor layer 21 and the first electrode 24 .

[0104] As an example, the thickness of the insulating layer 41 may be 5000 angstroms.

[0105] In the second step, a plurality of reflective protrusions 42 are formed on the surface of the insulating layer 41 .

[0106] The reflective protrusion 42 includes a first protrusion 421 and a second protrusion 422 sequentially stacked on the insulating layer 41 , and the orthographic projection of the second protrusion 422 on the substrate 10 is located within the orthographic projection of the first protrusion 421 on the substrate 10 .

[0107] When manufacturing the first bump 421 , 12 pairs of alternately stacked silicon oxide films and titanium oxide films may be formed on the insulating layer 41 , the reflection wavelength is set to 465 nm, and the film layer is patterned to form a plurality of first bumps 421 distributed at intervals.

[0108] When manufacturing the second bumps 422 , 24 pairs of film layers of alternately stacked silicon oxide films and titanium oxide films are formed on the first bumps 421 , and the film layers are patterned to form a plurality of second bumps 422 corresponding to the first bumps 421 .

[0109] The third step is to make a scattering film 43 on the surface of the reflective protrusion 42 .

[0110] The scattering film 43 covers the surface of the first bump 421 and the surface of the second bump 422 . The scattering film 43 is filled with titanium oxide particles. The distribution density of the titanium oxide particles on the surface of the first bump 421 is less than the distribution density of the titanium oxide particles on the surface of the second bump 422 .

[0111] Specifically, the method may include: first, making a SiO2 film layer mixed with TiO2 particles on the surface of the first bump 421 , and then performing image processing on the SiO2 film layer to retain the film layer on the surface of the first bump 421 to form the first part 431 of the scattering layer 40 .

[0112] Next, a SiO2 film layer mixed with TiO2 particles is formed on the surface of the second bump 422 , and then the SiO2 film layer is patterned to retain the film layer on the surface of the second bump 422 to form the second portion 432 of the scattering layer 40 .

[0113] The distribution density of the TiO 2 particles in the first portion 431 is less than the distribution density of the TiO 2 particles in the second portion 432 .

[0114] After forming the scattering layer 40, as Fig.10 As shown, the preparation method may further include: forming a first via hole 51 and a second via hole 52 on the surface of the scattering layer 40 away from the substrate 10. Forming a first soldering point block 31 on the surface of the scattering layer 40 by photolithography, so that the first soldering point block 31 is connected to the first electrode 24 through the first via hole 51; then, forming a second soldering point block 32 on the surface of the scattering layer 40 by photolithography, so that the second soldering point block 32 is connected to the second electrode 25 through the second via hole 52.

[0115] The first soldering point block 31 and the second soldering point block 32 each include a first Ti layer 301 , a first Al layer 302 , a second Ti layer 303 , a second Al layer 304 and an Au layer 305 sequentially stacked on the surface of the scattering layer 40 .

[0116] Exemplarily, in the first solder joint block 31 and the second solder joint block 32, the thickness of the first Ti layer 301 is 100 angstroms to 300 angstroms, the thickness of the first Al layer 302 is 8000 angstroms to 12000 angstroms, the thickness of the second Ti layer 303 is 100 angstroms to 300 angstroms, the thickness of the second Al layer 304 is 8000 angstroms to 12000 angstroms, and the thickness of the Au layer 305 is 2000 angstroms to 4000 angstroms.

[0117] As an example, in the first solder joint block 31 and the second solder joint block 32, the thickness of the first Ti layer 301 is 200 angstroms, the thickness of the first Al layer 302 is 10,000 angstroms, the thickness of the second Ti layer 303 is 200 angstroms, the thickness of the second Al layer 304 is 10,000 angstroms, and the thickness of the Au layer 305 is 3,000 angstroms.

[0118] In step S14, Figure 1 As shown, after the first soldering point block 31 and the second soldering point block 32 are formed, a protective layer 53 may be formed on the surface of the scattering layer 40 , and the protective layer 53 extends from the surface of the scattering layer 40 to the substrate 10 .

[0119] For example, in the embodiment of the present disclosure, the protective layer 53 may be a silicon oxide layer, and the thickness of the silicon oxide layer is 2000 angstroms.

[0120] It should be noted that after the protective layer 53 is grown on the surface of the scattering layer 40 , a through hole exposing the solder joint block can be etched on the surface of the protective layer 53 using a photolithography technique to facilitate electrical connection.

[0121] In step S14 , after forming the protection layer 53 , the following step may be further performed: thinning the sapphire substrate 10 , wherein the final thickness after thinning is 80 μm.

[0122] Finally, the sapphire can be cut and scratched invisible, which can effectively reduce the loss of brightness. Then, the micro light-emitting diode chip is obtained by testing.

[0123] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A micro light emitting diode chip, characterized in that: The micro light emitting diode chip comprises: a substrate (10), a light emitting structure (20), a first soldering point block (31), a second soldering point block (32) and a scattering layer (40); The light emitting structure (20) is located on a surface of the substrate (10), the scattering layer (40) is located on a surface of the light emitting structure (20) away from the substrate (10), the first soldering point block (31) and the second soldering point block (32) are both located on a surface of the scattering layer (40) away from the substrate (10), and the first soldering point block (31) and the second soldering point block (32) are respectively connected to two electrodes of the light emitting structure (20); The scattering layer (40) comprises an insulating layer (41) and a plurality of reflective protrusions (42); the insulating layer (41) is located on a surface of the light-emitting structure (20) away from the substrate (10); the plurality of reflective protrusions (42) are arranged at intervals on a surface of the insulating layer (41) away from the substrate (10); the reflective protrusions (42) comprise a first protrusion (421) and a second protrusion (422) sequentially stacked on the insulating layer (41); an orthographic projection of the second protrusion (422) on the substrate (10) is located within an orthographic projection of the first protrusion (421) on the substrate (10); The diameter of the first convex block (421) is greater than the diameter of the second convex block (422), and the reflective protrusion (42) formed by stacking the second convex block (422) and the first convex block (421) is in a stepped shape.

2. The micro light emitting diode chip according to claim 1, characterized in that: The first bump (421) and the second bump (422) both include a plurality of silicon oxide layers and a plurality of titanium oxide layers that are alternately stacked.

3. The micro light emitting diode chip according to claim 1, characterized in that: The thickness of the second bump (422) is greater than the thickness of the first bump (421).

4. The micro light emitting diode chip according to claim 3, characterized in that: The thickness of the first bump (421) is 2.8 μm to 3.2 μm, and the thickness of the second bump (422) is 4.8 μm to 5.2 μm.

5. The micro light emitting diode chip according to claim 1, characterized in that: The first convex block (421) and the second convex block (422) are both cylindrical, and the first convex block (421) and the second convex block (422) are coaxial.

6. The micro light emitting diode chip according to claim 1, characterized in that: A scattering film (43) is provided on the surface of the reflective protrusion (42), the scattering film (43) covers the surface of the first convex block (421) and the surface of the second convex block (422), the scattering film (43) is filled with titanium oxide particles, and the distribution density of the titanium oxide particles located on the surface of the first convex block (421) is less than the distribution density of the titanium oxide particles located on the surface of the second convex block (422).

7. The micro light emitting diode chip according to claim 6, characterized in that: The scattering film (43) is a silicon oxide film.

8. A method for preparing a micro light emitting diode chip, characterized in that: The preparation method comprises: providing a substrate; forming a light emitting structure on the substrate; A scattering layer is formed on the surface of the light emitting structure away from the substrate, the scattering layer includes an insulating layer and a plurality of reflective protrusions, the insulating layer is located on the surface of the light emitting structure away from the substrate, the plurality of reflective protrusions are arranged at intervals on the surface of the insulating layer away from the substrate, the reflective protrusions include a first protrusion and a second protrusion sequentially stacked on the insulating layer, the orthographic projection of the second protrusion on the substrate is located within the orthographic projection of the first protrusion on the substrate, the diameter of the first protrusion is greater than the diameter of the second protrusion, and the reflective protrusion formed by stacking the second protrusion and the first protrusion is stepped; A first soldering point block and a second soldering point block are made on a surface of the scattering layer away from the substrate, and the first soldering point block and the second soldering point block are respectively connected to two electrodes of the light emitting structure.

9. The preparation method according to claim 8, characterized in that: The forming of a scattering layer on a surface of the light emitting structure away from the substrate comprises: Depositing the insulating layer on the surface of the light emitting structure; Making a plurality of the reflective protrusions on the surface of the insulating layer; A scattering film is made on the surface of the reflective protrusion, the scattering film covers the surface of the first protrusion and the surface of the second protrusion, the scattering film is filled with titanium oxide particles, and the distribution density of the titanium oxide particles located on the surface of the first protrusion is less than the distribution density of the titanium oxide particles located on the surface of the second protrusion.

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