Low voltage protection programming circuit for fuse trimming

Abstract

The application provides a low-voltage protection programming circuit for fuse trimming, which has low probability of false programming, high reliability, easy trimming, low power consumption and simple operation. The circuit comprises a bias circuit and a main circuit. The bias circuit is used for providing a bias voltage for the main circuit. The bias circuit comprises a triode Q1, eight MOS tubes M1-M8, a first resistor R1, a second resistor R2 and a third resistor R3. The main circuit comprises a MOS tube one M1', a MOS tube two M2', a MOS tube three M3', a MOS tube four M4', a pressure-sensitive resistor fuse and a level shifter. The MOS tube two M2', the MOS tube three M3', the pressure-sensitive resistor fuse in the main circuit and the fourth MOS tube M4, the seventh MOS tube M7 and the third resistor R3 in the bias circuit constitute a comparator. The comparator is used for judging the output level of an output point by comparing the resistance values of the pressure-sensitive resistor fuse and the third resistor R3.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit chip tuning technology, specifically a low-voltage protection programming circuit for fuse tuning. Background Technology

[0002] With the rapid development of electronic technology, high-precision analog integrated circuits have been widely used. A fuse is a single-time programmable (OTP) non-volatile memory cell, often used for tuning integrated circuits. High-precision amplifiers and other modules typically use fuse tuning programming units to calibrate parameters such as offset voltage and capacitance mismatch, making it widely used.

[0003] Fuse adjustment places high demands on the voltage (or current) source, thus posing certain risks and yield issues. Inappropriate solutions or methods, or problems with the adjustment technique, can result in incomplete fuse burning, leading to unsatisfactory results. Current technologies typically use high-voltage resistors to reliably melt the antifuse and provide sufficient current limiting to protect other circuits. This requires high resistance values, resulting in a large circuit area. Furthermore, the resistor's voltage rating must be much higher than the antifuse's melting voltage, placing certain demands on the manufacturing process and limiting its compatibility. Therefore, traditional programming units suffer from poor reliability, high probability of misprogramming, high power consumption, and large circuit area. Summary of the Invention

[0004] To address the problems existing in the prior art, this invention provides a low-voltage protection programming circuit for fuse adjustment, which has a low probability of false programming, high reliability, easy adjustment, low power consumption, and simple operation.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A low-voltage protection programming circuit for fuse adjustment includes a bias circuit and a main circuit. The bias circuit provides a bias voltage to the main circuit and includes a transistor Q1, a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a fifth MOSFET M5, a sixth MOSFET M6, a seventh MOSFET M7, an eighth MOSFET M8, and a first resistor R1, a second resistor R2, and a third resistor R3. The main circuit includes a first MOSFET M1', a second MOSFET M2', a third MOSFET M3', a fourth MOSFET M4', a varistor, and a level shifter.

[0007] The main circuit consists of MOSFETs M2' and M3', a varistor fuse, and the bias circuit consists of MOSFETs M4, M7, and R3, which together form a comparator. The comparator is used to determine the output level of the output point by comparing the resistance values ​​of the varistor fuse and the third resistor R3.

[0008] Preferably, in the bias circuit, one end of the first resistor R1 is connected to the operating voltage FVDD, and the other end is connected to the collector of transistor Q1 and the gate of the first MOSFET M1. The emitter of transistor Q1 is grounded to GND, the base of transistor Q1 is connected to the source of the first MOSFET M1 and the second resistor R2, and the other end of the second resistor R2 is grounded to GND. The drain of the first MOSFET M1 is connected to the drain of the second MOSFET M2. The source of the second MOSFET M2 is connected to the operating voltage FVDD. The gate of the second MOSFET is connected to the gate of the third MOSFET M3. The source of the third MOSFET M3 is connected to the operating voltage FVDD, and the drain of the third MOSFET M3 is connected to the drain of the fourth MOSFET M4. The source of the fourth MOSFET M4 is grounded to GND. The gate of the fourth MOSFET M4 is connected to the gate of the fifth MOSFET M5 to output bias voltage VB2. The source of the fifth MOSFET M5 is grounded to GND. The drain of the fifth MOSFET M5 is connected to the drain of the seventh MOSFET M7. The source of the seventh MOSFET M7 is connected to the third resistor R3. The other end of the third resistor R3 is connected to the working voltage FVDD. The gate of the seventh MOSFET M7 is used to output bias voltage VB1. The source of the eighth MOSFET M8 is connected to the gate of the seventh MOSFET M7. The drain of the eighth MOSFET M8 is connected to the working voltage FVDD. The gate of the eighth MOSFET M8 is used to output bias voltage VB3. The bias voltage VB3 is connected to the gate of the sixth MOSFET M6 through an inverter. The drain of the sixth MOSFET M6 is connected to the bias voltage VB2.

[0009] Preferably, the drain and gate of the second MOS transistor M2 are connected, the drain and gate of the fourth MOS transistor M4 are connected, and the drain and gate of the seventh MOS transistor M7 are connected.

[0010] Preferably, the bias voltage VB1 output by the seventh MOS transistor M7 in the bias circuit is used to provide bias for the third MOS transistor M3' in the main circuit;

[0011] The bias voltage VB2 output by the fifth MOS transistor M5 in the bias circuit is used to provide bias for the second MOS transistor M2' in the main circuit.

[0012] The bias voltage VB3 output by the eighth MOS transistor M8 in the bias circuit is used to provide bias for the fourth MOS transistor M4' in the main circuit.

[0013] Preferably, the main circuit further includes a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, and a first logic gate NAND1, a second logic gate NAND2, a third logic gate NAND3, and a fourth logic gate NAND4.

[0014] In this circuit, one end of the varistor fuse is connected to the operating voltage FVDD, and the other end is connected to the drain of MOSFET M1' and the source of MOSFET M3'. The drains of MOSFET M2' and M3' are connected together. The source of MOSFET M2' is grounded to GND. The drain of MOSFET M4' is connected to the drain of MOSFET M2', and the source of MOSFET M4' is connected to the operating voltage FVDD. The drains of MOSFET M2' and M3' are connected to the first inverter INV1 via a level shifter. Inverter INV1 is connected to the input of the first logic gate NAND1, and the second inverter INV2 is connected to the input of the first logic gate NAND1. The outputs of the first logic gate NAND1 and the second logic gate NAND2 are connected to the inputs of the third logic gate NAND3 and the fourth logic gate NAND4. The output of the fourth logic gate NAND4 is connected to the gate of MOSFET M1' through the third inverter INV3, the fourth inverter INV4 and the fifth inverter INV5 connected in sequence. The source of MOSFET M1' is grounded to GND.

[0015] Preferably, the second logic gate NAND2 is connected to a W_SEL signal control terminal as the input terminal of the second logic gate NAND2;

[0016] The input terminals of the fourth logic gate NAND4 are connected to the SIGNAL signal control terminal and the W_EN signal control terminal as the input terminals of the fourth logic gate NAND4.

[0017] Preferably, the first inverter INV1, the second inverter INV2, the third inverter INV3, the fourth inverter INV4, the fifth inverter INV5, and the first logic gate NAND1, the second logic gate NAND2, the third logic gate NAND3, and the fourth logic gate NAND4 are all manufactured using CMOS technology with ISO.

[0018] Preferably, before programming, the varistor fuse is powered by a 5V operating voltage VDD;

[0019] In the programming state, the varistor fuse is powered by a 4V operating voltage FVDD.

[0020] Preferably, the second MOSFET M2, the third MOSFET M3, the fourth MOSFET M4, the fifth MOSFET M5, and the seventh MOSFET M7 all adopt a current mirror structure.

[0021] Preferably, both the second resistor R2 and the third resistor R3 are M-class resistors.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] This invention provides a low-voltage protection programming circuit for fuse adjustment, comprising a bias circuit and a main circuit. Compared to traditional bias circuits, this circuit combines the fourth MOSFET M4, the seventh MOSFET M7, and the third resistor R3 in the bias circuit with the second MOSFET M2', the third MOSFET M3', and the varistor fuse in the main circuit to form a comparator. By comparing the resistance value of the third resistor R3 in the bias circuit with that of the varistor fuse in the main circuit, it determines whether the output is high or low. Based on the determined high or low level, it controls the conversion to a suitable high or low level within the appropriate range and keeps it at the same level as the power supply. The comparator output has only two states, resulting in a low probability of incorrect programming of the varistor fuse, high reliability, and easy adjustment. It can also be easily expanded to multi-digit programming. Furthermore, by controlling and adjusting the resistance values ​​of the second and third resistors in the bias circuit, a larger resistance value can reduce the bias current flowing through the circuit during programming, thereby reducing power consumption and simplifying operation. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the bias circuit in one embodiment of the present invention;

[0025] Figure 2 This is a schematic diagram of the main circuit principle of one embodiment of the present invention. Detailed Implementation

[0026] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0027] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0028] The present invention will now be described in further detail with reference to the accompanying drawings:

[0029] This invention discloses a low-voltage protection programming circuit for fuse adjustment, comprising a bias circuit and a main circuit. The bias circuit provides a bias voltage to the main circuit and includes a transistor Q1, a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a fifth MOSFET M5, a sixth MOSFET M6, a seventh MOSFET M7, an eighth MOSFET M8, and a first resistor R1, a second resistor R2, and a third resistor R3. The main circuit includes a first MOSFET M1', a second MOSFET M2', a third MOSFET M3', a fourth MOSFET M4', a varistor, and a level shifter.

[0030] The main circuit consists of MOSFETs M2' and M3', a varistor fuse, and the bias circuit consists of MOSFETs M4, M7, and R3, which together form a comparator. The comparator is used to determine the output level of the output point by comparing the resistance values ​​of the varistor fuse and the third resistor R3.

[0031] This invention provides a low-voltage protection programming circuit for fuse adjustment, comprising a bias circuit and a main circuit. Compared with traditional bias circuits, the fourth MOSFET M4, the seventh MOSFET M7, and the third resistor R3 in the bias circuit, along with the second MOSFET M2', the third MOSFET M3', and the varistor fuse in the main circuit, form a comparator. By comparing the resistance value of the third resistor R3 in the bias circuit with that of the varistor fuse in the main circuit, the output point is determined to be either high or low. Based on the determined high or low level, the circuit is controlled to convert to a suitable high or low level within the appropriate range and maintain the same level as the power supply. The comparator output has only two states, resulting in a low probability of the varistor fuse being accidentally burned out, high reliability, and easy adjustment. It can also be easily expanded to multi-digit programming. Furthermore, by controlling and adjusting the resistance values ​​of the second and third resistors in the bias circuit, a larger resistance value can reduce the bias current flowing through the circuit during programming, thereby reducing power consumption and simplifying operation. Additionally, the programming circuit of this invention uses a single-ended pull-down resistor structure, which can significantly reduce the area.

[0032] like Figure 1As shown, in one embodiment of the present invention, the bias circuit includes three resistors, one NPN transistor, four NMOS transistors, four PMOS transistors, and two inverters. Specifically, one end of the first resistor R1 is connected to the operating voltage FVDD, and the other end is connected to the collector of transistor Q1 and the gate of the first MOS transistor M1. The emitter of transistor Q1 is grounded to GND, the base of transistor Q1 is connected to the source of the first MOS transistor M1 and the second resistor R2, and the other end of the second resistor R2 is grounded to GND. The drain of the first MOS transistor M1 and the drain of the second MOS transistor M2 are connected. The source of the second MOS transistor M2 is connected to the operating voltage FVDD. The gate of the second MOS transistor is connected to the gate of the third MOS transistor M3. The source of the third MOS transistor M3 is connected to the operating voltage FVDD, and the drain of the third MOS transistor M3 is connected to the drain of the fourth MOS transistor M4. The source of the fourth MOS transistor M4... The first stage is grounded to GND. The gates of the fourth MOSFET M4 and the fifth MOSFET M5 are connected to each other for output bias voltage VB2. The source of the fifth MOSFET M5 is grounded to GND. The drain of the fifth MOSFET M5 is connected to the drain of the seventh MOSFET M7. The source of the seventh MOSFET M7 is connected to the third resistor R3. The other end of the third resistor R3 is connected to the working voltage FVDD. The gate of the seventh MOSFET M7 is used for output bias voltage VB1. The source of the eighth MOSFET M8 is connected to the gate of the seventh MOSFET M7. The drain of the eighth MOSFET M8 is connected to the working voltage FVDD. The gate of the eighth MOSFET M8 is used for output bias voltage VB3. The W_EN signal control terminal is connected to the bias voltage VB3 through an inverter, and then connected to the gate of the sixth MOSFET M6 through another inverter. The drain of the sixth MOSFET M6 is connected to the bias voltage VB2. The source of the sixth MOSFET M6 is grounded.

[0033] In this configuration, the drain and gate of the second MOS transistor M2 are connected, the drain and gate of the fourth MOS transistor M4 are connected, and the drain and gate of the seventh MOS transistor M7 are connected.

[0034] In this invention, the bias voltage VB1 output by the seventh MOS transistor M7 in the bias circuit is used to provide bias for the third MOS transistor M3' in the main circuit;

[0035] The bias voltage VB2 output by the fifth MOS transistor M5 in the bias circuit is used to provide bias for the second MOS transistor M2' in the main circuit.

[0036] The bias voltage VB3 output by the eighth MOS transistor M8 in the bias circuit is used to provide bias for the fourth MOS transistor M4' in the main circuit.

[0037] like Figure 2As shown, in one embodiment of the present invention, the main circuit includes one varistor fuse, two NMOS transistors, two PMOS transistors, five inverters, and four NAND gates.

[0038] Specifically, the inverters include a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, and a fifth inverter INV5, and the NAND gates include a first logic gate NAND1, a second logic gate NAND2, a third logic gate NAND3, and a fourth logic gate NAND4.

[0039] In this circuit, one end of the varistor fuse is connected to the operating voltage FVDD, and the other end is connected to the drain of MOSFET M1' and the source of MOSFET M3'. The drains of MOSFET M2' and M3' are connected together. The source of MOSFET M2' is grounded to GND. The drain of MOSFET M4' is connected to the drain of MOSFET M2', and the source of MOSFET M4' is connected to the operating voltage FVDD. The drains of MOSFET M2' and M3' are connected to the first inverter INV1 via a level shifter. Inverter INV1 is connected to the input of the first logic gate NAND1, and the second inverter INV2 is connected to the input of the first logic gate NAND1. The outputs of the first logic gate NAND1 and the second logic gate NAND2 are connected to the inputs of the third logic gate NAND3 and the fourth logic gate NAND4. The output of the fourth logic gate NAND4 is connected to the gate of MOSFET M1' through the third inverter INV3, the fourth inverter INV4 and the fifth inverter INV5 connected in sequence. The source of MOSFET M1' is grounded to GND.

[0040] The second logic gate NAND2 is connected to the W_SEL signal control terminal as the input terminal of the second logic gate NAND2;

[0041] The input terminals of the fourth logic gate NAND4 are connected to the SIGNAL signal control terminal and the W_EN signal control terminal as the input terminals of the fourth logic gate NAND4.

[0042] For ease of understanding, the present invention is as follows: Figure 1 and Figure 2 The specific device types shown are not intended to limit the invention. In one embodiment of the invention, the circuit structure operates under a 5V operating voltage supply. The operating voltage FVDD is a low voltage that is lower than the operating voltage VDD. If the operating voltage VDD is 5V, the operating voltage FVDD is 4V.

[0043] Preferably, the first inverter INV1, the second inverter INV2, the third inverter INV3, the fourth inverter INV4, the fifth inverter INV5, and the first logic gate NAND1, the second logic gate NAND2, the third logic gate NAND3, and the fourth logic gate NAND4 are all manufactured using ISO-compliant CMOS technology, allowing them to operate under both high and low voltage conditions and to be replaced without affecting the core content of this patent. The lack of an exhaustive description of these situations in this invention is merely for the sake of brevity and resource conservation. Therefore, this invention is not limited to the specific embodiments disclosed herein, and these combinations are also included within the scope of the claims.

[0044] Before programming, the varistor fuse is powered by a 5V operating voltage VDD.

[0045] During the programming process, the varistor fuse is powered by a 4V operating voltage FVDD, meaning that the varistor fuse is powered by different operating voltages before and during programming.

[0046] Preferably, the second MOSFET M2, the third MOSFET M3, the fourth MOSFET M4, the fifth MOSFET M5, and the seventh MOSFET M7 all adopt a current mirror structure.

[0047] Preferably, both the second resistor R2 and the third resistor R3 are M-level large resistors to generate a uA-level current to start the circuit (this current can be adjusted by changing the resistance value of R5 according to actual needs, as long as it can achieve the starting effect).

[0048] The basic working principle of the low-voltage protection programming circuit described in this invention is as follows:

[0049] (1) As Figure 1 As shown, the bias circuit is used to generate the bias voltage, and the first resistor R1 serves as the start-up circuit to turn on the first MOSFET M1.

[0050] In this context, the current I = VB1 / R2, so the current value can be determined by the resistance value of the second resistor R2. The second MOSFET M2, the third MOSFET M3, the fourth MOSFET M4, the fifth MOSFET M5, and the seventh MOSFET M7 are all current mirror structures used to replicate the current and generate the corresponding bias voltage VB. The enable signal W_EN is used to control operations such as VBF reset.

[0051] (2) Figure 2 As shown, the varistor fuse is powered by the working voltage VDD before programming and by the working voltage FVDD after programming. The working voltage FVDD should be lower than the power supply 5V. It is obtained by converting the power supply voltage by a dedicated module and is about 4V, which has a protective function for the varistor fuse.

[0052] When W_EN = 0, the program has not been written, MOSFET M1' is turned off, and the varistor fuse supply voltage of 5V is not burned out.

[0053] When W_EN = 1, MOSFET M1' (inverting transistor to reduce power consumption) is turned on, and the varistor fuse is powered by 4V and is burned out. At this time, MOSFETs M2' and M3' in the main circuit, the varistor fuse, and the fourth MOSFET M4, seventh MOSFET M7, and third resistor R3 in the bias circuit form a comparator. By comparing the resistance values ​​of the varistor fuse and the third resistor R3, it is determined whether the output point is high or low. The obtained high and low levels are then passed through a level shifter to be converted to a 0-5V high and low level to keep it at the same level as the power supply. The W_SEL signal control terminal is used to select the output level before and after programming.

[0054] (3) Except for the varistor fuse, which is powered by a 4-V operating voltage FVDD during programming, all other logic gate bias circuit modules are powered by a 5-V power supply. The second resistor R2 in the bias circuit is designed with a large resistance value, using an M-level resistor to generate a uA-level current, making the bias current particularly small. At the same time, the third resistor R3 is also designed with a relatively large resistance value, so that when the output level flips during programming, the current flowing through MOSFET M2' or MOSFET M3' is particularly small, which can reduce power consumption.

[0055] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A low-voltage protection programming circuit for fuse adjustment, characterized in that, It includes a bias circuit and a main circuit. The bias circuit is used to provide a bias voltage to the main circuit. The bias circuit includes a transistor Q1, a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a fifth MOSFET M5, a sixth MOSFET M6, a seventh MOSFET M7, an eighth MOSFET M8, and a first resistor R1, a second resistor R2, and a third resistor R3. The main circuit includes a first MOSFET M1', a second MOSFET M2', a third MOSFET M3', a fourth MOSFET M4', a varistor fuse, and a level shifter. The main circuit consists of MOSFETs M2' and M3', a varistor fuse, and the bias circuit consists of MOSFETs M4, M7, and R3, which together form a comparator. The comparator is used to determine the output level of the output point by comparing the resistance values ​​of the varistor fuse and the third resistor R3. Before programming, the varistor fuse is powered by a 5V operating voltage VDD; In the programming state, the varistor fuse is powered by a 4V operating voltage FVDD.

2. The low-voltage protection programming circuit for fuse adjustment according to claim 1, characterized in that, In the bias circuit, one end of the first resistor R1 is connected to the operating voltage FVDD, and the other end is connected to the collector of transistor Q1 and the gate of the first MOSFET M1. The emitter of transistor Q1 is grounded to GND, the base of transistor Q1 is connected to the source of the first MOSFET M1 and the second resistor R2, and the other end of the second resistor R2 is grounded to GND. The drain of the first MOSFET M1 is connected to the drain of the second MOSFET M2. The source of the second MOSFET M2 is connected to the operating voltage FVDD. The gate of the second MOSFET is connected to the gate of the third MOSFET M3. The source of the third MOSFET M3 is connected to the operating voltage FVDD. The drain of the third MOSFET M3 is connected to the drain of the fourth MOSFET M4. The source of the fourth MOSFET M4 is grounded to GND. The gate of MOSFET M4 is connected to the gate of the fifth MOSFET M5 to output bias voltage VB2. The source of the fifth MOSFET M5 is grounded to GND. The drain of the fifth MOSFET M5 is connected to the drain of the seventh MOSFET M7. The source of the seventh MOSFET M7 is connected to the third resistor R3. The other end of the third resistor R3 is connected to the working voltage FVDD. The gate of the seventh MOSFET M7 is used to output bias voltage VB1. The source of the eighth MOSFET M8 is connected to the gate of the seventh MOSFET M7. The drain of the eighth MOSFET M8 is connected to the working voltage FVDD. The gate of the eighth MOSFET M8 is used to output bias voltage VB3. The bias voltage VB3 is connected to the gate of the sixth MOSFET M6 through an inverter. The drain of the sixth MOSFET M6 is connected to the bias voltage VB2.

3. A low-voltage protection programming circuit for fuse adjustment according to claim 2, characterized in that, The drain and gate of the second MOS transistor M2 are connected, the drain and gate of the fourth MOS transistor M4 are connected, and the drain and gate of the seventh MOS transistor M7 are connected.

4. A low-voltage protection programming circuit for fuse adjustment according to claim 2, characterized in that, The bias voltage VB1 output by the seventh MOS transistor M7 in the bias circuit is used to provide bias for the third MOS transistor M3' in the main circuit. The bias voltage VB2 output by the fifth MOS transistor M5 in the bias circuit is used to provide bias for the second MOS transistor M2' in the main circuit. The bias voltage VB3 output by the eighth MOS transistor M8 in the bias circuit is used to provide bias for the fourth MOS transistor M4' in the main circuit.

5. A low-voltage protection programming circuit for fuse adjustment according to claim 1, characterized in that, The main circuit also includes a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, and a first logic gate NAND1, a second logic gate NAND2, a third logic gate NAND3, and a fourth logic gate NAND4; In this circuit, one end of the varistor fuse is connected to the operating voltage FVDD, and the other end is connected to the drain of MOSFET M1' and the source of MOSFET M3'. The drains of MOSFET M2' and M3' are connected together. The source of MOSFET M2' is grounded to GND. The drain of MOSFET M4' is connected to the drain of MOSFET M2', and the source of MOSFET M4' is connected to the operating voltage FVDD. The drains of MOSFET M2' and M3' are connected to the first inverter INV1 via a level shifter. Inverter INV1 is connected to the input of the first logic gate NAND1, and the second inverter INV2 is connected to the input of the first logic gate NAND1. The outputs of the first logic gate NAND1 and the second logic gate NAND2 are connected to the inputs of the third logic gate NAND3 and the fourth logic gate NAND4. The output of the fourth logic gate NAND4 is connected to the gate of MOSFET M1' through the third inverter INV3, the fourth inverter INV4 and the fifth inverter INV5 connected in sequence. The source of MOSFET M1' is grounded to GND.

6. A low-voltage protection programming circuit for fuse adjustment according to claim 5, characterized in that, The second logic gate NAND2 is connected to the W_SEL signal control terminal as the input terminal of the second logic gate NAND2; The input terminals of the fourth logic gate NAND4 are connected to the SIGNAL signal control terminal and the W_EN signal control terminal as the input terminals of the fourth logic gate NAND4.

7. A low-voltage protection programming circuit for fuse adjustment according to claim 5, characterized in that, The first inverter INV1, the second inverter INV2, the third inverter INV3, the fourth inverter INV4, the fifth inverter INV5, and the first logic gate NAND1, the second logic gate NAND2, the third logic gate NAND3, and the fourth logic gate NAND4 are all manufactured using CMOS technology with ISO.

8. A low-voltage protection programming circuit for fuse adjustment according to claim 1, characterized in that, The second MOSFET M2, the third MOSFET M3, the fourth MOSFET M4, the fifth MOSFET M5, and the seventh MOSFET M7 all adopt a current mirror structure.

9. A low-voltage protection programming circuit for fuse adjustment according to claim 1, characterized in that, The second resistor R2 and the third resistor R3 are both M-class resistors.

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