Capacity expansion for memory subsystems

Abstract

A memory subsystem includes: a memory subsystem controller including at least one host channel; a memory device including a plurality of memory dies; and at least one input / output (I / O) expander circuitry coupled to the at least one host channel of the memory subsystem controller and the memory device. The at least one I / O expander circuitry includes: one or more I / O buffers for transmitting and receiving signals on the at least one host channel; selection circuitry coupled to the one or more I / O buffers; and command processing logic for enabling the selection circuitry to route the signals on a selected one of the plurality of expanded channels coupled to the at least one I / O expander circuitry. Each of the plurality of expanded channels is coupled to a corresponding subgroup of the plurality of memory dies.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to capacity expansion of memory subsystems for memory subsystem controllers with input / output port constraints. Background Technology

[0002] A memory subsystem may contain one or more memory components for storing data. These memory components may be, for example, non-volatile memory components and volatile memory components. Generally, a host system can utilize a memory subsystem to store data at memory components and retrieve data from memory components. Attached Figure Description

[0003] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments thereof. However, the drawings should not be construed as limiting this disclosure to the specific embodiments, but are for explanation and understanding only.

[0004] Figure 1 This describes an instance computing environment including a memory subsystem according to some embodiments of the present disclosure.

[0005] Figure 2 This is a block diagram illustrating a memory subsystem with an input / output port-constrained memory subsystem controller according to some embodiments of the present disclosure, the controller implementing an I / O expander to increase storage capacity.

[0006] Figure 3 This is a block diagram illustrating an I / O expander used in a memory subsystem with an input / output port-constrained memory subsystem controller to increase storage capacity, according to some embodiments of the present disclosure.

[0007] Figure 4A This is a block diagram illustrating the selection of expansion channels for an I / O expander in a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 4B This is a timing diagram illustrating the selection of expansion channels for an I / O expander in a memory subsystem according to some embodiments of the present disclosure.

[0009] Figure 5 This is a flowchart illustrating an example method of I / O expander operation in a memory subsystem with an input / output port-constrained memory subsystem controller to increase storage capacity, according to some embodiments of the present disclosure.

[0010] Figure 6 This is a block diagram of an example computer system operable according to an embodiment of the present disclosure. Detailed Implementation

[0011] This disclosure relates to capacity expansion for memory subsystems used in controllers with input / output port constraints. The memory subsystem can be a storage device, a memory module, or a hybrid of both. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem comprising one or more memory components, such as memory devices for storing data. The host system can provide data for storage in the memory subsystem and can request retrieval of data from the memory subsystem.

[0012] The memory subsystem may contain multiple memory devices capable of storing data from the host system. An example of a non-volatile memory device is a NAND flash memory device. (The following section will discuss this further.) Figure 1 Other examples of non-volatile memory devices are described. The memory subsystem includes a memory subsystem controller that can communicate with the memory device to perform operations such as reading data, writing data, or erasing data at the memory device, and other such operations. The following is combined with... Figure 1 The memory subsystem controller is described in more detail.

[0013] The host system may send access requests (e.g., write commands, read commands) to the memory subsystem to, for example, store data on and read data from memory devices on the memory subsystem. The data to be read or written, as specified by the host request, is referred to hereinafter as "host data". The host request may contain logical address information (e.g., logical block address (LBA), namespace) for the host data, which is the location associated between the host system and the host data. The logical address information (e.g., LBA, namespace) may be part of the metadata of the host data. The metadata, together with the host data, is referred to hereinafter as "payload". Metadata for error correction, host data, and parity data may together form an error correction code (ECC) codeword. The metadata may also contain data versioning (e.g., to distinguish the aging of written data), a validity bitmap (whose LBA or logical transfer unit contains valid data), etc.

[0014] Each memory device may contain one or more arrays of memory cells. A memory cell (“cell”) is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logic states associated with the number of bits stored. Logic states may be represented by binary values ​​(such as “0” and “1”) or combinations of these values. For example, a single-level cell (SLC) may store one bit of information and have two logic states.

[0015] The memory subsystem may initiate media management operations, which may include, for example, performing write or read operations on host data stored on the memory device. For instance, the memory subsystem may rewrite previously written host data from a location on the memory device to the same location as a portion of a write-to-refresh operation or to a new location. In another instance, a media management operation may include rereading host data stored on the memory device as part of a read-to-refresh operation. "User data" as used below generally refers to both host data and the data rewritten for media management. "System data" as used below refers to data generated and / or maintained by the memory subsystem for operation in response to host requests and for media management. Examples of system data include, but are not limited to, system tables (e.g., logical-to-physical address mapping tables), data from records, scratch pad data, etc.

[0016] The evolution of host systems necessitates memory subsystems that offer increased capacity and performance at a lower cost. Memory subsystem controllers (e.g., system-on-a-chip (SoC)) can be extremely expensive components. Therefore, one way to reduce the cost of a memory subsystem is to reduce the size of the memory subsystem controller, for example, by limiting the number of host input / output (I / O) ports and channels within the controller. However, this port constraint limits the available capacity of the memory subsystem.

[0017] Conventional solutions have attempted to address this issue by using simple switches (e.g., passive extenders) on each host channel to increase the number of memory devices that can be connected to each host channel. While this approach increases the capacity of the memory subsystem, it still introduces a full impedance load of additional memory devices on the corresponding host channel. This increased load can affect the maximum operating data transfer rate on the channel, leading to performance degradation due to excessive signal reflections and signal integrity issues. Such degraded performance is unacceptable for many host system applications.

[0018] This disclosure addresses the above and other drawbacks by implementing capacity expansion for memory subsystems with I / O port-constrained memory subsystem controllers. The improved memory subsystem incorporates a buffering scheme that reduces the load on the host channels of the memory subsystem controller, thereby allowing for higher-speed operation while still providing memory capacity expansion at a lower cost. In one embodiment, the memory subsystem includes one or more I / O expanders (IOEs) in each of the existing host channels. Each I / O expander can support up to four expansion channels, where each expansion channel can support up to four memory devices (e.g., NAND memory dies). Thus, each I / O expander can support up to 16 individual memory devices while providing a buffering scheme that does not increase the impedance load on the existing host channels of the memory subsystem controller. Depending on the embodiment, each host channel may include multiple I / O expanders, such as two I / O expanders (i.e., 32 memory devices) or even up to four I / O expanders (i.e., 64 memory devices). Because there is no impedance load of additional memory devices on the host channel, the memory subsystem controller can still utilize the host channel at the maximum data rate acceptable to host system operation. Therefore, additional memory capacity can be made available to the host system without requiring an additional host channel in the memory subsystem controller.

[0019] Figure 1 An example computing environment 100 including a memory subsystem 110 is illustrated according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., storage device 140), one or more non-volatile memory devices (e.g., storage device 130), or a combination of the like.

[0020] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, NVM Rapid (NVMe) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and non-volatile dual in-line memory modules (NVDIMMs).

[0021] The computing environment 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1This describes an example of a host system 120 coupled to a memory subsystem 110. The host system 120 uses, for example, the memory subsystem 110 to write data to and read data from the memory subsystem 110. As used herein, “coupled to” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intervening component), whether wired or wireless, and includes connections such as electrical, optical, magnetic, etc.

[0022] Host system 120 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., aircraft, drone, train, automobile, or other means of transportation), Internet of Things (IoT) device, embedded computer (e.g., an embedded computer contained in a vehicle, industrial equipment, or networked commercial device), or such computing device containing memory and processing power. Host system 120 may be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), etc. The physical host interface can be used to transmit data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 may further utilize an NVM High Speed ​​(NVMe) interface to access memory components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data and other signals between the memory subsystem 110 and the host system 120.

[0023] The memory device may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. The volatile memory device (e.g., memory device 140) may be, but is not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0024] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory. A 3D crosspoint memory device is a crosspoint array of non-volatile memory cells that can perform bit storage based on changes in volume resistance by incorporating a stackable cross-grid data access array. Furthermore, unlike many flash-based memories, crosspoint non-volatile memories can be written in-place, where non-volatile memory cells can be programmed without pre-erasing them.

[0025] While non-volatile memory components such as 3D cross-point type and NAND type memory are described, memory device 130 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), auto-select memory, other chalcogenide-based memory, ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0026] One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), and four-level cells (QLC), may store multiple bits per cell. In some embodiments, a particular memory component may include an SLC portion of the memory cells, as well as an MLC portion, a TLC portion, or a QLC portion. The memory cells of memory device 130 may be grouped into pages or codewords that may refer to cells of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks. For some types of memory (e.g., 3D cross-connect), pages may be grouped across the die and channels to form management units (MUs).

[0027] The memory subsystem controller 115 can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include digital circuitry with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0028] The memory subsystem controller 115 may include a processor (processing device) 117 configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines for controlling the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0029] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although in Figure 1 The instance memory subsystem 110 in the present disclosure is described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 may not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0030] Typically, the memory subsystem controller 115 receives commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to enable the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical block addresses and physical block addresses associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into instructions for accessing the memory device 130 and translate responses associated with the memory device 130 into information for the host system 120.

[0031] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., row decoder and column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0032] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0033] In one embodiment, the local media controller 135 includes one or more I / O extenders (IOEs) in each of the host channels coupled between the memory subsystem controller 115 and the memory device 130. For example, the memory device 130 may include multiple individual NAND memory dies, where each I / O extender may support up to four expansion channels, and each expansion channel may support up to four NAND memory dies. Thus, each I / O extender may support up to 16 individual memory dies while providing a buffered approach that does not increase the impedance load on the existing host channels of the memory subsystem controller. In another embodiment, the I / O extender may be implemented in another portion of the memory device 130 or coupled in another circuitry between the memory subsystem controller 115 and the memory device 130. For example, in another embodiment, the memory device 130 may actually represent a single memory die that can be coupled to an expansion channel provided by the I / O extender, as will be described in more detail below. Depending on the embodiment, each host channel may include multiple I / O expanders, such as two I / O expanders (i.e., 32 memory devices) or even up to four I / O expanders (i.e., 64 memory devices). Since there is no impedance load of additional memory devices on the host channel, the memory subsystem controller can still utilize the host channel at the maximum data rate acceptable for the operation of host system 120. Further details regarding the use of I / O expanders in memory subsystem 110 are described below.

[0034] Figure 2 This is a block diagram illustrating a memory subsystem 110 with an input / output port-constrained memory subsystem controller 115 according to some embodiments of the present disclosure, the controller implementing I / O expanders 220-222 to increase storage capacity. In one embodiment, the memory subsystem controller 115 includes a plurality of host input / output ports, each having a corresponding host channel. For example, Figure 2 The host channel 210 shown may be one of a plurality of host channels connected to the memory subsystem controller 115. Depending on the embodiment, the memory subsystem controller 115 may have two host channels, four host channels, eight host channels, or some other number of host channels. As the number of host input / output ports and host channels increases, the complexity, cost, and size of the memory subsystem controller also increase. Therefore, it may be necessary to limit the number of host input / output ports and channels in the memory subsystem controller 115.

[0035] In one embodiment, each of the host channels may include one or more I / O expanders (also referred to herein as "I / O expander circuitry"). For example, several I / O expanders 220-222 may be connected to host channel 210. I / O expanders 220-222 may be implemented, for example, in the local media controller 135 of memory device 130. In other embodiments, I / O expanders 220-222 may be implemented in a separate circuit coupled between memory subsystem controller 115 and memory device 130, or elsewhere in memory subsystem 110. Each of the other host channels connected to memory subsystem controller 115 may also have a corresponding number of I / O expanders, expanded channels, and connected memory dies.

[0036] Depending on the embodiment, each host channel may include one or more I / O expanders, such as one, two, three, or four I / O expanders. Each I / O expander may support up to four expansion channels. For example, I / O expander 220 may include expansion channels 230, 232, 234, and 236. I / O expander 222 may similarly include four expansion channels 238 or some other number of expansion channels, each coupled to a number of memory dies (not shown). Each of the expansion channels may support up to four memory devices (e.g., NAND memory dies). In one embodiment, memory die 240 is connected to expansion channel 230, memory die 242 is connected to expansion channel 232, memory die 244 is connected to expansion channel 234, and memory die 246 is connected to expansion channel 236. In one embodiment, each expansion channel is connected to the same number of memory dies. However, in other embodiments, each expansion channel from the same I / O expander can be connected to a different number of memory dies. For example, one expansion channel can be connected to two memory dies, while another expansion channel can be connected to four memory dies. Thus, each I / O expander, such as I / O expander 220, can support up to 16 individual memory devices. As will be described in more detail below, each I / O expander can provide a buffered solution that does not increase the impedance load associated with the additional memory dies 240, 242, 244, 246 on the existing host channel 210 of the memory subsystem controller 115.

[0037] Figure 3 This is a block diagram illustrating an I / O expander 220 used to increase storage capacity in a memory subsystem having an input / output port-constrained memory subsystem controller, according to some embodiments of the present disclosure. Figure 3The structure and layout of I / O expander 220 shown may represent the structure and layout of other I / O expanders, such as I / O expander 222, in memory subsystem 110. In other embodiments, other I / O expanders may have a different structure and / or layout. In one embodiment, I / O expander 220 includes a host port 302 configured to couple to a corresponding host channel, such as host channel 210, and a target port 304 configured to couple to a plurality of extended channels, such as channels A, B, C, D, etc., which may represent, for example, extended channels 230, 232, 234, 236. The I / O expander further includes a first set of I / O buffers 312 that can be coupled to or form at least a portion of the host port 302 for transmitting and receiving signals on host channel 210, and a second set of I / O buffers 314 that can be coupled to or form at least a portion of the target port 304 for transmitting and receiving signals on extended channels A, B, C, D. Additionally, the I / O expander circuit 220 includes a selection circuit 320 coupled to the first set of I / O buffers 312 and the second set of I / O buffers 314, and command forward logic 330 enabling the selection circuit 320 to select an up-route signal in the expansion channels A, B, C, and D. As described above, each of the expansion channels A, B, C, and D can be coupled to a corresponding subgroup of memory dies in the memory device 130.

[0038] In one embodiment, the first set of I / O buffers 312 includes I / O buffer pairs coupled to the data lines (DQ) of the host channel 210 and I / O buffer pairs coupled to the data strobe lines (DQS) of the host channel 210. Since the data lines DQ and DQS are bidirectional paths, one buffer in each I / O buffer pair buffers incoming signals from the memory subsystem controller 115, and the other buffer in each I / O buffer pair buffers outgoing signals. Similarly, the second set of I / O buffers 314 includes I / O buffer pairs coupled to the data lines (DQ) of the extended channel A and I / O buffer pairs coupled to the data strobe lines (DQS) of the extended channel A. One buffer in each of these I / O buffer pairs buffers signals sent to the memory die coupled to the extended channel A, and the other buffer in each I / O buffer pair buffers signals received from the memory die.

[0039] In one embodiment, command processing logic 330 monitors signals received on host channel 210, determines whether the signals received on host channel 210 correspond to a write request or a read request, and selectively enables the corresponding buffer in the first set of I / O buffers 312 and the second set of I / O buffers 314. In one embodiment, command processing logic 330 tracks command cycle states to ensure that the shared buses DQ and DQS are driven in the appropriate direction and that die-on-delivery termination (ODT) is performed at the appropriate time for the transfer sequence. Command cycle phases (e.g., address cycle, data transfer cycle) are identified using specific control signals (e.g., from the ONFI interface) received at host port 302 via host channel 210, as will be described herein. The DQ signal is a bidirectional signal used to transfer address, command, and data into and out of I / O extender 220. CE_n is a chip enable signal for selecting the target I / O extender. ALE is an address latch enable signal indicating an address bus cycle, and CLE is a command latch enable signal indicating a command bus cycle. DQS is a data strobe signal used to select data transfers on the data line DQ. RE is a read enable signal sent by the memory subsystem controller 115 to switch NAND data transfer in a dual-state manner for read operations. WE is a write enable signal for latching control commands and addresses, and WP is a write protection signal.

[0040] In one embodiment, the command processing logic generates several path control signals 332 that enable various buffers in the I / O expander 220 when appropriate. `hp_drv_en` is a host port driver enable signal that enables host ports DQ and DQS for IOE-to-controller transfers (e.g., read page data transfers). `hp_odt_en` is a host port ODT enable signal that enables ODT on host ports DQ and DQS for controller-to-IOE transfers (e.g., program page data transfers). This signal can be gated by whether ODT is enabled and whether ODT is required for the corresponding command. `tp_drv_en` is a destination port driver enable signal that enables destination ports DQ and DQS for IOE-to-NAND transfers (e.g., command / address loops and program page data transfers to NAND). `tp_odt_en` is a destination port receive and ODT enable signal that conditionally enables ODT on destination ports DQ and DQS for NAND-to-IOE transfers (e.g., read page data transfers). This signal can be selected based on whether ODT is enabled and whether ODT is required for the corresponding command. Therefore, when a write request is received, the command processing logic 330 can assert hp_odt_en and tp_drive_en_A to enable the corresponding I / O buffers from the first I / O buffer 312 and the second I / O buffer 314, respectively. Conversely, when a read request is received, the command processing logic 330 can assert tp_odt_en_A and hp_drv_en to enable the corresponding I / O buffers from the second I / O buffer 314 and the first I / O buffer 312, respectively.

[0041] In one embodiment, the signal received on host channel 210 includes an I / O extender identifier and a memory address. The I / O extender identifier uniquely identifies a given I / O extender among multiple I / O extenders coupled to the same host channel, such as I / O extender 220. The memory address uniquely identifies a given memory location on a specific memory die among multiple memory dies of various extension channels A, B, C, D coupled to the identified I / O extender. In one embodiment, as will be referred to below relative to... Figure 4A and 4BIn more detail, command processing logic 330 can compare an I / O extender identifier from a signal received on host channel 210 with a volume identifier associated with I / O extender circuitry 220. In response to an I / O extender identifier matching a volume identifier, command processing logic 330 determines the memory die corresponding to a memory address and identifies the corresponding extension channel coupled to the determined memory die. In one embodiment, command processing logic 330 applies channel selection signal 334 to selection circuitry 320 (e.g., a multiplexer) such that selection circuitry 320 routes the received signal on a corresponding one of extension channels A, B, C, D. Similarly, channel selection signal 334 can cause selection circuitry 320 to route signals from extension channels back to destination port 302 and onto host channel 210.

[0042] In one embodiment, command processing logic 330 is configured based on configuration values ​​336 related to, for example, ODT and drive strength. ODT configuration for the host port 302 interface is performed using ONFI commands, while vendor-defined configuration commands for the target port 304 interface may exist. This vendor-defined setting can be applied across all expansion channels A, B, C, and D. In one embodiment, ODT may support 50, 75, and 150 ohm terminations. Similarly, drive strength for the host port 302 interface is performed using standard setting feature commands, while vendor-defined addresses for the target port 304 interface may exist. Drive strength may support 37.5 and 50 ohm terminations. In one embodiment, configuration values ​​are portions of a configuration template associated with the capacity of the memory die in the memory device 130. For example, the configuration template may contain predefined configuration values ​​optimized for a given capacity (e.g., for ODT and drive strength).

[0043] Figure 4A This is a block diagram illustrating expansion channel selection for an I / O expander 220 in a memory subsystem according to some embodiments of the present disclosure. In one embodiment, expansion channel selection is based on an encoded chip enable (CE) signal received by the I / O expander 220 from the memory subsystem controller 115 via host channel 210 and an IOE identifier signal (ADDR) for IOE volume selection. Figure 4AThe description states that this configuration can support up to four multi-branch I / O expander packages on a single host channel. enCE[0] is a chip enable signal for the ONFI command sequence. enCE[2:1] is a chip enable signal used when I / O expander 220 is not configured in volume select mode and can indicate specific expansion channels A, B, C, D. When I / O expander 220 is configured in volume select mode, enCE[2:1] can be ignored because channel selection is based on the volume identifier contained in the ONFI command signal. enCE[3] is a chip enable signal indicating where the received command is directed to the memory die coupled to the expansion channel or I / O expander 220 itself (e.g., command processing).

[0044] In one embodiment, ADDR[1:0] are address signals external to the package (e.g., directly on the circuit board) that are associated with a given logic value. These address signals provide an I / O extender identifier that uniquely identifies I / O extender 220 and can be used in volume select mode. In volume select mode, command processing logic 330 of I / O extender 220 compares the volume identifier contained in an ONFI command signal received on host channel 210 with the I / O extender identifier associated with I / O extender 220. If the volume identifier matches the I / O extender identifier, then command processing logic 330 determines that the ONFI command signal is addressed to I / O extender 220. If the volume identifier and I / O extender do not match, then I / O extender 220 can ignore the ONFI command because it is addressed to a different I / O extender coupled to host channel 210. Therefore, in response to a volume identifier matching an I / O extender identifier, command processing logic 330 determines the memory die corresponding to the memory address contained in the ONFI command signal. Multi-Die Stack (MDS) addressing allows multiple dies to share a common chip enable signal on host channel 210. With MDS, addressing uses an extended "6-address cycle" mode to support four or more LUNs sharing a common chip enable per host channel. Addressing can be extended to include 3 bits to encode the LUN address on the channel.

[0045] Figure 4BThis is a timing diagram illustrating expansion channel selection for I / O expanders in a memory subsystem according to some embodiments of the present disclosure. In one embodiment, volume select mode is disabled immediately upon power-up of memory subsystem 110. In multi-branch applications, memory subsystem controller 115 can enable volume select mode by issuing a configuration feature command to all I / O expanders in the memory subsystem. In one embodiment, each of the I / O expanders listens on host channel 210 regardless of its selected state to detect volume select commands. In one embodiment, the volume identifier includes IOE_SEL and CHN_SEL. Command processing logic 330 compares the volume identifier (Vol_ID) of the command with the values ​​of IOE_SEL and CHN_SEL. If IOE_SEL matches the wired to the packaged IOE_ID, then the I / O expander should transition to the selected (i.e., active) state; otherwise, the IOE transitions or remains in the unselected state. The CHN_SEL signal is used to select the expansion channel on the newly activated I / O expander. In one embodiment, the volume select command is sent by the memory subsystem controller 115 as a normal ONFI command. For example... Figure 4B As shown, the volume select command proceeds along the previously selected path. Following the command, the previously expanded channel is placed in a bus hold state. The selected I / O expander switches during the tSWITCH time period to enable the new expanded channel path; this time period can be defined to ensure a minimum time greater than tCAH / tCALH and a maximum time less than tVDLY. The next NAND command CMD2 issued by the memory subsystem controller 115 can then be directed to the new expanded channel.

[0046] Figure 5 This is a flowchart illustrating an example method of I / O expander operation in a memory subsystem with an input / output port-constrained memory subsystem controller to increase storage capacity, according to some embodiments of this disclosure. Method 500 may be executed by processing logic that may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 500 is executed by, for example... Figures 2-4B The I / O expander 220 and other I / O expanders shown are executed. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are also possible.

[0047] In operation 510, the processing logic receives a signal on host channel 210. In one embodiment, the signal is an ONFI signal sent by memory controller subsystem controller 115 on host channel 210. Memory subsystem 110 may be a multi-branch system in which multiple devices (e.g., I / O expander circuits) coupled to the same host channel 210 exist. Therefore, each of the I / O expander circuits may receive the same signal. In one embodiment, the signal includes a volume identifier that can be used to identify the I / O expander to which the signal is addressed, and a memory address that can be used to determine the expansion channel and memory die associated with the I / O expander.

[0048] In operation 520, the processing logic determines that the signal is addressed to I / O extender 220. In one embodiment, command processing logic 330 of I / O extender 220 can compare the volume identifier of the signal received on host channel 210 with the I / O extender identifier associated with I / O extender circuitry 220. If the volume identifier matches the I / O extender identifier, then command processing logic 330 can determine that the ONFI command signal is addressed to I / O extender 220. If the volume identifier and I / O extender do not match, then I / O extender 220 can ignore the ONFI command because it is addressed to a different I / O extender coupled to host channel 210.

[0049] In operation 530, the processing logic identifies the corresponding expansion channel of I / O expander 220. In response to a volume identifier matching an I / O expander identifier, the command processing logic can determine the memory die corresponding to the memory address. In one embodiment, a multi-die stacking addressing scheme allows multiple dies to share a common chip enable signal on host channel 210. Therefore, through multi-die stacking addressing, multiple memory dies 240, 242, 244, 246 attached to multiple expansion channels 230, 232, 234, 236 can share a common address space. Therefore, command processing logic 330 can decode the memory address received in the signal on host channel 210 and determine the associated memory die and the corresponding expansion channel to which the memory die is attached.

[0050] In operation 540, the processing logic selectively enables the I / O buffer corresponding to the selected extended channel. In one embodiment, command processing logic 330 determines whether the ONFI command corresponds to a write request or a read request, and thus generates path control signal 332. When a write request is received, command processing logic 330 may assert hp_odt_en and to_drive_en_A to enable the corresponding I / O buffers from the first group of I / O buffers 312 and the second group of I / O buffers 314, respectively. When a read request is received, command processing logic 330 may assert tp_odt_en_A and hp_drv_en to enable the corresponding I / O buffers from the second group of I / O buffers 314 and the first group of I / O buffers 312, respectively.

[0051] In operation 550, the processing logic routes signals on the selected extended channel to subgroups of the plurality of memory dies coupled to the selected extended channel. In one embodiment, command processing logic 330 applies a channel selection signal 334 to selection circuitry 320 (e.g., a multiplexer) such that selection circuitry 320 routes the received signal on a corresponding one of extended channels A, B, C, D. Similarly, channel selection signal 334 may cause selection circuitry 320 to route signals from the extended channel back to destination port 302 and to host channel 210.

[0052] Figure 6 This describes an example machine of computer system 600, in which a set of instructions is executable to cause the machine to perform any or more of the methods discussed herein. In some embodiments, computer system 600 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform operations of the controller or other components (e.g., to execute instructions to perform operations corresponding to...). Figure 3 (Operation of I / O extender 220 or command processing logic 330). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, operating at the capacity of a server or client machine in a client-server network environment.

[0053] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should be understood to include any set of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0054] The example computer system 600 includes a processing device 602 that communicates with each other via a bus 630, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618.

[0055] Processing device 602 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may further include a network interface device 608 for communication via network 620.

[0056] Data storage system 618 may include machine-readable storage medium 624 (also referred to as computer-readable medium) storing one or more instruction sets 626 or software embodying any or more of the methods or functions described herein. Instructions 626 may also reside wholly or at least partially within main memory 604 and / or processing device 602 during execution by computer system 600, which also constitute machine-readable storage medium. Machine-readable storage medium 624, data storage system 618, and / or main memory 604 may correspond to... Figure 1 The memory subsystem 110.

[0057] In one embodiment, instruction 626 includes instructions for implementing the corresponding Figure 3The I / O expander 220 or command processing logic 330 provides functional instructions. Although the machine-readable storage medium 624 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0058] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. In this document, and generally in general, an algorithm is conceived as a self-consistent sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of a physical quantity. Typically (but not always), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for common use.

[0059] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations for application to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of a computer system into other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0060] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each connected to a computer system bus.

[0061] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as illustrated in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0062] This disclosure may be provided as a computer program product or software, which may include machine-readable media on which instructions are stored for programming a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0063] In the foregoing description, embodiments of this disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A memory subsystem comprising: A memory subsystem controller, which includes at least one host channel; A memory device comprising a plurality of memory dies; as well as At least one input / output (I / O) expander circuit coupled between the at least one host channel of the memory subsystem controller and the memory device to connect the plurality of memory dies to the memory subsystem controller, the at least one I / O expander circuit comprising: One or more I / O buffers for transmitting and receiving signals on the at least one host channel; Selection circuitry, coupled to the one or more I / O buffers; and Command processing logic enables the selection circuit to route the signal on a selected one of a plurality of expansion channels coupled to the at least one I / O expander circuit, each of the plurality of expansion channels being coupled to a corresponding subgroup of the plurality of memory dies, and wherein the one or more I / O buffers limit the impedance load present on the at least one host channel to the impedance load of the corresponding subgroup of the plurality of memory dies associated with the selected one of the plurality of expansion channels.

2. The memory subsystem of claim 1, wherein the one or more I / O buffers comprise: A first I / O buffer pair, which is coupled to the at least one host channel; as well as A second I / O buffer pair, which is coupled to one of the plurality of extended channels.

3. The memory subsystem according to claim 2, wherein the command processing logic is configured to: Monitor the signals received on the at least one host channel; Determine whether the signal received on the at least one host channel corresponds to a write request or a read request from the memory subsystem controller; as well as Selectively enable the corresponding I / O buffer in the first I / O buffer pair and the corresponding buffer in the second I / O buffer pair.

4. The memory subsystem of claim 3, wherein the signal received on the at least one host channel includes a volume identifier and a memory address, and wherein the command processing logic is configured to: The volume identifier of the signal received from the at least one host channel is compared with the I / O expander identifier associated with the at least one I / O expander circuit. In response to the volume identifier matching the I / O expander identifier, a memory die corresponding to the memory address is determined; as well as Identify the selected one of the plurality of extended channels coupled to the determined memory die.

5. The memory subsystem according to claim 1, further comprising: A plurality of I / O expander circuits coupled to the at least one host channel, wherein each of the plurality of I / O expander circuits is coupled to four expansion channels, and each of the four expansion channels of each of the plurality of I / O expander circuits is coupled to a corresponding subgroup of four of the plurality of memory dies.

6. The memory subsystem of claim 1, wherein the memory subsystem controller includes a plurality of host channels, and further includes: At least one input / output expander circuit is coupled to each of the plurality of host channels.

7. An input / output (I / O) expander circuit, comprising: A host port configured to couple to at least one host channel of the memory subsystem controller; A first set of I / O buffers, coupled to the host port, to send and receive signals on the at least one host channel; The selection circuit is coupled to the first group of I / O buffers; A target port configured to couple to a plurality of expansion channels, each of which is coupled to a corresponding subgroup of a plurality of memory dies, wherein the I / O expander circuitry connects the plurality of memory dies to the memory subsystem controller; as well as Command processing logic enables the selection circuit to route the signal on a selected one of the plurality of extended channels, wherein the first set of I / O buffers limits the impedance load present on the at least one host channel to the impedance load of the corresponding subgroup of the plurality of memory dies associated with the selected one of the plurality of extended channels.

8. The I / O expander circuit according to claim 7, further comprising: A second set of I / O buffers is coupled to the target port to send and receive signals on the plurality of extended channels.

9. The I / O expander circuit of claim 8, wherein the command processing logic is configured to: Monitor the signals received on the at least one host channel; Determine whether the signal received on the at least one host channel corresponds to a write request or a read request from the memory subsystem controller; as well as Selectively enable the corresponding I / O buffer in the first group of I / O buffers and the corresponding I / O buffer in the second group of I / O buffers.

10. The I / O expander circuit of claim 9, wherein the signal received on the at least one host channel includes a volume identifier and a memory address, and wherein the command processing logic is configured to: The volume identifier of the signal received from the at least one host channel is compared with the I / O expander identifier associated with the I / O expander circuitry; In response to the volume identifier matching the I / O expander identifier, a memory die corresponding to the memory address is determined; as well as Identify the selected one of the plurality of extended channels coupled to the determined memory die.

11. The I / O expander circuit of claim 7, wherein the command processing logic is configured based on a command template associated with the capacity of the plurality of memory dies according to configuration values ​​for die-on-derivative (ODT) at the host port and the target port.

12. A memory device comprising: Multiple memory dies; as well as At least one input / output (I / O) expander circuit configured to couple to at least one host channel of the memory subsystem controller and to the plurality of memory dies, the at least one I / O expander circuit connecting the plurality of memory dies to the memory subsystem controller, the at least one I / O expander circuit comprising: One or more I / O buffers configured to transmit and receive signals on the at least one host channel; Selection circuitry, coupled to the one or more I / O buffers; and Command processing logic enables the selection circuit to route the signal on a selected one of a plurality of expansion channels coupled to the at least one I / O expander circuit, each of the plurality of expansion channels being coupled to a corresponding subgroup of the plurality of memory dies, and wherein the one or more I / O buffers limit the impedance load present on the at least one host channel to the impedance load of the corresponding subgroup of the plurality of memory dies associated with the selected one of the plurality of expansion channels.

13. The memory device of claim 12, wherein the one or more I / O buffers comprise: A first I / O buffer pair, configured to be coupled to the at least one host channel; as well as A second I / O buffer pair, which is coupled to one of the plurality of extended channels.

14. The memory device of claim 13, wherein the command processing logic is configured to: Monitor the signals received on the at least one host channel; Determine whether the signal received on the at least one host channel corresponds to a write request or a read request from the memory subsystem controller; as well as Selectively enable the corresponding I / O buffer in the first I / O buffer pair and the corresponding buffer in the second I / O buffer pair.

15. The memory device of claim 14, wherein the signal received on the at least one host channel includes a volume identifier and a memory address, and wherein the command processing logic is configured to: The volume identifier of the signal received from the at least one host channel is compared with the I / O expander identifier associated with the at least one I / O expander circuit. In response to the volume identifier matching the I / O expander identifier, a memory die corresponding to the memory address is determined; as well as Identify the selected one of the plurality of extended channels coupled to the determined memory die.

16. The memory device of claim 12, wherein the command processing logic is configured based on a command template associated with the capacity of the plurality of memory dies according to a configuration value for an on-die termination (ODT) in at least one I / O expander circuit.

17. The memory device of claim 12, further comprising: A plurality of I / O expander circuits configured to couple to the at least one host channel, wherein each of the plurality of I / O expander circuits is coupled to four expansion channels, and each of the four expansion channels of each of the plurality of I / O expander circuits is coupled to a corresponding subgroup of four of the plurality of memory dies.

Images