System and method for stabilizing cell threshold voltage

Abstract

The present disclosure relates to a memory device comprising: a plurality of memory cells, each memory cell programmable to a logic state corresponding to a threshold voltage exhibited by the memory cell in response to an applied voltage; and a logic circuit portion operably coupled to the plurality of memory cells, wherein the logic circuit portion is configured to scan a memory address of the memory device and generate a set-up pulse to apply to an addressed page of the memory device. Also disclosed is a related electronic system and a related method.

Description

Technical Field

[0001] This disclosure relates to systems and methods for stabilizing cell threshold voltages, and more particularly, to systems and methods for stabilizing cell threshold voltages during a first set-reset cycle. Background Technology

[0002] A memory device comprises multiple memory cells adapted to store data in programmable logic states. For example, a binary memory cell can be programmed to two different logic states, typically represented by a logic "1" (also known as a "SET" state) or a logic "0" (also known as a "RESET" state). To access the stored data, dedicated circuitry can read or sense the stored logic states in the memory device. To store data, dedicated circuitry can write or program logic states into the memory device.

[0003] Memory devices are used in many electronic systems, such as mobile phones, personal digital assistants, laptop computers, digital cameras, and the like. Non-volatile memory retains its contents when power is cut off (i.e., memory cells can retain stored data by maintaining their programmed logical state for an extended period, even in the absence of external power), making it a good choice among memory devices for storing information to be retrieved after a system power cycle. Several types of non-volatile memory devices are known in the art, and a non-exhaustive list includes read-only memory devices, flash memory devices, ferroelectric random access memory (RAM) devices, magnetic memory storage devices (e.g., hard disk drives), optical memory devices (e.g., CD-ROM disks, DVD-ROM disks, Blu-ray discs), and phase-change memory (PCM) devices.

[0004] It is important to improve the stability of the threshold voltage of memory cells as much as possible. Many cell voltage stabilization techniques exist, which involve performing a conditioning process to age the cell at a sufficient level. This process requires the use of a test machine that interacts with the device. Therefore, it is desirable to have cost-effective, time-saving, and efficient systems and methods for stabilizing cell threshold voltages without the need for any external test machine. Attached Figure Description

[0005] Figure 1 This is a block diagram illustrating a model memory cell;

[0006] Figure 2 A portion of an exemplary memory cell array is illustrated schematically.

[0007] Figure 3 It is a graph illustrating the threshold voltage value relative to the number of set-reset cycles applied to the exemplary memory cell;

[0008] Figure 4 This is an exemplary block design of a memory device including a logic circuit portion for stabilizing cell threshold voltages according to the present disclosure.

[0009] Figure 5 A schematic block diagram of a system including a memory device according to the present disclosure is shown;

[0010] Figure 6 This is a flowchart illustrating the steps of the method according to this disclosure;

[0011] Figure 7 This is a flowchart illustrating the steps of a method according to an embodiment of the present disclosure. Detailed Implementation

[0012] Referring to the diagrams described herein, an improved system and method for stabilizing cell threshold voltages will be disclosed herein.

[0013] When power is cut off, non-volatile memory retains its contents, making it a good choice for storing information to be retrieved after a system power cycle. Flash memory is a type of non-volatile memory that retains stored data and is characterized by very fast access times. Furthermore, it can be erased in blocks, rather than one byte at a time. Each erasable block of memory comprises multiple non-volatile memory cells arranged in a matrix of rows and columns. Each cell is coupled to an access line and / or a data line. The cell is programmed and erased by manipulating voltages on the access and data lines.

[0014] Figure 1 A block diagram illustrating an exemplary memory cell 100 with a stable threshold voltage according to this disclosure.

[0015] exist Figure 1 In the embodiments described herein, memory cell 100 includes storage material 102 between access lines 104 and 106. Access lines 104 and 106 electrically couple memory cell 100 to circuitry 142 for writing to and reading from memory cell 100. The term “coupled” can refer to elements of direct or indirect physical, electrical, and / or communication connections, and is used interchangeably with the term “connection” herein. Physical coupling may include direct contact. Electrical coupling includes interfaces or interconnections that allow current and / or signal transmission between components. Communication coupling includes connections that enable components to exchange data, including wired and wireless connections.

[0016] In one embodiment, the storage material 102 comprises a self-selecting material exhibiting a memory effect. A self-selecting material is one that enables memory cells in the array to be selected without the need for individual selector elements. Therefore, Figure 1The storage material 102 is referred to as a “selector / storage material”. The material exhibits a memory effect if the circuitry used to access the memory cell causes the material to be in one of several states (e.g., via a write operation) and subsequently determines a programmed state (e.g., via a read operation). The circuitry used to access the memory cell (e.g., via read and write operations) is generally referred to as an “access circuit” and is further discussed below with reference to access circuitry 143. The access circuitry can store information in the memory cell 100 by causing the storage material 102 to be in a specific state. The storage material 102 may comprise, for example, chalcogenide materials such as Te-Se alloys, As-Se alloys, Ge-Te alloys, As-Se-Te alloys, Ge-As-Se alloys, Te-As-Ge alloys, Si-Ge-As-Se alloys, Si-Te-As-Ge alloys, or other materials that can be used as both a storage element and a selector to address a specific memory cell and determine the state of the memory cell. Therefore, in one embodiment, the memory cell 100 is a self-selecting memory cell comprising a single material layer that serves as both a selector element for selecting the memory cell and a memory element for storing logical states (i.e., states associated with a given polarity of the cell).

[0017] In one embodiment, the storage material 102 is a phase change material. A phase change material can electrically switch between substantially amorphous and substantially crystalline states across the entire spectrum between fully amorphous and fully crystalline states. The memory cell 100 may further include a selection device (not shown) between access lines 104 and 106; this selection device may be coupled in series to the storage material 200. In another embodiment, the storage material 102 is not a phase change material. In one embodiment where the storage material 102 is not a phase change material, the storage material is capable of switching between two or more stable states without changing its phase. The access circuit 143 can program the memory cell 100 by applying a voltage of a specific polarity to induce the storage material 102 to be in a desired stable state.

[0018] In one embodiment, the programmable memory cell 100 causes the memory cell 100 to be “thresholded” or experience a “threshold event.” When the memory cell is thresholded (e.g., during a programming voltage pulse), the memory cell undergoes a physical change that causes the memory cell to exhibit a specific threshold voltage in response to the application of a subsequent voltage (e.g., a read voltage with a specific magnitude and polarity). The programmable memory cell 100 may therefore involve applying a voltage of a given polarity to trigger a programming threshold event, which causes the memory cell 100 to exhibit a specific threshold voltage at subsequent read voltages of the same or different polarities. In one embodiment, the storage material 102 is a self-selected material (e.g., a non-phase change chalcogenide material or other self-selected material) that can be programmed by triggering a threshold event.

[0019] As mentioned above, access lines 104 and 106 electrically couple memory cell 100 to circuit 142. Access lines 104 and 106 may be referred to as bit lines and word lines, respectively. Word lines are used to access specific words in the memory array, and bit lines are used to access specific positions within those words. Access lines 104 and 106 may be composed of: one or more metals, including: Al, Cu, Ni, Cr, Co, Ru, Rh, Pd, Ag, Pt, Au, Ir, Ta, and W; conductive metal nitrides, including TiN, TaN, WN, and TaCN; conductive metal silicides, including tantalum silicide, tungsten silicide, nickel silicide, cobalt silicide, and titanium silicide; conductive metal silicide nitrides, including TiSiN and WSiN; conductive metal carbide nitrides, including TiCN and WCN; or any other suitable conductive material.

[0020] In one embodiment, electrode 108 is disposed between storage material 102 and access lines 104, 106. Electrode 108 electrically couples access lines 104, 106 to storage material 102. Electrode 108 may be composed of one or more conductive and / or semiconductive materials, for example, carbon (C), carbon nitride (C2), etc. x N y); n-doped polycrystalline silicon and p-doped polycrystalline silicon; metals, including: Al, Cu, Ni, Cr, Co, Ru, Rh, Pd, Ag, Pt, Au, Ir, Ta and W; conductive metal nitrides, including TiN, TaN, WN and TaCN; conductive metal silicides, including tantalum silicide, tungsten silicide, nickel silicide, cobalt silicide and titanium silicide; conductive metal silicide nitrides, including TiSiN and WSiN; conductive metal carbide nitrides, including TiCN and WCN; conductive metal oxides, including RuO2; or other suitable conductive materials. In one embodiment, the conductive word line layer may comprise: any suitable metal, including, for example, metals comprising Al, Cu, Ni, Cr, Co, Ru, Rh, Pd, Ag, Pt, Au, Ir, Ta, and W; conductive metal nitrides comprising TiN, TaN, WN, and TaCN; conductive metal silicides comprising tantalum silicide, tungsten silicide, nickel silicide, cobalt silicide, and titanium silicide; conductive metal silicide nitrides comprising TiSiN and WSiN; conductive metal carbide nitrides comprising TiCN and WCN; or another suitable conductive material.

[0021] Referring again to circuit 142, according to an embodiment, access lines 104, 106 communicatively couple circuit 142 to memory cell 100. Circuit 142 includes access circuitry 143 and sensing circuitry 145. The circuitry includes electronic components electrically coupled to perform analog or logical operations on received or stored information, output information, and / or store information. Hardware logic is circuitry used to perform logical operations, such as those involved in data processing. In one embodiment, access circuitry 143 applies voltage pulses to access lines 104, 106 to write to or read from memory cell 100. The terms “write” and “program” are used interchangeably to describe the act of storing information in a memory cell. To write to memory cell 100, access circuitry applies voltage pulses of a specific magnitude and polarity to access lines 104, 106, which can select or program memory cell 100.

[0022] For example, access circuit 143 applies a pulse of one polarity to program memory cell 100 to one logic state, and applies pulses of different polarities to program memory cell 100 to different logic states. Access circuit 143 can then distinguish between different logic states due to the programming polarity of the memory cell. For example, in the case of memory read, access circuit 143 applies a voltage pulse of a specific magnitude and polarity to access lines 104, 106, which results in an electrical response detectable by sensing circuit 145. Detecting the electrical response may include, for example, detecting one or more of the following: a voltage drop across the terminals of a given memory cell in the array (e.g., a threshold voltage); a current through the given memory cell; and a threshold event of the given memory cell. In some cases, detecting the threshold voltage of a memory cell may include determining that the threshold voltage of the cell is below or above a reference voltage, such as a read voltage. Access circuit 143 can determine the logic state of memory cell 100 based on the electrical response to one or more of the voltage pulses in the read sequence.

[0023] The current generated when a read voltage is applied therefore depends on the threshold voltage of the memory cell, determined by the resistance of the logic state storage element. For example, a first logic state (e.g., a SET state) may correspond to a finite amount of current, while a second logic state (e.g., a RESET state) may correspond to no current or a negligible amount of current. Alternatively, a first logic state may correspond to a current above a current threshold, while a second logic state may correspond to a current below a current threshold.

[0024] Memory cell 100 is an example of a memory cell. Other embodiments may include having, but are not limited to, memory cells. Figure 1 The material layer described herein is outside or different from the material layer described herein. Figure 1 The material layer described herein is a memory cell of the material layer (e.g., a thin dielectric material between the storage material and the access line).

[0025] Figure 2 The illustration may include, for example, examples, according to embodiments. Figure 1 The memory cell array 200 is part of the memory cell array 100. The memory cell array 200 is an example of a three-dimensional crosspoint memory structure (3D X Point). The memory cell array 200 includes multiple access lines 204, 206, which can be connected to... Figure 1 The access lines 104 and 106 described are the same or similar. Access lines 204 and 206 can be referred to as bit lines and word lines, respectively. Figure 2 In the embodiments described herein, bit lines (e.g., access lines 204) are orthogonal to word lines (e.g., access lines 206). Storage material 202 (e.g. Figure 1Storage material 202 is disposed between access lines 204 and 206. In some instances, storage material 202 may be a selectable storage material; in other instances, storage material 202 may be coupled in series to a selection device (not shown). In one embodiment, a "crossover point" is formed at the intersection of a bit line and a word line. Memory cells are generated from storage material 202 between the bit line and the word line, where the bit line intersects the word line. Storage material 202 may be a chalcogenide material, such as those described above. Figure 1 The storage material 102 is described. In one embodiment, the access lines 204, 206 are composed of one or more conductive materials, such as those described above. Figure 1 Access lines 104 and 106 are described. Although... Figure 2 The image shows a single memory cell hierarchy or layer, but the memory cell array 200 may contain multiple memory cell hierarchies or layers (e.g., in the z-direction). Generally, the intersection points define the addresses of the memory cells.

[0026] Figure 1 and 2 Examples of memory cell structures and arrays are illustrated. However, other memory cell structures and arrays can be used, where the memory cells exhibit a special electrical response, i.e., a special threshold voltage.

[0027] As described above, memory materials (e.g., phase change materials) can exhibit different resistivity values ​​depending on their phase, which are associated with different logic states. For example, the resistivity of a phase change material in an amorphous phase is higher than that of the same material in a crystalline phase. Different degrees of crystallinity are also possible, i.e., there is an intermediate resistivity value between one of the (fully) amorphous phases and one of the (fully) crystalline phases.

[0028] Ideally, all memory cells in a memory device should be characterized by the same (nominal) resistivity and therefore the same threshold voltage for the same logic state, where the threshold voltage is the voltage to be applied to the memory cell to induce its conduction current, i.e., the minimum voltage required to create a conduction path between terminals, as defined above. However, since different cells programmed to the same logic state actually exhibit different resistivity values ​​due to several factors (for example, such as variations in the electrical properties of the phase change material due to the number of read-write operations and / or manufacturing tolerances), each logic state is actually associated with a corresponding resistivity distribution (typically Gaussian), and therefore with a corresponding threshold voltage distribution.

[0029] To evaluate the logic state of a cell, a read operation is performed to assess the threshold voltage distribution to which the cell's threshold voltage belongs. For example, a read voltage can be applied to the cell and the logic state of the cell can be evaluated based on the presence or absence of a current in response to the read voltage, the presence or absence of which depends on the cell's threshold voltage. A cell is thresholded (e.g., becomes conductive) when a suitable voltage difference is applied between its two terminals; this voltage difference can be obtained in different ways, such as biasing one terminal (e.g., a word line terminal) to a negative voltage (e.g., a select voltage) and the other terminal (e.g., a bit line terminal) to a positive voltage (e.g., a read voltage). Other bias configurations can produce the same effect (e.g., both word line and bit line terminals are biased to a positive voltage, or the word line terminal is biased to a reference voltage (e.g., ground voltage), and the bit line terminal is biased to a positive voltage).

[0030] It is known that the cell threshold voltage for a given logic state decreases rapidly in the first set-reset loop, and stabilizes to an acceptable range after a certain number of application loops, such as... Figure 3 As shown in the image, Figure 3 It is a schematic graph illustrating the threshold voltage value relative to the number of set-reset cycles applied to the exemplary memory cell.

[0031] Typically, cell threshold voltage stabilization techniques involve performing a tuning process (i.e., applying tuning pulses to the cell) at a sufficient level to age the cell. More specifically, the tuning process cycles through the cells of an array to stabilize their threshold voltages to an acceptable range. According to known solutions, this tuning process is performed in test mode, where a test machine interacts with the memory device by providing the address of the page to be tuned. In this case, the test machine controls the memory device for the entire tuning time, which can be very long. This results in high cost, poor efficiency, and latency in performing cell threshold voltage stabilization.

[0032] As mentioned above Figure 3 The threshold voltage V of the unit is mentioned. TH The voltage decreases rapidly after the first set-reset cycle. After several set-reset cycles, the threshold voltage V is reduced. TH The variation is constrained to an acceptable range, making the threshold voltage variation manageable during the operation phase of the device. Typically, for feasibility reasons, pulses can be applied to the pages of the device according to a given sequence, such as every given number of nanoseconds. Furthermore, the number of tuning pulses required for a cell to stabilize its threshold voltage can be approximately several hundred, resulting in a very long tuning time. Therefore, a test machine is applied to the memory device for this entire long tuning time. This disadvantage can be overcome by the system and method of this disclosure.

[0033] According to this disclosure, the autonomous stabilization system and method for stabilizing the cell threshold voltage during the first set-reset cycle is implemented by a dedicated logic circuit portion of the memory device, such as... Figure 4 As shown in the figure. Advantageously, the memory device is capable of performing tuning and therefore can perform cell threshold voltage stabilization without the control or intervention of an external test machine.

[0034] refer to Figure 4 The memory device 400 includes a control logic or logic circuit section 401 capable of autonomously performing a tuning process. The logic circuit section 401 is capable of scanning all addresses of the memory device 400, applying tuning pulses to the addressed pages, and then repeating the full scan of the device an appropriate number of times to achieve proper stability of the cell threshold voltage. In an embodiment, during the autonomous tuning process, the memory device is set to a busy state and does not perform any other activities.

[0035] More specifically, such as Figure 4 As shown, the memory device 400 includes a plurality of memory cells 402, each memory cell being programmable to at least two logic states, each logic state corresponding to a corresponding threshold voltage being exhibited by the memory cell in response to an applied voltage. The memory cells 402 may be similar to... Figure 1 The units disclosed therein or Figure 2 The unit.

[0036] The logic circuitry 401 is operatively coupled to a plurality of memory cells 402 and configured to scan the memory addresses of the memory device 400 and generate tuning pulses to be applied to the addressed pages. In an embodiment, the tuning pulses are applied according to a given sequence comprising a predetermined number of pulses, as further explained below.

[0037] According to this disclosure, due to the presence of the logic circuit section 401, the memory device 400 is thus able to autonomously perform pre-tuning of the memory cells 402 to stabilize their threshold voltages without the need for an external tester. The logic circuit section 401 is able to provide the address of the page (or a subset of the address) to be tuned and generate appropriate tuning pulses to be applied to the addressed page.

[0038] For this purpose, the logic circuit section 401 includes a counter 403 configured to scan the memory addresses of the memory device 400. The memory device 400 also includes a management unit 404 operatively coupled to the counter 403.

[0039] The management unit 404 is configured to manage the operation of the logic circuit section 401, specifically to manage the generation of the tuning pulse and its application to the addressed page.

[0040] According to this disclosure, a predetermined pulse sequence is used to repeatedly generate and apply stabilizing pulses, wherein the applied pulse sequence includes a preset number of stabilizing pulses, the preset number being stored in a logic circuit section 401 of a memory device 400. Therefore, the logic circuit section 401 (besides scanning memory addresses and generating pulses to apply to addressed pages) is configured to generate appropriate commands to repeatedly apply the stabilizing pulses to the addressed pages an appropriate number of times.

[0041] In an embodiment, the stabilization pulses can be designed to accelerate the stabilization process, thereby reducing the total stabilization time. Furthermore, pulses can be allocated or supplied to pages of the memory device every specific number of nanoseconds (e.g., every 100 ns to 200 ns).

[0042] According to embodiments of this disclosure, logic circuitry 401 is configured to generate a stabilization pulse having a duration longer than the programming pulse used for the memory cell. In this case, the stabilization pulse is essentially an amplified reset pulse. In other words, according to this disclosure, a "stabilization pulse" is an initial pulse applied to the cell that may be longer than subsequent programming pulses, the purpose of which is to adjust the resistance to a stable value and thus adjust the threshold voltage of the cell.

[0043] Embodiments of this disclosure therefore provide an autonomous, low-cost, efficient, and reliable tuning system for stabilizing a cell threshold voltage during a first set-reset cycle without the need for a test machine to control the device throughout the tuning time. This autonomous tuning is designed to accelerate the tuning process, thereby reducing the total tuning time.

[0044] According to an embodiment of this disclosure, the logic circuit section 401 includes another counter 405 adapted to count the number of applied adjustment pulses. The management unit 404 of the logic circuit section 401 is then adapted to compare the counted pulses with a stored preset number, and to stop applying adjustment pulses when the number of applied pulses equals the preset number. In this embodiment, the preset number is stored in the management unit 404.

[0045] In one embodiment, the memory device 400 is configured to be in a busy state during the application of a stabilization pulse, preventing it from performing any other activities. In this case, only the circuit logic portion 401 of the memory device 400 is operated to perform autonomous stabilization.

[0046] In one embodiment, logic circuitry section 401 is configured to initiate a tuning process in response to receiving a specific command or a specific sequence of signals applied to its input / output pads, or also in response to a specific supply voltage that is different from the specification voltage (i.e., different from the nominal supply voltage). In one embodiment, the device only requires a supply voltage after initiating the autonomous tuning process.

[0047] For example, memory device 400 may receive a supply voltage at its voltage input 408, and then dedicated circuitry 409 is configured to evaluate whether the applied supply voltage is greater than the nominal supply voltage required for standard operation of the device. If the applied supply voltage is greater than the nominal supply voltage, then circuitry 409 generates an activation signal sent to logic circuitry section 401 to initiate a tuning process. In another embodiment, memory device 400 includes at least one dedicated pad 410 structured to receive commands for performing a tuning process, e.g., from a controller.

[0048] Typically, memory devices undergo various conditioning events during their manufacturing process. More specifically, conditioning processes can be performed at the wafer level, at the cell level after assembly and bonding, and possibly at the cell level during quality control testing. All of these conditioning events are usually performed by the manufacturer during the manufacturing steps of the device, such as during wafer-level testing / sorting.

[0049] Furthermore, according to this disclosure, the tuning process can also be performed autonomously at the cell level after soldering, i.e., it can also be performed autonomously at the client level. In any case, as mentioned above, the autonomous tuning process can be easily initiated by a specific command applied to the pads of the device or by a specific supply voltage. After initiating the autonomous tuning process according to this disclosure, the memory device is able to perform the autonomous tuning process without an external tester, only requiring the supply voltage to be delivered to the device. In fact, advantageously according to this disclosure, the memory device 400 includes a logic circuit portion 401 having been appropriately structured and configured to perform autonomous tuning.

[0050] To minimize the impact of the stabilization process on the last mentioned stabilization event (i.e., stabilization at the unit level after welding), a portion of the stabilization of the device can be performed in the foreground with direct influence on the customer, thereby reducing the direct impact on the customer.

[0051] More specifically, according to embodiments of this disclosure, the logic circuitry is configured to apply a preset number of adjustment pulses to a selected portion of the memory cells (i.e., a selected portion of the addressed pages) during a first adjustment process, and then apply the preset number of adjustment pulses to a selected second portion of the memory cells of the memory device during a second adjustment process. In some embodiments, the selected second portion of the memory cells includes all memory cells not in the selected portion (i.e., the second adjustment process is applied to the remaining addressed pages); in other embodiments, the device-wide adjustment process is completed in two or more steps (e.g., an additional adjustment process may exist after the first and second adjustment processes).

[0052] In other words, the calibration process can be performed on only a portion of the memory device 400. For example, in the case where the memory device 400 is used in a mobile application (e.g., it is embedded in a mobile phone), selected portions of the memory device include a portion of the source measurement unit (SMU) and a portion of the line monitoring unit (LMU). This minimizes the impact on the user. After the first calibration process in the foreground, calibration is completed in the background once the device begins to operate in the application, thus reducing testing costs and the impact on the user; the impact of background calibration on the user is negligible.

[0053] Furthermore, according to another embodiment of this disclosure, the logic circuitry can be configured to apply only a first number of adjustment pulses to all addressed pages of the memory device during a first adjustment process (i.e., in the foreground), and then apply subsequent adjustment pulses to all addressed pages of the memory device during a second adjustment process (i.e., in the background). For example, an additional second number of adjustment pulses can be applied during the second adjustment process; in some cases, the total number of (first plus second) pulses is equal to a preset number of adjustment pulses. In this case, only a specific number of pulses are applied at the first time so that the threshold voltage shifts close to, for example, Figure 3 The diagram shows the device's operating range, and then the remaining pulse is completed at the second moment.

[0054] like Figure 4 As shown, the memory device 400 includes a controller 406, which may include embedded firmware and is adapted to manage and control the operation of the overall memory device 400. In an embodiment, the controller is configured to generate access commands, and the memory controller 406 is coupled to a plurality of memory cells 402 and configured to apply a read voltage to the memory cells during a read operation to evaluate their logic state. According to an embodiment, the controller 406 is responsible for interfacing the memory device 400 with a host and programming the memory cells.

[0055] The memory device 400 may also include other components, such as a processor unit coupled to the controller 406, an antenna, a connection member (not shown) to the host device, and the like.

[0056] even though Figure 4 A controller 406 is shown that is separate from the logic circuit section 401. According to an embodiment, the logic circuit section 401 may be embedded in the controller 406.

[0057] Furthermore, according to embodiments of this disclosure, logic circuit portion 401 is coupled to decoder 407 via counter 403, decoder 407 allowing access to memory unit 402.

[0058] Therefore, access to memory cell 402 is controlled by decoder 407. Decoder 407 may include a row decoder that receives row addresses and powers the corresponding word lines according to the received row addresses. Similarly, decoder 407 may include a column decoder that receives column addresses and powers the corresponding set of bit lines accordingly.

[0059] According to an embodiment, decoder 407 receives addresses from counter 403, which in turn scans all addresses of memory device 400 via an address interface connected to a normal address path. When accessing memory cell 402, voltage can be applied using corresponding word lines and bit lines.

[0060] A tuning pulse is generated by the tuning pulse generation unit 411 of the logic circuit section 401. The generated tuning pulse is then applied to the corresponding addressed page provided by the counter 403 connected to the decoder 407.

[0061] As previously mentioned, according to the embodiments, the tuning pulse differs from the standard reset pulse (which is generated by the pulse generation unit 412 of the memory device) in that the former has a longer duration (approximately 100 ns) and can have a similar voltage. Therefore, in one embodiment, the memory device may include a timing unit 414 (which may be embedded in the logic control circuitry 401, although other architectures may also be possible) to provide appropriate timing for the generated pulse. The timing unit may be connected to the pulse generation unit.

[0062] The management unit 404 is therefore operatively connected to the stabilization pulse generation unit 411 to generate the stabilization pulse and apply the stabilization pulse to the memory unit 402. In one embodiment, the multiplexer 413 may receive the pulses generated by units 411 and 412 at its input and may be configured to deliver the pulses to the memory unit 402.

[0063] Figure 5 This is a high-order solution for an autonomously stabilizing electronic system 500' according to the present disclosure. System 500' includes a memory device 500, which in turn includes a memory cell array 502 and a logic circuit portion 501 operatively coupled to the memory cells 502; Figure 5 The memory device 500, logic circuit section 501, and memory cell 502 can respectively correspond to Figure 4 The memory device 400, the logic circuit section 401, and the memory unit 402.

[0064] Memory device 500 includes memory controller 506 (corresponding to Figure 4The memory controller 506 represents control logic that generates memory access commands, for example, in response to commands from the host 520. The memory controller 506 accesses memory cells 502. In one embodiment, the memory controller 506, operatively coupled to the host processor 521, may also be implemented in the host 520, particularly as part of the host processor 521, even though this disclosure is not limited to a particular architecture.

[0065] Multiple signal lines couple the memory controller 506 to the memory cell 502 and the logic circuit section 501. For example, such signal lines may include clock, command / address, write data (DQ), read DQ, and zero or more other signal lines. The memory controller 506 is thus operatively coupled to the memory section of the device via a suitable bus.

[0066] Memory cell 502 represents the memory resources of system 500'. In one embodiment, memory cell array 502 is managed as data rows and accessed via word lines (rows) and bit lines (individual bits within a row). In one embodiment, memory cell array 502 includes a 3D cross-dot array, for example... Figure 2 The memory cell array 200. The memory cell array 502 can be organized into individual memory channels, memory ranks, and memory banks. A channel is an independent control path to a memory location within a memory segment. A rank refers to a common location across multiple memory devices (e.g., the same row address in different devices). A bank refers to an array of memory locations within a memory device. In one embodiment, a memory bank is divided into sub-banks that share at least a portion of circuitry (e.g., drivers, signal lines, control logic). It should be understood that channels, ranks, banks, or other organization of memory locations, and combinations thereof, may overlap with physical resources. For example, the same physical memory location may be accessed through a specific channel that is also a specific bank belonging to a rank. Therefore, the organization of memory resources will be understood in an inclusive rather than exclusive manner.

[0067] In one embodiment, the memory controller 506 includes refresh (REF) logic 561. In one embodiment, refresh logic 561 indicates the location for a refresh and the type of refresh to be performed. Refresh logic 561 can trigger a self-refresh within the memory and issue an external refresh by sending a refresh command to trigger the execution of a refresh operation.

[0068] exist Figure 5In the exemplary embodiment illustrated, the memory controller 506 further includes error detection / correction circuitry 562. Error detection / correction circuitry 562 may include hardware logic to implement error correction codes (ECC) to detect errors occurring in data read from a portion of the memory. In one embodiment, error detection / correction circuitry 562 also corrects errors (based on the implemented ECC code up to a specific error rate). However, in other embodiments, error detection / correction circuitry 562 only detects but does not correct errors.

[0069] In the illustrated embodiment, the memory controller 506 includes command (CMD) logic 563, which represents logic OR circuitry used to generate commands to be sent to the logic circuitry section 501 and the memory cell 502. Obviously, other architectures may also be employed.

[0070] The memory device 500 is operatively coupled to the host device 520, for example, via a controller 506. The host device 520 represents a computing device according to any embodiment described herein and may be a laptop computer, desktop computer, server, game or entertainment control system, scanner, copier, printer, routing or switching device, embedded computing device, or other electronic device (e.g., a smartphone). In a preferred embodiment of this disclosure, the host device 520 is a mobile phone. The memory device 500 may also be embedded within the host device 520.

[0071] In one embodiment, system 500' includes an interface 530 coupled to processor 521, which may represent a high-speed or high-throughput interface for system components and / or graphics interface components requiring high-bandwidth connectivity. The graphics interface interfaces with the graphics components to provide a visual display to a user of system 500. In one embodiment, the graphics interface generates the display based on data stored in a memory device or based on operations performed by the processor, or both. System 500' may also include a network interface 540 communicatively coupled to a host or memory device, such as for connecting to other systems, and / or a battery coupled to provide power to said system. In other words, system 500' may further include a communication module configured to enable communication with other electronic systems, and / or an interface device configured to enable user access.

[0072] As mentioned above, in one embodiment, logic circuitry 501 is configured to apply a preset number of tuning pulses to a selected portion of the addressable pages of the memory device in the foreground during processor operation, and then apply the preset number of tuning pulses to a selected second portion of the addressable pages of the memory device in the background during processor operation. In some embodiments, the selected second portion of the memory cells includes all pages not in the first selected portion (i.e., the second tuning process is applied to the remaining addressable pages); in other embodiments, the tuning process for the entire device is completed in the background in two or more steps (e.g., several partial tuning processes may exist after the first and second tuning processes). These embodiments provide partial tuning of the device in the foreground, which helps to minimize the impact of the tuning process on the user.

[0073] For example, in mobile applications, selected portions of the memory device may include a portion of the source measurement unit (SMU) and a portion of the line monitoring unit (LMU).

[0074] In another embodiment, the logic circuitry is configured to apply a first number of tuning pulses to all addressed pages of the memory device in the foreground during processor operation, and then apply subsequent tuning pulses to all addressed pages of the memory device in the background during processor operation. For example, an additional second number of tuning pulses may be applied during a second tuning process; in some cases, the total number of pulses (first plus second) is equal to a preset number of tuning pulses. In this case, only a specific number of pulses are applied during the first tuning process, and the application of the remaining pulses is completed during the second tuning process (however, additional subsequent tuning processes are conceivable; for example, the complete process may be split into two or more sub-processes).

[0075] This disclosure also relates to a method for stabilizing threshold voltages of a plurality of memory cells included in a memory device, each memory cell being programmable into a logic state, each logic state corresponding to a respective threshold voltage exhibited by the memory cell in response to an applied voltage.

[0076] Figure 6 This is a flowchart illustrating the steps of method 600 according to this disclosure. For example... Figure 6 As shown, the method includes a first step 610 of scanning memory addresses associated with memory cells of the memory device, which is done using a counter within the memory device (e.g., Figure 4 The counter 403 is used to execute this.

[0077] The method then includes step 620, whereby a tuning pulse is generated by dedicated circuitry within the memory device and applied to the addressed pages of the memory device. The dedicated circuitry may be, for example... Figure 4The logic circuit section 401 or Figure 5 501.

[0078] Method 600 provides at step 630 the application of a stabilization pulse sequence to an addressable page of a memory device to obtain the desired stabilization of the cell threshold voltage without the need for an external tester.

[0079] More specifically, according to embodiments of the present disclosure, the application of the stabilization pulse sequence includes applying a predetermined number of stabilization pulses corresponding to the number required to stabilize the threshold voltage within an acceptable operating range (i.e., within a range where changes in the threshold voltage are negligible).

[0080] Next, the actual number of applied pulses is compared with the preset number of stabilizing pulses, so that once the number of applied pulses equals the preset threshold number, the application stops.

[0081] According to embodiments of this disclosure, the application of the stabilization pulse sequence includes a first step of applying a preset number of stabilization pulses to a selected portion of the addressed page during a first stabilization process, and a second step of applying the stabilization pulse sequence to a second selected portion of the addressed page during a second stabilization process.

[0082] In another embodiment, the method includes a first step of applying a first number of stabilization pulses to all addressed pages during a first stabilization process, and a second step of applying subsequent stabilization pulses to all addressed pages during a second stabilization process.

[0083] According to an embodiment, the tuning pulse has a longer pulse duration than the programming pulse used to program the memory cell.

[0084] As mentioned above, the device may undergo several stabilization events during its manufacturing and testing. For example, according to Figure 7 The method 700 described herein performs a first tuning process at the wafer level in a first step 710. Next, in step 720, the method provides a second tuning process at the cell level after assembling and bonding the memory device. Finally, in step 730, the method provides a third tuning process at the cell level after soldering the memory device. One or more, or even all of these tuning processes, are performed autonomously by dedicated logic circuitry of this disclosure.

[0085] This has the advantage that the tuning process can be performed independently by the customer, especially in the final step 730, outside of the manufacturer, and the possibility of performing partial tuning reduces the impact of tuning on the customer.

[0086] In summary, this document discloses an autonomous tuning system and method for stabilizing a cell threshold voltage during a first set-reset cycle (i.e., during a first state change cycle). The tuning process can be performed at the wafer level, at the cell level after assembly and bonding, and at the cell level during quality testing. Furthermore, advantageously according to this disclosure, the tuning process can be performed autonomously at the cell level after soldering, i.e., it can also be performed autonomously at the customer level outside the manufacturer. The autonomous tuning process can be initiated by a specific command or specific signal sequence applied to the input or output pads and / or also by a specific supply voltage greater than the nominal supply voltage. After initiating the autonomous tuning method, the only requirement for the device is to have a supply voltage.

[0087] More specifically, an exemplary memory device includes a plurality of memory cells, each memory cell being programmable to exhibit a logic state corresponding to a threshold voltage in response to an applied voltage, and includes logic circuitry operatively coupled to the plurality of memory cells, wherein the logic circuitry is configured to scan the memory address of the memory device and generate stabilization pulses to be applied, for example, according to a predetermined sequence, to the addressed pages of the memory device to stabilize the threshold voltage of the memory cells. An exemplary related electronic system and an exemplary related method are also disclosed.

[0088] In the foregoing detailed description, reference is made to the accompanying drawings, which form part of the description, and specific examples are illustrated therein. Throughout the drawings, similar numbers depict generally similar components. Other examples may be utilized and structural, logical, and / or electrical changes may be made without departing from the scope of this disclosure. Furthermore, it will be understood that the scale and relative dimensions of the elements provided in the figures are intended to illustrate embodiments of this disclosure and should not be considered limiting.

[0089] As used herein, “a,” “one,” or “several” can refer to one or more such things. “Several” means two or more. As used herein, the term “coupling” can include non-electrical coupling, direct coupling and / or direct connection (e.g., through direct physical contact) or indirect coupling and / or connection with an intermediate element. The term coupling can further include two or more elements that cooperate or interact with each other (e.g., as in a causal relationship).

[0090] Although specific examples have been illustrated and described herein, those skilled in the art will understand that arrangements calculated to achieve the same results can replace the specific embodiments shown. This disclosure is intended to cover adaptations or variations of one or more embodiments of this disclosure. Therefore, it should be understood that the above description has been presented in an illustrative and non-limiting manner. Descriptions of well-known components and processing techniques have been omitted to avoid unnecessarily obscuring the embodiments herein. The examples used herein are intended only to facilitate an understanding of how the embodiments herein can be practiced and to further enable those skilled in the art to practice the embodiments herein. Accordingly, the examples should not be construed as limiting the scope of the embodiments herein. The scope of one or more examples of this disclosure should be determined by reference to the appended claims and the full scope of their equivalents.

Claims

1. A memory device comprising: - Multiple memory cells, each of which can be programmed to exhibit a logic state corresponding to a threshold voltage in response to an applied voltage; and - A logic circuit section, which is operatively coupled to the plurality of memory cells. The logic circuit section is configured to: - Scan multiple memory addresses of the memory device; and - Generate multiple stabilization pulses to be applied to multiple addressed pages of the memory device to stabilize the threshold voltage of the multiple memory cells.

2. The memory device of claim 1, wherein the logic circuitry includes a counter configured to scan the plurality of memory addresses of the memory device, the counter being operatively coupled to a management unit of the memory device to apply the plurality of tuning pulses to the plurality of addressed pages.

3. The memory device of claim 1, wherein the logic circuit portion is configured such that a sequence comprising a preset number of tuning pulses is applied to the plurality of memory cells.

4. The memory device of claim 3, wherein the logic circuitry includes another counter adapted to count the number of applied stabilization pulses, and wherein the logic circuitry is further configured to compare the number of applied stabilization pulses with the preset number.

5. The memory device of claim 1, wherein the logic circuit portion is configured to generate a plurality of tuning pulses having a duration longer than that of the programming pulses for the plurality of memory cells.

6. The memory device of claim 1, wherein the logic circuitry is configured to apply a preset number of adjustment pulses to a selected first portion of the plurality of addressable pages of the memory device during a first adjustment process, and then apply the preset number of adjustment pulses to a selected second portion of the plurality of addressable pages of the memory device during a second adjustment process.

7. The memory device of claim 1, wherein the logic circuitry is configured to apply a first plurality of stabilization pulses to all of the plurality of addressed pages of the memory device during a first stabilization process, and then apply a subsequent plurality of stabilization pulses to all of the plurality of addressed pages of the memory device during a second stabilization process.

8. The memory device of claim 1, further comprising a controller configured to generate access commands, the controller being coupled to the plurality of memory cells and configured to apply a read voltage to the plurality of memory cells during a read operation to evaluate their logic state.

9. The memory device of claim 8, wherein the logic circuitry portion is embedded in the controller and operatively coupled to the decoder of the memory device.

10. The memory device of claim 1, wherein the memory device comprises a 3D XPoint memory.

11. The memory device of claim 1, wherein the logic circuitry portion is configured to scan the plurality of memory addresses and generate the plurality of tuning pulses in response to receiving a specific command or specific signal sequence applied to the input / output pads of the device and / or in response to receiving a specific supply voltage different from the nominal supply voltage.

12. The memory device of claim 1, wherein the memory device is configured to be in a busy state during the application of the plurality of tuning pulses.

13. An electronic system comprising: -The host device, which includes a processor module; - A memory device operatively coupled to the host device; and -The management unit of the memory device, The memory device includes: - Multiple memory cells, each of which can be programmed to exhibit a logic state corresponding to a threshold voltage in response to an applied voltage; and - A logic circuit section, which is operatively coupled to the plurality of memory cells. The logic circuit section is configured to: - Scan multiple memory addresses of the memory device; and - Generate multiple stabilization pulses to be applied to multiple addressed pages of the memory device to stabilize the threshold voltage of the multiple memory cells.

14. The electronic system of claim 13, wherein the logic circuit portion is configured to apply a predetermined number of tuning pulses to selected portions of the plurality of addressable pages of the memory device in the foreground during operation of the processor, and then apply the predetermined number of tuning pulses to selected second portions of the plurality of addressable pages of the memory device in the background during operation of the processor.

15. The electronic system of claim 14, wherein the host is a mobile phone, and wherein the selected portion of the memory device includes a portion of a source measurement unit (SMU) and a portion of a line monitoring unit (LMU).

16. The electronic system of claim 13, wherein the logic circuit portion is configured to apply a first number of tuning pulses to all of the plurality of addressed pages of the memory device in the foreground during operation of the processor, and then apply a subsequent plurality of tuning pulses to all of the plurality of addressed pages of the memory device in the background during operation of the processor.

17. The electronic system of claim 13, further comprising a counter configured to scan the plurality of memory addresses of the memory device, the counter being operatively coupled to the management unit of the memory device to apply the plurality of tuning pulses to the plurality of addressed pages.

18. The electronic system of claim 13, further comprising a controller configured to generate access commands, the controller being operatively connected to the processor module.

19. The electronic system of claim 13, wherein the management unit of the logic circuit portion is operatively connected to the stabilization pulse generation unit to generate the plurality of stabilization pulses and apply the plurality of stabilization pulses to the plurality of memory cells of the memory device.

20. The electronic system of claim 13, wherein the logic circuitry is configured to scan the plurality of memory addresses and generate the plurality of tuning pulses after receiving a specific command or a specific signal sequence applied to the input / output pads of the system and / or after receiving a specific supply voltage different from the nominal supply voltage.

21. The electronic system of claim 13, further comprising: A communication module configured to communicate with other electronic systems; and / or an interface device configured to enable user interfacing.

22. A method for stabilizing a threshold voltage of a plurality of memory cells included in a memory device, each memory cell being programmable to exhibit a logic state corresponding to the threshold voltage in response to an applied voltage, the method comprising the steps of: - Scan multiple memory addresses of the memory device, wherein the scan is performed by a logic circuit portion within the memory device; - A tuning pulse is generated within the logic circuit portion of the memory device to be applied to a plurality of addressable pages of the memory device; and - Apply a stabilization pulse sequence to the plurality of addressed pages of the memory device.

23. The method of claim 22, wherein applying the stabilization pulse sequence comprises applying a preset number of stabilization pulses corresponding to the number required to stabilize the threshold voltage, the method further comprising the step of comparing the actual number of applied pulses with the preset number of stabilization pulses.

24. The method of claim 22, wherein applying the stabilization pulse sequence involves applying a pulse having a pulse duration longer than that of the programming pulse used to program the unit.

25. The method of claim 22, wherein a busy state is set during the application of the stabilization pulse and no other operations are performed.

26. The method of claim 22, comprising a first step of applying the stabilization pulse sequence to a selected portion of the addressed page during a first stabilization process, and a second step of applying the stabilization pulse sequence to a second selected portion of the addressed page during a second stabilization process.

27. The method of claim 22, comprising a first step of applying a first number of the stabilization pulses to all the addressed pages during a first stabilization process, and a second step of applying a subsequent plurality of stabilization pulses to all the addressed pages during a second stabilization process.

28. The method of claim 22, wherein the step is performed after receiving a specific command or a specific signal sequence and / or after receiving a specific supply voltage different from the nominal supply voltage.

29. A method for operating a memory device, comprising the steps of: - Perform the first stabilization process at the chip level; - After assembling and bonding the memory device, a second tuning process is performed at the cell level; and - After soldering the memory device, a third tuning process is performed at the cell level. At least one of the stabilization processes is performed autonomously according to claim 22.

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