Solid-state imaging device and imaging device having combined dynamic vision sensor and imaging function

Abstract

This disclosure provides an imaging apparatus having a plurality of image sensing pixels and a plurality of event detection pixels. Each image sensing pixel includes a photoelectric conversion element and an imaging signal generation and readout circuit. The image sensing readout circuit can be shared by the plurality of photoelectric conversion elements. Each event detection pixel includes a photoelectric conversion element and an event detection readout circuit. The event detection readout circuit can be shared by the plurality of photoelectric conversion elements. Furthermore, the photoelectric conversion element of the event detection pixel can be selectively connected to the shared imaging signal generation and readout circuit. The number of image sensing pixels is greater than the number of event detection pixels. Furthermore, the area of ​​the photoelectric conversion element of the event detection pixel can be greater than the area of ​​the photoelectric conversion element of the image sensing pixel.

Description

Technical Field

[0001] This disclosure relates to an imaging device having both a dynamic vision sensor and imaging capabilities. Background Technology

[0002] In related technologies, synchronous solid-state imaging devices that capture image data synchronously with a synchronization signal such as a vertical synchronization signal have been used in imaging devices. In typical synchronous solid-state imaging devices, it is difficult to acquire image data for each cycle of the synchronization signal (e.g., every 1 / 60th of a second), thus hindering the application of relatively high-speed processing in fields requiring high-speed (e.g., real-time) processing, such as autonomous vehicles and robots. In this regard, an asynchronous solid-state imaging device has been proposed, in which a detection circuit is provided for each pixel to detect in real time when the amount of light received exceeds a threshold as an address event. This asynchronous solid-state imaging device that detects address events for each pixel is also known as a dynamic vision sensor (DVS). Summary of the Invention

[0003] [Technical Issues]

[0004] Various methods can be used to implement sensors that combine DVS and conventional frame-based imaging. These include devices characterized by time-based readout using additional photodiodes, known as asynchronous time-based image sensor (ATIS) systems. However, because ATIS systems require two photodiodes per pixel to provide both image sensor and DVS signals, their resolution and image quality decrease compared to configurations that do not require additional photodiodes. Other devices are characterized by pixels using a shared photodiode to provide both image sensor signals and dynamic vision sensor (DVS) event signals, known as dynamic and active pixel vision sensor (DAVIS) systems. However, the sensitivity of DAVIS systems is reduced because interference between image and event detection functions needs to be suppressed, as these functions are not well isolated. Furthermore, the difficulty in readout of both DVS and active image sensor signals reduces the dynamic range of DAVIS sensors.

[0005] Therefore, this disclosure provides a solid-state imaging device and an imaging apparatus that, compared with other configurations, can provide both imaging and event detection functions and has improved event detection capability and light receiving efficiency.

[0006] [Solution to the problem]

[0007] According to embodiments and aspects of this disclosure, an imaging apparatus is provided comprising a plurality of photoelectric conversion regions or pixels (also referred to herein as unit pixels) configured in a pixel array. At least some pixels are configured as event detection pixels, while others are configured as image sensing or capture pixels. Typically, the event detection pixels are distributed among the image capture pixels within the pixel array. In operation, the detection of an event by one or more event detection pixels triggers the operation of the image sensing pixels.

[0008] Each pixel includes a single photoelectric conversion region and an associated readout circuit. More specifically, each image sensing pixel includes a photoelectric conversion region and a first readout circuit, also referred to herein as an imaging generation unit or circuit. Each event detection pixel includes a photoelectric conversion region and a second readout circuit, also referred to herein as an event detection circuit.

[0009] According to at least some embodiments and aspects of this disclosure, each event detection pixel occupies an area of ​​the pixel array larger than any image sensing pixel. As an example, but not limited to, each event detection pixel may occupy an area four times the area of ​​each image sensing pixel. According to other embodiments and aspects of this disclosure, each event detection pixel may occupy an area equal to the area of ​​each image sensing pixel. According to yet another embodiment of this disclosure, different ratios of image sensing pixels to event detection pixels may be included within the pixel array. As an example, but not limited to, this ratio may be 3:1, 4:1, 12:1, 15:1, 32:1, or 35:1. According to at least some embodiments and aspects of this disclosure, any ratio of the areas of the photoelectric conversion regions of each event detection pixel occupies a larger area in the plane of the pixel array.

[0010] According to another embodiment and aspect of this disclosure, an isolation structure is provided to isolate at least some unit pixels from other unit pixels. For example, a full-thickness dielectric trench isolation (RFTI) isolation structure may be formed around each event detection pixel. As another example, a rear deep trench isolation (RDTI) isolation structure may be formed around at least a portion of an image sensing pixel to provide isolation between adjacent image sensing pixels. According to another embodiment and aspect of this disclosure, at least some readout circuit elements may be shared by multiple photoelectric conversion regions. For example, a group of image sensing pixels may share readout circuit elements. As an example, but not limited to, the group of image sensing pixels may be in the form of a Bayer array. According to another embodiment of this disclosure, some or all of the event detection pixels may additionally act as image sensing pixels. Furthermore, in this embodiment, image sensor readout circuit elements and event detection circuit elements within a group of event detection pixels may be shared. As an example, but not limited to, such a group of event detection pixels may be in the form of a Bayer array.

[0011] This disclosure provides an imaging device with dynamic visual sensing and imaging capabilities that can improve light receiving efficiency. Attached Figure Description

[0012] Figure 1 This is a block diagram illustrating a schematic configuration example of a solid-state imaging apparatus according to an embodiment of the present disclosure.

[0013] Figure 2 This is a diagram illustrating an example of a stacked structure of a solid-state imaging device according to an embodiment of the present disclosure.

[0014] Figure 3 This is a block diagram illustrating a functional configuration example of a solid-state imaging device according to an embodiment of the present disclosure.

[0015] Figure 4 This is a schematic diagram illustrating an example of a unit pixel array according to an embodiment of the present disclosure in the case of using a Bayer array in a color filter array.

[0016] Figure 5A This is a circuit diagram illustrating a schematic configuration example of a unit pixel having combined event detection and image sensor functions according to an embodiment of the present disclosure.

[0017] Figure 5B This is a circuit diagram illustrating a schematic configuration example of an image sensing pixel group according to an embodiment of the present disclosure.

[0018] Figure 5C This is a circuit diagram illustrating a schematic configuration example of an event detection pixel according to an embodiment of the present disclosure.

[0019] Figure 6 This is a block diagram illustrating a schematic configuration example of an address event detection unit according to an embodiment of the present disclosure.

[0020] Figure 7 This is a circuit diagram illustrating a schematic configuration example of a subtractor and a quantizer according to an embodiment of the present disclosure.

[0021] Figure 8 This is a block diagram illustrating a schematic configuration example of a column ADC according to an embodiment of the present disclosure.

[0022] Figure 9A This is a timing diagram illustrating an operational example of a solid-state imaging apparatus according to an embodiment of the present disclosure.

[0023] Figure 9B This is a timing diagram illustrating an operational example of a solid-state imaging apparatus according to other embodiments of the present disclosure.

[0024] Figure 10 This is a flowchart illustrating an operational example of a solid-state imaging apparatus according to an embodiment of the present disclosure.

[0025] Figure 11A It is a plan view of a portion of a pixel array that includes pixel groups constructed as in the first exemplary embodiment.

[0026] Figure 11B It is a plan view that includes a portion of another pixel array comprising pixel groups constructed as in the first exemplary embodiment.

[0027] Figure 11C It is a plan view that includes a portion of another pixel array comprising pixel groups constructed as in the first exemplary embodiment.

[0028] Figure 12A It is a cross-sectional view of a portion of a pixel array that includes pixel groups constructed as in the first exemplary embodiment.

[0029] Figure 12B It is a cross-sectional view of a portion of another pixel array that includes pixel groups constructed as in the first exemplary embodiment.

[0030] Figure 13 It is a plan view of the composition of the image sensing pixel group according to the first exemplary embodiment.

[0031] Figure 14 It is a planar diagram of the composition of event detection pixels as constructed as in the first exemplary embodiment.

[0032] Figure 15 This is a circuit diagram illustrating a schematic configuration example of an event detection and image sensing pixel group according to other embodiments of the present disclosure.

[0033] Figure 16A It is a plan view of a pixel array that includes pixel groups constructed as in the second exemplary embodiment.

[0034] Figure 16B It is a plan view that includes a portion of another pixel array comprising pixel groups constructed as in the second exemplary embodiment.

[0035] Figure 16C It is a plan view that includes a portion of another pixel array comprising pixel groups constructed as in the second exemplary embodiment.

[0036] Figure 17A This is a cross-sectional view of a portion of a pixel array according to a second exemplary embodiment of the present disclosure.

[0037] Figure 17B This is a cross-sectional view of a portion of another pixel array according to a second exemplary embodiment of this disclosure.

[0038] Figure 18It is a plan view of the composition of the image sensing pixel group according to the second exemplary embodiment.

[0039] Figure 19 It is a plan view of the composition of event detection and image sensing pixel groups according to the combination of the second exemplary embodiment.

[0040] Figure 20 This is a circuit diagram illustrating a schematic configuration example of an event detection and image sensing pixel combination according to an embodiment of the present disclosure.

[0041] Figure 21A It is a plan view of a pixel array that includes pixel groups constructed as in the third exemplary embodiment.

[0042] Figure 21B It is a plan view that includes a portion of another pixel array comprising pixel groups constructed as in the third exemplary embodiment.

[0043] Figure 21C It is a plan view that includes a portion of another pixel array comprising pixel groups constructed as in the third exemplary embodiment.

[0044] Figure 22A It is a cross-sectional view of a portion of a pixel array according to a third exemplary embodiment.

[0045] Figure 22B It is a cross-sectional view of a portion of another pixel array according to a third exemplary embodiment.

[0046] Figure 23 It is a plan view of the composition of the image sensing pixel group according to the third exemplary embodiment.

[0047] Figure 24 It is a planar diagram of event detection and image sensing pixels according to a combination of the third exemplary embodiment.

[0048] Figure 25 This is a circuit diagram illustrating a schematic configuration example of an image sensing pixel group according to an embodiment of the present disclosure.

[0049] Figure 26A It is a plan view of a portion of a pixel array that includes pixel groups constructed as in the fourth exemplary embodiment.

[0050] Figure 26B It is a plan view that includes a portion of another pixel array comprising pixel groups constructed as in the fourth exemplary embodiment.

[0051] Figure 26C It is a plan view that includes a portion of another pixel array comprising pixel groups constructed as in the fourth exemplary embodiment.

[0052] Figure 27A This is a cross-sectional view of a portion of a pixel array according to a fourth exemplary embodiment of the present disclosure.

[0053] Figure 27B This is a cross-sectional view of a portion of another pixel array according to a fourth exemplary embodiment of this disclosure.

[0054] Figure 28A It is a plan view of a portion of a pixel array that includes pixel groups constructed as in the fifth exemplary embodiment.

[0055] Figure 28B It is a plan view that includes a portion of another pixel array comprising pixel groups constructed as in the fifth exemplary embodiment.

[0056] Figure 29A This is a cross-sectional view of a portion of a pixel array according to a fifth exemplary embodiment.

[0057] Figure 29B It is a cross-sectional view of a portion of another pixel array according to the fifth exemplary embodiment.

[0058] Figure 30 It is a plan view of the composition of the image sensing pixel group according to the fifth exemplary embodiment.

[0059] Figure 31 This is a block diagram illustrating an example of the schematic configuration of a vehicle control system.

[0060] Figure 32 This is a diagram showing an example of the installation location of the vehicle exterior information detection unit and the imaging unit. Detailed Implementation

[0061] In the following, embodiments of the present disclosure will be described in detail based on the accompanying drawings. Furthermore, in the following embodiments, the same reference numerals are used for the same parts, and repeated descriptions thereof are omitted.

[0062] A typical dynamic vision sensor (DVS) employs a so-called event-driven approach, in which the presence or absence of an address event ignition is detected for each unit pixel, and the pixel signal is read out from the unit pixel in which the address event ignition is detected.

[0063] Furthermore, in this specification, a unit pixel refers to a pixel comprising a photoelectric conversion element (also known as a "photoreceiving element") or the smallest unit of a unit pixel, and as an example, may correspond to each point in the image data read from the image sensor. Additionally, an address event represents an event occurring for each address that can be assigned to each of a plurality of unit pixels arranged in a two-dimensional lattice. The event detection sensor responds asynchronously to changes in intensity. Intensity changes are correlated with changes in photocurrent, and if such a change exceeds a constant threshold, it can be detected as an event.

[0064] Figure 1 This is a block diagram illustrating a schematic configuration example of an imaging apparatus according to at least some embodiments of the present disclosure. For example... Figure 1 As shown, for example, imaging device 100 includes imaging lens 110, solid-state imaging device 200, recording unit 120, and control unit 130. As an example, imaging device 100 may be configured as a camera mounted in an industrial robot, a vehicle-mounted camera, or part thereof, or as part of or connected to other equipment or instruments.

[0065] The imaging lens 110 may include an optical system that guides (e.g., converges) incident light and images the incident light onto the light-receiving surface of the solid-state imaging device 200 (also referred to herein as imaging device 200). The light-receiving surface is the surface of a substrate on which photoelectric conversion elements of the solid-state imaging device 200 are disposed. The solid-state imaging device 200 performs photoelectric conversion on the incident light to generate image data. In addition, the solid-state imaging device 200 may perform predetermined signal processing on the generated image data, such as noise removal and white balance adjustment. The result obtained by the signal processing and a detection signal indicating the presence or absence of an address event ignition are output to the recording unit 120 via signal line 209. Furthermore, a method for generating the detection signal indicating the presence or absence of an address event ignition will be described later.

[0066] For example, the recording unit 120 is composed of flash memory, dynamic random access memory (DRAM), static random access memory (SRAM), etc., and records data input from the solid-state imaging device 200.

[0067] For example, the control unit 130 is composed of a central processing unit (CPU) and outputs various instructions through signal line 139 to control various units in the imaging device 100, such as the solid-state imaging device 200.

[0068] Next, the configuration example of the solid-state imaging device 200 will be described in detail with reference to the accompanying drawings.

[0069] Figure 2 This is a diagram illustrating an example of a stacked structure of a solid-state imaging device 200 according to at least some embodiments of the present disclosure. Figure 2 As shown, the solid-state imaging device 200 can have a structure in which a light-receiving chip 201 and a logic chip 202 are vertically stacked. In the bonding of the light-receiving chip 201 and the logic chip 202, for example, a so-called direct bonding can be used, in which the bonding surfaces of the chips are planarized and the chips are stacked using inter-electron forces. However, it is not limited to this; for example, a so-called Cu-Cu bonding, bump bonding, etc., in which copper (Cu) electrode pads formed on the bonding surfaces are bonded can also be used.

[0070] Alternatively, for example, the optical receiver chip 201 and the logic chip 202 are electrically connected to each other via a connection such as a through-silicon via (TSV) that penetrates the semiconductor substrate. In TSV-based connections, for example, a so-called dual TSV method can be used, in which two TSVs, including a TSV formed in the optical receiver chip 201 and a TSV formed from the optical receiver chip 201 to the logic chip 202, are connected to each other on the outer surface of the chip; or a so-called shared TSV method, in which the optical receiver chip 201 and the logic chip 202 are connected via a TSV penetrating both chips.

[0071] However, when Cu-Cu bonding or bump bonding is used in the bonding of the optical receiver chip 201 and the logic chip 202, the optical receiver chip 201 and the logic chip 202 are electrically connected to each other through Cu-Cu connectors or bump connectors.

[0072] Figure 3 This is a block diagram illustrating functional configuration examples of a solid-state imaging device according to at least some embodiments of the present disclosure. For example... Figure 3 As shown, the solid-state imaging device 200 includes a driving circuit 211, a signal processing unit 212, an arbitrator 213, a column ADC 220, and a pixel array 300.

[0073] In this document, the unit cells or pixels 310, also referred to as pixels 310, are arranged in a two-dimensional lattice in the pixel array 300. Details of the unit pixels 310 will be described later. For example, each unit pixel 310 includes a photoelectric conversion element such as a photodiode and circuitry (hereinafter referred to as pixel circuitry) that generates a pixel signal corresponding to the amount of charge generated in the photoelectric conversion element. Furthermore, as discussed in more detail herein, the pixel circuitry may include either or both of a first or imaging signal generation circuitry and a second or address event detection readout circuitry. Each photoelectric conversion element may be associated with a separate pixel circuitry, or multiple photoelectric conversion elements may be associated with a shared pixel circuitry.

[0074] Multiple unit pixels 310 are arranged in a two-dimensional grid in the pixel array 300. The multiple unit pixels 310 can be grouped into multiple pixel blocks or groups, each comprising a predetermined number of unit pixels. In the following text, the set of unit pixels arranged in the horizontal direction is referred to as a "row", and the set of unit pixels arranged in a direction orthogonal to the row is referred to as a "column".

[0075] Each unit pixel 310 generates a charge corresponding to the amount of light received at its respective photoelectric conversion element. Furthermore, at least some of the unit pixels 310 can be operated to detect the presence or absence of an address event ignition based on whether the value of the current (hereinafter referred to as photocurrent) generated by the charge produced in the photoelectric conversion element, or the amount of change thereof, exceeds a predetermined threshold. Additionally, when an address event is ignited, a request for a pixel signal to read the voltage value corresponding to the amount of light received by the photoelectric conversion element is output to the arbitrator 213.

[0076] The driving circuit 211 drives each unit pixel 310 and allows each unit pixel 310 to output pixel signals to the column ADC 220.

[0077] Arbitrator 213 arbitrates requests from unit pixel 310 and sends a predetermined response to the requesting unit pixel 310 based on the arbitration result. Unit pixel 310 receiving the response provides a detection signal (hereinafter referred to as "address event detection signal") indicating the presence or absence of address event ignition to drive circuit 211 and signal processing unit 212.

[0078] For each unit pixel (310 columns), the column ADC 220 converts the analog pixel signal from that column into a digital signal. Furthermore, the column ADC 220 supplies the generated digital signal to the signal processing unit 212.

[0079] The signal processing unit 212 performs predetermined signal processing on the digital signal transmitted from the column ADC 220, such as correlated double sampling (CDS) processing (noise removal) and white balance adjustment. Additionally, the signal processing unit 212 provides the signal processing results and address event detection signals to the recording unit 120 via signal line 209.

[0080] The unit pixels 310 within the pixel array unit 300 can be arranged in the pixel group 314. For example, in Figure 3In the configuration shown, the pixel array unit 300 is composed of pixel groups 314, which include a set of unit pixels 310 that receive the wavelength components required for color reconstruction. For example, in the case of color reconstruction based on the three primary colors of RGB, in the pixel array unit 300, unit pixels 310 that receive red (R) light, unit pixels 310 that receive green (G) light, and unit pixels 310 that receive blue (B) light are configured into group 314a according to a predetermined color filter array.

[0081] Examples of color filter array configurations include various arrays or pixel groups, such as a 2×2 pixel Bayer array, a 3×3 pixel color filter array used in X-Trans (registered trademark) CMOS sensors (hereinafter also referred to as an "X-Trans (registered trademark) type array"), a 4×4 pixel quad Bayer array (also referred to as a "Quadra array"), and a 4×4 pixel color filter in which a white RGB color filter is combined into a Bayer array (hereinafter also referred to as a "white RGB array"), etc. Additionally, as discussed in more detail elsewhere in this document, event detection pixels can be distributed or included within the pixel array 300. Similarly, as discussed in more detail elsewhere in this document, event detection pixels can be configured as dedicated event detection pixels that perform only event detection functions, or as event detection and image sensing pixels that perform a combination of both event detection and image sensor functions.

[0082] Figure 4 This is a schematic diagram illustrating an example array of unit pixels 310 in the case of using pixel group 314, wherein the arrangement of unit pixels 310 and associated color filters in the color filter array is configured to form multiple Bayer arrays 310A. Figure 4 As shown, when a Bayer array is used as the color filter array, in the pixel array 300, a basic pattern 310A comprising a total of four unit pixels 310 of 2×2 pixels is repeated in the column and row directions. For example, the basic pattern 310A consists of unit pixels 310R including a red (R) color filter 401, unit pixels 310Gr including a green (Gr) color filter 401, unit pixels 310Gb including a green (Gb) color filter 401, and unit pixels 310B including a blue (B) color filter 401.

[0083] Next, we will explain an example of the composition of a unit pixel 310. Figure 5A This is a circuit diagram illustrating a schematic configuration example of a unit pixel 310 according to at least some embodiments of the present disclosure, particularly according to an embodiment of pixel 310 including an event detection (DVS) and image sensor (IS) pixel 501 configured to perform a combination or shared function of both event detection and image sensor. Figure 5AAs shown, the unit pixel 310 includes, for example, a pixel imaging signal generation unit (or readout circuit) 320, a light receiving unit 330, and an address event detection unit (or readout circuit) 400. According to at least one exemplary embodiment, the readout circuit 400 is configured to control the readout circuit 320 based on the charge generated by the photoelectric conversion element (or photoelectric conversion region) 333. Furthermore, Figure 5A The logic circuit 210 in the middle includes, for example, Figure 3 The logic circuits of the drive circuit 211, signal processing unit 212 and arbitrator 213 are included.

[0084] For example, the light receiving unit 330 includes a first or imaging transmission transistor or gate (first transistor) 331, a second or address event detection transmission transistor or gate (second transistor) 332, and a photoelectric conversion element 333. A first transmission signal TG1 sent from the driving circuit 211 is selectively supplied to the gate of the first transmission transistor 331 of the light receiving unit 330, and a second transmission signal TG2 sent from the driving circuit 211 is selectively supplied to the gate of the second transmission transistor 332. The output of the first transmission transistor 331 of the light receiving unit 330 is connected to the pixel imaging signal generation unit 320, and the output of the second transmission transistor 332 is connected to the address event detection unit 400.

[0085] For example, the pixel imaging signal generation unit 320 includes a reset transistor (third transistor) 321, an amplification transistor (fourth transistor) 322, a selection transistor (fifth transistor) 323, and a floating diffusion layer (FD) 324.

[0086] According to at least some embodiments of this disclosure, the first transmission transistor 331 and the second transmission transistor 332 of the light receiving unit 330 are configured, for example, using an N-type metal-oxide-semiconductor (MOS) transistor (hereinafter simply referred to as "NMOS transistor"). Similarly, the reset transistor 321, the amplification transistor 322, and the selection transistor 323 of the pixel imaging signal generation unit 320 are each configured, for example, using an NMOS transistor.

[0087] For example, the address event detection unit 400 includes a current-to-voltage conversion unit 410 and a subtractor 430. However, the address event detection unit 400 also includes a buffer, a quantizer, and a transmission unit. These will be explained in the following description using... Figure 6 Details of the address event detection unit 400 will be explained later.

[0088] In the illustrated configuration, the photoelectric conversion element 333 of the light receiving unit 330 performs photoelectric conversion on the incident light to generate charge. The first transmission transistor 331 transmits the charge generated in the photoelectric conversion element 333 to the floating diffusion layer 324 according to the first transmission signal TG1. The second transmission transistor 332 supplies an electrical signal (photocurrent) based on the charge generated in the photoelectric conversion element 333 to the address event detection unit 400 according to the second control signal TG2.

[0089] When the control unit 130 issues an instruction for image sensing, the drive circuit 211 in the logic circuit 210 outputs a control signal TG1 to set the first transmission transistor 331 of the light receiving unit 330 in the pixel array 300 to the on state. With this configuration, the photocurrent generated in the photoelectric conversion element 333 of the light receiving unit 330 is supplied to the pixel imaging signal generation and readout circuit 320 through the first transmission transistor 331. More specifically, the floating diffusion layer 324 accumulates the charge transferred from the photoelectric conversion element 333 through the first transmission transistor 331. The reset transistor 321 discharges (initializes) the charge accumulated in the floating diffusion layer 324 according to the reset signal transmitted from the drive circuit 211. The amplifying transistor 322 allows a pixel signal with a voltage value corresponding to the amount of charge accumulated in the floating diffusion layer 324 to appear in the vertical signal line VSL. The selection transistor 323 switches the connection between the amplifying transistor 322 and the vertical signal line VSL according to the selection signal SEL transmitted from the drive circuit 211. In addition, the analog pixel signals appearing in the vertical signal line VSL are read out by the column ADC 220 and converted into digital pixel signals.

[0090] When the control unit 130 issues a command to initiate address event detection, the drive circuit 211 in the logic circuit 210 outputs a control signal to set the second transmission transistor 332 of the light receiving unit 330 in the pixel array unit 300 to the on state. With this configuration, the photocurrent generated in the photoelectric conversion element 333 of the light receiving unit 330 is supplied to the address event detection unit 400 of each unit pixel 310 through the second transmission transistor 332.

[0091] When an address event ignition occurs based on photocurrent detection from the light receiving unit 330, the address event detection unit 400 of each unit pixel 310 outputs a request to the arbitrator 213. In response, the arbitrator 213 arbitrates the requests sent from each unit pixel 310 and sends a predetermined response to the requesting unit pixel 310 based on the arbitration result. The unit pixel 310 receiving the response supplies a detection signal (hereinafter referred to as the "address event detection signal") indicating the presence or absence of the address event ignition to the driving circuit 211 and signal processing unit 212 in the logic circuit 210.

[0092] The driving circuit 211 can also set the second transmission transistor 332 in the unit pixel 310, which serves as the supply source for the address event detection signal, to an off state. With this configuration, the supply of photocurrent from the light receiving unit 330 to the address event detection unit 400 in the unit pixel 310 is stopped.

[0093] Next, the driving circuit 211 sets the first transmission transistor 331 in the light receiving unit 330 of the unit pixel 310 to the on state via the transmission signal TG1. With this configuration, the charge generated in the photoelectric conversion element 333 of the light receiving unit 330 is transferred to the floating diffusion layer 324 through the first transmission transistor 331. In addition, a pixel signal with a voltage value corresponding to the amount of charge accumulated in the floating diffusion layer 324 appears in the vertical signal line VSL connected to the selection transistor 323 of the pixel imaging signal generation unit 320.

[0094] As described above, in the solid-state imaging apparatus 200, a pixel signal SIG is output from a unit pixel 310 where an address event ignition is detected to a column ADC 220. According to another embodiment of this disclosure, a pixel signal is output from a group or subarray of unit pixels 310 associated with the address of the unit pixel 310 to which the address event detection signal has been supplied.

[0095] Furthermore, for example, two logarithmic (LG) transistors (sixth and seventh transistors) 411 and 414 and two amplifying transistors (eighth and ninth transistors) 412 and 413 in the current-to-voltage conversion unit 410 of the light receiving unit 330, the pixel imaging signal generation unit 320, and the address event detection unit 400 are configured in, for example, Figure 2 The light receiver chip 201 is shown, and other components can be configured in, for example, a logic chip 202 that is bonded to the light receiver chip 201 via a Cu-Cu bonding. Therefore, in the following description, the configuration configured in the light receiver chip 201 in a unit pixel 310 is referred to as the "upper layer circuit".

[0096] Figure 5BThe diagram illustrates a configuration example of a group of unit pixels 310 of image sensing pixels 502, constructed to have a shared pixel imaging signal generation and readout circuit 320, according to at least some embodiments of the present disclosure. In this example, each photoelectric conversion element 333 is selectively connected to the floating diffusion layer 324 via its respective transmission gate 331. Furthermore, components of the pixel imaging signal readout circuit 320 are shared by the photoelectric conversion units 333. In this example, four photoelectric conversion units 333a-333d and four corresponding transmission gates 331a-331d are shown. However, any number of photoelectric conversion units 333 and their respective transmission gates 331 can be included by incorporating the shared pixel imaging signal readout circuit 320.

[0097] Figure 5C The figure illustrates an example of a unit pixel 310 configured as a single-function address event detection pixel 503 and an associated address event detection readout circuit 400. As shown, this example includes a single photoelectric conversion element 333, which is selectively connected via a transfer gate 332 to a component of the address event detection readout circuit 400 that is not associated with any other photoelectric conversion element 333. An event scan control block 415 controls the operation of the address event detection readout circuit 400. In response to the detection of an event by the address event detection readout circuit 400 when the circuit 400 is activated, image sensor capture of the associated image sensing pixel or group of pixels 310 is initiated at 417.

[0098] Figure 6 This is a block diagram illustrating a schematic configuration example of an address event detection unit 400 according to at least some embodiments of the present disclosure. Figure 6 As shown, the address event detection unit 400 includes a current-to-voltage conversion unit 410, a buffer 420, a subtractor 430, a quantizer 440, and a transmission unit 450.

[0099] The current-to-voltage conversion unit 410 converts the photocurrent from the light receiving unit 330 into a voltage signal in logarithmic form, and supplies the voltage signal generated by the conversion to the buffer 420.

[0100] The buffer 420 corrects the voltage signal transmitted from the current-to-voltage conversion unit 410 and outputs the corrected voltage signal to the subtractor 430.

[0101] Subtractor 430 reduces the voltage level of the voltage signal transmitted from buffer 420 according to the row drive signal transmitted from drive circuit 211, and supplies the reduced voltage signal to quantizer 440.

[0102] The quantizer 440 quantizes the voltage signal transmitted from the subtractor 430 into a digital signal, and outputs the digital signal generated by quantization as a detection signal to the transmission unit 450.

[0103] The transmission unit 450 sends the detection signal transmitted from the quantizer 440 to the signal processing unit 212, etc. For example, when an address event ignition is detected, the transmission unit 450 provides a request to transmit the address event detection signal from the transmission unit 450 to the drive circuit 211 and from the signal processing unit 212 to the arbitrator 213. Furthermore, when a response to the request is received from the arbitrator 213, the transmission unit 450 supplies the detection signal to the drive circuit 211 and the signal processing unit 212.

[0104] For example, in Figure 6 The current-to-voltage conversion unit 410 shown in the configuration may include, for example: Figure 5A The diagram shows two LG transistors 411 and 414, two amplifying transistors 412 and 413, and a constant current circuit 415.

[0105] For example, the source of LG transistor 411 and the gate of amplifying transistor 413 are connected to the drain of the second transmission transistor 332 of the light receiving unit 330. Additionally, for example, the drain of LG transistor 411 is connected to the source of LG transistor 414 and the gate of amplifying transistor 412. For example, the drain of LG transistor 414 is connected to the power supply terminal VDD.

[0106] Additionally, for example, the source of amplifying transistor 413 is grounded, and its drain is connected to the gate of LG transistor 411 and the source of amplifying transistor 412. For example, the drain of amplifying transistor 412 is connected to the power supply terminal VDD via constant current circuit 415. For example, constant current circuit 415 is composed of a load MOS transistor such as a p-type MOS transistor.

[0107] This connection constitutes a ring source follower circuit. With this configuration, the photocurrent from the photoreceiving unit 330 is converted into a logarithmic voltage signal corresponding to its charge amount. Furthermore, for example, LG transistors 411 and 414 and amplifying transistors 412 and 413 can each be constructed from NMOS transistors.

[0108] Figure 7 This is a circuit diagram illustrating a schematic configuration example of a subtractor 430 and a quantizer 440 according to at least some embodiments of the present disclosure. Figure 7 As shown, the subtractor 430 includes capacitors 431 and 433, an inverter 432, and a switch 434. Additionally, the quantizer 440 includes a comparator 441.

[0109] One end of capacitor 431 is connected to the output terminal of buffer 420, and the other end is connected to the input terminal of inverter 432. Capacitor 433 is connected in parallel to inverter 432. Switch 434 opens or closes the path connecting the two ends of capacitor 433 according to the row drive signal.

[0110] Inverter 432 inverts the voltage signal input through capacitor 431. Inverter 432 outputs an inverted signal to the non-inverting input terminal (+) of comparator 441.

[0111] When switch 434 is turned on, the voltage signal Vinit is input to the buffer 420 side of capacitor 431. The opposite side becomes a virtual ground terminal. For convenience, the potential of the virtual ground terminal is set to zero. At this time, when the capacitance of capacitor 431 is set to C1, the accumulated potential Qinit in capacitor 431 is represented by the following equation (1). On the other hand, the two ends of capacitor 433 are short-circuited, therefore its accumulated charge is zero.

[0112] Qinit=C1×Vinit (1)

[0113] Next, when considering that switch 434 is open and the voltage change of capacitor 431 on the buffer 420 side reaches Vafter, the charge Qafter accumulated in capacitor 431 is represented by the following equation (2).

[0114] Qafter=C1×Vafter (2)

[0115] On the other hand, when the output voltage is set to Vout, the charge Q2 accumulated in capacitor 433 is represented by the following equation (3).

[0116] Q2=-C2×Vout (3)

[0117] At this time, the total charge of capacitors 431 and 433 remains unchanged, therefore equation (4) holds true.

[0118] Qinit=Qafter+Q2 (4)

[0119] When equations (1) to (3) are substituted into equation (4), the following equation (5) is obtained.

[0120] Vout=-(C1 / C2)×(Vafter-Vinit) (5)

[0121] Equation (5) represents the subtraction operation of the voltage signal, and the gain of the subtraction result is C1 / C2. Generally, it is desirable to maximize the gain (or alternatively, increase it), so it is preferable to design the system to make C1 larger and C2 smaller. On the other hand, when C2 is too small, kTC noise increases, thus raising concerns about noise characteristic degradation. Therefore, the reduction in the capacity of C2 is limited to a range that allows for noise reduction. Furthermore, since an address event detection unit 400 including a subtractor 430 is installed for each unit pixel 310, there is an area limitation in the capacities C1 and C2. The values ​​of capacities C1 and C2 are determined taking this limitation into account.

[0122] Comparator 441 compares the voltage signal transmitted from subtractor 430 with a predetermined threshold voltage Vth applied to the inverting input terminal (-). Comparator 441 outputs a signal indicating the comparison result as a detection signal to transmission unit 450.

[0123] Additionally, when the conversion gain of the current-to-voltage conversion unit 410 is set to CG log Furthermore, when the gain of buffer 420 is set to "1", the overall gain A of address event detection unit 400 is represented by the following formula (6).

[0124] [Mathematical Expression 1]

[0125]

[0126] In equation (6), i photo _n represents the photocurrent of the nth unit pixel 310, and its unit is, for example, ampere (A). N represents the number of unit pixels 310 in the pixel block, and is "1" in this embodiment.

[0127] Figure 8 This is a block diagram illustrating a schematic configuration example of a column ADC according to at least some embodiments of the present disclosure. The column ADC 220 includes a plurality of ADCs 230 configured for each column of a unit pixel 310.

[0128] Each ADC 230 converts the analog pixel signal appearing in the vertical signal line VSL into a digital signal. For example, the pixel signal is converted into a digital signal in which the bit length is greater than the bit length of the detection signal. For example, when the detection signal is set to two bits, the pixel signal is converted into a digital signal of three bits or more (16 bits, etc.). The ADC 230 supplies the generated digital signal to the signal processing unit 212.

[0129] Next, the operation of the solid-state imaging apparatus 200 according to at least some embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0130] First, an operational example of the solid-state imaging device 200 will be explained using a timing diagram. Figure 9A This is a timing diagram illustrating an example of the operation of an image sensor according to an embodiment of the present disclosure.

[0131] like Figure 9A As shown, at time T0, when the control unit 130 issues a command to initiate address event detection, the drive circuit 211 raises the control signal TG2 applied to the gates of the second transmission transistors 332 of all light receiving units 330 in the pixel array unit 300 to a high level. With this configuration, the second transmission transistors 332 of all light receiving units 330 are turned on, and photocurrent based on the charge generated in the photoelectric conversion element 333 of each light receiving unit 330 is supplied from each light receiving unit 330 to each of the plurality of address event detection units 400.

[0132] Furthermore, while the control signal TG2 is high, all transmission signals TG1 applied to the gate of the first transmission transistor 331 in each optical receiving unit 330 remain low. Therefore, during this period, the multiple transmission transistors 331 in all optical receiving units 330 are in an off state.

[0133] Next, it will be assumed that the address event detection unit 400, configured to perform event detection on any unit pixel 310, detects an address event ignition during a period when the control signal TG2 is high. In this case, the address event detection unit 400 detecting the address event ignition sends a request to the arbitrator 213. In response, the arbitrator 213 arbitrates the request and returns a response to the request to the address event detection unit 400 that issued the request.

[0134] For example, during the period from time T1 to time T2, the address event detection unit 400, which receives the response, raises the detection signal input to the drive circuit 211 and the signal processing unit 212 to a high level. Furthermore, in this specification, it is assumed that the detection signal is a one-bit signal.

[0135] At time T1, the drive circuit 211, which inputs a high-level detection signal from the address event detection unit 400, lowers all control signals TG2 to a low level at the subsequent time T2. This configuration stops the supply of photocurrent from all light receiving units 330 of the pixel array unit 300 to the address event detection unit 400.

[0136] Additionally, at time T2, the drive circuit 211 raises the selection signal SEL, applied to the gate of the selection transistor 323 in the pixel imaging signal generation unit 320 where the address event ignition is detected (hereinafter referred to as the "readout target unit pixel"), to a high level, and raises the reset signal RST, applied to the gate of the reset transistor 321 in the same pixel imaging signal generation unit 320, to a high level during a constant pulse period, thereby draining (initializing) the charge accumulated in the floating diffusion layer 324 of the pixel imaging signal generation unit 320. In this way, the voltage appearing in the vertical signal line VSL in the state where the floating diffusion layer 324 is initialized is read out by the ADC 230 connected to the vertical signal line VSL in the column ADC 220 as a pixel signal at the reset level (hereinafter simply referred to as the "reset level"), and is converted into a digital signal.

[0137] Next, at time T3 after the readout reset level, the drive circuit 211 applies a transmission signal TRG with a constant pulse period to the gate of the first transmission transistor 331 of the light receiving unit 330 in the readout target pixel 310. With this configuration, the charge generated in the photoelectric conversion element 333 of the light receiving unit 330 is transferred to the floating diffusion layer 324 in the pixel imaging signal generation unit 320, and a voltage corresponding to the charge accumulated in the floating diffusion layer 324 appears in the vertical signal line VSL. In this way, the voltage appearing in the vertical signal line VSL is read out by the ADC 230 connected to the vertical signal line VSL in the column ADC 220 as a pixel signal (hereinafter simply referred to as "signal level") of the signal level of the light receiving unit 330, and is converted into a digital value.

[0138] The signal processing unit 212 performs CDS processing, wherein the difference between the reset level and the signal level read as described above is obtained as a net pixel signal corresponding to the amount of light received by the photoelectric conversion element 333.

[0139] Next, at time T4, the drive circuit 211 lowers the selection signal SEL of the gate of the selection transistor 323 in the readout circuit 320, which is used to generate the pixel imaging signal applied to the readout target unit pixel 310, to a low level, and raises the control signal TG2 of the gate of the second transmission transistor 332 applied to all the light receiving units 330 in the pixel array unit 300 to a high level. With this configuration, the address event firing detection in all the light receiving units 330 in the pixel array unit 300 is restarted.

[0140] Figure 9BThis is a timing diagram illustrating an example of the operation of an image sensor according to other embodiments of the present disclosure. At time T0, when the control unit 130 issues a command to initiate address event detection, the drive circuit 211 raises the control signal TG2 applied to the gate of the transfer transistor 332 associated with the photoelectric conversion element 333 of the selectively activated address event detection unit 400. More specifically, some or all of the address event detection units 400 may be activated.

[0141] Additionally, the transmission signal TG1 applied to the gate of the first transmission transistor 331 is held at a low level. Therefore, the associated transmission transistor 331 is in an off state.

[0142] In this example, at time T1, during which control signal TG2 is high and the associated transmission transistor 332 is in the on state, the arbitrary address event detection unit 400 detects an address event ignition. In response to the event trigger, image frame capture begins. Image frame capture can be a full-frame image capture involving all image sensing pixels 502 included in the pixel array 300. Alternatively, event detection performed by a specific event detection unit 400 can be operated to trigger image capture of a set of image sensing pixels 502 near or otherwise associated with the event detection unit 400. The readout of signals obtained from the image sensing pixels can then be performed.

[0143] Next, an operational example of the solid-state imaging device 200 will be illustrated using a flowchart. Figure 10 This is a flowchart illustrating an example of operation of a solid-state imaging apparatus according to at least some embodiments of the present disclosure. For example, the operation is initiated when a predetermined application for detecting address events is executed.

[0144] like Figure 10 As shown, in this operation, firstly, each unit pixel 310 in the pixel array unit 300 detects the presence or absence of an address event ignition (step S901). Additionally, the drive circuit 211 determines whether an address event ignition is detected in any given unit pixel 310 (step S902).

[0145] If no address event ignition is detected ("No" in step S902), the operation proceeds to step S904. On the other hand, if an address event ignition is detected ("Yes" in step S902), the drive circuit 211 performs pixel signal reading for the unit pixel 310 in which the address event ignition is detected (step S903), and proceeds to step S904.

[0146] In step S904, it is determined whether to terminate the operation. If the operation is not terminated ("No" in step S904), the operation returns to step S901 and the subsequent operation is repeated. On the other hand, if the operation is terminated ("Yes" in step S904), the operation is terminated.

[0147] Figure 11A-11C It is a planar view of a pixel array that includes a portion of a subarray or subset 1101 of pixels constructed as in the first exemplary embodiment. Pixel array 300 may include any number of subarrays 1101. More specifically, in the first exemplary embodiment, the area of ​​each image sensing pixel 502 is smaller than the area of ​​each event detection pixel 503. Furthermore, the ratio of image sensing pixels 502 to event detection pixels 503 varies between various examples. Specifically, in Figure 11A In the example shown, the ratio of image sensing pixels 502 to event detection pixels 503 within the depicted subarray 1101a is 4:1. This same ratio can be applied to the entire pixel array 300. Figure 11B In the example shown, the ratio of image sensing pixels 502 to event detection pixels 503 is 12:1. Figure 11C In the example shown, the ratio of image sensing pixels 502 to event detection pixels 503 is 32:1. Other ratios are also possible. Additionally, the image sensing pixels 502 can be configured into groups 314, including but not limited to groups including Bayer arrays. One or more separation structures 1210 may be included to provide isolation between adjacent unit pixels 310. For example, but not limited to, an RFTI 1208 structure may be formed around each event detection pixel 503. Similarly, RFTI 1208 and / or RDTI 1212 structures may be formed around each image sensing pixel 502.

[0148] Figure 12AThis is a cross-sectional view of a portion of a pixel array 300 including a group 314 of image sensing pixels 502 constructed as in the first exemplary embodiment. As shown, a separation structure 1210 in the form of an RDTI structure 1212 can be provided to separate adjacent unit pixels 310. Additionally, each image sensing pixel 502 may include an insulating or planarization layer 1236 formed on the light-incident surface of a substrate 1216 in which photoelectric conversion elements 333 are formed. Color filters 1240 may be provided for each image sensing pixel 502. In this example, a red color filter 1240R is provided as a portion of the first of the illustrated image sensing pixels 502, and a green color filter 1240Gr is provided as a portion of the second of the illustrated image sensing pixels 502. Furthermore, one or more floating diffusion layers 324 may be associated with the group 314 of image sensing pixels 502. In this example, when using the RDTI isolation structure 1212, one or more floating diffusion layers 324 may be located on or near the second surface of the substrate 1216 and adjacent to the end of the RDTI structure 1212.

[0149] Figure 12B This is a cross-sectional view of a portion of another pixel array including group 314 of image sensing pixels 502 constructed as in the first exemplary embodiment. This example is similar to the previous example, except that the RFTI separation structure 1208 is disposed between the individual image sensing pixels 502. As a result, the floating diffusion layer 324 cannot overlap with the separation structure 1210 in the planar view.

[0150] Figure 13 This is a plan view of the configuration of the group 314 of image sensing pixels 502 according to a first exemplary embodiment. In the example shown, the group 314 of image sensing pixels 502 are separated from each other by the RDTI structure 1212. Additionally, as also... Figure 12A As shown in the example, the individual image sensing pixels 502 are separated from each other by an RDTI structure. Each image sensing pixel 502 includes a photoelectric conversion element 333 and an associated transmission gate 331. Furthermore, in this example, the image sensing pixels 502 within the group 314 share a pixel imaging signal generation unit or readout circuit 320, or a portion thereof. For example, the group of image sensing pixels 502 may have, for example, a... Figure 5B The circuit configuration is shown.

[0151] Figure 14This is a plan view of the configuration of the event detection pixel 503 as shown in the first exemplary embodiment. More specifically, each event detection pixel 503 in this embodiment includes a single photoelectric conversion element 333 and components of an address event detection readout circuit 400 configured for that photoelectric conversion element 333. That is, the components of the address event detection readout circuit 400 are not shared among the multiple photoelectric conversion elements 333. In addition, the event detection pixel 503 is isolated from adjacent unit pixels 310 by an RFTI separation structure 1208.

[0152] Figure 15 This is a circuit diagram illustrating a schematic configuration example of a group of event detection and image sensing pixels 501 having a combination of shared circuit elements according to other embodiments of the present disclosure. In this embodiment, each photoelectric conversion element 333 is associated with a first transmission transistor 331 and a second transmission transistor 332. More specifically, the first transmission transistor 331 selectively connects the associated photoelectric conversion element 333 to elements of a shared pixel imaging signal generation readout circuit 320, and the second transmission transistor 332 selectively connects the associated photoelectric conversion element 333 to components of a shared address event detection readout circuit 400. According to at least some embodiments of the present disclosure, the second transmission transistor 332 associated with multiple photoelectric conversion units 333 within a group 314 of combined event detection and image sensing pixels 501 can be simultaneously turned on. In this example, four photoelectric conversion elements 333a-333d share the associated pixel imaging signal generation readout circuit 320 and the address event detection readout circuit 400. However, any number of unit pixels 310 and associated photoelectric conversion elements 333 can share associated circuits 320 and 400.

[0153] Figures 16A-16C This is a plan view of a portion of a pixel array constructed as in the second exemplary embodiment, specifically a subarray or subset 1601 of pixels. More specifically, in the second exemplary embodiment, groups of combined event detection and image sensing pixels 501 are distributed within a pixel array 300 having groups of image sensing pixels 502. In this example, each group 314 of image sensing pixels 502 comprises four image sensing pixels 502, while each group 314 of combined event detection and image sensing pixels 501 comprises four combined event detection and image sensing pixels 501. The image sensing pixels 502 may be associated with a readout circuit where each image sensing pixel 502 within a group 314 of image sensing pixels shares elements of the readout circuitry 320, such as... Figure 5B As shown. Figure 15As shown, the combined event detection and image sensing pixels 501 can be associated with components of the shared pixel imaging signal generation readout circuit 320 and the shared address event detection readout circuit 400. Furthermore, the ratio of group 314 of image sensing pixels 502 to group 314 of the combined event detection and image sensing pixels 501 can vary. For example, in... Figure 16A In the exemplary subarray 1601a shown, the ratio of image sensing pixels 502 to the combined event detection and image sensing pixels 501 is 1:1. Figure 16B In the exemplary subarray 1601b shown, the ratio of image sensing pixels 502 to the combined event detection and image sensing pixels 501 is 3:1. Figure 16C In the exemplary subarray 1601c shown, the ratio of image sensing pixels 502 to the combined event detection and image sensing pixels 501 is 8:1. Other ratios are also possible. In at least some embodiments, for example, color filters may be associated with unit pixels 310 within a group to form a Bayer array. Isolation between adjacent unit pixels 310 may be provided by RFTI 1208 and / or RDTI 1212 or separation structures 1210. For example, an RDTI 1212 separation structure may be formed around the group of combined event detection and image sensing pixels 501, while an RFTI 1208 separation structure may be formed around each unit pixel 310.

[0154] Figure 17A This is a cross-sectional view of a portion of a pixel array according to a second exemplary embodiment of the present disclosure. As shown in this example, a separation structure 1210 in the form of an RDTI structure 1212 can be provided to separate adjacent unit pixels 310. When using the RDTI separation structure 1212, circuit elements or portions thereof, such as a floating diffusion layer 324 or amplifying transistors 322 or 412, can be formed adjacent to the ends of the RDTI structure 1212. Figure 17B This is a cross-sectional view of a portion of another pixel array according to a second exemplary embodiment of the present disclosure. In this additional example, a separation structure 1210 in the form of an RFTI separation structure 1208 is provided to separate adjacent unit pixels 310.

[0155] Figure 18 This is a plan view of the configuration of the group of image sensing pixels 502 according to the second exemplary embodiment. In this example, the group 314 of image sensing pixels 502 are separated from each other by the RDTI structure 1212. Additionally, as... Figure 17AAs shown in the example, each image sensing pixel 502 is separated from each other by an RDTI structure. Each image sensing pixel 502 includes a photoelectric conversion element 333 and an associated transmission gate 331. Furthermore, in this example, the image sensing pixels 502 within group 314 share a pixel imaging signal generation unit or readout circuit 320, or a portion thereof. For example, the group of image sensing pixels 502 may have, as shown in the example... Figure 5B The circuit configuration is shown. When using the RDTI split structure 1212, circuit elements or parts thereof, such as the floating diffusion layer 324 or the amplifying transistor 322, can be formed adjacent to the end of the RDTI structure 1212.

[0156] Figure 19 This is a plan view of the configuration of a group of combined event detection and image sensing pixels according to a second exemplary embodiment. In this example, each group of event detection and image sensing pixels 503 includes a photoelectric conversion element 333, which is selectively connected to a shared pixel imaging signal generation readout circuit 320 via a first transfer transistor 331 and selectively connected to a shared event detection readout circuit 400 via a second transfer transistor 332. The RDTI structure 1212 provides isolation between the combined event detection and image sensing pixels 501 within the group, while the group is isolated from the unit pixel 310 and other groups via the RFTI structure 1208. When using the RDTI separation structure 1212, circuit elements or portions of circuit elements such as amplifying transistors 322 or 413, LG transistors 411, etc., can be formed adjacent to the ends of the RDTI structure 1212.

[0157] Figure 20 This is a circuit diagram illustrating a schematic configuration example of a combined event detection and image sensing pixel 503 according to an embodiment of the present disclosure. In this example, the photoelectric conversion element 333 of the combined event detection image sensing pixel 503 is selectively connected to a dedicated pixel imaging signal generation readout circuit 320 via a first transfer transistor 331, and selectively connected to a dedicated address event detection readout circuit 400 via a second transfer transistor 332. That is, the pixel imaging signal generation readout circuit 320 and the address event detection readout circuit 400 are not shared with any other photoelectric conversion unit 333.

[0158] Figures 21A-21CThis is a plan view of a portion of a pixel array constructed as in the third exemplary embodiment, specifically a subarray or subset 2101 of pixels. More specifically, in the third exemplary embodiment, groups of combined event detection and image sensing pixels 501 are distributed within a pixel array 300 having groups of image sensing pixels 502. Each group of combined event detection and image sensing pixels 501 comprises four combined event detection and image sensing pixels 501. However, the circuitry is shared. Therefore, the combined event detection and image sensing pixels 501 can be coupled with, for example... Figure 20 The readout circuit shown is associated with this. Groups of image sensing pixels 502 each include four image sensing pixels 502. Groups of image sensing pixels 502 can share circuit elements and can be configured as follows: Figure 5B The structure shown is as described. In Figure 21A In the exemplary subarray 2101a shown, the ratio of image sensing pixels 502 to the combined event detection and image sensing pixels is 1:1. Figure 21B In the exemplary subarray 2101b shown, the ratio of image sensing pixels 502 to the combined event detection and image sensing pixels 501 is 3:1. Figure 21C In the exemplary subarray 2101c shown, the ratio of image sensing pixels 502 to combined event detection and image sensing pixels 501 is 8:1. Other ratios are also possible. An RFTI 1208 separation structure is disposed around the groups of combined event detection and image sensing pixels 501, and the RFTI 1208 separation structure provides isolation between adjacent combined event detection and image sensing pixels 501 within each group of such pixels. An RDTI 1212 separation structure provides isolation between adjacent image sensing pixels 502.

[0159] Figure 22A This is a cross-sectional view of a portion of a pixel array according to a second exemplary embodiment of the present disclosure. As shown in this example, a separation structure 1210 in the form of an RDTI structure 1212 can be provided to separate adjacent unit pixels 310. When using the RDTI separation structure 1212, circuit elements or portions thereof, such as a floating diffusion layer 324 or an amplifying transistor 322, can be formed adjacent to the ends of the RDTI structure 1212. Figure 22B This is a cross-sectional view of a portion of another pixel array according to a second exemplary embodiment of the present disclosure. In this additional example, a separation structure 1210 in the form of an RFTI separation structure 1208 is provided to separate adjacent unit pixels 310.

[0160] Figure 23This is a plan view of the configuration of a group of image sensing pixels 502 according to a third exemplary embodiment. In this example, the group 314 of image sensing pixels 502 are separated from each other by the RDTI structure 1212. Additionally, as... Figure 21B and Figure 21C As shown in the example, the individual image sensing pixels 502 are separated from each other by an RDTI structure. Each image sensing pixel 502 includes a photoelectric conversion element 333 and an associated transmission gate 331. Furthermore, in this example, the image sensing pixels 502 within group 314 share a pixel imaging signal generation unit or readout circuit 320, or a portion thereof. For example, the group of image sensing pixels 502 may have, as shown in the example... Figure 5B The circuit configuration is shown.

[0161] Figure 24 This is a plan view of the configuration of a combination of event detection and image sensing pixels 501 according to a third exemplary embodiment. In this example, each combination of event detection and image sensing pixels 503 includes a photoelectric conversion element 333, which is selectively connected to the pixel imaging signal generation readout circuit 320 via a first transfer transistor 331 and selectively connected to the event detection readout circuit 400 via a second transfer transistor 332. Furthermore, the photoelectric conversion element 333 of each combination of event detection and image sensing pixels 503 does not share its imaging signal generation readout circuit 320 or its event detection readout circuit 400 with any other photoelectric conversion element 333. The RDTI structure 1212 provides isolation around each combination of event detection and image sensing pixels 501. For example, each combination of event detection and image sensing pixels 501 may have, for example, […]. Figure 5A The circuit configuration is shown.

[0162] Figure 25 This is a circuit diagram illustrating a schematic configuration example of a group of image sensing pixels 502 according to an embodiment of the present disclosure. In this example, the photoelectric conversion elements 333 of the group of three image sensing pixels 502 share a pixel imaging signal generation and readout circuit 320. Each of the photoelectric conversion elements 333a-c in this group is selectively connected to an element of the pixel imaging signal generation and readout circuit 320 via its respective first transmission gate 331a-c.

[0163] Figures 26A-26C This is a plan view of a pixel array that includes a subset 2601 of pixels constructed as in the fourth exemplary embodiment. In the fourth exemplary embodiment, the size or area of ​​each image sensing pixel 502 is the same as or substantially the same as the size of each event detection pixel 503. Furthermore, the ratio of image sensing pixels 502 to event detection pixels 503 varies between various examples. For example, in... Figure 26AIn the example shown, the ratio of image sensing pixels 502 to event detection pixels 503 is 3:1. Furthermore, the image sensing pixels 502 are configured in three groups of 2601, while the event detection pixels 503 are configured separately. Figure 26B In the example shown, the ratio of image sensing pixels 502 to event detection pixels 503 is 15:1. Figure 26C In the example shown, the ratio of image sensing pixels 502 to event detection pixels 503 is 35:1. Additionally, in Figure 26B and Figure 26C In the example, some image sensing pixels 502 are configured in groups of 3 pixels 2601, while other image sensing pixels are configured in groups of 4 pixels 2602.

[0164] Figure 27A This is a cross-sectional view of a portion of a pixel array according to a fourth exemplary embodiment of the present disclosure. As shown in this example, the RDTI structure 1212 can be configured to separate adjacent unit pixels 310. Figure 27B This is a cross-sectional view of a portion of another pixel array according to a fourth exemplary embodiment of the present disclosure, wherein the RFTI structure 1208 separates adjacent unit pixels 310. When using the RDTI separation structure 1212, circuit elements or portions thereof may be formed adjacent to the ends of the RDTI structure 1212.

[0165] In the plan view, the configuration of the group of three image sensing pixels according to the fourth exemplary embodiment can be as follows: Figure 13 The configuration is the same in the first embodiment shown, except that, apart from the group 2601 of three image sensing pixels 502, this group only includes three photoelectric conversion elements 333 with associated first transmission transistors 331, to selectively connect the photoelectric conversion elements 333 to elements of the shared pixel imaging signal generation readout circuit 320. Furthermore, the group 314 of image sensing pixels 502 is separated from each other by the RDTI structure 1212. Also, as... Figure 28A and Figure 28B As shown in the example, each image sensing pixel 502 is separated from each other by an RDTI structure. Each image sensing pixel 502 includes a photoelectric conversion element 333 and an associated transmission gate 331. Furthermore, the image sensing pixels 502 within the group 314 share a pixel imaging signal generation unit or readout circuit 320 or a portion thereof. For example, the group of image sensing pixels 502 may have, as shown in the example... Figure 5B The circuit configuration is shown.

[0166] As previously stated, in the fourth embodiment, the event detection pixel 503 and the image sensing pixel 502 have the same size. The configuration of the event detection and image sensing pixel 501, according to the combination of the third exemplary embodiment, can be as follows: Figure 14The configuration of the first exemplary embodiment shown is the same or similar. Therefore, each event detection pixel 503 in this embodiment includes a single photoelectric conversion element 333 and components of an address event detection readout circuit 400 configured for that photoelectric conversion element 333. That is, components of the address event detection readout circuit 400 are not shared among the multiple photoelectric conversion elements 333. In addition, the event detection pixel 503 is isolated from adjacent unit pixels 310 by an RFTI separation structure 1208.

[0167] Figures 28A-28B This is a plan view of a pixel array that includes a subset 2801 of pixels constructed as in the fifth exemplary embodiment. In the fifth exemplary embodiment, the size or area of ​​each imaging sensing pixel 502 is the same as or substantially the same as the size of each event detection pixel 503. Alternatively, the image sensing pixels 502 are configured in groups 2802 or 2803, each pixel within the group having the same color sensitivity. For example, as... Figure 28A As shown, the image sensing pixel 502 can be configured in a group of three unit pixels 2802. As another example, the image sensing pixel can be configured in a group of four unit pixels 2803, except in the area surrounding the group of four event detection pixels 503, where each surrounding group of the image sensing pixel 502 consists of three unit pixels 2802, as shown. Figure 28B As shown. All event detection pixels 503 can be configured in groups of four. As shown, the groups of image sensing pixels 502 can be arranged to form a four-Bayer filter pattern, wherein the overall Bayer pattern is formed by a subset of pixels including two groups of green image sensing pixels 502, one group of red image sensing pixels 502, and one group of blue image sensing pixels. Some or all of the groups of event detection pixels 503 can be surrounded by groups of image sensing pixels 502 that together form the overall Bayer pattern. In addition, the ratio of image sensing pixels 502 to event detection pixels 503 varies between various examples. For example, in Figure 28A In the example shown, the ratio of image sensing pixels 502 to event detection pixels 503 is 3:1. Figure 28B In the example shown, the ratio of image sensing pixel 502 to event detection pixel 503 is 35:1.

[0168] Figure 29A This is a cross-sectional view of a portion of a pixel array according to a fourth exemplary embodiment of the present disclosure. As shown in this example, the RDTI structure 1212 can be configured to separate adjacent unit pixels 310. Figure 29B This is a cross-sectional view of a portion of another pixel array according to a fourth exemplary embodiment of the present disclosure, wherein the RFTI structure 1208 separates adjacent unit pixels 310.

[0169] Figure 30This is a plan view of the configuration of a group of image sensing pixels 502 according to a fifth exemplary embodiment. Each photoelectric conversion element 333 within the group is sensitive to the same color. For example, each photoelectric conversion element 333 within the group of image sensing pixels 502 may be associated with a filter of the same color. Furthermore, the group 314 of image sensing pixels 502 is separated from each other by the RDTI structure 1212, and each individual image sensing pixel 502 is separated from each other by the RDTI structure. In addition, in this example, the image sensing pixels 502 within the group 314 share a pixel imaging signal generation unit or readout circuit 320 or a portion thereof. For example, the group of image sensing pixels 502 may have, for example, a... Figure 5B The circuit configuration is shown. When using the RDTI split structure 1212, circuit elements or parts thereof, such as the floating diffusion layer 324 or the amplifying transistor 322, can be formed adjacent to the end of the RDTI structure 1212.

[0170] Therefore, embodiments of this disclosure provide an imaging apparatus 100 having a pixel array 300 capable of performing both event detection and imaging operations. Furthermore, the circuitry of any unit pixel 310 can be optimized for either image sensing or event detection. According to another embodiment of this disclosure, the pixel array 300 may include pixels optimized for image sensing combined with pixels performing both image sensing and event detection. According to yet another embodiment of this disclosure, the pixel array 300 may include event detection pixels having a larger area than the image sensing pixels. Additionally, embodiments of this disclosure may include different numbers and proportions of image sensing pixels and event detection pixels. For example, the imaging apparatus 100 may combine a pixel array 300 according to embodiments of this disclosure having a greater number of image sensing pixels 502 than event detection pixels 503, a greater number of event detection pixels 503 than image sensing pixels 502, or the same number of image sensing pixels 502 and event detection pixels 503. Furthermore, a pixel array according to embodiments of this disclosure may include any number and proportion of image sensing pixels 502, event detection pixels 503, and combined event detection and image sensing pixels 501.

[0171] Figure 31 This is a block diagram illustrating a schematic configuration example of a vehicle control system, which serves as an example of a mobile body control system to which the technology according to this disclosure is applicable.

[0172] The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. Figure 31In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a main system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and a comprehensive control unit 12050. Furthermore, as part of the functional configuration of the comprehensive control unit 12050, a microcomputer 12051, a sound and image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0173] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 is used as a drive force generating device such as an internal combustion engine or drive motor to generate drive force for the vehicle, a drive force transmission mechanism to transmit drive force to the wheels, a steering mechanism to adjust the vehicle's steering angle, and a control device to generate braking force for the vehicle.

[0174] The main system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the main system control unit 12020 is used as a control device for keyless entry systems, smart key systems, power windows, or various lights such as headlights, taillights, brake lights, turn signals, or fog lights. In this case, radio waves transmitted from a portable device or signals from various switches, used to replace buttons, can be input to the main system control unit 12020. The main system control unit 12020 receives the input radio waves or signals and controls the vehicle's door locking devices, power windows, lights, etc.

[0175] The exterior information detection unit 12030 detects external information of the vehicle on which the vehicle control system 12000 is installed. For example, the exterior information detection unit 12030 is connected to the imaging unit 12031. The exterior information detection unit 12030 causes the imaging unit 12031 to capture images of the exterior of the vehicle and receives the captured images. The exterior information detection unit 12030 can perform object detection processing such as people, cars, obstacles, signs, and text on the road, or distance detection processing based on the received images.

[0176] Imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. Imaging unit 12031 can output an electrical signal as an image or as ranging information. Furthermore, the light received by imaging unit 12031 can be visible light or invisible light such as infrared. In addition, according to embodiments of this disclosure, imaging unit 12031 may include a solid-state imaging device 200 that incorporates pixel array unit 300 and unit pixel 310, wherein the unit pixel 310 is configured and isolated from other unit pixels 310 within pixel array unit 300.

[0177] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041, which detects the driver's state, is connected to the in-vehicle information detection unit 12040. For example, the driver state detection unit 12041 includes a camera that captures images of the driver, and based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level, or determine whether the driver is dozing off.

[0178] For example, the microcomputer 12051 calculates control target values ​​for the drive force generating device, steering mechanism, or braking device based on information about the vehicle's interior and exterior obtained by the external information detection unit 12030 or the internal information detection unit 12040, and can output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control to implement functions of an advanced driver assistance system (ADAS), including collision avoidance or mitigation, distance-based tracking, speed maintenance, collision warning, and lane departure warning.

[0179] In addition, the microcomputer 12051 can coordinate and control the drive force generating device, steering mechanism, braking device, etc., based on information about the vehicle's surroundings obtained by the external information detection unit 12030 or the internal information detection unit 12040, so as to achieve autonomous driving, where the vehicle drives itself without relying on the driver's operation.

[0180] The microcomputer 12051 can output control commands to the main system control unit 12020 based on information about the exterior of the vehicle obtained by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 can coordinate the control of the headlights by controlling the position of the vehicle in front or oncoming vehicles detected by the vehicle exterior information detection unit 12030 to achieve glare prevention, such as switching the high beams to low beams.

[0181] The sound and image output unit 12052 transmits at least one output signal between sound and image to an output device capable of visually or audibly informing occupants inside the vehicle or to the outside of the vehicle. Figure 31 In the example, an audio speaker 12061, a display unit 12062, and a dashboard 12063 are shown as output devices. For example, the display unit 12062 may include at least one of an in-vehicle display and a head-up display.

[0182] Figure 32 This is a diagram showing an example of the mounting location of the imaging unit 12031.

[0183] exist Figure 32The imaging unit 12031 is provided with imaging units 12101, 12102, 12103, 12104 and 12105.

[0184] For example, imaging units 12101, 12102, 12103, 12104, and 12105 are mounted in locations such as the front of the vehicle 12100, side mirrors, rear bumper, rear door, and the upper part of the windshield inside the vehicle. Imaging unit 12101, mounted at the front of the vehicle, and imaging unit 12105, mounted on the upper part of the windshield inside the vehicle, primarily acquire images of the front of the vehicle 12100. Imaging units 12102 and 12103, mounted in the side mirrors, primarily acquire images of the sides of the vehicle 12100. Imaging unit 12104, mounted on the rear bumper or rear door, primarily acquires images of the rear of the vehicle 12100. Imaging unit 12105, mounted on the upper part of the windshield inside the vehicle, is mainly used to detect vehicles, pedestrians, obstacles, traffic signals, traffic signs, lanes, etc., ahead.

[0185] also, Figure 32 An example of the imaging range of imaging units 12101 to 12104 is shown. Imaging range 12111 represents the imaging range of imaging unit 12101 located in the front of the vehicle; imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103 located in the side mirrors, respectively; and imaging range 12114 represents the imaging range of imaging unit 12104 located in the rear bumper or rear door. For example, when image data captured by imaging units 12101 to 12104 are superimposed on each other, a bird's-eye view of the vehicle 12100 can be obtained.

[0186] At least one of the imaging units 12101 to 12104 may have the function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including multiple imaging elements, or may be an imaging element including pixels for phase difference detection.

[0187] For example, based on the distance information obtained from imaging units 12101 to 12104, microcomputer 12051 can extract, by obtaining the distance to each stereoscopic object within each imaging range 12111 to 12114 and the time change of that distance (relative speed relative to vehicle 12100), the stereoscopic object located on the driving path of vehicle 12100, particularly the closest stereoscopic object, and traveling in approximately the same direction as vehicle 12100 at a predetermined speed (e.g., 0 km / h or more), as the vehicle ahead. Furthermore, microcomputer 12051 can set a pre-determined distance between vehicles in front of the vehicle ahead to perform automatic braking control (including tracking stop control), automatic acceleration control (including tracking start control), etc. As described above, coordinated control such as autonomous driving, where the vehicle drives autonomously without relying on driver operation, can be performed.

[0188] For example, based on distance information obtained from imaging units 12101-12104, by classifying multiple sets of three-dimensional object data into data for two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, and other three-dimensional objects such as utility poles, the microcomputer 12051 can extract three-dimensional object data and automatically avoid obstacles using the extracted data. For example, the microcomputer 12051 identifies obstacles around vehicle 12100 as obstacles that can be visually recognized by the driver of vehicle 12100 and obstacles that are difficult to visually recognize. In addition, the microcomputer 12051 determines the collision risk, indicating the degree of danger of colliding with each obstacle. When the collision risk is equal to or higher than a set value and a collision is possible, the microcomputer 12051 can provide collision avoidance driving assistance by outputting a warning to the driver via audio speaker 12061 or display unit 12062, or by performing forced deceleration or evasive steering via drive system control unit 12010.

[0189] At least one of the imaging units 12101 to 12104 can be an infrared camera for detecting infrared light. For example, the microcomputer 12051 can identify a pedestrian by determining whether a pedestrian exists in the images captured by the imaging units 12101 to 12104. For example, pedestrian identification is performed by extracting feature points from the images captured by the imaging units 12101 to 12104 (which are infrared cameras) and performing pattern matching processing on a series of feature points indicating the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and identifies the pedestrian, the sound and image output unit 12052 controls the display unit 12062 to display superimposed quadrilateral outlines to emphasize the identified pedestrian. Furthermore, the sound and image output unit 12052 can control the display unit 12062 to display an icon indicating the pedestrian at a desired location.

[0190] Examples of vehicle control systems applicable to the technology of this disclosure have been described above. The technology of this disclosure is applicable to the imaging unit 12031, driver state detection unit 12041, etc., in the above-described configuration.

[0191] The embodiments of the present invention have been described above. However, the technical scope of this disclosure is not limited to the above embodiments, and various modifications can be made without departing from the spirit of this disclosure. In addition, the constituent elements of other embodiments and modifications can be appropriately combined.

[0192] Furthermore, the effects of the embodiments described in this specification are merely exemplary, and other effects may exist without limitation.

[0193] In addition, this technology may include the following components.

[0194] (1) A sensor, comprising:

[0195] Pixel array unit, wherein the pixel array unit includes:

[0196] Multiple event detection pixels, the multiple event detection pixels including a first pixel, the first pixel including:

[0197] First photoelectric conversion region; and

[0198] An amplifying transistor connected to the first photoelectric conversion region;

[0199] Multiple image sensing pixels, the multiple image sensing pixels including a second pixel, the second pixel including:

[0200] Second photoelectric conversion region;

[0201] The third photoelectric conversion region; and

[0202] Amplifying transistors connected to the second and third photoelectric conversion regions;

[0203] A first isolation region is configured between the first pixel and the second pixel; and

[0204] A second isolation region is configured between the second and third photoelectric conversion regions.

[0205] (2) According to the sensor described in (1), wherein in the cross-sectional view, the first isolation region is deeper than the second isolation region.

[0206] (3) The sensor according to (1) or (2) further includes:

[0207] Multiple image signal generation and readout circuits, wherein for each photoelectric conversion region of each image sensing pixel, an associated transfer transistor selectively connects the photoelectric conversion region to one of the image signal generation and readout circuits.

[0208] (4) According to the sensor described in (3), each image signal generation and readout circuit is shared by multiple image sensing pixels.

[0209] (5) The sensor according to (4) further includes:

[0210] Multiple event detection readout circuits, wherein each photoelectric conversion region of each event detection pixel is connected to one of the event detection readout circuits.

[0211] (6) The sensor according to (5) further includes:

[0212] Multiple second image signal generation and readout circuits

[0213] Each event detection pixel also includes a transmission transistor.

[0214] For each photoelectric conversion region of each event detection pixel, the associated transmission transistor selectively connects that photoelectric conversion region to one of the second image signal generation and readout circuits.

[0215] (7) The sensor according to (6), wherein each second image signal generation and readout circuit is shared by multiple event detection pixels.

[0216] (8) The sensor according to (7), wherein each event detection readout circuit is shared by multiple event detection pixels.

[0217] (9) The sensor according to any one of (1) to (8), wherein the plurality of image sensing pixels includes a first number of image sensing pixels, wherein the plurality of event detection pixels includes a second number of event detection pixels, and wherein the first number is greater than the second number.

[0218] (10) The sensor according to any one of (1) to (9), wherein the area of ​​the photoelectric conversion region of each event detection pixel is greater than the area of ​​the photoelectric conversion region of each image sensing pixel.

[0219] (11) The sensor according to (9) or (10), wherein the first quantity is at least three times the second quantity.

[0220] (12) The sensor according to any one of (1) to (11), wherein the area of ​​each event detection pixel is greater than the area of ​​each image sensing pixel.

[0221] (13) The sensor according to any one of (1) to (12), wherein each event detection pixel is surrounded by a full-thickness trench isolation structure.

[0222] (14) The sensor according to any one of (1) to (13), wherein each image sensing pixel is separated from the adjacent image sensing pixel by a deep trench isolation structure.

[0223] (15) The sensor according to any one of (1) to (12), wherein each event detection pixel is separated from the adjacent event detection pixel by a deep trench isolation structure.

[0224] (16) The sensor according to (15), wherein each event detection pixel is separated from the adjacent image sensing pixel by a full-thickness trench isolation structure.

[0225] (17) The sensor according to (15) or (16), wherein each image sensing pixel is separated from the adjacent image sensing pixel by a deep trench isolation structure.

[0226] (18) An electronic device comprising:

[0227] Imaging lens; and

[0228] Solid-state imaging device, the solid-state imaging device comprising:

[0229] At least one pixel array unit, wherein the pixel array unit comprises:

[0230] Multiple event detection pixels, the multiple event detection pixels including a first pixel, the first pixel including:

[0231] First photoelectric conversion region; and

[0232] Amplifying transistors;

[0233] Multiple image sensing pixels, the multiple image sensing pixels including a second pixel, the second pixel including:

[0234] Second photoelectric conversion region;

[0235] The third photoelectric conversion region; and

[0236] Amplifying transistors connected to the second and third photoelectric conversion regions;

[0237] A first isolation region is configured between the first pixel and the second pixel; and

[0238] A second isolation region is configured between the second and third photoelectric conversion regions; and

[0239] A control unit, wherein the control unit controls the operation of the solid-state imaging device.

[0240] (19) A method for operating a pixel array unit, comprising:

[0241] A pixel array unit is provided, wherein the pixel array unit includes:

[0242] Multiple event detection pixels, the multiple event detection pixels including a first pixel, the first pixel including:

[0243] First photoelectric conversion region; and

[0244] Amplifying transistors;

[0245] Multiple image sensing pixels, the multiple image sensing pixels including a second pixel, the second pixel including:

[0246] Second photoelectric conversion region;

[0247] The third photoelectric conversion region; and

[0248] Amplifying transistors connected to the second and third photoelectric conversion regions;

[0249] A first isolation region is configured between the first pixel and the second pixel; and

[0250] A second isolation region is configured between the second and third photoelectric conversion regions.

[0251] Those skilled in the art will understand that various modifications, combinations, sub-combinations and alterations can be made depending on design requirements and other factors, as long as they are within the scope of the appended claims or their equivalents.

Claims

1. A sensor, comprising: Pixel array unit, wherein the pixel array unit includes: Multiple event detection pixels, the multiple event detection pixels including a first pixel, the first pixel including: First photoelectric conversion region; and An amplifying transistor connected to the first photoelectric conversion region; Multiple image sensing pixels, the multiple image sensing pixels including a second pixel, the second pixel including: Second photoelectric conversion region; The third photoelectric conversion region; and Amplifying transistors connected to the second and third photoelectric conversion regions; A first isolation region is configured between the first pixel and the second pixel; and A second isolation region is configured between the second and third photoelectric conversion regions. In the cross-sectional view, the first isolation region is deeper than the second isolation region.

2. The sensor according to claim 1, further comprising: Multiple image signal generation and readout circuits, wherein for each photoelectric conversion region of each image sensing pixel, an associated transfer transistor selectively connects the photoelectric conversion region to one of the image signal generation and readout circuits.

3. The sensor of claim 2, wherein each image signal generation and readout circuit is shared by a plurality of image sensing pixels.

4. The sensor according to claim 3, further comprising: Multiple event detection readout circuits, wherein each photoelectric conversion region of each event detection pixel is connected to one of the event detection readout circuits.

5. The sensor according to claim 4, further comprising: Multiple second image signal generation and readout circuits Each event detection pixel also includes a transmission transistor. For each photoelectric conversion region of each event detection pixel, the associated transmission transistor selectively connects that photoelectric conversion region to one of the second image signal generation and readout circuits.

6. The sensor of claim 5, wherein each second image signal generation and readout circuit is shared by a plurality of event detection pixels.

7. The sensor of claim 6, wherein each event detection readout circuit is shared by a plurality of event detection pixels.

8. The sensor of claim 7, wherein the plurality of image sensing pixels comprises a first number of image sensing pixels, wherein the plurality of event detection pixels comprises a second number of event detection pixels, and wherein the first number is greater than the second number.

9. The sensor of claim 8, wherein the area of ​​the photoelectric conversion region of each event detection pixel is larger than the area of ​​the photoelectric conversion region of each image sensing pixel.

10. The sensor of claim 8, wherein the first quantity is at least three times the second quantity.

11. The sensor of claim 1, wherein the plurality of image sensing pixels comprises a first number of image sensing pixels, wherein the plurality of event detection pixels comprises a second number of event detection pixels, and wherein the first number is greater than the second number.

12. The sensor of claim 11, wherein the area of ​​each event detection pixel is larger than the area of ​​each image sensing pixel.

13. The sensor of claim 11, wherein the area of ​​the photoelectric conversion region of each event detection pixel is larger than the area of ​​the photoelectric conversion region of each image sensing pixel.

14. The sensor of claim 11, wherein the first quantity is at least three times the second quantity.

15. The sensor of claim 1, wherein each event detection pixel is surrounded by a full-thickness trench isolation structure.

16. The sensor of claim 1, wherein each image sensing pixel is separated from adjacent image sensing pixels by a deep trench isolation structure.

17. The sensor of claim 16, wherein each event detection pixel is separated from adjacent event detection pixels by a deep trench isolation structure.

18. The sensor of claim 17, wherein each event detection pixel is separated from the adjacent image sensing pixel by a full-thickness trench isolation structure.

19. An electronic device comprising: Imaging lens; and Solid-state imaging device, the solid-state imaging device comprising: At least one pixel array unit, wherein the pixel array unit comprises: Multiple event detection pixels, the multiple event detection pixels including a first pixel, the first pixel including: First photoelectric conversion region; and An amplifying transistor connected to the first photoelectric conversion region; Multiple image sensing pixels, the multiple image sensing pixels including a second pixel, the second pixel including: Second photoelectric conversion region; The third photoelectric conversion region; and Amplifying transistors connected to the second and third photoelectric conversion regions; A first isolation region is configured between the first pixel and the second pixel; and A second isolation region is configured between the second and third photoelectric conversion regions. In the cross-sectional view, the first isolation region is deeper than the second isolation region; and A control unit, wherein the control unit controls the operation of the solid-state imaging device.

20. A method for operating a pixel array unit, comprising: A pixel array unit is provided, wherein the pixel array unit includes: Multiple event detection pixels, the multiple event detection pixels including a first pixel, the first pixel including: First photoelectric conversion region; and An amplifying transistor connected to the first photoelectric conversion region; Multiple image sensing pixels, the multiple image sensing pixels including a second pixel, the second pixel including: Second photoelectric conversion region; The third photoelectric conversion region; and Amplifying transistors connected to the second and third photoelectric conversion regions; A first isolation region is configured between the first pixel and the second pixel; and A second isolation region is configured between the second and third photoelectric conversion regions. In the cross-sectional view, the first isolation region is deeper than the second isolation region.

Images