Partial product summation module design method and multiplier

Abstract

The application provides a partial product summation module design method and a multiplier, wherein the partial product summation module comprises at least one adder group, each of the adder groups is used to obtain an addition result based on a plurality of input data to be added, and each of the adder groups comprises a plurality of logic units in a plurality of cascaded stages; the partial product summation module design method comprises the following steps: determining a flipping rate of each of the data to be added corresponding to each of the adder groups respectively; and determining a data connection mode of each of the adder groups based on the flipping rate of each of the data to be added. The partial product summation module design method provided by the embodiment of the application reduces the dynamic power consumption of the partial product summation module, thereby reducing the dynamic power consumption of the multiplier.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a partial product summation module design method and multiplier. Background Technology

[0002] Multipliers are crucial computational units in digital integrated circuits (DIC chips). They are essential for performing multiplication in application-specific integrated circuits (ASICs) used for digital signal processing, information encryption, and scientific computing. In recent years, the continuous development of deep learning, such as the practical application of convolutional neural networks (CNNs) in image classification and object recognition, has made accelerating ASICs for neural networks a hot design topic. Since CNNs involve a large number of multiply-accumulate operations, designing energy-efficient multipliers is a key focus in designing ASICs for accelerating neural network computations.

[0003] Currently, existing multipliers suffer from high energy consumption when applied to neural network computations. Summary of the Invention

[0004] This invention provides a partial product summation module design method and a multiplier to solve the problem of high energy consumption when multipliers are applied to neural network calculations in the prior art, thereby reducing the energy consumption of multipliers.

[0005] In a first aspect, the present invention provides a design method for a partial product summation module, wherein the partial product summation module includes at least one adder group, each adder group is used to obtain an addition result based on multiple input data to be added, and each adder group includes multiple logic units cascaded in multiple levels;

[0006] Determine the to-be-added rate for each of the data to be added corresponding to each of the adder groups;

[0007] The data connection method for each adder group is determined based on the flip rate of each of the data to be added.

[0008] Optionally, determining the data connection method for each adder group based on the flip rate of each of the data to be added includes:

[0009] The high-flip-rate data to be added is input to the subsequent logic unit in the adder group;

[0010] The low-flip-rate data to be added is input to the front-end logic unit in the adder group.

[0011] Optionally, determining the data connection method for each adder group based on the flip rate of each of the data to be added includes:

[0012] Based on the flip rate of each of the data to be added, the hold rate of each of the data to be added, and the formula for the output flip rate, the output flip rate of each logic unit in each candidate data connection method is determined;

[0013] The total output toggle rate of each adder group is determined based on the output toggle rate of each logic unit.

[0014] The candidate data connection method corresponding to the minimum total output flip rate is selected as the preferred data connection method.

[0015] The formula for the output flip rate is:

[0016] α=f(β1,β2,…,β n ,γ1,…,γ n );

[0017] Where α is the output toggle rate, (β1, β2, ..., β... n Let γ be the toggle rate of the n inputs of the logic unit from 0 to 1, (γ1, ..., γ2) n ) represents the hold rate of the n inputs of the logic unit, which keeps the inputs from 1 to 1, and f is a function determined according to the logic expression of the logic unit.

[0018] Optionally, the method further includes:

[0019] When the logic function of the logic unit can be implemented by multiple candidate logic gates, the logic gate of the logic unit is determined based on the fan-in number of the basic unit in each candidate logic gate.

[0020] In a second aspect, the present invention also provides a multiplier, comprising: a partial product generation module and a partial product summation module; the partial product summation module is obtained by the partial product summation module design method as described in the first aspect;

[0021] The partial product generation module includes N partial product generation units, each of which includes an encoder and a selector connected in series. The partial product generation module is used to obtain the multiplicand and the multiplier, obtain N partial products based on the multiplicand and the multiplier, and input the N partial products into the partial product summation module.

[0022] The partial product summation module is used to receive the N partial products input by the partial product generation module, and obtain the product based on the N partial products;

[0023] Where N is a positive integer greater than or equal to 1.

[0024] Optionally, the circuit structure of the first selector to the (N-2)th selector is a first structure, which includes a first XOR gate unit and a first selector unit;

[0025] The first input terminal of the first XOR gate unit is connected to the multiplicand A, and the second input terminal of the first XOR gate unit is connected to the multiplier B;

[0026] The first input terminal of the first selector unit is connected to the output terminal of the first XOR gate unit, the second input terminal of the first selector unit is connected to the double signal, and the third input terminal of the first selector unit is connected to the single signal.

[0027] The circuit structure of the N-1th selector and the Nth selector is the second structure, which includes a second selector unit and a second XOR gate unit.

[0028] The first input terminal of the second selector unit is connected to the double signal, the second input terminal of the second selector unit is connected to the single signal, and the third input terminal of the second selector unit is connected to the multiplicand A.

[0029] The first input terminal of the second XOR gate unit is connected to the output terminal of the second selector unit, and the second input terminal of the second XOR gate unit is connected to the NEG signal.

[0030] Optionally, the input signal of each encoder includes the 2i-th bit, the 2i+1-th bit, and the 2i+2-th bit of the multiplier B; the output signal of each encoder includes a single signal, a double signal, and a neg signal.

[0031] The logical expression for the single signal is:

[0032]

[0033] The logical expression for the double signal is:

[0034]

[0035] The logical expression for the neg signal is:

[0036]

[0037] Where i is a natural number greater than or equal to 0, b 2i b represents the 2i-th bit of the multiplier B. 2i+1 This represents the (2i+1)th bit of the multiplier B, b 2i+2 This represents the (2i+2)th bit of the multiplier B.

[0038] Optionally, the input signal of each encoder further includes the 0th bit of the multiplicand A, and the output signal of each encoder further includes the neg_c signal and the s signal;

[0039] The logical expression for the neg_c signal is:

[0040]

[0041] The logical expression for the s signal is:

[0042] s = A0·single;

[0043] Where, neg represents the neg signal, single represents the single signal, and A0 represents the 0th bit of the multiplicand A.

[0044] Optionally, the encoder circuit includes a single signal output circuit, a double signal output circuit, a neg signal output circuit, a sum bit output circuit, and a carry output circuit;

[0045] The single signal output circuit includes a first XOR gate circuit, and the first input terminal of the first XOR gate circuit is connected to the input signal b. 2i The second input terminal of the first XOR gate circuit is connected to the input signal b. 2i+1 ;

[0046] The double signal output circuit includes a first inverter, a second inverter, a third inverter, a first NAND gate, a second NAND gate, and a third NAND gate.

[0047] The input terminal of the first inverter is connected to the input signal b. 2i+2 ;

[0048] The input terminal of the second inverter is connected to the input signal b. 2i ;

[0049] The input terminal of the third inverter is connected to the input signal b. 2i+1 ;

[0050] The first input terminal of the first NAND gate is connected to the input signal b. 2i The second input terminal of the first NAND gate is connected to the input signal b. 2i+1 The third input terminal of the first NAND gate is connected to the output terminal of the first inverter;

[0051] The first input terminal of the second NAND gate is connected to the output terminal of the second inverter, the second input terminal of the second NAND gate is connected to the output terminal of the third inverter, and the third input terminal of the second NAND gate is connected to the input signal b. 2i+2 ;

[0052] The first input terminal of the third NAND gate is connected to the output terminal of the first NAND gate, and the second input terminal of the third NAND gate is connected to the output terminal of the second NAND gate.

[0053] The NEG signal output circuit includes the second inverter, the third inverter, the first OR gate circuit, and the first AND gate circuit;

[0054] The first input terminal of the first OR gate circuit is connected to the output terminal of the second inverter, and the second input terminal of the first OR gate circuit is connected to the output terminal of the third inverter.

[0055] The first input terminal of the first AND gate is connected to the output terminal of the first OR gate, and the second input terminal of the first AND gate is connected to the input signal b. 2i+2 ;

[0056] The sum-bit output circuit includes a second AND gate circuit, the first input terminal of the second AND gate circuit is connected to the output terminal of the first XOR gate circuit, and the second input terminal of the second AND gate circuit is connected to the input signal A0.

[0057] The carry-out output circuit includes a fourth inverter and a first NOR gate circuit. The input terminal of the fourth inverter is connected to the NEG signal, the first input terminal of the first NOR gate circuit is connected to the output terminal of the fourth inverter, and the second input terminal of the first NOR gate circuit is connected to the output terminal of the second AND gate circuit.

[0058] Optionally, the partial product summation module is used to add the 2Nth bit of the Nth neg_c signal to the partial product generated by the first partial product generation unit;

[0059] Where N is the total number of partial product generating units.

[0060] The partial product summation module design method and multiplier provided by the present invention determine the data connection mode of each adder group by the flip rate of each of the data to be added, thereby reducing the flip power consumption of the partial product summation module and thus reducing the dynamic power consumption of the partial product summation module. When the partial product summation module is applied to the multiplier, it can reduce the dynamic power consumption of the multiplier. Attached Figure Description

[0061] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0062] Figure 1This is a flowchart illustrating a partial product summation module design method provided in an embodiment of the present invention;

[0063] Figure 2 This is the transistor-level schematic diagram of the full adder provided by the present invention;

[0064] Figure 3 This is a correlation statistics chart of feature maps of each layer of the AlexNet neural network provided in this embodiment of the invention;

[0065] Figure 4 This is a correlation statistics diagram of feature maps of each layer of the ResNet50 neural network provided in this embodiment of the invention;

[0066] Figure 5 This is a correlation statistics chart of feature maps of each layer of the GoogLeNet neural network provided in this embodiment of the invention;

[0067] Figure 6 This is a diagram of candidate connection methods for summing 6-bit data provided in an embodiment of the present invention;

[0068] Figure 7 This is the optimal connection method and port allocation diagram for 6-bit summation provided in the embodiments of the present invention;

[0069] Figure 8 This is a schematic diagram of the structure of the multiplier provided in an embodiment of the present invention;

[0070] Figure 9 This is a schematic diagram of the structure of a partial product generation unit in a conventional radix-4 Booth encoded multiplier provided by the present invention;

[0071] Figure 10 This is a circuit diagram of a Booth selector module that performs a shift followed by an inversion, provided in an embodiment of the present invention.

[0072] Figure 11 This is a circuit diagram of a Booth selector module that first inverts and then shifts bits, provided in an embodiment of the present invention.

[0073] Figure 12 This is a schematic diagram of the structure of a partial product generation module in a radix-4 Booth encoder multiplier provided in an embodiment of the present invention;

[0074] Figure 13 This is a circuit diagram of the Booth encoder module, a partial product generation module in a radix-4 Booth encoder multiplier provided in an embodiment of the present invention.

[0075] Figure 14 This is a partial product array diagram generated by the partial product generation module of the radix-4 Booth encoder multiplier provided in this embodiment of the invention;

[0076] Figure 15This is a partial product array diagram generated by the partial product generation module of the conventional radix 4 Booth encoding multiplier provided by the present invention;

[0077] Figure 16 This is a schematic diagram of the partial product summation module implemented using the Wallace tree compression method provided in this embodiment of the invention;

[0078] Figure 17 This is a schematic diagram of the structure of an 8-bit radix-4 Booth encoded multiplier provided in an embodiment of the present invention;

[0079] Figure 18 This is a schematic diagram of the structure of a radix-4 Booth-encoded 16-bit multiplier provided in an embodiment of the present invention;

[0080] Figure 19 This is a schematic diagram of the partial product generation module of the radix-4 Booth encoded 16-bit multiplier provided in an embodiment of the present invention;

[0081] Figure 20 This is a schematic diagram of the partial product summation module of the radix-4 Booth encoded 16-bit multiplier provided in an embodiment of the present invention;

[0082] Figure 21 This is a statistical distribution diagram of the weights of a common three-layer neural network provided by the present invention;

[0083] Figure 22 This is a statistical distribution diagram of the feature maps of a common three-layer neural network provided by the present invention. Detailed Implementation

[0084] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0085] The present invention will now be described in conjunction with its design concept.

[0086] Digital multipliers multiply two binary numbers, using them as both multiplicand and multiplier, to obtain a product, also represented in binary. Digital multipliers can be broadly classified into two categories: serial multipliers and parallel multipliers. Serial multipliers are primarily used in application-specific integrated circuits (ASICs) with limited power consumption and area, such as those used in bank cards. While serial multipliers have low power consumption and small area, they require multiple clock cycles to complete a single multiplication operation. For chips requiring high energy efficiency, such as ASICs used to accelerate neural network computations, considering both clock tree energy consumption and control circuit energy consumption, serial multipliers have lower energy efficiency and are not suitable for applications demanding high energy efficiency. Parallel multipliers are implemented using three modules: a partial product generation module, a partial product compression module, and a final summation module. The latter two modules, since they both involve adding partial products, can also be collectively referred to as partial product summation modules. Therefore, the parallel multiplier can be divided into two modules, which is the method adopted in this paper. There are several implementation methods for the partial product generation module and the partial product summation module. Parallel multipliers are classified according to the implementation methods of the two modules, such as radix-4 Booth encoded tree multipliers.

[0087] There are three methods for implementing partial product generation modules: bitwise AND, Booth encoding, and Verdi encoding. Booth encoding is further divided into radix-2 Booth encoding, radix-4 Booth encoding, and radix-8 Booth encoding. In terms of the number of partial product rows, the bitwise AND method, Verdi algorithm, and radix-2 Booth encoding algorithm generate a partial product row count equal to the number of bits in the multiplier. The radix-4 Booth encoding algorithm generates a partial product row count equal to half the number of bits in the multiplier. This means that the partial product summation module can be implemented using fewer compressors. While radix-8 Booth encoding and higher radix Booth encoding algorithms generate even fewer partial product rows than radix-4 Booth encoding, they sometimes require calculating non-multiplicative multiples of 2 (e.g., 3 x multiplicand), making the implementation circuit more complex. Therefore, radix-4 Booth encoding is a commonly used method for partial product generation modules in parallel multipliers. From the perspective of partial product generation, radix-4 Booth encoding requires grouping the multiplicand into 3-bit segments and processing the multiplicand based on each group of 3 bits to generate a corresponding row of partial products. Let A represent the multiplicand; the generated partial product has six possible values: -0, 0, A, -A, 2A, and -2A. Compared to bitwise AND operations, this partial product generation method requires additional encoding circuitry. However, considering the characteristic of a fixed operand in convolutional neural network computation, using the fixed operand in booth encoding can eliminate the dynamic energy consumption caused by this additional circuitry. Furthermore, existing partial product generation modules based on radix-4 Booth encoding introduce redundancy during summation due to the irregular shape of the partial product array, and none of them consider the characteristic of convolutional neural network computation where one operand is fixed and the other operand is correlated.

[0088] Partial product summation modules employ two methods: array addition and tree addition. Tree addition is further divided into Wallace tree addition, Dadda tree addition, and so on. The essential difference between these methods lies in the different ways the compressors are connected within the partial product summation module. Similarly, existing partial product summation modules do not take into account the characteristic in convolutional neural network computation where one operand is fixed while the other operand is correlated.

[0089] The following is combined Figure 1 - Figure 7 This invention describes a partial product summation module design method provided by an embodiment of the invention.

[0090] Figure 1 This is a flowchart illustrating a partial product summation module design method provided in an embodiment of the present invention, such as... Figure 1As shown, the partial product summation module provided in this embodiment of the invention includes at least one adder group, each of the adder groups being used to obtain an addition result based on multiple input data to be added, and each adder group including multiple cascaded logic units.

[0091] For example, Table 1 is a sample table of binary multiplication arrays. Taking 101010×101 as an example, the resulting multiplication array is shown in Table 1:

[0092] Table 1. Examples of Binary Multiplication Arrays

[0093]

[0094]

[0095] It should be understood that each column represents a set of data to be added, and each column corresponds to a set of adders. The adder set adds the corresponding data to obtain the sum. For example, if the first column corresponds to the data to be added, "0", "1", and "0", the adder set corresponding to the first column performs "0+1+0", resulting in a sum output of 1 and a carry output of 0. The carry output "0" is then input into the adder set corresponding to the second column.

[0096] The partial product summation module design method provided in this embodiment of the invention includes:

[0097] Step 110: Determine the toggle rate of each of the data to be added corresponding to each of the adder groups;

[0098] Optionally, the flip rate of each of the data to be added corresponding to each of the adder groups can be obtained by Synopsys VCS software. For example, in a neural network computing scenario, the target neural network is input into Synopsys VCS, and the flip rate result of the target neural network data output by Synopsys VCS is obtained. The data of the target neural network is the same as the data to be added by the partial product summation module.

[0099] Step 120: Determine the data connection method for each adder group based on the flip rate of each of the data to be added.

[0100] It should be understood that when the data connection method of the adder group is determined based on the flip rate of the data to be added, the logic unit is an adder, which may include a full adder or a half adder.

[0101] Specifically, in neural network accelerator chips using CMOS digital logic circuits, the dynamic power consumption of multipliers accounts for over 95%, while the static power consumption accounts for less than 5%. The dynamic power consumption of CMOS logic circuits is divided into two parts: the switching power consumption caused by the charging and discharging of the logic unit to the load capacitor, and the short-circuit power consumption caused by the simultaneous conduction of P-channel and N-channel transistors within the logic unit. The formula for calculating the dynamic power consumption of any logic unit is:

[0102] P dynamic =P switch +P short ;

[0103] P switch =αfCV 2 ;

[0104] P short =2αt sc VI peak f;

[0105] Among them, P dynamic For dynamic power consumption, P switch For switching power consumption, P short For short-circuit power consumption, α is the 0→1 switching probability of an output of the logic unit, or simply the switching rate; C is the load capacitance of the logic unit's output, including the logic unit's own load and external load; V is the operating voltage of the logic unit; t sc I is the equivalent pulse width of the short-circuit current pulse; peak Here, is the short-circuit pulse current pulse height; f is the clock frequency. It can be seen that the dynamic power consumption of a logic unit is closely related to the 0→1 transition probability α of one of its outputs, and the output transition rate α is calculated based on the input transition rate β and the logic relationship of the logic unit.

[0106] α=f(β1,β2,…,β n );

[0107] Where β1, ... β n Let f be the 0→1 toggle rate of the n inputs of the logic unit, and f be a function related to the logic expression of the logic unit.

[0108] For example, when there are multiple candidate connection methods, such as method 1: inputting data A to adder A and inputting data B to adder B; method 2: inputting data B to adder A and inputting data A to adder B, after obtaining the flip rate of each of the data to be added, the flip power consumption of each data connection method is determined by the flip rate, thereby determining the dynamic power consumption of each data connection method, and selecting the data connection method of the adder group with the lowest dynamic power consumption.

[0109] The partial product summation module design method provided in this embodiment of the invention determines the data connection mode of each adder group by the flip rate of each of the data to be added, thereby reducing the flip power consumption of the partial product summation module and thus reducing the dynamic power consumption of the partial product summation module. When the partial product summation module is applied to the multiplier, it can reduce the dynamic power consumption of the multiplier.

[0110] The following is a further explanation of the possible implementation methods of the above steps in specific embodiments.

[0111] Optionally, determining the data connection method for each adder group based on the flip rate of each of the data to be added includes:

[0112] Step 121: Input the high-flip-rate data to be added to the subsequent logic unit in the adder group;

[0113] Step 122: Input the low-flip-rate data to be added to the front-end logic unit in the adder group.

[0114] Specifically, high and low flip rates refer to the relative magnitudes of the values ​​to be added among multiple data sets in the adder group. For example, if the data to be added includes A and B, and A has a flip rate of 0.1 while B has a flip rate of 0.01, then A is a data set with a high flip rate relative to B. The subsequent logic unit processes the data sent by the preceding unit; that is, at least one input to the subsequent logic unit is the output of the preceding logic unit. For example, taking adders as an example, if the number of cascaded adders in the adder group is greater than or equal to three, the adders can be compared pairwise. For instance, if the output of the first adder is connected to the input of the second adder, and the output of the second adder is connected to the input of the third adder, then the second adder is a preceding adder relative to the third adder, and a subsequent adder relative to the first adder.

[0115] General assumptions: The input signals of the logic unit are independent of each other, and the previous input is also independent of the next input. α can be calculated from the input flip rate and the logic relationship of the logic unit.

[0116] Taking a full adder as an example, let the three inputs of the full adder be A, B, and C, the carry output Co, and the sum output S; let the probabilities that the three inputs of the full adder are 1 be P(A=1)=a, P(B=1)=b, and P(C=1)=c respectively. Table 2 is the truth table of the full adder provided by this invention, as shown in Table 2:

[0117] Table 2. Truth Table of Full Adder

[0118]

[0119]

[0120] Then, according to the formula for the probability of independent events, the probabilities of outputs S and Co being 1 are respectively...

[0121] S=P(S=1)=a(1-b)(1-c)+b(1-a)(1-c)+c(a-1)(b-1)+abc;

[0122] Co=P(Co=1)=ab(c-1)+ac(b-1)+bc(a-1)+abc;

[0123] Similarly, using the independent event probability formula, the flip rates α(S) and α(Co) of the outputs S and Co are respectively:

[0124] α(S) = s(1-s);

[0125] α(Co) = co(1-co);

[0126] The full adder used in this embodiment of the invention is a mirror full adder. Figure 2 This is the transistor-level schematic diagram of the full adder provided by the present invention, such as... Figure 2 As shown, the two output terminals Co and S are connected to the input terminals of the next full adder, with 10 and 8 gate capacitors respectively as loads. The load capacitance is much higher than that of other nodes in the circuit. Therefore, the switching power consumption of the full adder can be approximated by the switching rate of the two output terminals Co and S.

[0127] Figure 3 This is a correlation statistics chart of feature maps of each layer of the AlexNet neural network provided in this embodiment of the invention. Figure 4 This is a correlation statistics diagram of feature maps of each layer of the ResNet50 neural network provided in this embodiment of the invention. Figure 5 This is a correlation statistics chart of feature maps of each layer of the GoogLeNet neural network provided in this embodiment of the invention. The correlation of each layer of a common neural network is as follows: Figure 3 , Figure 4 and Figure 5 As shown. In neural network computation, the convolutional property of neural networks is often utilized to fix one operand while changing the other, thereby reducing memory access and energy consumption. Therefore, in multiplier computation, there is a characteristic where one operand is fixed, and the other operand has a correlation between its two inputs.

[0128] Because there is a strong correlation between two actual inputs, the traditional method for calculating the flip rate α yields results that differ significantly from reality. Therefore, this invention proposes a method for calculating the flip rate when the input data is correlated.

[0129] Output flip rate formula:

[0130] α=f(β1,β2,…,β n ,γ1,…,γ n );

[0131] Where α is the output toggle rate, (β1, β2, ..., β... n Let γ1, ..., γ2 be the toggle rate of the n inputs of a logic unit from 0 to 1. n ) represents the hold rate of the n inputs of the logic unit, which keeps the inputs from 1 to 1, and f is a function determined according to the logic expression of the logic unit.

[0132] It should be understood that f is determined based on the input and output of the logic unit, calculating the probability of all corresponding input scenarios when the logic unit's output is flipped. Therefore, f varies depending on the logic unit; however, for a given logic unit, f is fixed. Examples are given using AND gates and adders. It should be understood that these examples are provided for ease of understanding and should not be construed as limiting the invention in any way. Functions corresponding to logic units not illustrated in these examples are also within the scope of this invention.

[0133] Taking an AND gate as an example, A and B are the inputs of the AND gate, and C is the output of the AND gate. Table 3 is the truth table of the AND gate provided by this invention, as shown in Table 3:

[0134] Table 3. Truth Table for AND Gates

[0135] A B C 0 0 0 0 1 0 1 0 0 1 1 1

[0136] From the truth table of the AND gate and the law of total probability, we can obtain the formula for calculating the output inversion rate of the AND gate:

[0137] α(C)=P 0→1 (C) =

[0138] P 0→1 (A)P 0→1 (B)+P 0→1 (A)P 1→1 (B)+P 1→1 (A)P 0→1 (B)

[0139] Taking a full adder as an example, referring to the truth table and toggle rate calculation formula of the full adder mentioned above, the output toggle rate formula of the full adder can be obtained as follows:

[0140] α(S)=P 0→0 (A)P 0→0 (B)P 0→1 (C)+P 0→0 (A)P 0→1 (B)P 0→0 (C)

[0141] +P 0→1 (A)P 0→0 (B)P 0→0 (C)

[0142] +P 0→1 (A)P 0→1 (B)P 0→1 (C)+P 0→0 (A)P 1→0 (B)P 1→1 (C)

[0143] +P 0→0 (A)P 1→1 (B)P 1→0 (C)

[0144] +P 0→1 (A)P 1→0 (B)P 1→0 (C)+P 0→1 (A)P 1→1 (B)P 1→1 (C)

[0145] +P 1→0 (A)P 0→0 (B)P 1→1 (C)

[0146] +P 1→0 (A)P 0→1 (B)P 1→0 (C)+P 1→1 (A)P 0→0 (B)P 1→0 (C)

[0147] +P 1→1 (A)P 0→1 (B)P 1→1 (C)

[0148] +P 1→0 (A)P 0→0 (B)P 1→1 (C)+P 1→0 (A)P 0→1 (B)P 1→0 (C)

[0149] +P 1→1 (A)P 0→0 (B)P 1→0 (C)

[0150] +P 1→1 (A)P 0→1 (B)P 1→1 (C);

[0151] α(CO)=P 0→0 (A)P 0→1 (B)P 0→1 (C)+P 0→1 (A)P 0→1 (B)P 0→0 (C)

[0152] +P 0→1 (A)P 0→0 (B)P 0→1 (C)

[0153] +P 0→1 (A)P 0→1 (B)P 0→1 (C)+P 0→0 (A)P 0→1 (B)P 1→1 (C)

[0154] +P 0→1 (A)P 0→1 (B)P 1→0 (C)

[0155] +P 0→1 (A)P 0→0 (B)P 1→1 (C)+P 0→1 (A)P 0→1 (B)P 1→1 (C)

[0156] +P 0→0 (A)P 1→1 (B)P 0→1 (C)

[0157] +P 0→1 (A)P 1→1 (B)P 0→0 (C)+P 0→1 (A)P 1→0 (B)P 0→1 (C)

[0158] +P 0→1 (A)P 1→1 (B)P 0→1 (C)

[0159] +P 1→0 (A)P 0→1 (B)P 0→1 (C)+P 1→1 (A)P 0→1 (B)P 0→0 (C)

[0160] +P 1→1 (A)P 0→0(B)P 0→1 (C)

[0161] +P 1→1 (A)P 0→1 (B)P 0→1 (C).

[0162] For the case of two cascaded full adders, let the first-stage full adder be FA1, with inputs A1, B1, and C1, and outputs S1 and CO1; and the second-stage full adder be FA2, with inputs S1, B2, and C2, and outputs CO2 and S2. As mentioned above, when the loads at the S and CO terminals of the full adder are not significantly different, α(S1) + α(CO1) + α(S2) + α(CO2) can represent the energy consumption of the two full adders. Distributing the five ports P1 to P5, sorted by their toggle ratios from low to high, to the five ports A1, B1, C1, B2, and C2, the addition result S2 remains the same for different distribution methods, and its toggle ratio remains unchanged. Therefore, it is necessary to compare the values ​​of α(S1) + α(CO1) + α(CO2) to compare the energy consumption of different distribution methods.

[0163] The following demonstrates that when two full adders are cascaded, the high toggle rate port is allocated to the later stage, resulting in lower power consumption: This is based on statistical input data, showing that input P... 0→0 P 1→1 Change relative P 0→1 It is very small, therefore it has:

[0164] α(S1)=f s (α(A1), α(B1), α(C1));

[0165] α(CO1)=f CO (α(A1), α(B1), α(C1));

[0166] α(CO2)=f CO (f s (α(A1), α(B1), α(C1)), α(B2), α(C2)).

[0167] In the case where some ports on high-flip ports P4 and P5 are assigned to the first level, compared to the case where both P4 and P5 are assigned to the second level, it is easy to see from the formula that α(S1) and α(CO1) are higher in the former case than in the latter, while α(CO2) may conversely be higher in the latter case. However, if f s Among the three terms (α(A1), α(B1), α(C1)), α(B2), α(C2), there exists a higher term in the second case, f s(α(A1), α(B1), α(C1)) must be lower, so the sum of α(CO1) and α(CO2) is still higher in the first case. Therefore, when two full adders are cascaded, the energy consumption is lower when the high switching rate port is allocated to the later stage.

[0168] Therefore, for several logic units in a multi-level cascade, input data with a high flip rate is connected to the subsequent logic unit, while input data with a low flip rate is connected to the preceding logic unit.

[0169] For example, the partial product summation module is composed of several full-adders (FA) and half-adders (HA) connected together. The connection method calculates the torsion rate using the improved torsion rate calculation formula in this embodiment, resulting in the optimal connection method. Figure 14 Taking the summation of the fifth column as an example, the fifth column summation has a total of 6 bits of input, including 3 bits for the partial product and 3 bits for the carry generated from the summation of the fourth column. Simulation using existing neural network data yields the toggle rates of these six inputs, which are then renamed P1 to P6 from low to high. To minimize the carry generated in this column, the summation circuit should use as few half-adders as possible. Therefore, this column uses two full adders and one half-adder, resulting in five possible connection methods. Figure 6 This is a diagram of candidate connection methods for summing 6-bit data provided in an embodiment of the present invention. Each connection method also has multiple ways to allocate P1 to P6 with the input port. Calculations show that the fourth connection method is optimal, having the lowest flip rate. Figure 7 This is the optimal connection method and port allocation diagram for 6-bit summation provided in this embodiment of the invention. The final connection method is as follows: Figure 7 As shown.

[0170] The summation in the sixth column has 7 bits of input, including 4 bits for the partial product and 3 bits for the carry generated from the summation in the fifth column. After determining the connection method of the fifth column, simulation yields the toggle rate information of the sixth column input. Then, using the same steps as for the fifth column, the compressor connection method and input port allocation method for the sixth column summation are determined. This allows us to obtain the connection methods for all columns of the partial product. The final partial product summation module is as follows: Figure 17 The area within the dashed box and Figure 20 As shown.

[0171] The partial product summation module design method provided in this embodiment of the invention is based on the correlation characteristics of the two inputs of the neural network. By obtaining the flip rate relationship of each node inside the partial product summation module, the data connection method of the adder is optimized according to the relationship, thereby reducing the flip energy consumption of the partial product summation module.

[0172] Optionally, the data connection method of each adder group is determined based on the flip rate of each of the data to be added, including:

[0173] Based on the flip rate of each of the data to be added, the hold rate of each of the data to be added, and the formula for the output flip rate, the output flip rate of each logic unit in each candidate data connection method is determined;

[0174] The total output toggle rate of each adder group is determined based on the output toggle rate of each logic unit.

[0175] The candidate data connection method corresponding to the minimum total output flip rate is selected as the preferred data connection method.

[0176] The formula for the output flip rate is:

[0177] α=f(β1,β2,…,β n ,γ1,…,γ n );

[0178] Where α is the output toggle rate, (β1, β2, ..., β... n ) represents the toggle rate of the n inputs of the logic unit from 0 to 1 (i.e., the toggle rate of the data to be added), (γ1, ..., γ n ) represents the retention rate of the n inputs of the logic unit, which keeps the values ​​of 1 to 1 (the retention rate of the data to be added), and f is a function determined according to the logic expression of the logic unit.

[0179] The partial product summation module design method provided in this invention calculates the output toggle rate of the logic unit based on the toggle rate and hold rate of the data to be added, thereby obtaining the total output toggle rate of the adder group, selecting the minimum output toggle rate, optimizing the data connection method of the adders, and reducing the toggle energy consumption of the partial product summation module. Optionally, each adder includes one or more logic units;

[0180] When the logic function of the logic unit can be implemented by multiple candidate logic gates, the logic gate of the logic unit is determined based on the fan-in number of the basic unit in each candidate logic gate.

[0181] It should be understood that, given a logic gate circuit, a logic unit refers to a unit module that implements a logic function, which can be a basic logic gate circuit or a combination thereof.

[0182] For the same logic function, it can be implemented using either Method 1: a large fan-in logic gate or Method 2: several small fan-in logic gates. The short-circuit power consumption of these two circuits are as follows:

[0183] Short-circuit power consumption of method 1: P short=2αt sc VI peak f;

[0184] Short-circuit power consumption of method 2:

[0185] Among them, the equivalent pulse width t of the short-circuit current pulse sc The width of the rising and falling edges of the input is determined by the input's rising and falling edge widths. Since Mode 1 and Mode 2 perform the same logical function, the inputs are the same, and therefore the rising and falling edge widths are the same. sc They are also the same; the operating voltage V is set to be the same; the clock frequency f is set to be the same; I peak Determined by the operating voltage and the resistance in the short-circuit path, since large-fan-in logic gates have more stacked transistors than small-fan-in logic gates, the resistance in the short-circuit path of large-fan-in logic gates is greater. peak Smaller.

[0186] For example, consider completing Y = a&b&c&d using one four-input AND gate and three two-input AND gates: Assuming the inputs a, b, c, and d all have a 50% flip rate and are uncorrelated, then using one four-input AND gate:

[0187]

[0188]

[0189] Using three two-input AND gates, let Y1 = a & b, Y2 = c & d, Y = Y1 & Y2, then:

[0190]

[0191]

[0192]

[0193]

[0194]

[0195]

[0196]

[0197] It is evident that the short-circuit power consumption of using three two-input AND gates is higher than that of using one four-input AND gate.

[0198] Therefore, try to use large-fan-in logic gates provided in the standard cell library and use small-fan-in logic gates as little as possible. It should be understood that large or small fan-in here refers to a numerical comparison relative to another candidate logic gate circuit.

[0199] The partial product summation module design method provided in this embodiment of the invention determines the logic gate circuit of the logic unit based on the fan-in number of the basic unit in each candidate logic gate circuit, thereby reducing the short-circuit power consumption of the partial product summation module and thus reducing the dynamic power consumption of the partial product summation module.

[0200] The following is combined Figure 8 - Figure 22 This invention describes a multiplier provided in an embodiment of the invention.

[0201] Figure 8 This is a schematic diagram of the structure of the multiplier provided in an embodiment of the present invention, as shown below. Figure 8 As shown, the multiplier provided in this embodiment of the invention includes: a partial product generation module and a partial product summation module; the partial product summation module is obtained using the partial product summation module design method described in the above embodiment;

[0202] The partial product generation module includes N partial product generation units, each of which includes an encoder and a selector connected in series. The partial product generation module is used to obtain the multiplicand and the multiplier, obtain N partial products based on the multiplicand and the multiplier, and input the N partial products into the partial product summation module.

[0203] The partial product summation module is used to receive the N partial products input by the partial product generation module, and obtain the product based on the N partial products;

[0204] Where N is a positive integer greater than or equal to 1.

[0205] Optionally, the multiplier provided in this embodiment of the invention can be a radix-4 Booth multiplier. The partial product generation module is used to obtain the partial product of two operands A and B (also called multiplicand A and multiplier B) of arbitrary bit length according to the radix-4 Booth encoding algorithm. The process is as follows: the multiplier B is divided into three groups of three, and the most significant bit of the first group overlaps with the least significant bit of the second group by one bit (if the last group is less than 3 bits, 0 is padded in the most significant bit). Table 4 shows the partial products obtained by the traditional radix-4 Booth encoding algorithm. The corresponding partial products of each group generated by the radix-4 Booth encoder are shown in Table 4.

[0206] Table 4. Partial products obtained by the traditional radix-4 Booth coding algorithm

[0207] <![CDATA[b 2i+1 b 2i b 2i-1 ]]> Partial product 000 0 001 A 010 A 011 2A 100 -2A 101 -A 110 -A 111 -0

[0208] The algorithm can be expressed by the following mathematical formula:

[0209]

[0210] The partial product generation module can be divided into an encoder module and a selector module. Figure 9 This is a schematic diagram of the structure of a partial product generation unit in a conventional radix-4 Booth encoded multiplier provided by the present invention, as shown below. Figure 9 As shown, the encoder encodes single, double, and negative signals based on a set of three bits of the multiplier. The negative signal is also a bit of the partial product, which needs to be summed in the partial product addition module. It should be understood that one or more partial product generation units connected together can form a partial product generation module. Table 5 shows the encoding logic of a traditional encoder.

[0211] Table 5. Encoding Logic of Traditional Encoders

[0212] <![CDATA[b 2i b 2i-1 b 2i-2 ]]> single double neg 000 0 0 0 001 1 0 0 010 1 0 0 011 0 1 0 100 0 1 1 101 1 0 1 110 1 0 1 111 0 0 1

[0213] Its logical expression is as follows:

[0214]

[0215]

[0216] neg = b2;

[0217] The Booth selector performs shifting and negation operations on the multiplicand A based on the single, double, and negative bits generated by the encoder. When single is 1 and double is 0, no shift is performed, and a partial product P = A or P = -A is generated based on negative being 0 or 1. When single is 0 and double is 1, the multiplicand is shifted left by one bit, and a partial product P = 2A or P = -2A is generated based on negative being 0 or 1. When single is 0 and double is 0, a partial product P = 0 is generated.

[0218] The partial product summation module in the multiplier provided in this embodiment of the invention is obtained by the partial product summation module design method described in the above embodiment, thus enabling the reduction of switching power consumption and / or short-circuit power consumption, thereby reducing the dynamic power consumption of the multiplier.

[0219] Optionally, the circuit structure of the first selector to the (N-2)th selector is a first structure, which includes a first XOR gate unit and a first selector unit;

[0220] The first input of the first XOR gate unit is connected to the multiplicand A, and the second input of the first XOR gate unit is connected to the neg signal;

[0221] The first input terminal of the first selector unit is connected to the output terminal of the first XOR gate unit, the second input terminal of the first selector unit is connected to the double signal, and the third input terminal of the first selector unit is connected to the single signal.

[0222] The circuit structure of the N-1th selector and the Nth selector is the second structure, which includes a second selector unit and a second XOR gate unit.

[0223] The first input terminal of the second selector unit is connected to the double signal, the second input terminal of the second selector unit is connected to the single signal, and the third input terminal of the second selector unit is connected to the multiplicand A.

[0224] The first input terminal of the second XOR gate unit is connected to the output terminal of the second selector unit, and the second input terminal of the second XOR gate unit is connected to the NEG signal.

[0225] Specifically, as mentioned above, the partial product has multiple possible values, and its generation requires two circuit components: a selector (MUX) that chooses from 0, A, and 2A, and an XOR gate that performs the inversion. It should be understood that an 8-bit multiplier contains 4 selectors, a 16-bit multiplier contains 8 selectors, and so on; therefore, N is usually greater than or equal to 4.

[0226] Specific implementation methods may include:

[0227] Method 1: Let the multiplicand A pass through MUX first and then through XOR, i.e., the second structure.

[0228] Method 2: Let the multiplicand A pass through XOR first and then through MUX, i.e., the first structure.

[0229] For example, taking an 8-bit input as an example, Figure 10 This is a circuit diagram of a Booth selector module that performs a shift followed by an inversion, provided in an embodiment of the present invention. Figure 11 This is a circuit diagram of a Booth selector module that performs a bit inversion followed by bit shifting, provided in an embodiment of the present invention. Figure 10 Corresponding to method 1, the second structure is adopted. Figure 11 Corresponding to method 2, the first structure is adopted. Figure 11 For example, Figure 11 As shown, each output corresponds to a selector, that is, P[1] to P[8] correspond to a selector respectively.

[0230] 8-bit multiplication requires 4 rows of partial products, i.e., 4 selectors. The absolute values ​​of the weights in common deep learning networks are usually small. When input to the multiplier B, B[7:5] and B[5:3] are often in the case of all 0 or all 1, as shown in Table 4. In the case of all 0 or all 1, the partial product is 0. Therefore, the probability of the partial product in the last 2 rows being 0 is high. In this embodiment of the invention, the last 2 selectors use the second structure, and the other selectors use the first structure. It should be understood that the selector corresponding to the highest bit is the last selector (the selector corresponding to P[8]), and so on.

[0231] In the first structure, the output of XOR changes with the change of A, resulting in dynamic power consumption. In the second structure, the selector will produce glitches due to the input delay mismatch of the logic gates. However, when the partial product always remains 0, the outputs of MUX and XOR both remain 0. The multiplier provided in this embodiment combines the first and second structures of the selector. The first selector to the (N-2)th selector adopts the first structure to avoid glitches caused by input delay. The last two selectors adopt the second structure. When the partial product always remains 0, the outputs of MUX and XOR both remain 0, reducing dynamic power consumption. The multiplier provided in this embodiment achieves a reduction in dynamic power consumption.

[0232] Optionally, the input signal of each encoder includes the 2i-th bit, the 2i+1-th bit, and the 2i+2-th bit of the multiplier B; the output signal of each encoder includes a single signal, a double signal, and a neg signal.

[0233] The logical expression for the single signal is:

[0234]

[0235] The logical expression for the double signal is:

[0236]

[0237] The logical expression for the neg signal is:

[0238]

[0239] Where i is a natural number greater than or equal to 0, b 2i b represents the 2i-th bit of the multiplier B. 2i+1 This represents the (2i+1)th bit of the multiplier B, b 2i+2 This represents the (2i+2)th bit of the multiplier B.

[0240] Specifically, according to Table 4, there are six cases for the traditional partial product: ±0, ±A, and ±2A. The case with a negative sign involves finding the two's complement, which is traditionally achieved by inverting all bits and adding 1 to the least significant bit. For example, the case of -0 involves finding the two's complement of 0, resulting in a partial product P = 111…1 + 1. Adding 1 is achieved by adding a negative bit to the partial product array. When the absolute value of the multiplier is small and fluctuates around 0, multiple rows of partial products will be 0 or -0. The traditional method of distinguishing between 0 and -0 causes the partial product to repeatedly flip between 000…0 and 111…1, resulting in unnecessary dynamic energy consumption.

[0241] Figure 12 This is a schematic diagram of the partial product generation module in the radix-4 Booth encoded multiplier provided in an embodiment of the present invention, as shown below. Figure 12 As shown, in this embodiment of the invention, the neg bit is expressed using the following logical expression:

[0242]

[0243] Table 6. One of the logical codes provided in the embodiments of the present invention

[0244] B[3:1] single double neg 000 0 0 0 001 1 0 0 010 1 0 0 011 0 1 0 100 0 1 1 101 1 0 1 110 1 0 1 111 0 0 0

[0245] Table 6 is one of the logic codes provided in the embodiments of the present invention. As shown in Table 6, the multiplier provided in the embodiments of the present invention can unify the two cases of partial product being 0 and -0, avoid dynamic flipping of 0 and -0, and reduce the dynamic energy consumption of the multiplier.

[0246] Optionally, the input signal of each encoder further includes the 0th bit of the multiplicand A, and the output signal of each encoder further includes the neg_c signal and the s signal;

[0247] The logical expression for the neg_c signal is:

[0248]

[0249] The logical expression for the s signal is:

[0250] s = A0·single;

[0251] Where, neg represents the neg signal, single represents the single signal, and A0 represents the 0th bit of the multiplicand A.

[0252] It should be understood that in the embodiments of the present invention, the bits are sorted in the manner of 0, 1, 2... and other structures, units or rows and columns are sorted in the manner of 1, 2, 3... The sorting method is for the purpose of understanding the embodiments of the present invention and should not constitute any limitation on the present invention.

[0253] Table 6. Logical encoding provided in the embodiments of the present invention (II)

[0254] neg single A[0] s neg_c 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 0 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0

[0255] Optionally, Figure 13 This is a circuit diagram of the Booth encoder module, a partial product generation module in a radix-4 Booth encoder multiplier provided in an embodiment of the present invention, as shown below. Figure 13 As shown, the encoder circuit includes a single signal output circuit, a double signal output circuit, a negative signal output circuit, a bit (s) output circuit, and a carry (n) output circuit;

[0256] The single signal output circuit includes a first XOR gate circuit, and the first input terminal of the first XOR gate circuit is connected to the input signal b. 2i The second input terminal of the first XOR gate circuit is connected to the input signal b. 2i+1 The output of the first XOR gate is a single signal.

[0257] The double signal output circuit includes a first inverter, a second inverter, a third inverter, a first NAND gate, a second NAND gate, and a third NAND gate.

[0258] The input terminal of the first inverter is connected to the input signal b. 2i+2 ;

[0259] The input terminal of the second inverter is connected to the input signal b. 2i ;

[0260] The input terminal of the third inverter is connected to the input signal b. 2i+1 ;

[0261] The first input terminal of the first NAND gate is connected to the input signal b. 2i The second input terminal of the first NAND gate is connected to the input signal b. 2i+1 The third input terminal of the first NAND gate is connected to the output terminal of the first inverter;

[0262] The first input terminal of the second NAND gate is connected to the output terminal of the second inverter, the second input terminal of the second NAND gate is connected to the output terminal of the third inverter, and the third input terminal of the second NAND gate is connected to the input signal b. 2i+2 ;

[0263] The first input terminal of the third NAND gate is connected to the output terminal of the first NAND gate, and the second input terminal of the third NAND gate is connected to the output terminal of the second NAND gate; the output terminal of the third NAND gate is a double signal.

[0264] The NEG signal output circuit includes the second inverter, the third inverter, the first OR gate circuit, and the first AND gate circuit;

[0265] The first input terminal of the first OR gate circuit is connected to the output terminal of the second inverter, and the second input terminal of the first OR gate circuit is connected to the output terminal of the third inverter.

[0266] The first input terminal of the first AND gate is connected to the output terminal of the first OR gate, and the second input terminal of the first AND gate is connected to the input signal b. 2i+2 The output of the first AND gate is the neg signal.

[0267] The sum-bit output circuit includes a second AND gate circuit. The first input terminal of the second AND gate circuit is connected to the output terminal of the first XOR gate circuit, and the second input terminal of the second AND gate circuit is connected to the input signal A0. The output terminal of the second AND gate circuit is the sum-bit output. Figure 13 (s is in the middle);

[0268] The carry-out output circuit includes a fourth inverter and a first NOR gate. The input of the fourth inverter is connected to the NEG signal. The first input of the first NOR gate is connected to the output of the fourth inverter. The second input of the first NOR gate is connected to the output of the second AND gate. The output of the first NOR gate is the carry-out signal. Figure 13 (where n is the number in the middle). It should be understood that... Figure 13 The NOR2B gate in the code is equivalent to a combination of the fourth inverter and the second NOR gate.

[0269] It should be understood that Figure 13 In this context, B[1] corresponds to the input signal b. 2i B[2] corresponds to the input signal b 2i+1 B[3] corresponds to the input signal b 2i+2 .

[0270] Optionally, the partial product summation module is used to add the 2Nth bit of the Nth neg_c signal to the partial product generated by the first partial product generation unit;

[0271] Where N is the total number of partial product generating units.

[0272] Specifically, Figure 14 This is a partial product array diagram generated by the partial product generation module of the radix-4 Booth encoder multiplier provided in this embodiment of the invention. Figure 15This is a partial product array diagram generated by the partial product generation module of the conventional radix-4 Booth encoded multiplier provided by this invention. In the conventionally generated Booth partial product array, the neg signal of each row of partial products is added to the least significant bit of that row. An 8-bit conventional Booth multiplier partial product array is shown below. Figure 15 As shown, the last row of the partial product array in a traditional Booth multiplier has an isolated negative bit. This makes the longest column in the array 5 units long, requiring a compressor. It should be understood that the partial product array diagram can represent the type and position of the data to be added, and the multiplier performs the addition operation on each column of data in the array diagram.

[0273] Specifically, the Nth neg_c signal is the neg_c signal corresponding to the Nth partial product generation unit, which is the neg_c bit of the last row of the partial product in the partial product array list. The partial product generated by the 1st partial product generation unit is the first row of the partial product in the partial product array list. For example... Figure 14 As shown, in this embodiment of the invention, the negative_c bit (i.e. the negative_c signal) of each row partial product is added to the second low bit, and the negative_c bit of the last row partial product is added to the first row partial product. This eliminates the problem of an isolated negative bit in the last row of the partial product array of the traditional Booth multiplier, and reduces the longest column length of the array to 4.

[0274] This invention shortens the array length and makes the partial product array shape more regular by adding the neg_c bits of the last row's partial product to the first row's partial product, making it easier for the subsequent partial product summation module to sum the partial products with fewer compressor units. The multiplier provided in this invention improves the partial product generation module by reducing the number of rows in the partial product array by one, thus reducing the summation circuitry and improving the multiplier's energy efficiency. Utilizing the characteristic in convolutional neural network computation where one operand is fixed and the other operand is correlated, the multiplier's partial product generation module is improved, and the compressor connection method in the partial product summation module is determined based on the relationship of the partial product flip rate, further improving the multiplier's energy efficiency in convolutional neural network computation.

[0275] In one embodiment, Figure 16 This is a schematic diagram of the partial product summation module implemented using the Wallace tree compression method provided in this embodiment of the invention. The partial product summation module provided in this embodiment of the invention uses a traditional Wallace tree structure for summation, as shown in the diagram. Figure 16 As shown.

[0276] In one embodiment, Figure 17 This is a schematic diagram of the structure of a radix-4 Booth-encoded 8-bit multiplier provided in an embodiment of the present invention; as shown below. Figure 17As shown, the multiplier is 8 bits, so the partial product generation module has four partial product generation sub-modules. According to the method described in Embodiment 1 of the present invention, the partial product generation module structure with the lowest flip rate can be calculated, that is, the selector in the partial product sub-module generating the first two rows of partial products uses the first structure, while the selector in the partial product sub-module generating the last two rows of partial products uses the second structure. A fixed operand is used as the multiplier Y, and another operand is used as the multiplicand X, input into the partial product generation module to obtain the following... Figure 14 The partial product array shown is input into the partial product summation module. According to the design method described in Embodiment 2 of the present invention, the compressor (partial product summation module) connection method with the lowest flip-flop rate can be obtained, such as... Figure 17 As shown in the dashed box, fa represents a full adder and ha represents a half adder. The partial product array is summed by the partial product summation module to obtain the final product result F[15:0].

[0277] Figure 18 This is a schematic diagram of the radix-4 Booth encoded 16-bit multiplier structure provided in an embodiment of the present invention. Figure 19 This is a schematic diagram of the partial product generation module of the radix-4 Booth-encoded 16-bit multiplier provided in an embodiment of the present invention. Figure 20 This is a schematic diagram of the partial product summation module of the radix-4 Booth encoded 16-bit multiplier provided in an embodiment of the present invention, as shown below. Figure 18 , Figure 19 and Figure 20 As shown, the 16-bit 4-Booth encoded multiplier provided in this embodiment of the invention includes a partial product generation module and a partial product summation module.

[0278] Partial product generation module: Refer to the partial product generation module described above in the embodiments of the present invention. Since the multiplier is 16 bits, the partial product generation module has eight partial product generation sub-modules. The partial product generation module structure with the lowest flip rate can be calculated, that is, the selector in the partial product sub-module that generates the last two rows of partial products uses, as shown in the example... Figure 10 The selector shown is used in the partial product submodule that generates the partial product of the first six rows, while the selector used in the partial product submodule is as follows: Figure 11 The selector is shown. A fixed operand is used as the multiplier Y, and another operand is used as the multiplicand X. These are input into the partial product generation module to obtain the following result: Figure 14 The partial product array shown is then input into the partial product summation module.

[0279] Partial product summation module: According to the design method provided in the embodiment of the present invention, the compressor connection method with the lowest flip rate can be obtained, as shown in the dashed box, where fa represents a full adder and ha represents a half adder. The partial product array is summed by the partial product summation module to obtain the final product result F[31:0].

[0280] Table 8. Comparison Results

[0281]

[0282]

[0283] Table 8 presents a comparison result table of the embodiments of the present invention. As shown in Table 8, the multiplier provided in the embodiments of the present invention is compared with three existing multipliers. The first comparison object is the multiplier published by Shiann-Rong Kuang et al. in IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II in 2009; the second comparison object is the multiplier published by Panagiotis Sakellariou et al. in IEEE Transaction on Computer in 2016; and the third comparison object is the multiplier published by H. Xue et al. in Electronics Letters in 2018. For the 8-bit multiplier, compared to the best-performing multiplier of the three types, this invention has a 6.78% lower latency, a 0.86% smaller area, a 12.10% lower energy consumption when the input data is random, a 27.65% lower energy consumption when performing AlexNet inference, a 28.74% lower energy consumption when performing VGG16 inference, and a 30.93% lower energy consumption when performing ResNet18 inference. For the 16-bit multiplier, compared to the best-performing multiplier of the three types, this invention has a 1.66% lower latency, a 6.01% smaller area, a 4.18% lower energy consumption when the input data is random, a 41.27% lower energy consumption when performing AlexNet inference, a 44.88% lower energy consumption when performing VGG16 inference, and a 40.35% lower energy consumption when performing ResNet18 inference. Performance comparisons are shown in Table 8. The simulation results for energy consumption, area, and delay are based on SMIC's 40nm logic process and were obtained through design using Verilog hardware description language and synthesis, placement and routing, and simulation using software such as Synopsys Design Compiler, Synopsys IC Compiler, and Synopsys PrimeTime.

[0284] In this embodiment of the invention, based on the characteristic that one operand is fixed and only the other operand is changed during neural network computation, a low-energy-consumption design method based on correlation and flip rate is used. The encoding part of the partial product generation module in the Booth multiplier has no dynamic energy consumption when the input is fixed. Therefore, the fixed operand is used as the multiplier input to the multiplier, while the other operand is used as the multiplicand input to the multiplier. Figure 21 This is a statistical distribution diagram of the weights of a common three-layer neural network provided by this invention, such as... Figure 21 As shown, by analyzing the neural network, we can obtain the statistical characteristic that the weight data of the neural network exhibits a normal distribution. Figure 22 This is a statistical distribution diagram of the feature maps of a common three-layer neural network provided in the embodiments of the present invention, such as... Figure 22 As shown, the feature map data exhibits a semi-normal distribution statistical characteristic; there is a strong correlation between adjacent points in the image data and feature map data. This means that under fixed-point representation, the low-bit flip rate of the weights and feature map data is high, the high-bit flip rate is low, and the probability of the high bits being all 0s and all 1s is high. For the multiplier, since the fixed operands are input to the encoder as multipliers, the flip rate between partial product rows gradually decreases from the first row to the last. Furthermore, due to the strong correlation between the inputs of variable operands, the flip rate between bits in each row of the partial product gradually decreases from low bits to high bits.

[0285] It should be noted that the apparatus provided in this embodiment of the invention can implement all the method steps implemented in the above method embodiment and can achieve the same technical effect. Therefore, the parts and beneficial effects that are the same as those in the method embodiment will not be described in detail here.

[0286] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0287] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for designing a partial product summation module, characterized in that, The partial product summation module includes at least one adder group, each adder group being used to obtain an addition result based on multiple input data to be added, and each adder group including multiple cascaded logic units. The toggle rate of each data to be added corresponding to each adder group is determined; wherein, the toggle rate of each data to be added corresponding to each adder group is determined by Synopsys VCS software; Based on the toggle rate of each of the data to be added, the data connection method of each adder group is determined; the determination of the data connection method of each adder group based on the toggle rate of each of the data to be added includes: inputting the data to be added with a high toggle rate to the subsequent logic unit in the adder group; inputting the data to be added with a low toggle rate to the preceding logic unit in the adder group; or the determination of the data connection method of each adder group based on the toggle rate of each of the data to be added includes: determining the output toggle rate of each logic unit in each candidate data connection method based on the toggle rate of each of the data to be added, the hold rate of each of the data to be added, and the output toggle rate formula; determining the total output toggle rate of each adder group based on the output toggle rate of each logic unit; and selecting the candidate data connection method corresponding to the minimum total output toggle rate as the preferred data connection method; the output toggle rate formula is: ； in, To output the toggle rate, ( () represents the toggle rate of the n inputs of a logic unit from 0 to 1. Let f be the hold rate of the n inputs of the logic unit, which keeps the inputs from 1 to 1, and f be a function determined according to the logic expression of the logic unit.

2. The partial product summation module design method according to claim 1, characterized in that, The method further includes: When the logic function of the logic unit is implemented by multiple candidate logic gates, the logic gate of the logic unit is determined based on the fan-in number of the basic unit in each candidate logic gate.

3. A multiplier, characterized in that, include: Partial product generation module and partial product summation module; The partial product summation module is obtained using the partial product summation module design method as described in any one of claims 1-2; The partial product generation module includes N partial product generation units, each of which includes an encoder and a selector connected in series. The partial product generation module is used to obtain the multiplicand and the multiplier, obtain N partial products based on the multiplicand and the multiplier, and input the N partial products into the partial product summation module. The partial product summation module is used to receive the N partial products input by the partial product generation module, and obtain the product based on the N partial products; Where N is a positive integer greater than or equal to 1.

4. The multiplier according to claim 3, characterized in that, The circuit structure of the first selector to the (N-2)th selector is the first structure, which includes a first XOR gate unit and a first selector unit. The first input terminal of the first XOR gate unit is connected to the multiplicand A, and the second input terminal of the first XOR gate unit is connected to the multiplicand B signal; The first input terminal of the first selector unit is connected to the output terminal of the first XOR gate unit, the second input terminal of the first selector unit is connected to the double signal, and the third input terminal of the first selector unit is connected to the single signal. The circuit structure of the N-1th selector and the Nth selector is the second structure, which includes a second selector unit and a second XOR gate unit. The first input terminal of the second selector unit is connected to the double signal, the second input terminal of the second selector unit is connected to the single signal, and the third input terminal of the second selector unit is connected to the multiplicand A. The first input terminal of the second XOR gate unit is connected to the output terminal of the second selector unit, and the second input terminal of the second XOR gate unit is connected to the NEG signal.

5. The multiplier according to claim 3, characterized in that, The input signal of each encoder includes the first multiplier B. Bit, number Bit and the Bits; the output signal of each encoder includes a single signal, a double signal, and a neg signal; The logical expression for the single signal is: ； The logical expression for the double signal is: ； The logical expression for the neg signal is: ； Where i is a natural number greater than or equal to 0. The multiplier B represents the first... Bit, The multiplier B represents the first... Bit, The multiplier B represents the first... Bit.

6. The multiplier according to claim 5, characterized in that, The input signal of each encoder also includes the 0th bit of the multiplicand A, and the output signal of each encoder also includes the neg_c signal and the s signal; The logical expression for the neg_c signal is: ; The logical expression for the s signal is: ; in, Indicates the neg signal. express Signal, This represents the 0th bit of the multiplicand A.

7. The multiplier according to claim 6, characterized in that, The encoder circuit includes a single signal output circuit, a double signal output circuit, a neg signal output circuit, a sum-bit output circuit, and a carry-out output circuit. The single signal output circuit includes a first XOR gate circuit, and the first input terminal of the first XOR gate circuit is connected to the input signal. The second input terminal of the first XOR gate circuit is connected to the input signal. ; The double signal output circuit includes a first inverter, a second inverter, a third inverter, a first NAND gate, a second NAND gate, and a third NAND gate. The input terminal of the first inverter is connected to the input signal. ; The input terminal of the second inverter is connected to the input signal. ; The input terminal of the third inverter is connected to the input signal. ; The first input terminal of the first NAND gate is connected to the input signal. The second input terminal of the first NAND gate is connected to the input signal. The third input terminal of the first NAND gate is connected to the output terminal of the first inverter; The first input terminal of the second NAND gate is connected to the output terminal of the second inverter, the second input terminal of the second NAND gate is connected to the output terminal of the third inverter, and the third input terminal of the second NAND gate is connected to the input signal. ; The first input terminal of the third NAND gate is connected to the output terminal of the first NAND gate, and the second input terminal of the third NAND gate is connected to the output terminal of the second NAND gate. The NEG signal output circuit includes the second inverter, the third inverter, the first OR gate circuit, and the first AND gate circuit; The first input terminal of the first OR gate circuit is connected to the output terminal of the second inverter, and the second input terminal of the first OR gate circuit is connected to the output terminal of the third inverter. The first input terminal of the first AND gate is connected to the output terminal of the first OR gate, and the second input terminal of the first AND gate is connected to the input signal. ; The bit output circuit includes a second AND gate circuit, the first input terminal of the second AND gate circuit is connected to the output terminal of the first XOR gate circuit, and the second input terminal of the second AND gate circuit is connected to the input signal. ; The carry-out output circuit includes a fourth inverter and a first NOR gate circuit. The input terminal of the fourth inverter is connected to the NEG signal, the first input terminal of the first NOR gate circuit is connected to the output terminal of the fourth inverter, and the second input terminal of the first NOR gate circuit is connected to the output terminal of the second AND gate circuit.

8. The multiplier according to any one of claims 6 or 7, characterized in that, The partial product summation module is used to add the 2Nth bit of the Nth neg_c signal to the partial product output by the first partial product generation unit; Where N is the total number of partial product generating units.

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