Gamma voltage generating circuit and display device including the same

Abstract

A gamma voltage generation circuit and a display apparatus including the same are provided. The display apparatus includes a display unit including a pixel, displaying an image based on a first power voltage and a data signal; a gamma voltage generator generating a plurality of gamma voltages; and a data driver generating the data signal using the gamma voltages, and providing the data signal to the pixel. The gamma voltage generator generates a first reference voltage and a second reference voltage, generates a first corrected reference voltage and a second corrected reference voltage by correcting the first reference voltage and the second reference voltage using a target voltage and an external power voltage provided from the display unit corresponding to the first power voltage, and generates the plurality of gamma voltages by dividing a voltage between the first corrected reference voltage and the second corrected reference voltage. The gamma voltage generator sets the target voltage based on at least one selected from among the first reference voltage, the second reference voltage, and a ground voltage.

Description

[0001] This application claims priority to and all benefits arising therefrom of Korean Patent Application No. 10-2021-0002883, filed on January 8, 2021, the contents of which are fully incorporated herein by reference. Technical Field

[0002] The disclosed embodiments relate to a gamma voltage generation circuit and a display device including the gamma voltage generation circuit. Background Technology

[0003] Display devices typically include a display panel and drivers. The display panel may include scan lines, data lines, and pixels. The drivers may include scan drivers that sequentially provide scan signals to the scan lines and data drivers that provide data signals to the data lines. Each pixel may emit light at a brightness corresponding to the data signal provided to it via the corresponding scan line in response to the scan signal provided to it via the corresponding scan line.

[0004] The gamma voltage generation circuit can generate gamma voltages corresponding to multiple gray levels, and the data driver can use the gamma voltages to convert the gray values ​​of image data into data signals. Summary of the Invention

[0005] The power voltage used to drive the pixels can be provided in the display device. When the power voltage changes (or fluctuates) due to various reasons such as voltage drop and noise, the driving current flowing through the pixels will change, and the pixels may not emit light at the desired brightness.

[0006] The disclosed embodiments provide a gamma voltage generating circuit capable of compensating for changes (or amounts) in electrical voltage, and a display device including the gamma voltage generating circuit.

[0007] In a disclosed embodiment, a display device includes: a display unit including pixels, displaying an image based on a first power voltage and a data signal; a gamma voltage generator generating a plurality of gamma voltages; and a data driver generating a data signal using the plurality of gamma voltages and providing the data signal to the pixels. In such an embodiment, the gamma voltage generator generates a first reference voltage and a second reference voltage, generates a first corrected reference voltage and a second corrected reference voltage by correcting the first and second reference voltages using a target voltage and an external power voltage supplied from the display unit corresponding to the first power voltage, and generates the plurality of gamma voltages by dividing the voltage between the first and second corrected reference voltages. In such an embodiment, the gamma voltage generator sets the target voltage based on at least one selected from the first reference voltage, the second reference voltage, and a ground voltage.

[0008] According to an embodiment, the gamma voltage generator may include a first reference voltage corrector that generates a first target voltage by dividing the voltage between a first reference voltage and a ground voltage, and generates a first corrected reference voltage by correcting the first reference voltage in proportion to the voltage difference between the first target voltage and an external power voltage.

[0009] According to an embodiment, the first reference voltage corrector may include: a first resistor string, which uses a plurality of resistors therein to divide the voltage between the first reference voltage and the ground voltage to generate a plurality of voltages; and a first decoder, which selects and outputs one of the plurality of voltages generated by the first resistor string as the first target voltage.

[0010] According to an embodiment, the first reference voltage corrector may further include: a first amplifier that outputs a first correction reference voltage through its output terminal; a first resistor connected between an external power voltage and a first input terminal of the first amplifier; a second resistor connected between the first reference voltage and the first input terminal of the first amplifier; a third resistor connected between the output terminal of the first decoder and a second input terminal of the first amplifier; and a fourth resistor connected between the second input terminal of the first amplifier and the output terminal of the first amplifier.

[0011] According to an embodiment, the gamma voltage generator may further include a second reference voltage corrector, which generates a second target voltage by dividing the voltage between the second reference voltage and the ground voltage, and generates a second corrected reference voltage by adding the second target voltage to the voltage difference between the external power voltage and the second reference voltage.

[0012] According to an embodiment, the second reference voltage corrector may include: a second resistor string, which uses a plurality of resistors therein to divide the voltage between the second reference voltage and the ground voltage to generate a plurality of voltages; and a second decoder, which selects and outputs one of the plurality of voltages generated by the second resistor string as the second target voltage.

[0013] According to an embodiment, the second reference voltage corrector may further include: a second amplifier that outputs a second corrected reference voltage through its output terminal; a fifth resistor connected between an external power voltage and a first input terminal of the second amplifier; a sixth resistor connected between an output terminal of the second decoder and a first input terminal of the second amplifier; a seventh resistor connected between the second reference voltage and a second input terminal of the second amplifier; and an eighth resistor connected between a second input terminal of the second amplifier and an output terminal of the second amplifier.

[0014] According to an embodiment, the gamma voltage generator may include a first reference voltage corrector that sets a ground voltage as a first target voltage and generates a first corrected reference voltage by correcting the first reference voltage in proportion to the voltage difference between the first target voltage and an external power voltage.

[0015] According to an embodiment, the gamma voltage generator may include a first reference voltage corrector that generates a first target voltage by dividing the voltage between a first reference voltage and a ground voltage, and generates a first corrected reference voltage by correcting the first reference voltage proportionally to an external power voltage and the voltage difference between a first target voltage, a third reference voltage, and a ground voltage. A third reference voltage may be generated together with the first and second reference voltages, and the third reference voltage may have a voltage level lower than the first reference voltage and higher than the second reference voltage.

[0016] According to an embodiment, the first reference voltage corrector may further include a multiplexer that selects and outputs one of a first target voltage, a third reference voltage, and a ground voltage based on a first selection signal.

[0017] According to an embodiment, the first reference voltage corrector may further include: a first amplifier that outputs a first corrected reference voltage through its output terminal; a first resistor connected between an external power voltage and a first input terminal of the first amplifier; a second resistor connected between the first reference voltage and the first input terminal of the first amplifier; a third resistor connected between the output terminal of a multiplexer and a second input terminal of the first amplifier; and a fourth resistor connected between the second input terminal of the first amplifier and the output terminal of the first amplifier.

[0018] According to an embodiment, the first reference voltage corrector may further include: a first resistor string, which uses a plurality of resistors therein to divide the voltage between the first reference voltage and the ground voltage to generate a plurality of voltages; and a first decoder, which selects and outputs one of the plurality of voltages generated by the first resistor string as the first target voltage.

[0019] According to an embodiment, the gamma voltage generator may further include: a second resistor string, which uses a plurality of resistors therein to divide the voltage between the second reference voltage and the ground voltage to generate a plurality of voltages; and a second decoder, which selects and outputs one of the plurality of voltages generated by the second resistor string as a second target voltage; and a multiplexer may select and output one of the first target voltage, the second target voltage, the third reference voltage and the ground voltage based on a first selection signal.

[0020] According to an embodiment, the gamma voltage generator may include a second reference voltage corrector that generates a second target voltage by dividing the voltage between a second reference voltage and a ground voltage, and generates a second corrected reference voltage by using an external power voltage and a corrected second reference voltage selected from the second target voltage and a third reference voltage. The third reference voltage may be generated together with the first and second reference voltages, and the third reference voltage may have a voltage level that is lower than the voltage level of the first reference voltage and higher than the voltage level of the second reference voltage.

[0021] According to an embodiment, the second reference voltage corrector may include: a first multiplexer that selects and outputs one of a second reference voltage and a second target voltage based on a second selection signal; and a second multiplexer that selects and outputs one of a third reference voltage and a second reference voltage based on the second selection signal.

[0022] According to an embodiment, the second reference voltage corrector may further include: a second amplifier that outputs a second corrected reference voltage through its output terminal; a fifth resistor connected between an external power voltage and a first input terminal of the second amplifier; a sixth resistor connected between an output terminal of a first multiplexer and a first input terminal of the second amplifier; a seventh resistor connected between an output terminal of the second multiplexer and a second input terminal of the second amplifier; and an eighth resistor connected between a second input terminal of the second amplifier and an output terminal of the second amplifier.

[0023] According to an embodiment, the second reference voltage corrector may further include: a second resistor string, which uses a plurality of resistors therein to divide the voltage between the second reference voltage and the ground voltage to generate a plurality of voltages; and a second decoder, which selects and outputs one of the plurality of voltages generated by the second resistor string as the second target voltage.

[0024] According to an embodiment, the gamma voltage generator may further include: a first resistor string, which uses a plurality of resistors therein to divide the voltage between a first reference voltage and a ground voltage to generate a plurality of voltages; and a first decoder, which selects and outputs one of the plurality of voltages generated by the first resistor string as a first target voltage; the second selection signal may include a first sub-selection signal and a second sub-selection signal, the first multiplexer may select and output one of a second reference voltage and a second target voltage based on the first sub-selection signal, and the second multiplexer may select and output one of a third reference voltage, a first target voltage, and a second reference voltage based on the second sub-selection signal.

[0025] In a disclosed embodiment, a gamma generation circuit includes: a reference voltage generator that generates a first reference voltage and a second reference voltage based on a source voltage; a first reference voltage corrector that generates a first corrected reference voltage by correcting the first reference voltage using a first target voltage and an external power voltage supplied from the outside corresponding to the first target voltage; a second reference voltage corrector that generates a second corrected reference voltage by correcting the second reference voltage using a second target voltage and an external power voltage; and a gamma voltage output unit that generates a plurality of gamma voltages by dividing the voltage between the first corrected reference voltage and the second corrected reference voltage. In such an embodiment, the first reference voltage corrector sets the first target voltage based on at least one selected from the first reference voltage and a ground voltage.

[0026] According to an embodiment, the first reference voltage corrector can generate a first target voltage by dividing the voltage between the first reference voltage and the ground voltage, and generate a first corrected reference voltage by correcting the first reference voltage in proportion to the voltage difference between the first target voltage and the external power voltage.

[0027] According to an embodiment, the second reference voltage corrector can generate a second target voltage by dividing the voltage between the second reference voltage and the ground voltage, and generate a second corrected reference voltage by adding the second target voltage to the voltage difference between the external power voltage and the second reference voltage.

[0028] According to an embodiment, the first reference voltage corrector can set the ground voltage as a first target voltage and generate a first corrected reference voltage by correcting the first reference voltage in proportion to the voltage difference between the first target voltage and the external power voltage.

[0029] According to an embodiment, the reference voltage generator can also generate a third reference voltage, and the first reference voltage corrector can generate a first target voltage by dividing the voltage between the first reference voltage and the ground voltage, and generate a first corrected reference voltage by correcting the first reference voltage proportionally to an external power voltage and the voltage difference between the first target voltage, the third reference voltage and the ground voltage.

[0030] According to an embodiment, the first reference voltage corrector can generate a first corrected reference voltage by correcting the first reference voltage in proportion to an external power voltage and the voltage difference between a first target voltage, a second target voltage, a third reference voltage, and a ground voltage.

[0031] According to an embodiment, the reference voltage generator can also generate a third reference voltage, and the second reference voltage corrector can generate a second target voltage by dividing the voltage between the second reference voltage and the ground voltage, and generate a second corrected reference voltage by using an external power voltage and a corrected second reference voltage selected from the second target voltage and the third reference voltage.

[0032] According to an embodiment, the second reference voltage corrector can generate a second corrected reference voltage by using an external power voltage and a corrected second reference voltage selected from a first target voltage, a second target voltage, and a third reference voltage.

[0033] In embodiments of the invention, the gamma voltage generation circuit and the display device including the gamma voltage generation circuit can correct a first reference voltage and a second reference voltage related to an external power voltage provided or measured by the display unit corresponding to the power voltage, and generate a gamma voltage based on the first and second correction reference voltages. In such embodiments, the data driver can generate a data signal based on the gamma voltage reflecting changes in the power voltage, and can correct the amount of power voltage change based on the pixel via the gamma voltage. Therefore, a decrease in display quality due to changes in power voltage can be prevented.

[0034] In such an embodiment, the gamma voltage generation circuit and the display device can use at least one selected from a first reference voltage, a second reference voltage, and a ground voltage to set the target voltage, instead of independently setting the target voltage, which serves as a reference for calculating changes in the power voltage, to the first and second reference voltages. Therefore, noise generated during the generation and correction of the first and second reference voltages can be eliminated using a target voltage with similar noise levels, and degradation of display quality can be prevented. Attached Figure Description

[0035] The above and other features of the invention will become clearer by referring to the accompanying drawings, which describe exemplary embodiments of the invention in further detail:

[0036] Figure 1 This is a block diagram illustrating a display device according to a disclosed embodiment;

[0037] Figure 2 It is shown that it includes Figure 1 A circuit diagram of an embodiment of pixels in a display device;

[0038] Figure 3 It is shown that it includes Figure 1 A diagram of an embodiment of a gamma voltage generator in a display device;

[0039] Figure 4 It is shown that it includes Figure 3 A diagram of an embodiment of the first reference voltage corrector in a gamma voltage generator;

[0040] Figure 5 It is shown Figure 4 The waveform of the signal measured by the first reference voltage corrector;

[0041] Figure 6 It is shown that it includes Figure 3 A diagram of an alternative embodiment of the first reference voltage corrector in a gamma voltage generator;

[0042] Figure 7 It is shown Figure 6 The waveform of the signal measured by the first reference voltage corrector;

[0043] Figure 8 It is shown that it includes Figure 3 A diagram of another alternative embodiment of the first reference voltage corrector in the gamma voltage generator;

[0044] Figure 9 It is shown that it includes Figure 3 A diagram of another alternative embodiment of the first reference voltage corrector in the gamma voltage generator;

[0045] Figure 10 It is shown that it includes Figure 3 A diagram of an embodiment of the second reference voltage corrector in a gamma voltage generator;

[0046] Figure 11 It is shown that it includes Figure 3 A diagram of an alternative embodiment of the second reference voltage corrector in a gamma voltage generator;

[0047] Figure 12 It is shown that it includes Figure 3 A diagram of another alternative embodiment of the second reference voltage corrector in the gamma voltage generator;

[0048] Figure 13 and Figure 14 It is shown that it includes Figure 3 A diagram of yet another alternative embodiment of the first reference voltage corrector in the gamma voltage generator; and

[0049] Figure 15 and Figure 16 It is shown that it includes Figure 3 A diagram of another alternative embodiment of the second reference voltage corrector in the gamma voltage generator. Detailed Implementation

[0050] The invention will now be described more fully below with reference to the accompanying drawings, in which various embodiments are illustrated. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0051] It will be understood that when an element is referred to as being "on" another element, the element may be directly on the other element, or there may be an intermediary element between the element and the other element. Conversely, when an element is referred to as being "directly on" another element, there is no intermediary element.

[0052] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, without departing from the teaching herein, “first element,” “first component,” “first region,” “first layer,” or “first part” discussed below may be referred to as a second element, second component, second region, second layer, or second part.

[0053] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, “a,” “an,” “the,” and “at least one” do not indicate a limitation of quantity and are intended to include both the singular and the plural. For example, unless the context clearly indicates otherwise, “element” has the same meaning as “at least one element.” “At least one” should not be construed as limited to “a” or “an.” “Or” means “and / or”. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that when the terms “comprising” and / or “including” are used in this specification, they indicate the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or combinations thereof.

[0054] Furthermore, relative terms (such as “below” or “bottom” and “above” or “top”) may be used here to describe the relationship between one element and another (other) element as shown in the accompanying drawings. It will be understood that relative terms are intended to encompass different orientations of the device other than those depicted in the drawings. For example, if the device in one of the drawings is flipped, then the element described as being “below” the other element will subsequently be positioned “above” the other element. Thus, depending on the specific orientation of the drawing, the term “below” can encompass both “below” and “above” orientations. Similarly, if the device in one of the drawings is flipped, then the element described as being “below” or “under” the other element will subsequently be positioned “above” the other element. Thus, the term “below” or “under” can encompass both “above” and “below” orientations.

[0055] As used herein, “about” or “approximately” includes the stated value and means: within an acceptable range of deviation from the stated value, as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0056] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in a general dictionary) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and in this disclosure, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0057] The embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but will include deviations in shape caused, for example, by manufacturing processes. For instance, regions shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, sharp corners (acute angles) shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the precise shapes of the regions, nor are they intended to limit the scope of this claim.

[0058] As is customary in the art, some embodiments of functional blocks, units, and / or modules are described and illustrated in the accompanying drawings. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented using electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc.) formed using semiconductor-based or other manufacturing techniques. Where blocks, units, and / or modules are implemented using microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can be optionally driven by firmware and / or software. It is also contemplated that each block, unit, and / or module can be implemented using dedicated hardware, or as a combination of dedicated hardware performing some functions and processors performing other functions (e.g., one or more programmed microprocessors and associated circuitry). Furthermore, without departing from the scope of the invention, each block, unit, and / or module of some exemplary embodiments may be physically divided into two or more interacting and discrete blocks, units, and / or modules. Furthermore, without departing from the scope of the invention, blocks, units, and / or modules of some exemplary embodiments may be physically combined into more complex blocks, units, and / or modules.

[0059] Furthermore, in the accompanying drawings, some components not directly related to the disclosed features may be omitted for clarity. Additionally, some components in the drawings may be shown exaggerated in size or scale. Throughout the drawings, even if the same or similar components are shown in different drawings, they will be represented by the same reference numerals and symbols as much as possible, and redundant descriptions will be omitted.

[0060] In the following description, embodiments of the invention will be described in detail with reference to the accompanying drawings.

[0061] Figure 1 This is a block diagram illustrating a display device according to a disclosed embodiment.

[0062] Reference Figure 1 An embodiment of the display device 100 may include a display unit 110 (or a display panel), a scan driver 120 (or a gate driver), a data driver 130 (or a source driver), a timing controller 140, a gamma voltage generator 150 (or a gamma voltage generation circuit), and a power supply 160.

[0063] Display unit 110 can display an image. Display unit 110 may include scan lines (or gate lines) SL1 to SLn (where n is a positive integer), data lines DL1 to DLm (where m is a positive integer) and pixels PXL. In one embodiment, for example, each pixel PXL may be disposed in an area (e.g., a pixel region) defined or divided by scan lines SL1 to SLn and data lines DL1 to DLm.

[0064] Each pixel PXL can be connected to a corresponding scan line among scan lines SL1 to SLn and a corresponding data line among data lines DL1 to DLm. In one embodiment, for example, a pixel PXL located in the i-th row and j-th column can be connected to the i-th scan line SL1 and the j-th data line DLj (where i and j are both positive integers, and i ≤ n, j ≤ m). However, the pixel PXL is not limited to this; alternatively, for example, the pixel PXL can be electrically connected to the scan line corresponding to the adjacent row (e.g., the scan line corresponding to the row preceding the row including the pixel PXL and the scan line corresponding to the row following the row including the pixel PXL). In an embodiment, the pixel PXL can be electrically connected between a first power line to which a first power voltage ELVDD is applied and a second power line to which a second power voltage ELVSS is applied. In such an embodiment, the first power voltage ELVDD and the second power voltage ELVSS can be driving voltages for the operation of the pixel PXL, and the first power voltage ELVDD can have a higher voltage level than the second power voltage ELVSS. The first power voltage ELVDD and the second power voltage ELVSS can be supplied to the display unit 110 from the power supply 160.

[0065] Pixel PXL can store or write data signals (or data voltages) provided to it via the j-th data line DLj in response to a scan signal provided to it via the i-th scan line SLi, and can emit light with a brightness corresponding to the stored data signal. (See below for further details.) Figure 2 Describes the detailed configuration (construction) of pixel PXL.

[0066] The first power voltage ELVDD and the second power voltage ELVSS can be provided to the display unit 110.

[0067] The scan driver 120 can generate scan signals based on the scan control signal SCS and sequentially provide the scan signals to scan lines SL1 to SLn. In an embodiment, the scan control signal SCS may include a start signal, a clock signal, etc., and may be provided to the scan driver 120 from the timing controller 140. In one embodiment, for example, the scan driver 120 may include a shift register that sequentially generates and outputs scan signals of a certain pulse type by using a clock signal to sequentially shift a start signal of a certain pulse type.

[0068] The data driver 130 can generate a data signal (or data voltage) based on the image data DATA2 and the data control signal DCS provided from the timing controller 140, and provide the data signal to the display unit 110 (or pixel PXL). In an embodiment, the data control signal DCS can be a signal that controls the operation of the data driver 130, and may include a load signal (or data enable signal) indicating the output of a valid data signal, a level start signal, a data clock signal, etc.

[0069] The data driver 130 can select a gamma voltage (or grayscale voltage) from the gamma voltage VGS (or grayscale voltage) that corresponds to the grayscale value (or data value) in the image data DATA2, and output the selected gamma voltage as a data signal. Here, the gamma voltage VGS can be provided to the data driver 130 from the gamma voltage generator 150.

[0070] In one embodiment, for example, data driver 130 may include a shift register, a latch, a digital-to-analog converter (or decoder), and a buffer (or amplifier). The shift register generates a sampling signal by shifting a level signal in sync with a data clock signal. The latch latches image data DATA2 in response to the sampling signal. The digital-to-analog converter (or decoder) converts the latched image data (e.g., digital data) into an analog data signal using a gamma voltage VGS. The buffer (or amplifier) ​​outputs the data signal to data lines DL1 to DLm.

[0071] The timing controller 140 can receive input image data DATA1 and a control signal CS from an external device (e.g., a graphics processor), generate a scan control signal SCS and a data control signal DCS based on the control signal CS, and generate image data DATA2 by converting the input image data DATA1. In an embodiment, the control signal CS may include a vertical synchronization signal, a horizontal synchronization signal, a reference clock signal, etc. The vertical synchronization signal may indicate the start of frame data (i.e., data corresponding to a frame period in which a frame of image is displayed), and the horizontal synchronization signal may indicate the start of a data line (i.e., one of a plurality of data lines included in the frame data). In one embodiment, for example, the timing controller 140 may convert the input image data DATA1 in RGB format into image data DATA2 in RGBG format corresponding to the pixel arrangement in the display unit 110.

[0072] Gamma voltage generator 150 can generate a gamma voltage VGS. In one embodiment, for example, gamma voltage generator 150 can use a first source voltage VLIN1 to generate a first reference voltage and a second reference voltage, and generate gamma voltage VGS by dividing the voltage between the first reference voltage and the second reference voltage using a resistor string. In one embodiment, the first source voltage VLIN1 can be provided from power supply 160. In one embodiment, for example, the first source voltage VLIN1 can have the same voltage level as the first power voltage ELVDD provided to display unit 110, but is not limited thereto. In one embodiment, for example, the first source voltage VLIN1 can be provided from data driver 130, or the first source voltage VLIN1 can have a voltage level different from the voltage level of the first power voltage ELVDD.

[0073] In one embodiment, the gamma voltage generator 150 can generate a gamma voltage VGS based on an external power voltage ELVDD_EXT. In another embodiment, the external power voltage ELVDD_EXT can be provided from the display unit 110, and can be a value obtained by measuring a first power voltage ELVDD supplied to the display unit 110. In one embodiment, for example, the external power voltage ELVDD_EXT can be provided to the gamma voltage generator 150 via wiring connected to the other side of the display unit 110.

[0074] Please refer to later Figure 3 This describes the detailed configuration and operation of the Gamma Voltage Generator 150.

[0075] Power supply 160 can supply a first power voltage ELVDD and a second power voltage ELVSS to display unit 110. Additionally, power supply 160 can supply a first source voltage VLIN1 to gamma voltage generator 150. Power supply 160 can be implemented as a power management integrated circuit (“PMIC”). The first power voltage ELVDD can be provided to one side of display unit 110. Due to the resistance of the internal wiring of display unit 110 and the capacitance generated between the wirings, the first power voltage ELVDD provided to the opposite side of display unit 110 can have a lower value than the first power voltage ELVDD provided to the opposite side of display unit 110.

[0076] At least one of the scan driver 120, data driver 130, timing controller 140, and gamma voltage generator 150 may be disposed on or formed on display unit 110, or may be implemented as an integrated circuit and connected to display unit 110 in a package type. In an embodiment, at least two of the scan driver 120, data driver 130, timing controller 140, and gamma voltage generator 150 may be implemented as a single integrated circuit. In one embodiment, for example, gamma voltage generator 150 may be included in data driver 130, or gamma voltage generator 150 and data driver 130 may be implemented as a single integrated circuit. As another example, data driver 130 and timing controller 140 may be implemented as a single integrated circuit.

[0077] Figure 2 It is shown that it includes Figure 1 A circuit diagram of an embodiment of pixels in a display device.

[0078] Reference Figure 1 and Figure 2 In an embodiment of pixel PXL, the i-th scan line SLi and the j-th data line DLj can be connected.

[0079] Pixel PXL may include a light-emitting element LD, a first transistor T1, a second transistor T2, and a storage capacitor Cst.

[0080] The first electrode (e.g., the anode electrode) of the light-emitting element LD can be connected to a first electric field line PL1 via a first transistor T1, and the second electrode (e.g., the cathode electrode) of the light-emitting element LD can be connected to a second electric field line PL2. A first electric field voltage ELVDD can be applied to the first electric field line PL1, and a second electric field voltage ELVSS can be applied to the second electric field line PL2. The light-emitting element LD may include an organic light-emitting diode, or may be constructed from an inorganic light-emitting diode such as a micro light-emitting diode (“LED”) or a quantum dot LED. In embodiments, the light-emitting element LD may be a light-emitting diode comprising both organic and inorganic materials.

[0081] The first electrode of the first transistor T1 (or driving transistor) can be connected to the first power line PL1, and the second electrode of the first transistor T1 can be connected to the first electrode of the light-emitting element LD. The gate electrode of the first transistor T1 can be connected to the first node N1. The first transistor T1 can control the amount of driving current supplied to the light-emitting element LD according to the voltage of the first node N1.

[0082] The first electrode of the second transistor T2 (or the switching transistor) can be connected to the j-th data line DLj, and the second electrode of the second transistor T2 can be connected to the first node N1. The gate electrode of the second transistor T2 can be connected to the i-th scan line SLi.

[0083] A storage capacitor Cst can be formed or connected between the first node N1 and the first power line PL1. In one embodiment, for example, one electrode of the storage capacitor Cst can be connected to the first node N1, and the other electrode of the storage capacitor Cst can be connected to the first power line PL1. The storage capacitor Cst can be charged with a voltage corresponding to a frame of data signal supplied to the first node N1, and can maintain the charging voltage until the next frame of data signal is supplied.

[0084] When a scan signal at a conduction level (low level) is supplied to the gate electrode of the second transistor T2 through the i-th scan line SL1, the second transistor T2 can connect one electrode of the j-th data line DLj and the storage capacitor Cst. Therefore, a voltage corresponding to the difference between the data signal (or data voltage) applied through the j-th data line DLj and the first power voltage ELVDD can be written to the storage capacitor Cst. In an embodiment, the data signal can correspond to a gamma voltage VGS selected from the gamma voltage VGS.

[0085] The first transistor T1 allows a drive current, determined by the voltage written to the storage capacitor Cst, to flow from the first power line PL1 to the second power line PL2. The light-emitting element LD emits light with a brightness corresponding to the amount of drive current.

[0086] For ease of description, Figure 2 An embodiment of a pixel circuit with a relatively simple structure is shown, which includes a second transistor T2 for transmitting a data signal to a pixel PXL, a storage capacitor Cst for storing the data signal, and a first transistor T1 for supplying a drive current corresponding to the data signal to a light-emitting element LD.

[0087] However, the disclosure is not limited thereto, and various changes or modifications can be made to the structure of the pixel circuit. In an alternative embodiment, for example, the pixel circuit may also include various transistors, such as a compensation transistor for compensating the threshold voltage of the first transistor T1, an initialization transistor for initializing the anode electrode of the first node N1 or the light-emitting element LD, and / or a light-emitting control transistor for controlling the light-emitting time of the light-emitting element LD.

[0088] In an embodiment, such as Figure 2As shown, the first transistor T1 and the second transistor T2 are P-type transistors, but are not limited thereto, and in an alternative embodiment, for example, the pixel PXL may include an N-type transistor.

[0089] Figure 3 It is shown that it includes Figure 1 A diagram of an embodiment of a gamma voltage generator in a display device.

[0090] Reference Figure 3 An embodiment of the gamma voltage generator 150 may include a reference voltage generator 210, a reference voltage corrector, and a gamma voltage output unit 240.

[0091] In one embodiment, the reference voltage generator 210 may generate and output a first reference voltage VREG1 and a second reference voltage VREF1 based on a first source voltage VLIN1. In such an embodiment, the voltage level of the first reference voltage VREG1 may be higher than the voltage level of the first power voltage ELVDD, and the voltage level of the second reference voltage VREF1 may be lower than the voltage level of the second power voltage ELVSS. In one embodiment, for example, the voltage level of the first reference voltage VREG1 may be about 5.7 volts (V), and the voltage level of the second reference voltage VREF1 may be about 0.5V. However, the disclosure is not limited thereto. In an alternative embodiment, for example, the voltage level of the first reference voltage VREG1 may be lower than the voltage level of the first power voltage ELVDD.

[0092] In an embodiment, the reference voltage generator 210 may output a third reference voltage NELVDD (or a reference target voltage). The third reference voltage NELVDD may correspond to a first power voltage ELVDD. In one embodiment, for example, the third reference voltage NELVDD may be the target voltage of the first power voltage ELVDD, that is, the target voltage of the first power voltage ELVDD used to normally drive the pixels PXL of the display unit 110. The third reference voltage NELVDD may be generated together with the first reference voltage VREG1 and the second reference voltage VREF1. The voltage level of the third reference voltage NELVDD may be lower than the voltage level of the first reference voltage VREG1 and higher than the voltage level of the second reference voltage VREF1. In one embodiment, for example, the voltage level of the third reference voltage NELVDD may be approximately 2.8V.

[0093] The voltage level of each of the first reference voltage VREG1, the second reference voltage VREF1, and the third reference voltage NELVDD can be predetermined through a gamma voltage setting process (process) performed during product manufacturing. During the gamma voltage setting process, the display device 100 can be connected to a separate testing device other than the power supply 160, and can receive a test power voltage (e.g., the first power voltage ELVDD) from the testing device. The voltage level of each of the first reference voltage VREG1, the second reference voltage VREF1, and the third reference voltage NELVDD can be set corresponding to the test power voltage.

[0094] In an embodiment, the reference voltage generator 210 may include a first reference voltage generation circuit 211 that outputs a first reference voltage VREG1, a second reference voltage generation circuit 212 that outputs a second reference voltage VREF1, and a third reference voltage generation circuit 213 (or target voltage generation circuit) that outputs a third reference voltage NELVDD. According to an optional embodiment, the third reference voltage generation circuit 213 may be omitted.

[0095] In one embodiment, the reference voltage generator 210 may use a series of resistors connected between a first source voltage VLIN1 (or the first source, the line to which the first source voltage VLIN1 is applied) and a second source voltage VSSA_REF (or the second source, the line to which the second source voltage VSSA_REF is applied) to output multiple divided voltages. In one embodiment, the second source voltage VSSA_REF may be ground, but is not limited thereto. In such an embodiment, the first reference voltage generation circuit 211 may use a decoder to select one of the multiple divided voltages and use a buffer to non-invert-amplify said one of the multiple divided voltages to output the amplified voltage as the first reference voltage VREG1. The buffer may include an amplifier and resistors, wherein said one divided voltage may be applied to the non-inverting terminal (+) of the amplifier, one of the resistors may be connected between the inverting terminal (-) of the amplifier and the output terminal, and another of the resistors may be connected between the inverting terminal (-) of the amplifier and the second source voltage VSSA_REF. The amplifier can receive a first source voltage VLIN1 and a third source voltage VSSA as drive power. In one embodiment, for example, the third source voltage VSSA can be the same as the second source voltage VSSA_REF, but is not limited thereto.

[0096] In such an embodiment, the second reference voltage generation circuit 212 can use a decoder to select another voltage divider from a plurality of voltage dividers, and use a buffer to amplify the other voltage divider non-invertingly, so as to output the non-inverted amplified voltage as the second reference voltage VREF1. The third reference voltage generation circuit 213 can use a decoder to select yet another voltage divider from a plurality of voltage dividers, and use a buffer to amplify the yet another voltage divider non-invertingly, so as to output the non-inverted amplified voltage as the third reference voltage NELVDD. Each configuration of the second reference voltage generation circuit 212 and the third reference voltage generation circuit 213 can be substantially the same as or similar to the configuration of the first reference voltage generation circuit 211.

[0097] In an embodiment, the reference voltage corrector can generate a first corrected reference voltage AVC_VREG1 and a second corrected reference voltage AVC_VREF1 by using an external power voltage ELVDD_EXT and its corresponding target voltage to correct a first reference voltage VERG1 and a second reference voltage VREF1. In such an embodiment, the first corrected reference voltage AVC_VREG1 may be equal to the maximum gamma voltage GAMMA_TOP (e.g., the gamma voltage corresponding to the minimum grayscale) in the gamma voltages VGS. The second corrected reference voltage AVC_VREF1 may be equal to the minimum gamma voltage GAMMA_BOTTOM (e.g., the gamma voltage corresponding to the maximum grayscale) in the gamma voltages VGS.

[0098] The reference voltage corrector can use the third reference voltage NELVDD generated by the reference voltage generator 210 as the target voltage, or set the target voltage based on at least one selected from the first reference voltage VREG1, the second reference voltage VREF1, and the second source voltage VSSA_REF.

[0099] The reference voltage corrector may include a first reference voltage corrector 220 (or a first reference voltage corrector block) and a second reference voltage corrector 230 (or a second reference voltage corrector block).

[0100] In one embodiment, the first reference voltage corrector 220 can output or generate a first corrected reference voltage AVC_VREG1 by associating a first reference voltage VREG1 with an external power voltage ELVDD_EXT. In such an embodiment, the first reference voltage corrector 220 can generate the first corrected reference voltage AVC_VREG1 by correcting the first reference voltage VREG1 based on the external power voltage ELVDD_EXT. In one embodiment, for example, the first reference voltage corrector 220 can generate the first corrected reference voltage AVC_VREG1 by reflecting the direct current offset and alternating current fluctuation of the external power voltage ELVDD_EXT onto the first reference voltage VREG1.

[0101] In an embodiment, the first reference voltage corrector 220 can output a first corrected reference voltage AVC_VREG1 by setting a target voltage corresponding to one of the first reference voltage VREG1, the third reference voltage NELVDD, and the second source voltage VSSA_REF, and reflecting the difference between the target voltage and the external power voltage ELVDD_EXT in the first reference voltage VREG1.

[0102] In the display device 100, the first power voltage ELVDD supplied from the power supply 160 to the display unit 110 may deviate from the test power voltage of the test device used in the gamma voltage setting process. During the gamma voltage setting process, for example, the resistance of the connector used to connect the display device 100 and the test device and the resistance of the connector used to connect the display unit 110 and the power supply 160 may differ from each other.

[0103] Furthermore, when actually applied to Figure 2 When the first power voltage ELVDD of the pixel PXL changes due to various reasons such as wiring resistance and capacitance between wirings, the desired drive current may not be able to flow through the light-emitting element LD in the pixel PXL, and the display quality of the display device 10 will be reduced.

[0104] Therefore, in an embodiment of the invention, the first reference voltage corrector 220 can generate a first corrected reference voltage AVC_VREG1 by correcting the first reference voltage VREG1 based on the target voltage and the external power voltage ELVDD_EXT provided from the display unit 110 corresponding to the first power voltage ELVDD.

[0105] The first reference voltage corrector 220 may include a first input terminal IN1, a second input terminal IN2, a third input terminal IN3, and a fourth input terminal IN4 (or may be connected to a first input node, a second input node, a third input node, and a fourth input node). An external power voltage ELVDD_EXT may be applied to the first input terminal IN1 (or the first input node), a first reference voltage VREG1 may be applied to the second input terminal IN2 (or the second input node), a third reference voltage NELVDD may be applied to the third input terminal IN3 (or the third input node), and a second source voltage VSSA_REF may be applied to the fourth input terminal IN4 (or the fourth input node). The first corrected reference voltage AVC_VREG1 may be output through the output terminal OUT (or the first output node) of the first reference voltage corrector 220. According to an embodiment, at least one of the third input terminal IN3 and the fourth input terminal IN4 may be omitted.

[0106] Please refer to later Figures 4 to 9 , Figure 13 and Figure 14 The configuration and operation of the first reference voltage corrector 220 will be described in more detail below.

[0107] In one embodiment, the second reference voltage corrector 230 can output a second corrected reference voltage AVC_VREF1 by associating the second reference voltage VREF1 with an external power supply voltage ELVDD_EXT. In such an embodiment, the second reference voltage corrector 230 can output a second corrected reference voltage AVC_VREF1 by correcting the second reference voltage VREF1 based on the external power supply voltage ELVDD_EXT.

[0108] In an embodiment, the second reference voltage corrector 230 can output a second corrected reference voltage AVC_VREF1 by setting a target voltage corresponding to the second reference voltage VREF1 or the third reference voltage NELVDD and reflecting the difference between the target voltage and the external power voltage ELVDD_EXT in the second reference voltage VREF1.

[0109] The second reference voltage corrector 230 may include a first input terminal IN1, a second input terminal IN2, and a third input terminal IN3 (or may be connected to a first input node, a fifth input node, and a third input node). An external power voltage ELVDD_EXT may be applied to the first input terminal IN1 (or the first input node), a second reference voltage VREF1 may be applied to the second input terminal IN2 (or the fifth input node), and a third reference voltage NELVDD may be applied to the third input terminal IN3 (or the third input node). The second corrected reference voltage AVC_VREF1 can be output through the output terminal OUT (or the second output node) of the second reference voltage corrector 230. According to an embodiment, the third input terminal IN3 may be omitted.

[0110] Please refer to later Figures 10 to 12 , Figure 15 and Figure 16 The configuration and operation of the second reference voltage corrector 230 will be described in more detail below.

[0111] The gamma voltage output unit 240 can divide the voltage between the first correction reference voltage AVC_VREG1 and the second correction reference voltage AVC_VREF1 to output the gamma voltage VGS.

[0112] The gamma voltage output unit 240 may include a gamma resistor string RST_GAMMA.

[0113] The gamma resistor string RST_GAMMA may include or be composed of multiple resistors connected in series, and the voltage between the first correction reference voltage AVC_VREG1 and the second correction reference voltage AVC_VREF1 may be divided by the resistors. At least some of the voltage divisions can be output as the gamma voltage VGS. In one embodiment, for example, the gamma resistor string RST_GAMMA may divide the voltage between the first correction reference voltage AVC_VREG1 and the second correction reference voltage AVC_VREF1 into 2048 voltages or voltages with 2048 different levels. In one embodiment, for example, the resistors may have the same resistance value, and the voltage division (or gamma voltage VGS) may be linear or may have equal intervals. In an alternative embodiment, for example, the resistors may have different resistance values, and the voltage division (or gamma voltage VGS) may be non-linear and may have a gamma characteristic (or gamma value) of, for example, 2.2.

[0114] In an embodiment, such as Figure 3As shown, the gamma voltage output unit 240 may include, but is not limited to, a single gamma resistor string RST_GAMMA. In an alternative embodiment, for example, the gamma voltage output unit 240 may include two resistor strings, a decoder (or multiplexer), and a gamma amplifier. The voltage between the first correction reference voltage AVC_VREG1 and the second correction reference voltage AVC_VREF1 can be divided by the first resistor string, reference gamma voltages can be selected by the decoder (e.g., 10 reference gamma voltages), reference gamma voltages can be output by the gamma amplifier, and the reference gamma voltages can be divided into multiple voltages (e.g., 2048 voltages) by the second resistor string. The gamma voltage output unit 240 may have various structures configured or designed to generate multiple gamma voltages VGS using two reference voltages (e.g., the first correction reference voltage AVC_VREG1 and the second correction reference voltage AVC_VREF1).

[0115] The gamma voltage VGS can be provided to the data driver 130. The digital-to-analog converter (DAC) of the data driver 130 can select one of the gamma voltages VGS corresponding to the grayscale value (or data value) in the image data DATA2, and the buffer SC_AMP (or source amplifier) ​​of the data driver 130 can output the gamma voltage as a data signal.

[0116] Here, the reference voltage generator 210, the first reference voltage corrector 220, the second reference voltage corrector 230, and the gamma voltage output unit 240 can be conceptually divided based on specific nodes in the gamma voltage generator 150 (e.g., input terminals IN1, IN2, IN3, and IN4, and the node corresponding to the output terminal OUT). According to an embodiment, the first reference voltage corrector 220 and the second reference voltage corrector 230 can be referred to as a single reference voltage corrector. According to an embodiment, the first reference voltage generation circuit 211 and the first reference voltage corrector 220 can be referred to as the first reference voltage generator, and the second reference voltage generation circuit 212 and the second reference voltage corrector 230 can be referred to as the second reference voltage generator.

[0117] Figure 4 It is shown that it includes Figure 3 A diagram of an embodiment of the first reference voltage corrector in a gamma voltage generator. Figure 5 It is shown Figure 4 The waveform of the signal measured by the first reference voltage corrector.

[0118] Reference Figure 3 , Figure 4 and Figure 5An embodiment of the first reference voltage corrector 220_1 may include a first amplifier AMP1 (or differential amplifier), a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4. The first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 may have the same resistance value as each other, but are not limited thereto. In such an embodiment, each of the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 may correspond to a line resistance or may be composed of individual components.

[0119] The first amplifier AMP1 can receive a first source voltage VLIN1 and a third source voltage VSSA as driving power, and for example, the third source voltage VSSA can be the same as the second source voltage VSSA_REF, but is not limited thereto.

[0120] A first resistor R1 can be connected between the first input terminal IN1 (or the first input node) and the non-inverting terminal (+) (or the first terminal) of the first amplifier AMP1, and a second resistor R2 can be connected between the second input terminal IN2 (or the second input node) and the non-inverting terminal (+) of the first amplifier AMP1. An external power supply voltage ELVDD_EXT can be applied to the first input terminal IN1, and a first reference voltage VREG1 can be applied to the second input terminal IN2. In such an embodiment, the intermediate value (or average value) of the external power supply voltage ELVDD_EXT and the first reference voltage VREG1 can be applied to the non-inverting terminal (+) of the first amplifier AMP1.

[0121] The third resistor R3 can be connected between the third input terminal IN3 (or the third input node) and the inverting terminal (-) (or the second terminal) of the first amplifier AMP1. The fourth resistor R4 can be connected between the inverting terminal (-) of the first amplifier AMP1 and the output terminal OUT (or the first output node) of the first amplifier AMP1. The third reference voltage NELVDD can be applied to the third input terminal IN3.

[0122] In such an embodiment, the first reference voltage corrector 220_1 can output a first corrected reference voltage AVC_VREG1 according to the following Equation 1.

[0123] [Equation 1]

[0124] AVC_VREG1=(NELVDD-ELVDD_EXT)+VREG1

[0125] In other words, the first correction reference voltage AVC_VREG1 can be proportional to or directly proportional to the value obtained by adding the voltage difference between the third reference voltage NELVDD and the external power voltage ELVDD_EXT to the first reference voltage VREG1. In such an embodiment, the first reference voltage VREG1 can be corrected based on the DC offset and AC fluctuation of the external power voltage ELVDD_EXT. In such an embodiment, the gamma voltage output unit 240 can generate a gamma voltage VGS based on the first correction reference voltage AVC_VREG1, which reflects the fluctuation of the external power voltage ELVDD_EXT, and the data driver 130 can generate a data signal based on the gamma voltage VGS, which reflects the fluctuation of the external power voltage ELVDD_EXT. Therefore, Figure 2 The pixel PXL can emit light with the desired brightness and can effectively prevent the display quality of the display device 100 from being reduced due to fluctuations in the external power voltage ELVDD_EXT (or the first power voltage ELVDD).

[0126] However, as Figure 5 As shown, when the phase and amplitude (or magnitude) of the first reference voltage VREG1 differ from the phase and amplitude of the third reference voltage NELVDD, noise is included in the first corrected reference voltage AVC_VREG1. In one embodiment, for example, due to the first reference voltage generation circuit 211 (refer to...) Figure 3 The buffer and the third reference voltage generation circuit 213 (refer to) Figure 3 Due to differences in the characteristics of the buffers, the phase of the first reference voltage VREG1 may differ from the phase of the third reference voltage NELVDD.

[0127] For example, the third reference voltage NELVDD can be approximately 2.8V, the external power voltage ELVDD_EXT can be approximately 2.8V, and the first reference voltage VREG1 can be approximately 5.7V. The phase and amplitude of the third reference voltage NELVDD may differ from the phase and amplitude of the external power voltage ELVDD_EXT. In this case, according to Equation 1, the first corrected reference voltage AVC_VREG1 can be “5.7V + α (i.e., noise)” (i.e., 2.8V - 2.8V + 5.7V + α). Figure 5 As shown, the first corrected reference voltage AVC_VREG1_REAL actually output from the first reference voltage corrector 220_1 will include noise in the form of AC, which is different from the desired form of the first corrected reference voltage AVC_VREG1_IDEAL (i.e., DC form).

[0128] Therefore, when the phase and amplitude (or magnitude) of the first reference voltage VREG1 are different from the phase and amplitude of the third reference voltage NELVDD, the first reference voltage corrector 220 (referencing) Figure 3 The noise generated during the process of associating the first reference voltage VREG1 with the external power voltage ELVDD_EXT can be removed by using at least one of the first reference voltage VREG1 and the second source voltage VSSA_REF.

[0129] Figure 6 It is shown that it includes Figure 3 A diagram of an alternative embodiment of the first reference voltage corrector in a gamma voltage generator. Figure 7 It is shown Figure 6 The waveform of the signal measured by the first reference voltage corrector.

[0130] Reference Figure 3 , Figure 4 , Figure 6 and Figure 7 ,and Figure 4 Compared to the first reference voltage corrector 220_1, Figure 6 An embodiment of the first reference voltage corrector 220_2 may also include a resistor string RST and a decoder DEC. In addition to the resistor string RST and the decoder DEC, Figure 6 The first reference voltage corrector 220_2 and Figure 4 The first reference voltage corrector 220_1 is similar, therefore any repeated detailed descriptions of its identical or similar components will be omitted below.

[0131] A resistor string RST (or a first resistor string) can be used to divide the voltage between the first reference voltage VREG1 and the second source voltage VSSA_REF using multiple resistors connected between the second input terminal IN2 and the second source voltage VSSA_REF. The decoder DEC (or the first decoder) can select and output one of the voltage divisions as the first target voltage NVREG1. A third resistor R3 can be connected between the output terminal of the decoder DEC and the inverting terminal (-) of the first amplifier AMP1. The first target voltage NVREG1 can be set to have a DC component substantially the same as the third reference voltage NELVDD through the control of the decoder DEC, and when the first target voltage NVREG1 is generated based on the first reference voltage VREG1, the first target voltage NVREG1 can have a phase (and amplitude) similar to the first reference voltage VREG1. That is, replacing... Figure 4The third reference voltage NELVDD shown generates a first target voltage NVREG1 with a phase (and magnitude) similar to that of the first reference voltage VREG1, and the first target voltage NVREG1 can be applied to Equation 1.

[0132] In such an embodiment, such as Figure 7 As shown, the first corrected reference voltage AVC_VREG1_REAL, actually output from the first reference voltage corrector 220_2, can become similar to the desired first corrected reference voltage AVC_VREG1_IDEAL (i.e., a voltage in DC form), or it can become flat. That is, noise in the first reference voltage VREG1 can be removed.

[0133] In the embodiments, as referred to Figure 6 and Figure 7 As described, the first reference voltage corrector 220_2 can generate a first target voltage NVREG1 with noise similar to that of the first reference voltage VREG1 by dividing the first reference voltage VREG1, and generate a first corrected reference voltage AVC_VREG1 using the first reference voltage VREG1, the external power supply voltage ELVDD_EXT, and the first target voltage NVREG1. That is, the first reference voltage corrector 220_2 can generate the first corrected reference voltage AVC_VREG1 by correcting the first reference voltage VREG1 proportionally or directly proportionally to the voltage difference between the first target voltage NVREG1 and the external power supply voltage ELVDD_EXT. Therefore, the first corrected reference voltage AVC_VREG1 can be correlated with the external power supply voltage ELVDD_EXT, and the noise of the first reference voltage VREG1 can be removed using the first target voltage NVREG1.

[0134] Figure 8 It is shown that it includes Figure 3 A diagram of another alternative embodiment of the first reference voltage corrector in the gamma voltage generator.

[0135] Reference Figure 3 , Figure 4 , Figure 7 and Figure 8 In addition to the connection configuration of the third resistor R3, Figure 8 The first reference voltage corrector 220_3 can be used with Figure 4 The first reference voltage corrector 220_1 is substantially the same as or similar to this one. Therefore, any repeated detailed descriptions of the same or similar components will be omitted below.

[0136] In this embodiment, the third resistor R3 can be connected between the fourth input terminal IN4 (or the fourth input node) and the inverting terminal (-) of the first amplifier AMP1. The second source voltage VSSA_REF can be applied to the fourth input terminal IN4. Here, the second source voltage VSSA_REF can be ground voltage. That is, the first reference voltage corrector 220_3 can set the second source voltage VSSA_REF as the target voltage.

[0137] For reference, noise in the first reference voltage VREG1 can be introduced through the second source voltage VSSA_REF1 (and the buffer of the first reference voltage generation circuit 211). Therefore, the first reference voltage corrector 220_3 can use the second source voltage VSSA_REF (instead of...) Figure 4 The third reference voltage NELVDD shown is used to remove noise from the first reference voltage VREG1. That is, the second source voltage VSSA_REF (instead of the third reference voltage NELVDD) can be applied to Equation 1.

[0138] In such an embodiment, such as Figure 7 As shown, the first corrected reference voltage AVC_VREG1_REAL actually output from the first reference voltage corrector 220_3 can be similar to the expected first corrected reference voltage AVC_VREG1_IDEAL (i.e., a voltage in DC form), or it can become flat.

[0139] In such an embodiment, as referred to above... Figure 8 As described, the first reference voltage corrector 220_3 can generate a first corrected reference voltage AVC_VREG1 using a first reference voltage VREG1, an external power supply voltage ELVDD_EXT, and a second source voltage VSSA_REF. Therefore, the first corrected reference voltage AVC_VREG1 can be correlated with the external power supply voltage ELVDD_EXT, and the noise in the first reference voltage VREG1 caused by the second source voltage VSSA_REF (or ground voltage) can be removed by the second source voltage VSSA_REF.

[0140] Figure 9 It is shown that it includes Figure 3 A diagram of another alternative embodiment of the first reference voltage corrector in the gamma voltage generator.

[0141] Reference Figures 3 to 9 ,and Figure 4 Compared to the first reference voltage corrector 220_1, Figure 9 The first reference voltage corrector 220_4 may also include a resistor string RST (or a first resistor string), a decoder DEC (or a first decoder), and a multiplexer MUX (or a selector).

[0142] Because the resistor string RST and the decoder DEC are the same as those mentioned above. Figure 6 The resistor string RST and decoder DEC are essentially the same or similar, so any repeated detailed descriptions will be omitted below.

[0143] In such an embodiment, the multiplexer MUX may include three input terminals. The first input terminal of the multiplexer MUX may be connected to the output terminal of the decoder DEC, and a first target voltage NVREG1 may be applied to the first input terminal of the multiplexer MUX. The second input terminal of the multiplexer MUX may be connected to the third input terminal IN3 (or the third input node), and a third reference voltage NELVDD may be applied to the second input terminal of the multiplexer MUX. The third input terminal of the multiplexer MUX may be connected to the fourth input terminal IN4 (or the fourth input node), and a second source voltage VSSA_REF may be applied to the third input terminal of the multiplexer MUX. A third resistor R3 may be connected between the output terminal of the multiplexer MUX and the inverting terminal (-) of the first amplifier AMP1.

[0144] The multiplexer MUX can select and output a signal applied to one of the input terminals based on a first selection signal AVREG1_IN_SEL. The first selection signal AVREG1_IN_SEL can be provided externally (e.g., by timing controller 140 or a setting pin). In one embodiment, for example, the first selection signal AVREG1_IN_SEL can have a 2-bit value. When the value of the first selection signal AVREG1_IN_SEL is “00”, a first target voltage NVREG1 can be output; when the value of the first selection signal AVREG1_IN_SEL is “01”, a third reference voltage NELVDD can be output; and when the value of the first selection signal AVREG1_IN_SEL is “10”, a second source voltage VSSA_REF can be output. When the gamma voltage generator 150, including the first reference voltage corrector 220_4, is installed on the display device 100 (see reference 100),... Figure 1 When measuring the gamma voltage VGS while changing the value of the first selection signal AVREG1_IN_SEL, the value of the first selection signal AVREG1_IN_SEL can be set to optimize the first correction reference voltage AVC_VREG1. In other words, the first correction reference voltage AVC_VREG1 can be selectively used. Figure 4 First reference voltage corrector 220_1 Figure 6 The first reference voltage corrector 220_2 and Figure 8 The first reference voltage corrector 220_3.

[0145] In such an embodiment, as referred to above... Figure 9 As described, the first reference voltage corrector 220_4 can generate a first target voltage NVREG1 with noise similar to that of the first reference voltage VREG1 by dividing the first reference voltage VREG1, selecting one of the third reference voltage NELVDD, the first target voltage NVREG1, and the second source voltage VSSA_REF (or setting one of the third reference voltage NELVDD, the first target voltage NVREG1, and the second source voltage VSSA_REF as the target voltage), and using the selected one (or the set target voltage), the first reference voltage VREG1, and the external power voltage ELVDD_EXT to generate a first corrected reference voltage AVC_VREG1. That is, the first reference voltage corrector 220_4 can generate the first corrected reference voltage AVC_VREG1 by proportionally or directly proportionally correcting the first reference voltage VREG1 to the voltage difference between the external power voltage ELVDD_EXT and one selected from the first target voltage NVREG1, the third reference voltage NELVDD, and the second source voltage VSSA_REF (ground voltage). Therefore, the first correction reference voltage AVC_VREG1 can be associated with the external power voltage ELVDD_EXT, and the noise of the first reference voltage VREG1 generated in various forms for each product can be removed by selecting one of the third reference voltage NELVDD, the first target voltage NVREG1, and the second source voltage VSSA_REF.

[0146] Figure 10 It is shown that it includes Figure 3 A diagram of an embodiment of the second reference voltage corrector in a gamma voltage generator.

[0147] Reference Figure 3 and Figure 10 An embodiment of the second reference voltage corrector 230_1 may include a second amplifier AMP2 (or a differential amplifier), a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and an eighth resistor R8. The fifth resistor R5, the sixth resistor R6, the seventh resistor R7, and the eighth resistor R8 may have the same resistance value as each other, but are not limited to this. In embodiments, each of the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, and the eighth resistor R8 may correspond to a line resistance or may be composed of individual components.

[0148] The second amplifier AMP2 can receive a first source voltage VLIN1 and a third source voltage VSSA as drive power. In one embodiment, for example, the third source voltage VSSA can be the same as the second source voltage VSSA_REF, but is not limited thereto.

[0149] A fifth resistor R5 can be connected between the first input terminal IN1 (or the first input node) and the non-inverting terminal (+) of the second amplifier AMP2, and a sixth resistor R6 can be connected between the second input terminal IN2 (or the fifth input node) and the non-inverting terminal (+) of the second amplifier AMP2. An external power supply voltage ELVDD_EXT can be applied to the first input terminal IN1, and a second reference voltage VREF1 can be applied to the second input terminal IN2. In such an embodiment, the intermediate value (or average value) of the external power supply voltage ELVDD_EXT and the second reference voltage VREF1 can be applied to the non-inverting terminal (+) of the second amplifier AMP2.

[0150] The seventh resistor R7 can be connected between the third input terminal IN3 (or the third input node) and the inverting terminal (-) of the second amplifier AMP2. The eighth resistor R8 can be connected between the inverting terminal (-) of the second amplifier AMP2 and the output terminal OUT (or the second output node) of the second amplifier AMP2. The third reference voltage NELVDD can be applied to the third input terminal IN3.

[0151] In such an embodiment, the second reference voltage corrector 230_1 can output a second corrected reference voltage AVC_VREF1 according to the following equation 2.

[0152] [Equation 2]

[0153] AVC_VREF1=(NELVDD-ELVDD_EXT)+VREF1

[0154] In other words, the second correction reference voltage AVC_VREF1 can be proportional to or directly proportional to the value obtained by adding the voltage difference between the third reference voltage NELVDD and the external power voltage ELVDD_EXT to the second reference voltage VREF1. In such an embodiment, the second reference voltage VREF1 can be corrected based on the DC offset and AC fluctuation of the external power voltage ELVDD_EXT.

[0155] In such an embodiment, similar to the reference above. Figure 5 The relationship between the first reference voltage VREG1 and the third reference voltage NELVDD is described. When the phase and amplitude (or magnitude) of the second reference voltage VREF1 differ from those of the third reference voltage NELVDD, noise will be included in the second corrected reference voltage AVC_VREF1. That is, the second corrected reference voltage actually output from the second reference voltage corrector 230_1 will include AC noise that differs from the expected second corrected reference voltage (i.e., the DC form of the voltage).

[0156] Therefore, in the embodiment, when the phase and amplitude (or magnitude) of the second reference voltage VREF1 are different from the phase and amplitude of the third reference voltage NELVDD, the second reference voltage corrector 230 (referring to...) Figure 3 The second target voltage NVREF1 (referencing the third reference voltage NELVDD) can be generated based on the second reference voltage VREF1 (rather than the third reference voltage NELVDD). Figure 11 This is used to remove noise from the second reference voltage VREF1.

[0157] Figure 11 It is shown that it includes Figure 3 A diagram of an alternative embodiment of the second reference voltage corrector in the gamma voltage generator.

[0158] Reference Figure 3 , Figure 10 and Figure 11 ,and Figure 10 Compared to the second reference voltage corrector 230_1, Figure 11 The second reference voltage corrector 230_2 may also include a resistor string RST and a decoder DEC. In addition to the resistor string RST and the decoder DEC, Figure 11 The second reference voltage corrector 230_2 and Figure 10 The second reference voltage corrector 230_1 is similar, therefore any repeated detailed descriptions of the same or identical components will be omitted below.

[0159] The resistor string RST (or the second resistor string) can divide the voltage between the second reference voltage VREF1 and the second source voltage VSSA_REF using multiple resistors connected between the second input terminal IN2 and the second source voltage VSSA_REF, and the decoder DEC (or the second decoder) can select and output one of the multiple voltage dividers as the second target voltage NVREF1.

[0160] The sixth resistor R6 can be connected between the output terminal of the decoder DEC and the non-inverting terminal (+) of the second amplifier AMP2. The seventh resistor R7 can be connected between the second input terminal IN2 (or the fifth input node) and the inverting terminal (-) of the second amplifier AMP2.

[0161] A second target voltage NVREF1 can be generated by dividing the voltage between the second reference voltage VREF1 and the second source voltage VSSA_REF, and the voltage level of the second reference voltage VREF1 can be lower than the voltage level of the external power voltage ELVDD_EXT. In such an embodiment, the voltage level of the second target voltage NVREF1 will be lower than the voltage level of the external power voltage ELVDD_EXT, and the second target voltage NVREF1 may not be suitable as a comparison reference for the external power voltage ELVDD_EXT. Therefore, Figure 11 The second reference voltage corrector 230_2 can compensate the second target voltage NVREF1 proportionally or directly proportionally to the voltage difference between the external power voltage ELVDD_EXT and the second reference voltage VREF1.

[0162] In such an embodiment, the second reference voltage corrector 230_2 can output a second corrected reference voltage AVC_VREF1 according to the following equation 3.

[0163] [Equation 3]

[0164] AVC_VREF1=ELVDD_EXT-VREF1+NVREF1

[0165] For example, the external power voltage ELVDD_EXT can be approximately 2.8V, the second reference voltage VREF1 can be approximately 2.8V, the second target voltage NVREF1 can be approximately 0.5V, and the second target voltage NVREF1 generated based on the second reference voltage VREF1 can have the same phase as the second reference voltage VREF1. In this case, according to Equation 3, the second corrected reference voltage AVC_VREF1 can be approximately 0.5V (2.8V - 2.8V + 0.5V). Similar to the reference above... Figure 7 The first corrected reference voltage AVC_VREG1_REAL actually output from the first reference voltage corrector 220_2 and the second corrected reference voltage actually output from the second reference voltage corrector 230_2 can be similar to the desired second corrected reference voltage (i.e., a voltage in DC form), or can become flat.

[0166] In the embodiments, as referred to above... Figure 11As described, the second reference voltage corrector 230_2 can generate a second target voltage NVREF1 with noise similar to that of the second reference voltage VREF1 by dividing the second reference voltage VREF1, and uses the second reference voltage VREF1, the external power voltage ELVDD_EXT, and the second target voltage NVREF1 to generate a second corrected reference voltage AVC_VREF1. Therefore, the second corrected reference voltage AVC_VREF1 can be correlated with the external power voltage ELVDD_EXT, and the noise of the second reference voltage VREF1 and the second target voltage NVREF1 can cancel each other out.

[0167] Figure 12 It is shown that it includes Figure 3 A diagram of another alternative embodiment of the second reference voltage corrector in the gamma voltage generator.

[0168] Reference Figure 3 , Figures 10 to 12 ,and Figure 10 Compared to the second reference voltage corrector 230_1, Figure 12 The second reference voltage corrector 230_3 may also include a resistor string RST, a decoder DEC, a first multiplexer MUX1, and a second multiplexer MUX2.

[0169] Because the resistor string RST and the decoder DEC are related to the reference Figure 11 The resistor string RST and decoder DEC described are essentially the same or similar, so any repeated detailed descriptions of the same or identical components will be omitted below.

[0170] In an embodiment, such as Figure 12 As shown, each of the first multiplexer MUX1 and the second multiplexer MUX2 may include two input terminals.

[0171] The first input terminal of the first multiplexer MUX1 can be connected to the second input terminal IN2 (or the fifth input node), and the second reference voltage VREF1 can be applied to the first input terminal of the first multiplexer MUX1. The second input terminal of the first multiplexer MUX1 can be connected to the output terminal of the decoder DEC, and the second target voltage NVREF1 can be applied to the second input terminal of the first multiplexer MUX1. The sixth resistor R6 can be connected between the output terminal of the first multiplexer MUX1 and the non-inverting terminal (+) of the second amplifier AMP2.

[0172] The first input terminal of the second multiplexer MUX2 can be connected to the third input terminal IN3 (or the third input node), and the third reference voltage NELVDD can be applied to the first input terminal of the second multiplexer MUX2. The second input terminal of the second multiplexer MUX2 can be connected to the second input terminal IN2 (or the fifth input node), and the second reference voltage VREF1 can be applied to the second input terminal of the second multiplexer MUX2. The seventh resistor R7 can be connected between the output terminal of the second multiplexer MUX2 and the inverting terminal (-) of the second amplifier AMP2.

[0173] Each of the first multiplexer MUX1 and the second multiplexer MUX2 can select and output a signal applied to one of the input terminals based on the second selection signal AVREF1_IN_SEL. Similar to the first selection signal AVREF1_IN_SEL, the second selection signal AVREF1_IN_SEL can be provided externally (e.g., by timing controller 140 or a setting pin). In one embodiment, for example, the second selection signal AVREF1_IN_SEL can have a 1-bit value. When the value of the second selection signal AVREF1_IN_SEL is "0", a second reference voltage VREF1 can be output from the first multiplexer MUX1, and a third reference voltage NELVDD can be output from the second multiplexer MUX2. When the value of the second selection signal AVREF1_IN_SEL is "1", a second target voltage NVREF1 can be output from the first multiplexer MUX1, and a second reference voltage VREF1 can be output from the second multiplexer MUX2.

[0174] In such an embodiment, selective use is possible. Figure 10 The second reference voltage corrector 230_1 and Figure 11 The second reference voltage corrector 230_2.

[0175] In the embodiments, as referred to above... Figure 12 As described, the second reference voltage corrector 230_3 can generate a second target voltage NVREF1 with noise similar to that of the second reference voltage VREF1 by dividing the second reference voltage VREF1, and generate a second corrected reference voltage AVC_VREF1 using a third reference voltage NELVDD or the second target voltage NVREF1, the second reference voltage VREF1, and an external power voltage ELVDD_EXT. Therefore, the second corrected reference voltage AVC_VREF1 can be correlated with the external power voltage ELVDD_EXT, and the noise of the second reference voltage VREF1 can be removed by the third reference voltage NELVDD or the second target voltage NVREF1.

[0176] Figure 13 and Figure 14 It is shown that it includes Figure 3 A diagram of another alternative embodiment of the first reference voltage corrector in the gamma voltage generator.

[0177] First, refer to Figure 3 , Figure 4 , Figure 7 , Figure 9 , Figure 11 , Figure 12 and Figure 13 Besides the multiplexer MUX_1, Figure 13 The first reference voltage corrector 220_5 can be used with Figure 9 The first reference voltage corrector 220_4 is essentially the same as or similar to it. Therefore, any repeated detailed descriptions of the same or identical components will be omitted below.

[0178] In this embodiment, the multiplexer MUX_1 may include four input terminals. The connection configuration of the first, second, and third input terminals of the multiplexer MUX_1 can be... Figure 9 The connection configurations of the first, second, and third input terminals of the multiplexer MUX shown are basically the same. In such an embodiment, since the operation of the multiplexer MUX_1 is similar to that of the reference... Figure 9 The operation of the multiplexer MUX described is essentially the same or similar, so any repeated detailed descriptions will be omitted.

[0179] The second target voltage NVREF1 can be applied to the fourth input terminal of the multiplexer MUX_1. In one embodiment, for example, the fourth input terminal of the multiplexer MUX_1 can be connected to... Figure 11 The second reference voltage corrector 230_2 decoder DEC (or the second decoder) or Figure 12 The second reference voltage corrector 230_3 is the decoder DEC. In such an embodiment, the first reference voltage corrector 220_5 can be connected with... Figure 11 Second reference voltage corrector 230_2 or Figure 12 The second reference voltage corrector 230_3 together constitutes the gamma voltage generator 150. However, the disclosure is not limited thereto, and the first reference voltage corrector 220_5 may also include the reference voltage as described above. Figure 11 The resistor string RST (or second resistor string) and decoder DEC (or second decoder) are described, and the second target voltage NVREF1 is generated using the second reference voltage VREF1, the resistor string RST (or second resistor string) and the decoder DEC (or second decoder).

[0180] The multiplexer MUX_1 can select and output a signal applied to one of the input terminals based on a first selection signal AVREG1_IN_SEL. In one embodiment, for example, the first selection signal AVREG1_IN_SEL has a 2-bit value, and when the value of the first selection signal AVREG1_IN_SEL is "11", a second target voltage NVREF1 can be output. In such an embodiment, Figure 14 The circuit shown can be configured such that the second target voltage NVREF1 can be used as the target voltage, and the second target voltage NVREF1 (instead of the third reference voltage NELVDD) can be applied to Equation 1.

[0181] In the embodiments, as referred to above... Figure 13 and Figure 14 As described, the first reference voltage corrector 220_5 can select one of the following: a first target voltage NVREG1 (i.e., a first target voltage NVREG1 with noise similar to that of the first reference voltage VREG1 by dividing the first reference voltage VREG1), a second target voltage NVREF1 (i.e., a second target voltage NVREF1 with noise similar to that of the second reference voltage VREF1 by dividing the second reference voltage VREF1), a third reference voltage NELVDD, and a second source voltage VSSA_REF (or set one of the first target voltage NVREG1, the second target voltage NVREF1, the third reference voltage NELVDD, and the second source voltage VSSA_REF as the target voltage), and use the selected one (or the set target voltage), the first reference voltage VREG1, and the external power voltage ELVDD_EXT to generate a first corrected reference voltage AVC_VREG1. Therefore, the first correction reference voltage AVC_VREG1 can be associated with the external power voltage ELVDD_EXT, and the noise of the first reference voltage VREG1 generated in various forms for each product can be removed by selecting one of the third reference voltage NELVDD, the first target voltage NVREG1, the second target voltage NVREF1, and the second source voltage VSSA_REF.

[0182] In an embodiment, such as Figure 13 As shown, when the value of the first selection signal AVREG1_IN_SEL is "11", the circuit can be configured as follows: Figure 14 The circuitry (i.e., the first reference voltage corrector 220_5) is disclosed, but is not limited thereto. In an alternative embodiment, for example, the first reference voltage corrector 220_5 may not include... Figure 13The resistor string RST (or the first resistor string), decoder DEC (or the first decoder), and multiplexer MUX_1 shown are included, and only those shown are included. Figure 14 The first amplifier AMP1 (or differential amplifier), the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 are shown in the diagram.

[0183] Figure 15 and Figure 16 It is shown that it includes Figure 3 A diagram of another alternative embodiment of the second reference voltage corrector in the gamma voltage generator.

[0184] First, refer to Figure 3 , Figure 6 , Figure 9 , Figures 10 to 12 as well as Figure 15 Besides the first multiplexer MUX1_1 and the second multiplexer MUX2_1, Figure 15 The second reference voltage corrector 230_4 can be used with Figure 12 The second reference voltage corrector 230_3 is essentially the same or similar. Therefore, any repeated detailed descriptions of the same or identical components will be omitted below.

[0185] The connection configuration and operation of the first multiplexer MUX1_1 can be referenced. Figure 12 The connection configuration and operation of the first multiplexer MUX1 described are substantially the same or similar. The first multiplexer MUX1_1 can select and output a signal applied to one of the input terminals based on the first sub-select signal AVREF1_IN_SEL1. The first sub-select signal AVREF1_IN_SEL1 can be included in the second selection signal controlling the operation of the second reference voltage corrector 230_4, and can be provided externally (e.g., from the timing controller 140 or a setting pin).

[0186] The second multiplexer MUX2_1 may include three input terminals. The connection configuration of the first and second input terminals of the second multiplexer MUX2_1 can be... Figure 12 The connection configuration of the first and second input terminals of the second multiplexer MUX2 shown is basically the same. In such an embodiment, since the operation of the second multiplexer MUX2_1 is similar to that described above... Figure 12 The operation of the second multiplexer MUX2 is substantially the same or similar, so any repeated detailed descriptions will be omitted.

[0187] In one embodiment, the first target voltage NVREG1 can be applied to the third input terminal of the second multiplexer MUX2_1. In one embodiment, for example, the third input terminal of the second multiplexer MUX2_1 can be connected to... Figure 6 The first reference voltage corrector 220_2 decoder DEC (or the first decoder) or Figure 9 The first reference voltage corrector 220_4 is connected to the decoder DEC. In such an embodiment, the second reference voltage corrector 230_4 can be used with... Figure 6 First reference voltage corrector 220_2 or Figure 9 The first reference voltage corrector 220_4 together constitutes the gamma voltage generator 150. However, the disclosure is not limited thereto, and the second reference voltage corrector 230_4 may also include, as reference... Figure 6 The resistor string RST (or the first resistor string) and decoder DEC (or the first decoder) are described, and a first target voltage NVREG1 is generated using the first reference voltage VREG1, the resistor string RST (or the first resistor string), and the decoder DEC (or the first decoder). The second multiplexer MUX2_1 can select and output a signal applied to one of the input terminals based on the second sub-selection signal AVREF1_IN_SEL2. The second sub-selection signal AVREF1_IN_SEL2 can be included in the second selection signal controlling the operation of the second reference voltage corrector 230_4.

[0188] In one embodiment, for example, when the value of the first sub-select signal AVREF1_IN_SEL1 is "0" and the value of the second sub-select signal AVREF1_IN_SEL2 is "00", a second reference voltage VREF1 can be output from the first multiplexer MUX1_1, and a third reference voltage NELVDD can be output from the second multiplexer MUX2_1. In such an embodiment, when the value of the first sub-select signal AVREF1_IN_SEL1 is "1" and the value of the second sub-select signal AVREF1_IN_SEL2 is "01", a second target voltage NVREF1 can be output from the first multiplexer MUX1_1, and a second reference voltage VREF1 can be output from the second multiplexer MUX2_1.

[0189] In such an embodiment, when the value of the first sub-select signal AVREF1_IN_SEL1 is "0" and the value of the second sub-select signal AVREF1_IN_SEL2 is "10", a second reference voltage VREF1 can be output from the first multiplexer MUX1_1, and a first target voltage NVREG1 can be output from the second multiplexer MUX2_1. In such an embodiment, the circuit can be configured as follows: Figure 16The circuit shown allows the first target voltage NVREG1 to be used as the target voltage, and the first target voltage NVREG1 (instead of the third reference voltage NELVDD) can be applied to Equation 2.

[0190] In the embodiments, as referred to above... Figure 15 and Figure 16 As described, the second reference voltage corrector 230_4 can select one of a first target voltage NVREG1 (i.e., a first target voltage NVREG1 with noise similar to that of the first reference voltage VREG1 by dividing the first reference voltage VREG1), a second target voltage NVREF1 (i.e., a second target voltage NVREF1 with noise similar to that of the second reference voltage VREF1 by dividing the second reference voltage VREF1), and a third reference voltage NELVDD, and uses the selected one (or set target voltage), the second reference voltage VREF1, and the external power voltage ELVDD_EXT to generate a second corrected reference voltage AVC_VREF1. Therefore, the second corrected reference voltage AVC_VREF1 can be associated with the external power voltage ELVDD_EXT, and the noise of the second reference voltage VREF1 can be removed by the third reference voltage NELVDD, the first target voltage NVREG1, or the second target voltage NVREF1.

[0191] In an embodiment, such as Figure 15 As shown, when the value of the first sub-select signal AVREF1_IN_SEL1 is "0" and the value of the second sub-select signal AVREF1_IN_SEL2 is "10", the circuit can be configured as follows: Figure 16 The circuit (i.e., the second reference voltage corrector 230_4) is disclosed, but is not limited thereto. In an alternative embodiment, for example, the second reference voltage corrector 230_4 may not include... Figure 15 The resistor string RST (or second resistor string), decoder DEC (or second decoder), and multiplexer shown are included, and only those are included. Figure 16 The second amplifier AMP2 (or differential amplifier), the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, and the eighth resistor R8 are shown in the diagram.

[0192] The invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the inventive concept to those skilled in the art.

[0193] Although the invention has been specifically shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made herein without departing from the spirit or scope of the invention as defined by the claims.

Claims

1. A display device, the display device comprising: The display unit includes pixels and displays an image based on a first power voltage and data signals; Gamma voltage generator, generates multiple gamma voltages; as well as A data driver generates the data signal using the plurality of gamma voltages and provides the data signal to the pixel. The gamma voltage generator generates a first reference voltage and a second reference voltage. It generates a first corrected reference voltage and a second corrected reference voltage by correcting the first reference voltage and the second reference voltage using a target voltage and an external power voltage provided from the display unit corresponding to the first power voltage. Furthermore, it generates the plurality of gamma voltages by dividing the voltage between the first corrected reference voltage and the second corrected reference voltage. The gamma voltage generator sets the target voltage based on at least one selected from the first reference voltage, the second reference voltage, and the ground voltage.

2. The display device according to claim 1, wherein, The gamma voltage generator includes a first reference voltage corrector, which generates a first target voltage by dividing the voltage between the first reference voltage and the ground voltage, and generates a first corrected reference voltage by correcting the first reference voltage proportionally to the voltage difference between the first target voltage and the external power voltage.

3. The display device according to claim 2, wherein, The first reference voltage corrector includes: A first resistor string, using multiple resistors therein, divides the voltage between the first reference voltage and the ground voltage to generate multiple voltages; and The first decoder selects and outputs one of the plurality of voltages generated by the first resistor string as the first target voltage.

4. The display device according to claim 3, wherein, The first reference voltage corrector further includes: The first amplifier outputs the first correction reference voltage through its output terminal; A first resistor is connected between the external power voltage and the first input terminal of the first amplifier; A second resistor is connected between the first reference voltage and the first input terminal of the first amplifier; A third resistor is connected between the output terminal of the first decoder and the second input terminal of the first amplifier; and A fourth resistor is connected between the second input terminal of the first amplifier and the output terminal of the first amplifier.

5. The display device according to claim 2, wherein, The gamma voltage generator further includes a second reference voltage corrector, which generates a second target voltage by dividing the voltage between the second reference voltage and the ground voltage, and generates a second corrected reference voltage by adding the second target voltage to the voltage difference between the external power voltage and the second reference voltage.

6. The display device according to claim 5, wherein, The second reference voltage corrector includes: A second resistor string, using multiple resistors therein, divides the voltage between the second reference voltage and the ground voltage to generate multiple voltages; and The second decoder selects and outputs one of the multiple voltages generated by the second resistor string as the second target voltage.

7. The display device according to claim 6, wherein, The second reference voltage corrector also includes: The second amplifier outputs the second correction reference voltage through its output terminal; The fifth resistor is connected between the external power voltage and the first input terminal of the second amplifier; A sixth resistor is connected between the output terminal of the second decoder and the first input terminal of the second amplifier; A seventh resistor is connected between the second reference voltage and the second input terminal of the second amplifier; and The eighth resistor is connected between the second input terminal and the output terminal of the second amplifier.

8. The display device according to claim 1, wherein, The gamma voltage generator includes a first reference voltage corrector that sets the ground voltage as a first target voltage and generates a first corrected reference voltage by correcting the first reference voltage in proportion to the voltage difference between the first target voltage and the external power voltage.

9. The display device according to claim 1, wherein, The gamma voltage generator includes a first reference voltage corrector that generates a first target voltage by dividing the voltage between the first reference voltage and the ground voltage, and generates a first corrected reference voltage by correcting the first reference voltage proportionally to the external power voltage and the voltage difference between the first target voltage, a third reference voltage, and the ground voltage. The third reference voltage is generated together with the first reference voltage and the second reference voltage, and the third reference voltage has a voltage level that is lower than the voltage level of the first reference voltage and higher than the voltage level of the second reference voltage.

10. A gamma voltage generating circuit, the gamma voltage generating circuit comprising: A reference voltage generator generates a first reference voltage and a second reference voltage based on a source voltage. The first reference voltage corrector generates a first corrected reference voltage by correcting the first reference voltage using a first target voltage and an external power voltage provided from an external display unit. The second reference voltage corrector generates a second corrected reference voltage by correcting the second reference voltage using a second target voltage and the external power voltage; as well as The gamma voltage output unit generates multiple gamma voltages by dividing the voltage between the first correction reference voltage and the second correction reference voltage. The first reference voltage corrector sets the first target voltage based on at least one selected from the first reference voltage and the ground voltage, and The second reference voltage corrector sets the second target voltage based on at least one selected from the second reference voltage and the ground voltage.

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