Channel pre-charge method, programming method, device and system

Abstract

The application provides a channel pre-charge method, a programming method, a device and a system, and belongs to the technical field of storage. The scheme provided by the application can pre-charge the channels of unselected memory strings by using different pre-charge methods before data is written to selected memory cells connected to different word lines, thereby effectively improving the flexibility of pre-charging the channels. Moreover, for the word lines with more serious programming interference, the pre-charge method with better pre-charge effect can be used, so that the programming interference can be effectively inhibited.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a channel pre-charging method, programming method, apparatus and system. Background Technology

[0002] Three-dimensional (3D) memory typically comprises multiple arrays of memory strings, each containing multiple memory cells connected in series. Within these multiple memory strings, memory cells located at the same level are connected to the same word line (WL).

[0003] When programming (i.e., writing data) a selected memory cell, a programming voltage needs to be applied to the selected gate (WL) connected to that cell to cause electrons in the cell's channel to tunnel to the floating gate. However, this programming voltage can also cause electron tunneling in the deselected memory cell connected to the selected WL, affecting subsequent programming or data reading of that deselected memory cell. In other words, when programming a selected memory cell, the deselected memory cell connected to the selected WL will be subject to programming interference.

[0004] To reduce programming interference, a pre-charge voltage can be applied to the channel of the deselected memory cell connected to the selected WL before applying the programming voltage, thereby reducing the number of electrons in the channel of the deselected memory cell. This effectively reduces the probability of electron tunneling in the deselected memory cell during programming, thus suppressing programming interference. However, the method of pre-charging the channel by applying a pre-charge voltage has limited flexibility. Summary of the Invention

[0005] This application provides a channel pre-charging method, programming method, apparatus, and system, which can solve the technical problem of low flexibility in related pre-charging methods. The technical solution is as follows:

[0006] On one hand, a channel pre-charging method is provided, the method comprising:

[0007] In the pre-charge phase before programming the selected memory cell connected to the first word line, the channel of the deselected memory string is pre-charged using the first pre-charge method.

[0008] In the pre-charge stage before programming the selected memory cell connected to the second word line, a second pre-charge method is used to pre-charge the channel of the deselected memory string, and the second word line is different from the first word line.

[0009] The severity of programming interference caused by programming the selected memory cell connected to the second word line is greater than the severity of programming interference caused by programming the selected memory cell connected to the first word line; the pre-charging effect of the second pre-charging method is better than the pre-charging effect of the first pre-charging method.

[0010] Optionally, the first pre-charging method and the second pre-charging method adopt different pre-charging modes; wherein, the pre-charging mode adopted by the first pre-charging method includes: turning on the first target selection transistor in the deselected memory string, and applying a pre-charging voltage to the channel of the deselected memory string through the first target selection transistor, wherein the first target selection transistor is an upper selection transistor or a lower selection transistor;

[0011] The pre-charge mode adopted by the second pre-charge method includes: applying a bias voltage to the second target select transistor in the deselect memory string to cause the second target select transistor to generate gate-induced drain leakage (GIDL), wherein the second target select transistor includes at least one of an upper select transistor and a lower select transistor.

[0012] Optionally, the first pre-charging method and the second pre-charging method adopt the same pre-charging mode, and the pre-charging time of the second pre-charging method is longer than the pre-charging time of the first pre-charging method.

[0013] Optionally, the pre-charging mode adopted by the first pre-charging method and the second pre-charging method includes: turning on the first target selection transistor in the deselected memory string, and applying a pre-charging voltage to the channel of the deselected memory string through the first target selection transistor, wherein the first target selection transistor is an upper selection transistor or a lower selection transistor;

[0014] Alternatively, a bias voltage may be applied to the second target select transistor in the deselect memory string to cause the second target select transistor to generate a GIDL, the second target select transistor including at least one of an upper select transistor and a lower select transistor.

[0015] Optionally, the stage of programming the second word line is performed after the stage of programming the first word line.

[0016] Optionally, the method further includes: in a pre-charge phase before programming the selected memory cell connected to the third word line, a third pre-charge method is used to pre-charge the channel of the deselected memory string, wherein the third word line is different from the first word line and different from the second word line;

[0017] The severity of the programming interference caused by programming the selected memory cell connected to the third word line is greater than the severity of the programming interference caused by programming the selected memory cell connected to the target word line, wherein the target word line is the first word line or the second word line.

[0018] The third pre-charging method uses the same pre-charging mode as the target pre-charging method, and the pre-charging duration of the third pre-charging method is longer than that of the target pre-charging method. The target pre-charging method is the pre-charging method used in the pre-charging stage before programming the selected memory cell connected to the target word line.

[0019] On the other hand, a method for programming a memory is provided, the method comprising:

[0020] The channels of the deselected memory strings in the memory are precharged using the precharge method provided above; and, in a programming phase following each precharge phase in the precharge method, selected memory cells in the memory are programmed.

[0021] In another aspect, a channel pre-charging device is provided, the device comprising:

[0022] The first precharge module is used to precharge the channel of the deselected memory string in a first precharge method during the precharge stage before programming the selected memory cell connected to the first word line.

[0023] The second precharge module is used to precharge the channel of the deselected memory string in a second precharge method during the precharge stage before programming the selected memory cell connected to the second word line. The second word line is different from the first word line.

[0024] The severity of programming interference caused by programming the selected memory cell connected to the second word line is greater than the severity of programming interference caused by programming the selected memory cell connected to the first word line; the pre-charging effect of the second pre-charging method is better than the pre-charging effect of the first pre-charging method.

[0025] Optionally, the first pre-charging method and the second pre-charging method adopt different pre-charging modes; wherein, the pre-charging mode adopted by the first pre-charging method includes: turning on the first target selection transistor in the deselected memory string, and applying a pre-charging voltage to the channel of the deselected memory string through the first target selection transistor, wherein the first target selection transistor is an upper selection transistor or a lower selection transistor;

[0026] The pre-charge mode adopted by the second pre-charge method includes: applying a bias voltage to the second target select transistor in the deselect memory string to cause the second target select transistor to generate GIDL, wherein the second target select transistor includes at least one of an upper select transistor and a lower select transistor.

[0027] Optionally, the first pre-charging method and the second pre-charging method adopt the same pre-charging mode, and the pre-charging time of the second pre-charging method is longer than the pre-charging time of the first pre-charging method.

[0028] Optionally, the pre-charging mode adopted by the first pre-charging method and the second pre-charging method includes: turning on the first target selection transistor in the deselected memory string, and applying a pre-charging voltage to the channel of the deselected memory string through the first target selection transistor, wherein the first target selection transistor is an upper selection transistor or a lower selection transistor;

[0029] Alternatively, a bias voltage may be applied to the second target select transistor in the deselect memory string to cause the second target select transistor to generate a GIDL, the second target select transistor including at least one of an upper select transistor and a lower select transistor.

[0030] Optionally, the stage of programming the second word line is performed after the stage of programming the first word line.

[0031] Optionally, the device further includes:

[0032] The third precharge module is used to precharge the channel of the deselected memory string in a third precharge method during the precharge stage before programming the selected memory cell connected to the third word line. The third word line is different from the first word line and different from the second word line.

[0033] The severity of the programming interference caused by programming the selected memory cell connected to the third word line is greater than the severity of the programming interference caused by programming the selected memory cell connected to the target word line, wherein the target word line is the first word line or the second word line.

[0034] The third pre-charging method uses the same pre-charging mode as the target pre-charging method, and the pre-charging duration of the third pre-charging method is longer than that of the target pre-charging method. The target pre-charging method is the pre-charging method used in the pre-charging stage before programming the selected memory cell connected to the target word line.

[0035] In another aspect, a memory programming device is provided, the device comprising: a precharge module and a programming module;

[0036] The pre-charge module is used to pre-charge the channels of the deselected memory string in the memory using the pre-charge method provided above.

[0037] The programming module is used to program selected memory cells in the memory during a programming phase following each pre-charge stage in the pre-charge method.

[0038] In another aspect, a control circuit is provided, the control circuit including programmable logic circuit and / or program instructions, the control circuit being used to implement the channel pre-charge method or memory programming method provided in the above aspects.

[0039] In another aspect, a computer-readable storage medium is provided, wherein instructions are stored therein, which, when executed on a control circuit, can implement the channel pre-charge method or the memory programming method described above.

[0040] In another aspect, a memory is provided, the memory comprising: a memory array and a control circuit, the control circuit being the control circuit described above, or the control circuit comprising the channel pre-charging device or the memory programming device described above.

[0041] In another aspect, a computer program product is provided, which stores instructions that, when run on a control circuit, cause the control circuit to execute the channel pre-charge method or the memory programming method described above.

[0042] In another aspect, a memory system is provided, the memory system comprising: a controller, and at least one memory as described above.

[0043] The technical solution provided in this application may include the following beneficial effects:

[0044] This application provides a channel pre-charging method, programming method, apparatus, and system. The solution provided by this application can pre-charge the channel of the deselected memory string using different pre-charging methods before writing data to selected memory cells connected to different word lines, thereby effectively improving the flexibility of channel pre-charging. Furthermore, since a better pre-charging method can be used for word lines with severe programming interference, it can effectively suppress programming interference. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 This is a schematic diagram of the structure of a 3D memory provided in an embodiment of this application;

[0047] Figure 2 This is a flowchart of a channel pre-charging method provided in an embodiment of this application;

[0048] Figure 3 This is a schematic diagram of forward programming provided in an embodiment of this application;

[0049] Figure 4 This is a schematic diagram of reverse programming provided in an embodiment of this application;

[0050] Figure 5 This is a flowchart of another channel pre-charging method provided in the embodiments of this application;

[0051] Figure 6 This is a schematic diagram illustrating the voltage change during each programming cycle in a forward programming scenario provided in an embodiment of this application.

[0052] Figure 7 This is a schematic diagram of the voltage change in each programming cycle during reverse programming, as provided in an embodiment of this application.

[0053] Figure 8 This is a schematic diagram illustrating the voltage change in each programming cycle when using a first pre-charge mode, as provided in an embodiment of this application.

[0054] Figure 9 This is a schematic diagram illustrating how the pre-charge duration varies with the severity of programming interference, as provided in an embodiment of this application.

[0055] Figure 10 This is a schematic diagram of the pre-charge mode adopted by each WL during forward programming, as provided in an embodiment of this application;

[0056] Figure 11 This is a schematic diagram of the pre-charge mode adopted by each WL during reverse programming according to an embodiment of this application;

[0057] Figure 12 This is a schematic diagram illustrating how the pre-charge duration changes with the programming cycle, as provided in an embodiment of this application.

[0058] Figure 13This is a flowchart illustrating a memory programming method provided in an embodiment of this application;

[0059] Figure 14 This is a schematic diagram of the structure of a channel pre-charging device provided in an embodiment of this application;

[0060] Figure 15 This is a schematic diagram of the structure of a memory programming device provided in an embodiment of this application;

[0061] Figure 16 This is a schematic diagram of the structure of a memory provided in an embodiment of this application;

[0062] Figure 17 This is a schematic diagram of the structure of a memory system provided in an embodiment of this application. Detailed Implementation

[0063] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0064] The channel pre-charge method provided in this application embodiment can be applied to a memory. This memory can be a 3D memory, such as a 3D NAND flash memory.

[0065] Figure 1 This is a schematic diagram of the structure of a 3D memory according to an embodiment of this application. Figure 1 As shown, the 3D memory includes multiple storage strings 01, which are arranged along a bearing surface parallel to the substrate (i.e., Figure 1 The memory cells are arranged in the XY plane of the substrate. Each memory string 01 includes multiple (e.g., 32 or 64) memory cells connected in series, which are arranged in a direction perpendicular to the substrate's bearing surface (i.e., ...). Figure 1 The memory cells are arranged in a Z-direction. Thus, the multiple memory cells included in this 3D memory can be arranged in a three-dimensional array on the substrate, thereby forming a memory array.

[0066] like Figure 1 As shown, each memory string 01 also includes at least one upper select transistor connected to the first pole of the first memory cell, and at least one lower select transistor connected to the second pole of the last memory cell. The upper select transistor is also called a top select gate (TSG) or drain select transistor. The lower select transistor is also called a bottom select gate (BSG) or source select transistor.

[0067] In this configuration, the gate of each TSG is connected to the drain select line (DSL), the second terminal of each TSG is connected to the first terminal of the first memory cell in its memory string, and the first terminal of each TSG is connected to the bit line (BL). Similarly, the gate of each BSG is connected to the source select line (SSL), the first terminal of each BSG is connected to the second terminal of the last memory cell in its memory string, and the second terminal of each BSG is connected to the source line (SL).

[0068] It is understandable that the first electrode mentioned above can refer to one of the source and drain electrodes, and the second electrode can refer to the other of the source and drain electrodes. For example, the first electrode can refer to the drain electrode, and the second electrode can refer to the source electrode.

[0069] from Figure 1 As can be seen, this 3D memory includes n BLs (BL1 to BLn) arranged along the X direction, x DSLs (DSL1 to DSLx) arranged along the Y direction, and x SSLs (SSL1 to SSLx) arranged along the Y direction. Here, n and x are both integers greater than 1. Each DSL is connected to the gate of the n TSGs arranged along the X direction, each BL is connected to the first electrode of the x TSGs arranged along the Y direction, and each SSL is connected to the gate of the n BSGs arranged along the X direction. Furthermore, the second electrode of each BSG is connected to the same SL, therefore this SL is also called the array common source (ACS).

[0070] Continue to refer to Figure 1 Each memory cell in memory string 01 shares a set of memory lines (WLs) with memory cells in other memory strings 01. Assuming each memory string 01 includes m memory cells, the 3D memory can include m WLs arranged along direction Z: WL1 to WLm, where m is an integer greater than 1. Each WL is connected to each memory cell located on the same layer (i.e., at the same height relative to the substrate's bearing surface). Alternatively, it can be understood that the control gates of each memory cell on the same layer, and the gate connection lines between the control gates, constitute a WL.

[0071] Based on the amount of data that a storage unit can store, storage units can be classified into single-level cells (SLC), multi-level cells (MLC), tri-level cells (TLC), and quadri-level cells (QLC). Each SLC can store 1 bit of data, each MLC can store 2 bits, each TLC can store 3 bits, and each QLC can store 4 bits. In 3D memory, the data stored in storage units located in the same layer can form k storage pages, where k is the number of bits of data that each storage unit can store.

[0072] from Figure 1 It can also be seen that virtual storage cells (dummy cells) can be set between TSG and storage cells, and between BSG and storage cells in each storage string 01. The virtual storage cells are interconnected with virtual storage cells in other storage strings 01 through dummy word lines (DWL).

[0073] In this embodiment, the storage cell 011 in the 3D memory can be a floating-gate field-effect transistor (FET) or a charge-trap FET, or other FETs capable of storing data. The TSG and BSG can be ordinary FETs or FETs capable of storing data. The floating-gate FET includes a source, a drain, and two gates. Both gates are conductors, and one is a control gate (CG), while the other is a floating gate (FG), referred to simply as a floating gate. The control gate is used to connect word lines, and the floating gate is used as a data storage cell. The charge-trap FET includes a source, a drain, a control gate, and a charge-trap layer. This charge-trap layer is used as a data storage cell and is made of an insulating material such as silicon nitride. The following section uses a floating-gate FET as an example to describe the data read / write principle of the storage cell.

[0074] When writing data into a memory cell, a programming voltage is applied to the control gate of the floating-gate field-effect transistor (FET), causing electrons in the FET's channel to tunnel to the floating gate. By controlling the magnitude of this programming voltage, the number of electrons tunneling to the floating gate can be controlled, thereby controlling the threshold voltage Vth of the FET. Generally, the higher the amount of charge stored in the floating gate, the higher the threshold voltage Vth of the FET. It is understandable that different threshold voltages Vth require different voltages applied to the control gate to turn the FET on. Therefore, the magnitude of the threshold voltage Vth of the FET reflects the content of the stored data.

[0075] When reading data stored in a memory cell, different levels of read voltage can be applied to the control gate of the floating-gate field-effect transistor (FET) in ascending order. After applying each level of read voltage, it can be detected whether the FET is conducting. This allows for the detection of the FET's threshold voltage Vth, thereby enabling the reading of data stored in the memory cell.

[0076] It should be understood that in a 3D memory, the channels of each memory cell in each memory string 01 can be connected sequentially to form a columnar structure perpendicular to the substrate. For ease of explanation, the channel corresponding to a memory string 01 will be referred to as the channel of memory string 01, and the channel corresponding to a memory cell 011 will be referred to as the channel of memory cell 011.

[0077] The following text is incomplete and cannot be translated. Figure 1 The memory cell U1 in the diagram is the memory cell to be programmed. Taking the selected memory cell as an example, the programming process for the selected memory cell will be introduced. This programming process includes:

[0078] Step S1: Ground the channel of the selected memory string and leave the channel of the deselected memory string floating.

[0079] In this context, the selected memory string refers to the memory string to which the selected memory cell belongs, and other memory strings outside the selected memory string are the deselected memory strings. In step S1 above, the TSG in the selected memory string can be turned on, the BSG in the selected memory string can be turned off, and the BL connected to the TSG can be grounded, so that the channel of the selected memory string is grounded. Furthermore, both the TSG and BSG in the deselected memory string can be turned off, so that the channel of the deselected memory string is floating. The BL connected to the TSG in the selected memory string can be called the selected (sel) BL.

[0080] Step S2: Apply programming voltage V to WL connected to the selected memory cell. pgm And apply a turn-on voltage V to other WLs besides the selected WL (i.e., deselected WLs). pass.

[0081] refer to Figure 1 Assuming that memory cell U1 is connected to WL1, WL1 is the selected (sel) WL, and a programming voltage V can be applied to WL1. pgm WL2 to WLm are unselected (unsel) WLs, and a conduction voltage V can be applied to these unsel WLs. pass The on-state voltage V pass Used to turn on all the unselected memory cells connected to unsel WL, so as to connect the selected memory cell to sel BL.

[0082] It is understandable that the programming voltage V pgm The voltage is typically high, thus allowing a large voltage difference to be created between the control gate and the channel of the selected memory cell. This enables electrons in the channel to tunnel to the floating gate of the selected memory cell, thereby storing data. Furthermore, by adjusting the programming voltage V... pgm The size of the value can be adjusted to change the number of electrons stored in the floating gate, which in turn can adjust the threshold voltage Vth of the selected memory cell.

[0083] Due to the on-voltage V pass Typically below the programming voltage V pgm Therefore, the voltage difference between the control gate and the channel of the deselected memory cell connected to unsel WL is relatively small, thus preventing electrons in the channel from tunneling to the floating gate. For the deselected memory cells connected to sel WL in the deselected memory string, since the channel of that deselected memory string is floating, the voltage difference between the control gate and the channel of the deselected memory cell connected to sel WL is also relatively small, again preventing electrons in the channel from tunneling to the floating gate. In other words, when programming a selected memory cell, neither the deselected memory cells connected to unsel WL nor those connected to sel WL will be programmed; that is, programming of the deselected memory cells is suppressed.

[0084] However, when programming a selected memory cell, due to the programming voltage V pgm Even at higher voltage levels, a small amount of electron tunneling is unavoidable in the deselected memory cells connected by sel WL. This causes a shift in the threshold voltage Vth of the deselected memory cell, thus affecting subsequent programming and data retrieval of that deselected memory cell. In other words, when programming a selected memory cell, the deselected memory cell connected by sel WL will be subject to programming interference.

[0085] To reduce programming interference, the channel of the deselect memory string connected to the sel WL can be pre-charged before applying the programming voltage to the sel WL, thereby raising the potential of the channel. Based on this, when programming the selected memory cell, the voltage difference between the control gate and the channel of the deselect memory cell connected to the sel WL is smaller, making it difficult for electrons in the channel to tunnel to the floating gate, thus effectively suppressing programming interference.

[0086] Pre-charging methods in related technologies include turning on the TSG or BSG of the deselected memory string before programming the selected memory cell. Then, a pre-charging voltage is applied to the channel of the deselected memory string through the turned-on select transistor, causing electrons in the channel to move out through the turned-on select transistor, thereby raising the potential of the memory string channel. However, this pre-charging method has limited flexibility.

[0087] Figure 2 This is a flowchart of a channel pre-charging method provided in an embodiment of this application, such as... Figure 2 As shown, the method provided in this application embodiment includes:

[0088] Step 101: In the pre-charge stage before programming the selected memory cell connected to the first word line, the channel of the deselected memory string is pre-charged using the first pre-charge method.

[0089] The stage of programming the selected memory cell connected to the first word line can be called the first programming stage. In this first programming stage, a programming voltage can be applied to the first word line to write data to the selected memory cell connected to the first word line. It is understood that the first word line is sel WL. The deselected memory string in step 101 refers to the memory string to which the deselected memory cell connected to the first word line belongs.

[0090] Step 102: In the pre-charge stage before programming the selected memory cell connected to the second word line, the channel of the deselected memory string is pre-charged using the second pre-charge method.

[0091] The stage of programming the selected memory cell connected to the second word line can be called the second programming stage. In this second programming stage, a programming voltage can be applied to the second word line to write data into the selected memory cell connected to the second word line. This second word line is different from the first word line. The deselected memory string in step 102 refers to the memory string to which the deselected memory cell connected to the second word line belongs.

[0092] In 3D memory, programming of memory cells is performed on a page-by-page basis. That is, at least one selected memory cell connected to a single sel WL can be programmed at a time, and each WL can be traversed sequentially according to a preset programming direction. (Reference) Figure 3If the programming direction is forward, i.e., using forward programming, then each root WL can be traversed sequentially from BSG to TSG. (Reference) Figure 4 If the programming direction is reversed, i.e., reverse programming is used, then each root WL can be traversed sequentially from TSG to BSG. Correspondingly, the second word line mentioned above can refer to the sel WL traversed before or after the first word line.

[0093] In this embodiment, the severity of programming interference caused by programming selected memory cells connected to the second word line is greater than the severity of programming interference caused by programming selected memory cells connected to the first word line. That is, the severity of programming interference in the second programming stage is greater than the severity of programming interference in the first programming stage. Furthermore, the pre-charging effect of the second pre-charging method is better than the pre-charging effect of the first pre-charging method, ensuring that programming interference in the second programming stage can be effectively suppressed.

[0094] In summary, the embodiments of this application provide a channel pre-charging method. This method allows for the pre-charging of the channels of the deselected memory string using different pre-charging methods before writing data to selected memory cells connected to different word lines, thereby effectively improving the flexibility of channel pre-charging. Furthermore, since a better pre-charging method can be used for word lines with severe programming interference, it can effectively suppress programming interference.

[0095] As a first possible implementation, the first pre-charging method and the second pre-charging method described above can employ different pre-charging modes. The pre-charging mode employed by the first pre-charging method (hereinafter referred to as the first pre-charging mode) may include: turning on the first target select transistor in the deselected memory string, and applying a pre-charging voltage to the channel of the deselected memory string through the first target select transistor.

[0096] The first target selection transistor is either a TSG or a BSG. The pre-charge voltage allows electrons in the channel of the deselected memory string to migrate out of the channel through the conducting first target selection transistor, thereby effectively reducing the number of electrons in the channel of the deselected memory string and thus raising the potential of the channel of the deselected memory string.

[0097] The second pre-charge method employs a pre-charge mode (hereinafter referred to as the second pre-charge mode) that may include: applying a bias voltage to a second target select transistor in the deselect memory string to cause the second target select transistor to undergo band-to-band tunneling and generate GIDL. The second target select transistor includes at least one of TSG and BSG.

[0098] The GIDL includes electron-hole pairs. Holes in the electron-hole pair can be transported to the channel of the deselect memory string and recombine with electrons in the channel, thereby raising the channel potential. Electrons in the electron-hole pair can then migrate out of the select memory string through the second target selector.

[0099] In this first precharge mode, if the programming direction of the 3D memory is positive, the TSG of the deselect memory string can be turned on, and a precharge voltage can be applied to the BL connected to the TSG. This precharge voltage can be applied to the channel of the deselect memory string through the turned-on TSG, causing electrons in the channel of the deselect memory string to migrate to the BL (i.e. be absorbed by the BL), thereby raising the potential of the channel of the deselect memory string.

[0100] If the 3D memory is programmed in reverse, the BSG of the selectable memory string can be turned on, and a pre-charge voltage can be applied to the SL. This pre-charge voltage can be applied to the channel of the selectable memory string through the turned-on BSG, causing the electrons remaining in the channel of the selectable memory string to migrate to the SL (i.e. be absorbed by the SL), thereby raising the potential of the channel of the selectable memory string.

[0101] In this second pre-charge mode, if the second target selection transistor includes a TSG, a first bias voltage can be applied to the gate of the TSG via a DSL, and a second bias voltage can be applied to the first terminal of the TSG via a BL. Accordingly, electrons in the GIDL generated by the TSG can migrate to the BL. If the second target selection transistor includes a BSG, a first bias voltage can be applied to the gate of the BSG via an SSL, and a second bias voltage can be applied to the second terminal of the BSG via an SL. Accordingly, electrons in the GIDL generated by the BSG can migrate to the SL.

[0102] Understandably, in order for the second target selection transistor to generate GIDL, the second bias voltage needs to be higher than the first bias voltage. For example, the first bias voltage can be 0 volts (V), and the second bias voltage can be from 2V to 10V. Optionally, the voltage difference between the second bias unit and the first bias voltage can be greater than or equal to 5V.

[0103] Based on the above analysis, it can be seen that the first precharge mode raises the channel potential by migrating electrons out of the channel of the deselected memory string, while the second precharge mode raises the channel potential by transferring holes into the channel of the deselected memory string. Since the mobility of electrons is higher than that of holes, the first precharge mode requires a shorter precharge time and has higher precharge efficiency.

[0104] It's also understandable that the threshold voltage Vth of a programmed memory cell is relatively high, and its channel is mostly filled with holes. If, when programming a selected memory cell connected to a certain sel WL, most WLs have already been traversed (i.e., most unsel WL-connected memory cells have completed programming), then the holes in the channels of the programmed memory cells in the deselected memory string will block electron transport. In other words, the channels of the programmed memory cells will cut off the channels of the deselected memory string. At this point, if a pre-charge voltage is applied to the channels of the deselected memory string using the first pre-charge mode, electrons in the channels of the deselected memory string will be difficult to migrate out, thus failing to achieve a good pre-charge effect.

[0105] Since the second precharge mode raises the channel potential of the select memory string by transferring holes, even if there are a large number of programmed memory cells in the select memory string, it can effectively reduce the number of electrons in the channel of the select memory string, thereby ensuring a better precharge effect.

[0106] In the first possible implementation described above, for the first programming stage where programming interference is relatively minor, the first pre-charge mode is used to pre-charge the channel of the deselected memory string. Therefore, the pre-charge efficiency can be further improved while ensuring effective suppression of programming interference, thereby improving programming efficiency. For the second programming stage where programming interference is relatively severe, the second pre-charge mode is used to pre-charge the channel of the deselected memory string. Therefore, this more severe programming interference can be effectively suppressed.

[0107] In the second possible implementation, the first pre-charging method and the second pre-charging method can adopt the same pre-charging mode, and the pre-charging time of the second pre-charging method is longer than the pre-charging time of the first pre-charging method.

[0108] It is understandable that a longer precharge duration results in a better precharge effect on the channel of the selectable memory string. Therefore, in this embodiment, by making the precharge duration of the second precharge method longer, it is possible to effectively suppress the relatively severe programming interference generated in the second programming stage. By making the precharge duration of the first precharge method shorter, the precharge duration can be shortened as much as possible while ensuring effective suppression of programming interference generated in the first programming stage, thereby improving programming efficiency.

[0109] Optionally, the pre-charging mode adopted by the first pre-charging method and the second pre-charging method can be either the first pre-charging mode or the second pre-charging mode mentioned above, which will not be elaborated here.

[0110] Based on the above analysis, it can be seen that both the first and second possible implementation methods can further improve the efficiency of precharging while ensuring effective suppression of programming interference, thereby improving the efficiency of programming.

[0111] Figure 5 This is a flowchart of another channel pre-charging method provided in the embodiments of this application, such as... Figure 5 As shown, the method provided in this application embodiment includes:

[0112] Step 201: In the first pre-charge stage before programming the selected memory cell connected to the first word line, the channel of the deselected memory string is pre-charged using the first pre-charge method.

[0113] The stage of programming the selected memory cell connected to the first word line can be called the first programming stage. In this first programming stage, a programming voltage can be applied to the first word line to write data to the selected memory cell connected to the first word line. The first word line refers to the currently traversed sel WL. The first precharge mode employed by this first precharge method may include: turning on the first target select transistor of the deselected memory string and applying a precharge voltage to the channel of the deselected memory string through the first target select transistor. The first target select transistor is either a TSG or a BSG.

[0114] It is understood that the process of programming selected memory cells connected to the first word line may include multiple programming loops, each programming loop including at least: a first pre-charge stage for pre-charging the channel, and a first programming stage for applying a programming voltage to the first word line. The programming voltage applied in the first programming stage of different programming loops is different, and the first programming stage of each programming loop may write data to one or more selected memory cells connected to the first word line.

[0115] Figure 6 This is a schematic diagram of the voltage change in each programming cycle during forward programming, provided in an embodiment of this application. Figure 6 In the code, `sel BL` indicates that the BL connected to the memory string is selected, and `unsel BL` indicates that the BL connected to the memory string is unselected; `sel TSG` indicates that the TSG of the memory string is selected, and `unsel TSG` indicates that the TSG of the memory string is unselected; `sel WL` indicates the currently selected WL, i.e., the first word line, and `unsel WL` indicates other WLs besides the first word line.

[0116] If the programming direction of the 3D memory is positive, then as follows Figure 6 As shown, in this first pre-charge phase, a turn-on voltage V can be applied to the gate of the unsel TSG. tsgThis allows the unsel TSG to be turned on. Furthermore, a pre-charge voltage V can be applied to the unsel BL connected to the unsel TSG. bl-pre The pre-charge voltage V bl-pre The unsel TSG can be applied to the channel of the deselect memory string to raise its potential. The on-state voltage Vunselect tsg The pre-charge voltage can be from 3V to 5V. bl-pre It can range from 0V to 2.2V.

[0117] Figure 7 This is a schematic diagram illustrating the voltage changes during each programming cycle in a reverse programming scenario provided in this application embodiment. If the programming direction of the 3D memory is reverse programming, then as... Figure 7 As shown, in this first pre-charge phase, a turn-on voltage V can be applied to the BSG of the deselected memory string. bsg This allows the BSG to be turned on. Furthermore, a pre-charge voltage V can be applied to the SL. sl-pre The pre-charge voltage V sl-pre The potential of the deselected memory string channel can be raised by applying a conducting BSG to the channel. This conducting voltage V... bsg The pre-charge voltage can be from 3V to 5V. sl-pre It can range from 0V to 2.2V.

[0118] Optionally, in the first precharge phase of each programming cycle, in addition to precharging the channels of the deselected memory string, the channels of the selected memory string can also be precharged. That is, in this first precharge phase, the channels of each memory string in the 3D memory can be precharged.

[0119] Accordingly, refer to Figure 6 During the first pre-charge phase of forward programming, a turn-on voltage V can also be applied to the gate of the sel TSG. tsg This allows the sel TSG to be turned on. Furthermore, a pre-charge voltage V can be applied to the sel BL connected to the sel TSG. bl-pre The pre-charge voltage V bl-pre It can load into the channel of the selected memory string via the activated sel TSG.

[0120] refer to Figure 7 In the first pre-charge stage of reverse programming, a turn-on voltage V can be applied to the gate of the BSG of each memory string. tsg This is to activate the BSG of each memory string. Simultaneously, a pre-charge voltage V can be applied to the SL. bl-pre The pre-charge voltage V bl-pre It can be loaded into the channels of each memory string through the activated BSG.

[0121] Step 202: In the second pre-charge stage before programming the selected memory cell connected to the second word line, the channel of the deselected memory string is pre-charged using the second pre-charge method.

[0122] The stage of programming the selected memory cell connected to the second word line can be called the second programming stage. In this second programming stage, a programming voltage can be applied to the second word line to write data to the selected memory cell connected to the second word line. The second word line refers to the sel WL traversed before or after the first word line. The second precharge mode employed by this second precharge method may include: applying a bias voltage to the second target select transistor in the deselect memory string to cause the second target select transistor to generate a GIDL. Holes in the GIDL can be transferred to the channel of the deselect memory string to raise the channel potential.

[0123] It is understood that the process of programming selected memory cells connected to the second word line may also include multiple programming cycles, each programming cycle including at least: a second pre-charge stage for pre-charging the channel, and a second programming stage for applying a programming voltage to the second word line. The programming voltage applied in the second programming stage of different programming cycles is different, and data can be written to one or more selected memory cells connected to the second word line in the second programming stage of each programming cycle.

[0124] For example, suppose the second target selection tube includes TSG and BSG. Then refer to... Figure 8 In the second pre-charge phase, a first bias voltage can be applied to both the gate of the sel TSG and the gate of the unsel TSG. Figure 8 Taking 0V as an example, a second bias voltage V is applied to both the first terminal of sel BL and unsel BL. bl-bias Simultaneously, a first bias voltage can be applied to the gate of each BSG, and a second bias voltage V can be applied to SL. sl-bias This allows each memory string's TSG and BSG to generate GIDL, thereby enabling pre-charging of the channels of each memory string in the memory.

[0125] like Figures 6 to 8 As shown, during the programming phase of each programming cycle, a bias voltage V can be applied to the gate of the selected memory string's sel TSG. tsg-pgm This allows the sel TSG to conduct. During the programming phase, a programming voltage V can also be applied to the sel WL. pgm And apply the on-state voltage V to unsel WL passFurthermore, to suppress programming of the unsel memory string, a suppression voltage V can be applied to the unsel BL connected to the unsel TSG. bl-inhibit .

[0126] Step 203: In the pre-charge stage before programming the selected memory cell connected to the third word line, the channel of the deselected memory string is pre-charged using the third pre-charge method.

[0127] The stage of programming the selected memory cell connected to the third word line can be called the third programming stage. In this third programming stage, a programming voltage can be applied to the third word line to write data into the selected memory cell connected to the third word line. The third word line refers to the sel WL traversed before or after the second word line. The pre-charge mode used in this third pre-charge method is the same as the pre-charge mode used in the target pre-charge method, which is either the first pre-charge method or the second pre-charge method described above. Furthermore, the pre-charge duration of the third pre-charge method is longer than the pre-charge duration of the target pre-charge method.

[0128] It is understood that the process of programming selected memory cells connected to the third word line may also include multiple programming cycles, each programming cycle including at least: a third pre-charge stage for pre-charging the channel, and a third programming stage for applying a programming voltage to the third word line. The programming voltage applied in the third programming stage of different programming cycles is different, and data can be written to one or more selected memory cells connected to the third word line in the third programming stage of each programming cycle.

[0129] In this embodiment, the severity of programming interference generated in the second programming stage is greater than that generated in the first programming stage. Furthermore, the severity of programming interference generated in the third programming stage is greater than that generated in the target programming stage. The target programming stage is either the first or second programming stage, and the aforementioned target pre-charging method refers to the pre-charging method used in the pre-charging stage preceding the target programming stage.

[0130] For example, if the target programming stage is the first programming stage, the third pre-charging method can adopt the first pre-charging mode, and the duration of the third pre-charging stage is longer than the duration of the first pre-charging stage. If the target programming stage is the second programming stage, the third pre-charging method can adopt the second pre-charging mode, and the duration of the third pre-charging stage is longer than the duration of the second pre-charging stage.

[0131] Because the second precharge mode provides better precharge performance, it can be used to precharge the channel of the deselected memory string before performing the second programming stage, where programming interference is relatively severe, to ensure effective suppression of programming interference. Conversely, before performing the first programming stage, where programming interference is relatively minor, the second precharge mode can be used to precharge the channel of the deselected memory string to reduce the precharge time and thus the programming cycle duration.

[0132] Furthermore, a longer precharge duration results in a better precharge effect on the deselection memory string channel. Therefore, in this embodiment, the precharge duration can be increased as the severity of programming interference in the programming stage increases. Based on this, before executing the third programming stage, which causes significant programming interference, the deselection memory string channel can be precharged for a longer period to ensure effective suppression of the programming interference. Conversely, before executing the target programming stage, where programming interference is relatively minor, the deselection memory string channel can be precharged for a shorter period, thereby minimizing the precharge duration while ensuring effective suppression of programming interference. The range of this precharge duration can be from a few microseconds to tens of microseconds.

[0133] Optionally, refer to Figure 9 In (a), the precharge duration can be increased in a stepwise manner as the severity of programming interference increases. That is, the severity of programming interference can be divided into several levels, each corresponding to a different precharge duration. Accordingly, if the severity of programming interference generated when programming a portion of the WL is different but all belong to the same level, then the precharge duration when precharging the channel of the deselected memory string connected to that portion of the WL can be the same.

[0134] Or, refer to Figure 9 In (b), the precharge time increases linearly with the severity of programming interference. That is, each level of programming interference corresponds to a precharge time. Accordingly, if the severity of programming interference generated when programming any two WLs is different, then the precharge time when precharging the channel of the deselected memory string connected to the two WLs will definitely be different.

[0135] Typically, as the number of traversed Write-Levels (WLs, also known as programmed WLs) increases, the channel potential of the select-up memory string to which the select-up memory cell belongs in the most recently traversed selWL gradually decreases, leading to increasingly severe programming interference. In other words, the severity of programming interference increases with the number of programmed WLs. Alternatively, it can be understood that the later the WL is programmed, the more severe the programming interference it generates during the programming phase.

[0136] Therefore, in this embodiment, the word lines programmed earlier can use a second precharge mode to precharge the channels of the deselect memory string. The word lines programmed later can use a first precharge mode to precharge the channels of the deselect memory string. Furthermore, for two word lines using the same precharge mode, the precharge time for the channel of the deselect memory string connected to the word line programmed earlier can be shorter, and the precharge time for the channel of the deselect memory string connected to the word line programmed later can be longer.

[0137] Accordingly, the first and second word lines mentioned above can be arranged sequentially along the programming direction of the 3D memory. Furthermore, the target word line and the third word line can also be arranged sequentially along this programming direction; the target word line refers to the word line corresponding to the target programming stage. That is, the first and second word lines are traversed in a first-to-last order, and the target and third word lines are traversed in a first-to-last order. Alternatively, it can be understood that the second programming stage is executed after the first programming stage, and the third programming stage is executed after the target programming stage.

[0138] For example, assuming the target programming stage is the second programming stage, i.e., the target word line is the second word line, then the first, second, and third word lines can be arranged sequentially along the programming direction, meaning they are traversed in order from first to last. Alternatively, it can be understood as the first, second, and third programming stages being executed sequentially in order from first to last.

[0139] The following section, with accompanying diagrams, describes the precharge modes used for different word lines. For forward programming scenarios, refer to... Figure 10 In (a) of the above, before programming the selected memory cell connected to the portion of WL near SL, a first precharge mode can be used to precharge the channel of the deselected memory string. For example, a precharge voltage can be applied to the channel of the deselected memory string via BL. When performing a programming operation on the selected memory cell connected to the portion of WL near BL, a second precharge mode can be used to precharge the channel. Figure 10 Each rectangle in the diagram can represent one or more storage units connected to a WL.

[0140] For reverse programming scenarios, refer to Figure 11 In (a) of this example, before programming the selected memory cells connected to the portion of WL near BL, a first precharge mode can be used to precharge the channel. For example, a precharge voltage can be applied to the channel via SL. When performing a programming operation on the selected memory cells connected to the portion of WL near SL, a second precharge mode can be used to precharge the channel.

[0141] It should be understood that the increase in the severity of programming interference with the number of programmed word lines (WLs) is only one possible scenario. In other scenarios, the severity of programming interference may vary according to other patterns. For other scenarios, the WLs that will cause more severe programming interference can be identified in advance through testing. Before programming the selected memory cells connected to these WLs, the channels of the deselected memory strings are precharged using a second precharge mode, and / or the channels of the deselected memory strings are precharged for a longer period. Accordingly, the first and third word lines mentioned above can be WLs with relatively severe programming interference as determined by testing, while the first word line is a WL with relatively mild programming interference as determined by testing.

[0142] Example, reference Figure 10 (b) and Figure 11 In (b), if the WL with the most severe programming interference is located in the middle of a group of WLs, the channel can be precharged using a second precharge mode before programming the selected memory cells connected to the middle WLs. Alternatively, refer to Figure 10 In (c) of the forward programming scenario, if the WL with more severe programming interference is located on the side closer to SL, a second pre-charge mode can be used to pre-charge the channel before programming the selected memory cells connected to the portion of WL closest to SL. Alternatively, refer to... Figure 11 In (c) of the reverse programming scenario, if the WL with more severe programming interference is located on the side closer to BL, the channel can be precharged using the second precharge mode before programming the selected memory cell connected to the part of WL closer to BL.

[0143] Optionally, as mentioned above, the process of programming a selected memory cell for each WL connection may include multiple programming cycles, in which the programming voltage applied during the programming phase increases sequentially. Since higher programming voltages typically lead to more severe programming interference, the duration of the pre-charge phase (i.e., pre-charge duration) in the programming cycle can also gradually increase with the number of programming cycles.

[0144] Example, reference Figure 12 In (a) of the diagram, the precharge duration can be increased in a stepwise manner with the increase of the programming loop. Alternatively, refer to... Figure 12 In (b), the precharge duration can increase linearly with the increase of the programming loop.

[0145] In summary, the embodiments of this application provide a channel pre-charge method. This method allows for the pre-charging of the channels of the deselected memory string using different pre-charging methods before writing data to selected memory cells connected to different word lines, thereby effectively improving the flexibility of channel pre-charging. Furthermore, since a better pre-charging method can be used for word lines with severe programming interference, it can effectively suppress programming interference.

[0146] Figure 13 This is a flowchart of a memory programming method provided in an embodiment of this application, such as... Figure 13 As shown, the method includes:

[0147] Step 301: Precharge the channels of the deselected memory string in the memory using a precharge method.

[0148] The implementation process of this pre-charging method can be referred to the above. Figure 2 or Figure 5 The relevant descriptions of the embodiments shown will not be repeated here.

[0149] Step 302: In the programming stage following each precharge stage in the precharge method, selected memory cells in the memory are programmed.

[0150] During this programming phase, a programming voltage can be applied to the WL (i.e., sel WL) connected to the selected memory cell, thereby writing data into the selected memory cell.

[0151] Understandably, the process of programming a selected memory cell for each WL connection can include multiple programming cycles, each consisting of a pre-charge phase and a programming phase. The programming voltage applied during the programming phase of these multiple programming cycles increases sequentially.

[0152] Figure 14 This is a schematic diagram of a channel pre-charging device provided in an embodiment of this application. This device can be used to implement... Figure 2 or Figure 5 The illustrated embodiment provides a channel pre-charging method. For example... Figure 14 As shown, the device includes:

[0153] The first precharge module 401 is used to precharge the channel of the deselected memory string using a first precharge method during the precharge stage before programming the selected memory cell connected to the first word line.

[0154] The second precharge module 402 is used to precharge the channel of the deselected memory string using a second precharge method during the precharge stage before programming the selected memory cell connected to the second word line. The second word line is different from the first word line.

[0155] The severity of programming interference caused by programming the selected memory cell connected to the second word line is greater than the severity of programming interference caused by programming the selected memory cell connected to the first word line; the pre-charging effect of the second pre-charging method is better than the pre-charging effect of the first pre-charging method.

[0156] Optionally, the first pre-charging method and the second pre-charging method can adopt different pre-charging modes; wherein, the pre-charging mode adopted by the first pre-charging method includes: turning on the first target selection transistor in the deselected memory string, and applying a pre-charging voltage to the channel of the deselected memory string through the first target selection transistor, wherein the first target selection transistor is an upper selection transistor or a lower selection transistor;

[0157] The second pre-charge method employs a pre-charge mode that includes: applying a bias voltage to a second target select transistor in the deselect memory string to cause the second target select transistor to generate a GIDL, the second target select transistor including at least one of an upper select transistor and a lower select transistor.

[0158] Optionally, the first pre-charging method and the second pre-charging method may adopt the same pre-charging mode, and the pre-charging time of the second pre-charging method is longer than the pre-charging time of the first pre-charging method.

[0159] Optionally, the pre-charging modes employed by the first pre-charging method and the second pre-charging method include:

[0160] Turn on the first target select transistor in the deselected memory string, and apply a pre-charge voltage to the channel of the deselected memory string through the first target select transistor. The first target select transistor is either an upper select transistor or a lower select transistor.

[0161] Alternatively, a bias voltage may be applied to a second target select transistor in the deselect memory string to cause the second target select transistor to generate a GIDL, the second target select transistor including at least one of an upper select transistor and a lower select transistor.

[0162] Optionally, the stage of programming the second word line is performed after the stage of programming the first word line.

[0163] Continue to refer to Figure 14 The device may also include:

[0164] The third precharge module 403 is used to precharge the channel of the deselected memory string in a third precharge method during the precharge stage before programming the selected memory cell connected to the third word line. The third word line is different from the first word line and different from the second word line.

[0165] The severity of programming interference caused by programming the selected memory cell connected to the third word line is greater than the severity of programming interference caused by programming the selected memory cell connected to the target word line, where the target word line is either the first word line or the second word line; the third pre-charge method uses the same pre-charge mode as the target pre-charge method, and the pre-charge duration of the third pre-charge method is greater than the pre-charge duration of the target pre-charge method, where the target pre-charge method is the pre-charge method used in the pre-charge stage before programming the selected memory cell connected to the target word line.

[0166] Optionally, the stage of programming the target word line is executed after the stage of programming the first word line. That is, the third programming stage is executed after the target programming stage.

[0167] In summary, the embodiments of this application provide a channel pre-charging device. Before writing data to selected memory cells connected to different word lines, this device can pre-charge the channels of the deselected memory string using different pre-charging methods, thereby effectively improving the flexibility of channel pre-charging. Furthermore, since a better pre-charging method can be used for word lines with severe programming interference, it can effectively suppress programming interference.

[0168] Figure 15 This is a schematic diagram of a memory programming device provided in an embodiment of this application. This device can be used to implement... Figure 13 The programming method provided in the illustrated embodiment. For example... Figure 15 As shown, the device includes: a pre-charging module 501 and a programming module 502;

[0169] The pre-charge module 501 is used to pre-charge the channels of the deselected memory string in the memory using the pre-charge method provided in the above method embodiment.

[0170] The programming module 502 is used to program selected memory cells in the memory during a programming phase following each precharge phase in the precharge method.

[0171] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the channel pre-charging device, the memory programming device, and each module in each device described above can all be referred to the relevant descriptions in the foregoing method embodiments, and will not be repeated here.

[0172] This application provides a control circuit that includes programmable logic circuitry and / or program instructions. The control circuit can be used to implement the channel pre-charge method or memory programming method provided in the foregoing embodiments of this application.

[0173] This application provides a computer-readable storage medium storing instructions that, when executed in a control circuit, cause the control circuit to implement the channel pre-charge method or memory programming method provided in the foregoing embodiments of this application.

[0174] Figure 16 This is a schematic diagram of the structure of a memory provided in an embodiment of this application. For example... Figure 16 As shown, the memory includes a memory array 001 and a control circuit 002. The memory array 001 includes multiple memory strings. The control circuit 002 can be the control circuit provided in the foregoing embodiments. Alternatively, the control circuit can include the channel pre-charging device provided in the foregoing embodiments, for example, it can include... Figure 14 or Figure 16 The device shown. Alternatively, the control circuit may include the memory programming device provided in the foregoing embodiments, for example, it may include... Figure 15 The apparatus shown.

[0175] This control circuit 002 can also be referred to as the peripheral circuit. For example... Figure 16 As shown, the control circuit 002 may include a voltage generator 0021, a control logic circuit 0022, an address decoder 0023, a data buffer 0024, and a read / write circuit 0025.

[0176] The voltage generator 0021 is connected to both the control logic circuit 0022 and the address decoder 0023. The voltage generator 0021 is used to generate various voltages under the control of the control logic circuit 0022. For example, it generates erase voltage, programming voltage, turn-on voltage, and read voltage.

[0177] Address decoder 0023 can be connected to memory array 001 via row lines RL. Row lines RL may include drain select lines, word lines, source select lines, and source lines. Address decoder 0023, under the control of control logic circuit 0022, applies the voltage generated by voltage generator 0021 to row lines RL. For example, address decoder 0023 can decode the address sent by control logic circuit 0022 and, based on the decoded address, apply the voltage generated by voltage generator 0021 to the corresponding word line.

[0178] The data buffer 0024 is connected to both the control logic circuit 0022 and the read / write circuit 0025. The data buffer 0024 is used to send received control signals and addresses to the control logic circuit 0022, to send data DATA input from an external device to the read / write circuit 0025, and to output data DATA received from the read / write circuit 0025 to an external device.

[0179] The read / write circuit 0025 is also connected to the control logic circuit 0022 and each bit line (e.g., BL1 to BLn). The read / write circuit 0025 operates under the control of the control logic circuit 0022. During programming operations, the read / write circuit 0025, under the control of the control logic circuit 0022, applies voltage to each bit line based on the data DATA sent from the data buffer 0024. During read operations, the read / write circuit 0025, under the control of the control logic circuit 0022, reads data DATA from the memory array 001 via the bit lines and outputs the read data DATA to the data buffer 0024.

[0180] This application also provides a memory system, such as... Figure 17 As shown, the memory system includes at least one memory 100 and a controller 200 connected to the at least one memory 100. For example, Figure 17 The diagram shows multiple memories 100. Each memory 100 can be the memory provided in the above embodiments. The controller 200 can also be called a memory controller, and each memory 100 can also be called a memory chip.

[0181] Optionally, such as Figure 17 As shown, the controller 200 can be connected to the host via the host interface.

[0182] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "at least one" means one or more, and the term "multiple" means two or more, unless otherwise expressly defined.

[0183] In this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0184] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. The scope of protection of this application should be determined by the scope of the claims.

Claims

1. A channel pre-charging method, characterized in that, The method includes: In the pre-charge phase before programming the selected memory cell connected to the first word line, the channel of the deselected memory string is pre-charged using the first pre-charge method. In the pre-charge stage before programming the selected memory cell connected to the second word line, the channel of the deselected memory string is pre-charged using the second pre-charge method. In the pre-charge stage before programming the selected memory cell connected to the third word line, the channel of the deselected memory string is pre-charged using a third pre-charge method, wherein the first word line, the second word line, and the third word line are different from each other. The programming stage for the second character line is executed after the programming stage for the first character line, and the programming stage for the third character line is executed after the programming stage for the target character line, wherein the target character line is either the first character line or the second character line. The pre-charging mode adopted by the first pre-charging method includes: turning on the first target selection transistor in the deselected memory string, and applying a pre-charging voltage to the channel of the deselected memory string through the first target selection transistor, so that electrons in the channel of the deselected memory string migrate out of the channel through the turned-on first target selection transistor, wherein the first target selection transistor is an upper selection transistor or a lower selection transistor. The pre-charge mode adopted by the second pre-charge method includes: applying a bias voltage to the second target select transistor in the deselect memory string to generate gate-induced drain leakage current (GIDL) in the second target select transistor, wherein the GIDL includes electron-hole pairs, and the holes in the electron-hole pairs can recombine with electrons in the channel of the deselect memory string, and the second target select transistor includes at least one of an upper select transistor and a lower select transistor. The third pre-charging method uses the same pre-charging mode as the target pre-charging method, and the pre-charging duration of the third pre-charging method is longer than that of the target pre-charging method. The target pre-charging method is the pre-charging method used in the pre-charging stage before programming the selected memory cell connected to the target word line.

2. The method according to claim 1, characterized in that, The process of programming the selected memory cell connected to each of the first word line, the second word line, and the third word line includes multiple programming loops, and the pre-charge duration of the pre-charge phase in the multiple programming loops increases with the increase of the programming loops.

3. The method according to claim 1 or 2, characterized in that, If the memory programming direction is positive, then the first target selector is the up selector; If the memory programming direction is reversed, then the first target selector is the down selector.

4. A method for programming a memory, characterized in that, The programming method includes: The channels of the deselected memory string in the memory are precharged using the precharge method as described in any one of claims 1 to 3; And, in the programming phase following each precharge phase in the precharge method, selected memory cells in the memory are programmed.

5. A channel pre-charging device, characterized in that, The device includes: The first precharge module is used to precharge the channel of the deselected memory string in a first precharge method during the precharge stage before programming the selected memory cell connected to the first word line. The second precharge module is used to precharge the channel of the deselected memory string in a second precharge method during the precharge stage before programming the selected memory cell connected to the second word line. The third precharge module is used to precharge the channel of the deselected memory string in the precharge stage before programming the selected memory cell connected to the third word line. The first word line, the second word line and the third word line are different from each other. The programming stage for the second character line is executed after the programming stage for the first character line, and the programming stage for the third character line is executed after the programming stage for the target character line, wherein the target character line is either the first character line or the second character line. The pre-charging mode adopted by the first pre-charging method includes: turning on the first target selection transistor in the deselected memory string, and applying a pre-charging voltage to the channel of the deselected memory string through the first target selection transistor, so that electrons in the channel of the deselected memory string migrate out of the channel through the turned-on first target selection transistor, wherein the first target selection transistor is an upper selection transistor or a lower selection transistor. The pre-charge mode adopted by the second pre-charge method includes: applying a bias voltage to the second target select transistor in the deselect memory string to generate gate-induced drain leakage current (GIDL) in the second target select transistor, wherein the GIDL includes electron-hole pairs, and the holes in the electron-hole pairs can recombine with electrons in the channel of the deselect memory string, and the second target select transistor includes at least one of an upper select transistor and a lower select transistor. The third pre-charging method uses the same pre-charging mode as the target pre-charging method, and the pre-charging duration of the third pre-charging method is longer than that of the target pre-charging method. The target pre-charging method is the pre-charging method used in the pre-charging stage before programming the selected memory cell connected to the target word line.

6. The apparatus according to claim 5, characterized in that, The process of programming the selected memory cell connected to each of the first word line, the second word line, and the third word line includes multiple programming loops, and the pre-charge duration of the pre-charge phase in the multiple programming loops increases with the increase of the programming loops.

7. The apparatus according to claim 5 or 6, characterized in that, If the memory programming direction is positive, then the first target selector is the up selector; If the memory programming direction is reversed, then the first target selector is the down selector.

8. A memory programming device, characterized in that, The device includes: a pre-charging module and a programming module; The pre-charge module is used to pre-charge the channels of the deselected memory string in the memory using the pre-charge method as described in any one of claims 1 to 3. The programming module is used to program selected memory cells in the memory during a programming phase following each pre-charge stage in the pre-charge method.

9. A control circuit, characterized in that, The control circuit includes programmable logic circuitry and / or program instructions, and the control circuit is used to implement the method as described in any one of claims 1 to 4.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores instructions that, when executed on a control circuit, implement the method as described in any one of claims 1 to 4.

11. A memory, characterized in that, The memory includes: a storage array and a control circuit; The control circuit is the control circuit as described in claim 9, or the control circuit includes the device as described in any one of claims 5 to 8.

12. A memory system, characterized in that, The memory system includes: a controller, and at least one memory as described in claim 11.

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