An antifuse array and programmable non-volatile memory

Abstract

The present disclosure relates to the technical field of integrated circuits, and discloses an anti-fuse array and a programmable non-volatile memory. The read circuit of the anti-fuse array comprises a comparison circuit, a first output control circuit and a latch circuit. The comparison circuit is connected to a second node, a third node and a fourth node, and has a first signal end and a second signal end. The first signal end or the second signal end is connected to a data port. The comparison circuit can output a first sensing signal to the third node and a second sensing signal to the fourth node according to the comparison result of the signals of the first signal end and the second signal end in response to the signal of the second node when the clock control signal is at a first level. The first output control circuit is connected to the second node and a ground end, and is used for turning on the second node and the ground end when the clock control signal is at the first level. The latch circuit is connected to the third node and the fourth node, and can output the data stored by the anti-fuse array according to the first sensing signal and the second sensing signal.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuits, and more specifically, to an antifuse array and a programmable nonvolatile memory. Background Technology

[0002] One-Time Programmable (OTP) memory is characterized by its storage state being unaffected by power outages, making it applicable to various technical fields. OTP memory cells can be divided into fuse OTP memory cells and anti-fuse OTP memory cells. Taking an anti-fuse OTP memory cell as an example, when an anti-fuse OTP memory cell is not programmed, it has a high impedance storage state; conversely, when an anti-fuse OTP memory cell is programmed, it has a low impedance storage state.

[0003] The stored information of the antifuse type OTP memory cell can be identified and output through the antifuse status reading circuit. In related technologies, the reading circuit in the antifuse type OTP memory is prone to power supply voltage instability.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] This disclosure provides an antifuse array and a programmable nonvolatile memory.

[0006] According to one aspect of this disclosure, an antifuse array is provided, the antifuse array including a readout circuit connected to a data port of the antifuse array, the readout circuit including: a comparator circuit connected to a second node, a third node, and a fourth node, and having a first signal terminal and a second signal terminal, the first signal terminal or the second signal terminal being connected to the data port, the comparator circuit being configured to, in response to a signal from the second node when a clock control signal is at a first level, output a first sensing signal to the third node and a second sensing signal to the fourth node based on a comparison result of the signals from the first signal terminal and the second signal terminal; a first output control circuit connected to the second node and a ground terminal, the first output control circuit being configured to turn on the second node and the ground terminal when the clock control signal is at the first level; and a latch circuit connected to the third node and the fourth node, the latch circuit being configured to output data stored in the antifuse array based on the first sensing signal and the second sensing signal.

[0007] In some embodiments, the comparison circuit includes: a comparison unit connected to the second node, the fifth node, and the sixth node, the comparison unit having a first signal terminal and a second signal terminal, the first signal terminal being connected to the data port, the second signal terminal being used to receive a preset reference signal, the comparison unit being configured to compare the data signal of the data port with the preset reference signal, and adjusting the voltage values ​​of the fifth node and the sixth node according to the comparison result in response to the signal of the second node; and a signal amplification unit connected to the fifth node, the sixth node, the third node, the fourth node, and the first node, the signal amplification unit being configured to amplify the voltage difference between the fifth node and the sixth node, and output the first sensing signal to the third node and the second sensing signal to the fourth node.

[0008] In some embodiments, the comparison unit includes: a sixth transistor, the first end of which is connected to a fifth node, the second end of which is connected to a second node, and the control terminal of which receives the preset reference signal; and a seventh transistor, the first end of which is connected to the sixth node, the second end of which is connected to the second node, and the control terminal of which is connected to the data port; the sixth transistor and the seventh transistor are of the same transistor type.

[0009] In some embodiments, the sixth transistor and the seventh transistor are both N-type field-effect transistors.

[0010] In some embodiments, the signal amplification unit includes: a fourth transistor, the first terminal of which is connected to the third node, the second terminal of which is connected to the fifth node, and a control terminal of which is connected to the fourth node; a fifth transistor, the first terminal of which is connected to the fourth node, the second terminal of which is connected to the sixth node, and a control terminal of which is connected to the third node; a first transistor, the first terminal of which is connected to the first node, the second terminal of which is connected to the third node, and a control terminal of which is connected to the fourth node; and a third transistor, the first terminal of which is connected to the first node, the second terminal of which is connected to the fourth node, and a control terminal of which is connected to the third node; wherein the fourth transistor and the fifth transistor are of the same type, and the first transistor and the third transistor are of the same type.

[0011] In some embodiments, the fourth transistor and the fifth transistor are N-type field-effect transistors; the first transistor and the third transistor are P-type field-effect transistors.

[0012] In some embodiments, the reading circuit further includes: a second output control circuit connected to the first node, the third node, and the fourth node, wherein the second output control circuit is configured to transmit the charging signal of the first node to the third node and the fourth node when the clock control signal is at a second level, wherein the first level of the clock control signal is out of phase with the second level.

[0013] In some embodiments, the second output control circuit includes: a tenth transistor, the first terminal of which is connected to the first node, the second terminal of which is connected to the third node, and the control terminal of which receives the clock control signal; a second transistor, the first terminal of which is connected to the first node, the second terminal of which is connected to the fourth node, and the control terminal of which receives the clock control signal; the second transistor and the tenth transistor are of the same type.

[0014] In some embodiments, the first output control circuit includes: an eighth transistor, a first terminal of which is connected to the second node, a second terminal of which is connected to ground, a control terminal of which receives the clock control signal, and the second transistor and the eighth transistor are of different types.

[0015] In some embodiments, the eighth transistor is an N-type field-effect transistor, and the second transistor and the tenth transistor are both P-type field-effect transistors.

[0016] In some embodiments, the readout circuit further includes a level adjustment circuit connected to the fifth node and the sixth node, the level adjustment circuit being configured to adjust the voltage of the fifth node and the sixth node according to the clock control signal.

[0017] In some embodiments, the level adjustment circuit includes: a ninth transistor, a first terminal of which is connected to the fifth node, a second terminal of which is connected to the sixth node, and a control terminal of which receives a first voltage signal.

[0018] In some embodiments, the latching circuit includes a first NAND gate and a second NAND gate, wherein the first input terminal of the first NAND gate is connected to the third node, and the second input terminal of the first NAND gate is connected to the output terminal of the second NAND gate; the first input terminal of the second NAND gate is connected to the fourth node, and the second input terminal of the second NAND gate is connected to the output terminal of the first NAND gate; the latching circuit outputs the data stored in the antifuse array through the output terminal of the first NAND gate or through the output terminal of the second NAND gate;

[0019] In some embodiments, after the data signal is output from the data port, the clock control signal transitions from the second level to the first level.

[0020] In some embodiments, the circuit further includes a pre-charge circuit, which is configured to correspond to the read circuit. The pre-charge circuit is connected to a first signal terminal of the comparison circuit and is configured to pre-charge the first signal terminal of the comparison circuit before the clock control signal is at the first level.

[0021] According to a second aspect of this disclosure, a programmable non-volatile memory is also provided, including the antifuse array described in any embodiment of this disclosure.

[0022] In some embodiments, the memory further includes: a plurality of output circuits, each of the output circuits being connected to a row of the read circuits in the antifuse array and receiving an array select signal, the output circuits being configured to output data read by the read circuits according to the array select signal.

[0023] In the antifuse array provided in this disclosure, the comparator circuit in the read circuit can compare the signals of the first signal terminal and the second signal terminal, and output a first sensing signal to the third node and a second sensing signal to the fourth node when the clock control signal is at the first level. The latch can output the data stored in the antifuse array according to the first sensing signal and the second sensing signal. The first output control circuit in the read circuit can turn on the second node and the ground terminal when the clock control signal is at the first level. Because the second node is connected to the ground terminal when the clock control signal is at the first level, and the signals received by the first signal terminal and the second signal terminal of the comparator circuit are different, the comparator circuit can output different sensing signals to the third node and the fourth node. The latch circuit can output the data stored in the antifuse array according to the sensing signals of the third node and the fourth node. At the same time, compared with the conventional read circuit, the read circuit provided in this disclosure is disconnected from ground when the clock control signal is at a stable first level and the second level, so it does not consume current. It only consumes current at the transition moment of the clock control signal (i.e., rising edge or falling edge). Therefore, the read circuit provided in this disclosure can reduce the power consumption of the memory.

[0024] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0025] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0026] Figure 1 This is a schematic diagram of the structure of an antifuse array according to one embodiment of the present disclosure;

[0027] Figure 2 for Figure 1 A schematic diagram of the reading circuit.

[0028] Figure 3 This is a schematic diagram of the readout circuit of an antifuse array in related technologies;

[0029] Figure 4 This is a schematic diagram of the structure of a programmable non-volatile memory according to one embodiment of the present disclosure;

[0030] Figure 5 This is a schematic diagram of the multiplexing of array selection sub-signals according to one embodiment of the present disclosure;

[0031] Figure 6 This is a schematic diagram of the output circuit according to one embodiment of the present disclosure;

[0032] Figure 7 This is a schematic diagram of the output circuit according to another embodiment of the present disclosure;

[0033] Figure 8 This is a schematic diagram of the structure of an output sub-circuit according to one embodiment of the present disclosure. Detailed Implementation

[0034] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0035] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0036] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0037] Figure 1 This is a schematic diagram of an antifuse array according to one embodiment of the present disclosure. Figure 2 for Figure 1 A schematic diagram of the reading circuit is shown below. Figure 1 , Figure 2 As shown, the antifuse array may include a read circuit 100 connected to the data port of the antifuse array. The read circuit 100 may include a comparator circuit 110, a first output control circuit 120, and a latch circuit 130. The comparator circuit 110 is connected to the second node N2, the third node N3, and the fourth node N4, and has a first signal terminal Vminus and a second signal terminal Vplus. The first signal terminal Vminus or the second signal terminal Vplus is connected to the data port. The comparator circuit 110 is configured to respond to the signal root of the second node N2 when the clock control signal CLK is at the first level. Based on the signal comparison result of the first signal terminal Vminus and the second signal terminal Vplus, a first sensing signal S1 is output to the third node N3 and a second sensing signal S2 is output to the fourth node N4; the first output control circuit 120 is connected to the second node N2 and the ground terminal, and the first output control circuit 120 is configured to turn on the second node N2 and the ground terminal when the clock control signal CLK is at the first level; the latch circuit 130 is connected to the third node N3 and the fourth node N4, and the latch circuit 130 is configured to output the data F_Data stored in the antifuse array according to the first sensing signal S1 and the second sensing signal S2.

[0038] In the antifuse array provided in this disclosure, the comparator circuit 110 in the read circuit 100 can compare the signals of the first signal terminal Vminus and the second signal terminal Vplus, and output a first sensing signal S1 to the third node N3 and a second sensing signal S2 to the fourth node N4 when the clock control signal CLK is at the first level. The latch can output the data F_Data stored in the antifuse array according to the first sensing signal S1 and the second sensing signal S2. The first output control circuit 120 in the read circuit 100 can turn on the second node N2 and the ground terminal when the clock control signal CLK is at the first level. Because the second node N2 is turned on and the ground terminal is connected when the clock control signal CLK is at the first level, and the signals received by the first signal terminal Vminus and the second signal terminal Vplus of the comparator circuit 110 are different, the comparator circuit 110 can output different sensing signals to the third node N3 and the fourth node N4. The latch circuit 130 can output the data F_Data stored in the antifuse array according to the sensing signals of the third node N3 and the fourth node N4. Meanwhile, compared with traditional read circuits, the read circuit 100 provided in this disclosure disconnects the comparison circuit 110 to ground when the clock control signal CLK is at a stable first level and a stable second level, so it does not consume current. It only consumes current when the clock control signal CLK is at a transition moment (i.e., rising edge or falling edge). Therefore, the read circuit 100 provided in this disclosure can reduce the power consumption of the memory.

[0039] like Figure 2 In this exemplary embodiment, the first level can be a high level, meaning that when the clock control signal CLK is high, the comparator circuit 110 can respond to the signal of the second node N2 by comparing the signals of the first signal terminal Vminus and the second signal terminal Vplus to output a first sensing signal S1 to the third node N3 and a second sensing signal S2 to the fourth node N4. The first sensing signal S1 and the second sensing signal S2 can be inverted signals, meaning that when the first sensing signal S1 is high, the second sensing signal S2 is low; or, when the first sensing signal S1 is low, the second sensing signal S2 is high.

[0040] In this exemplary embodiment, the data F_Data stored in the antifuse array is the status data of the antifuse storage cells in the antifuse array. The status data of the antifuse storage cells includes programmed status data and unprogrammed status data. When the antifuse storage cell has been programmed, its status can be represented by the data "1", and when the antifuse storage cell has not been programmed, its status can be represented by the data "0". The antifuse array read circuit 100 can read the status data F_Data of the selected antifuse storage cells in the antifuse array, and then output the read status data F_Data of the antifuse storage cells through the output circuit.

[0041] In this exemplary embodiment, the comparator circuit 110 has a first signal terminal Vminus and a second signal terminal Vplus. The first signal terminal Vminus can control one branch, and the second signal terminal Vplus can control another branch. The comparator circuit 110 can control each branch to have different states based on the comparison result between the signal of the first signal terminal Vminus and the signal of the second signal terminal Vplus, thereby outputting corresponding sensing signals to the third node N3 and the fourth node N4. One of the two signal terminals of the comparator circuit 110 is connected to the data port of the antifuse array to receive the data F_Data stored in the antifuse array. For example, the first signal terminal Vminus of the comparator circuit 110 can be connected to the data port of the antifuse array, and the second signal terminal Vplus can be used to receive a preset reference signal Vref. Thus, the comparator circuit 110 can compare the received data signal from the data port with the preset reference signal Vref, and output a first sensing signal S1 to the third node N3 and a second sensing signal S2 to the fourth node N4 based on the comparison result. Of course, in other embodiments, the first signal terminal Vminus of the comparator circuit 110 may receive a preset reference signal Vref, and the second signal may be connected to the data port of the antifuse array. This disclosure is not limited thereto.

[0042] In this exemplary embodiment, the latch circuit 130 in the read circuit 100 can output the data F_Data stored in the antifuse array according to the first sensing signal S1 and the second sensing signal S2. For example, when the selected antifuse unit in the antifuse array is not programmed, the data F_Data stored in the antifuse array is 0. Taking the first signal terminal Vminus of the comparator circuit 110 connected to the data port of the antifuse array as an example, the potential of the first signal terminal Vminus is pulled low by the data F_Data stored in the antifuse array, making the potential of the first signal terminal Vminus lower than the potential of the second signal terminal Vplus. The clock control signal CLK is high, the first output control circuit 120 is turned on, pulling the potential of the second node N2 low. The branch controlled by the first signal terminal Vminus of the comparator circuit 110 connects to the fourth node N4 and the second node N2, and the branch controlled by the second signal terminal Vplus connects to... The potentials of the third node N3 and the second node N2, and the fourth node N4 are all pulled low by the second node N2. Because the potential of the first signal terminal Vminus is lower than the potential of the second signal terminal Vplus, the potential of the fourth node N4 decreases more slowly than the potential of the third node N3. That is, the potential of the fourth node N4 is higher than the potential of the third node N3. As a result, the comparator circuit 110 outputs a low-level first sensing signal S1 to the third node N3 and a high-level second sensing signal S2 to the fourth node N4. The latch circuit 130 can output a low-level signal and latch it by inverting the output terminal based on these two sensing signals, so that the latch circuit 130 latches the data F_Data stored in the antifuse array.

[0043] The readout circuit 100 of the antifuse array of this disclosure will be further described below with reference to the accompanying drawings.

[0044] like Figure 2As shown in this exemplary embodiment, the comparison circuit 110 may include a comparison unit 111 and a signal amplification unit 112. The comparison unit 111 is connected to the second node N2, the fifth node N5, and the sixth node N6. The comparison unit 111 has a first signal terminal Vminus and a second signal terminal Vplus. The first signal terminal Vminus can be connected to a data port, and the second signal terminal Vplus can be used to receive a preset reference signal. The comparison unit 111 can be used to compare the data signal of the data port with the preset reference signal Vref, and adjust the voltage values ​​of the fifth node N5 and the sixth node N6 according to the comparison result in response to the signal of the second node N2. The signal amplification unit 112 is connected to the fifth node N5, the sixth node N6, the third node N3, the fourth node N4, and the first node N1. The signal amplification unit 112 can be used to amplify the voltage difference between the fifth node N5 and the sixth node N6, and output a first sensing signal S1 to the third node N3 and a second sensing signal S2 to the fourth node N4. For example, the comparison unit 111 can control two branches: one branch connects to the fifth node N5 and the second node N2, and the other branch connects to the sixth node N6 and the second node N2. The comparison unit 111 can compare the received data signal from the data port with the received reference signal Vref and adjust the state of the two branches accordingly, thereby adjusting the voltage values ​​of the fifth node N5 and the sixth node N6. For instance, when the second node N2 is at a low level, if the data signal is higher than the preset reference signal Vref, the comparison unit 111 can control one branch to quickly pull down the voltage of the fifth node N5 after comparison, thereby adjusting the voltage value of the fifth node N5 to be lower than the voltage value of the sixth node N6. The signal amplification unit 112 can amplify the voltage difference between the sixth node N6 and the fifth node N5, and control the voltage value of the fourth node N4 to be greater than the voltage value of the third node N3 to form positive feedback so that the voltage value of the fourth node N4 is increasingly greater than the voltage value of the third node N3, thereby ultimately outputting a low-level first sensing signal S1 to the third node N3 and a high-level second sensing signal S2 to the fourth node N4.

[0045] like Figure 2As shown in this exemplary embodiment, the comparison unit 111 and the signal amplification unit 112 can be implemented using transistors. For example, the comparison unit 111 may include a sixth transistor M6 and a seventh transistor M7. The first terminal of the sixth transistor M6 can be connected to the fifth node N5, and the second terminal of the sixth transistor M6 can be connected to the second node N2. The control terminal of the sixth transistor M6 can be used to receive a preset reference signal Vref to receive a data signal. The first terminal of the seventh transistor M7 can be connected to the sixth node N6, and the second terminal of the seventh transistor M7 can be connected to the second node N2. The control terminal of the seventh transistor M7 can be connected to a data port; and the sixth transistor M6 and the seventh transistor M7 are of the same transistor type. The signal amplification unit 112 may include a fourth transistor M4, a fifth transistor M5, a first transistor M1, and a third transistor M3. The first terminal of the fourth transistor M4 can be connected to the third node N3, the second terminal of the fourth transistor M4 can be connected to the fifth node N5, and the control terminal of the fourth transistor M4 can be connected to the fourth node N4. The first terminal of the fifth transistor M5 can be connected to the fourth node N4, the second terminal of the fifth transistor M5 can be connected to the sixth node N6, and the control terminal of the fifth transistor M5 can be connected to the third node N3. The first terminal of the first transistor M1 can be connected to the first node N1, the second terminal of the first transistor M1 can be connected to the third node N3, and the control terminal of the first transistor M1 can be connected to the fourth node N4. The first terminal of the third transistor M3 can be connected to the first node N1, the second terminal of the third transistor M3 can be connected to the fourth node N4, and the control terminal of the third transistor M3 can be connected to the third node N3. Furthermore, the fourth transistor M4 and the fifth transistor M5 are of the same type, and the first transistor M1 and the third transistor M3 are of the same type.

[0046] For example, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 can all be N-type field-effect transistors, and the first transistor M1 and the third transistor M3 can both be P-type field-effect transistors. When the second node N2 is low, if the data signal level of the data port is higher than the reference signal level, the turn-on degree of the sixth transistor M6 is less than that of the seventh transistor M7. Also, because the second node N2 is low, the sixth node N6 is pulled down faster than the fifth node N5, resulting in the voltage value of the sixth node N6 being less than the voltage value of the fifth node N5. When the fourth transistor M4 and the fifth transistor M5 are turned on at the same level, the potential of the first terminal of the fifth transistor M5 is lower than that of the first terminal of the fourth transistor M4. That is, the potential of the fourth node N4 is lower than that of the third node N3. Since the control terminal of the third transistor M3 is connected to the third node N3 and the control terminal of the first transistor M1 is connected to the fourth node N4, and both the first transistor M1 and the third transistor M3 are P-type field-effect transistors, the turn-on degree of the third transistor M3 is less than that of the first transistor M1. Since the first terminals of the first transistor M1 and the first terminals of the third transistor M3 are both connected to the high-level first voltage signal VDD, the voltage difference between the third node N3 and the fourth node N4 becomes larger and larger. That is, the voltage of the third node N3 is increasingly larger than the voltage of the fourth node N4. This further leads to the turn-on degree of the fourth transistor M4 becoming smaller and smaller, and the turn-on degree of the fifth transistor M5 becoming larger and larger, until the third transistor M3 and the fourth transistor M4 are completely turned off. The fourth node N4 is pulled down to the low-level second voltage signal VSS, and the third node N3 is pulled up to the high-level first voltage signal VDD. Ultimately, the signal amplification unit 112 amplifies the voltage difference between the fifth node N5 and the sixth node N6, and outputs the correct sensing signal through the third node N3 and the fourth node N4. Conversely, when the second node N2 is low, if the data signal level of the data port is lower than the reference signal level, the first transistor M1 and the fifth transistor M5 are completely turned off, the third node N3 is pulled low to the second voltage signal VSS, and the fourth node N4 is pulled high to the first voltage signal VDD. It should be understood that in other embodiments, the comparison unit 111 and the signal amplification unit 112 may have other circuit structures, and this disclosure is not limited thereto.

[0047] like Figure 2As shown in this exemplary embodiment, the latch circuit 130 may include a first NAND gate circuit 131 and a second NAND gate circuit 132. The first input terminal of the first NAND gate circuit 131 is connected to the third node N3, and the second input terminal of the first NAND gate circuit 131 is connected to the output terminal of the second NAND gate circuit 132. The first input terminal of the second NAND gate circuit 132 is connected to the fourth node N4, and the second input terminal of the second NAND gate circuit 132 is connected to the output terminal of the first NAND gate circuit 131. The latch circuit 130 can output the data F_Data stored in the antifuse array through the output terminal of the first NAND gate circuit 131 or through the output terminal of the second NAND gate circuit 132. For example, when both the third node N3 and the fourth node N4 are high (comparator circuit 110 is not enabled), the first input terminal SB of the first NAND gate circuit 131 and the first input terminal RB of the second NAND gate circuit 132 of the latch circuit 130 are both high-level signals. At this time, the output signal of the first NAND gate circuit 131 depends on the output signal of the second NAND gate circuit 132 at the previous moment, and the output signal of the second NAND gate depends on the output signal of the first NAND gate circuit 131 at the previous moment. Taking the data F_Data stored in the antifuse array that the read circuit 100 outputs through the output terminal of the second NAND gate of the latch circuit 130 as an example, if the first NAND gate circuit 131 output a low-level signal at the previous moment, then obviously the second NAND gate output a high-level signal at the previous moment. One input terminal of the second NAND gate circuit 132 obtains a high-level signal, and the other input terminal obtains a low-level signal. The second NAND gate circuit 132 then outputs a high-level signal, which is the same as the output signal at the previous moment, maintaining the output signal state at the previous moment. If the first NAND gate 131 output a high-level signal in the previous moment, then obviously the second NAND gate 132 output a low-level signal in the previous moment. Both input terminals of the second NAND gate 132 obtain high-level signals, and the second NAND gate 132 outputs a low-level signal at this time, maintaining the data signal state of the previous moment.

[0048] When the comparator circuit 110 is enabled, the third node N3 and the fourth node N4 are respectively a high-level signal and a low-level signal. Taking the example where the third node N3 is a high-level signal, the fourth node N4 is a low-level signal, and the read circuit 100 outputs the data F_Data stored in the antifuse array through the second NAND gate circuit 132 of the latch circuit 130, as can be seen from the above analysis, at this time, it is equivalent to the signal of the first signal terminal Vminus of the comparator circuit 110 being higher than the signal of the second signal terminal Vplus. That is, the selected antifuse unit in the antifuse array is programmed, and the data F_Data stored in the antifuse array received by the first signal terminal Vminus of the comparator circuit 110 is a high level. At this time, the first input terminal RB of the second NAND gate circuit 132 of the latch circuit 130 is a low-level signal, so the second NAND gate circuit 132 outputs a high-level signal, outputting the data F_Data stored in the antifuse array. Of course, in other embodiments, the latch circuit 130 may also have other circuit structures, and this disclosure is not limited thereto.

[0049] like Figure 2 As shown in this exemplary embodiment, the reading circuit 100 may further include a second output control circuit 140. The second output control circuit 140 is connected to the first node N1, the third node N3, and the fourth node N4. The second output control circuit 140 can be used to transmit the charging signal of the first node N1 to the third node N3 and the fourth node N4 when the clock control signal CLK is at the second level. Specifically, the first level of the clock control signal CLK is inversely related to the second level; the first level can be high, and the second level can be low. The first node N1 can receive a first voltage signal VDD. When the second output control circuit 140 is at the second level, the second output control circuit 140 is turned on, transmitting the high-level first voltage signal VDD from the first node N1 to the third node N3 and the fourth node N4, making both the third node N3 and the fourth node N4 high. That is, both inputs of the latch circuit 130 receive high-level signals, and the latch circuit 130 retains the antifuse array data signal acquired at the previous moment, thus realizing the function of locking the data F_Data.

[0050] like Figure 2As shown in this exemplary embodiment, both the first output control circuit 120 and the second output control circuit 140 can be implemented using transistors, and the types of transistors in the first output control circuit 120 and the second output control circuit 140 are different. For example, the first output control circuit 120 may include an eighth transistor M8, and the second output control circuit 140 may include a second transistor M2 and a tenth transistor M10. The first terminal of the eighth transistor M8 can be connected to the second node N2, and the second terminal of the eighth transistor M8 can be connected to ground. The control terminal of the eighth transistor M8 can be used to receive the clock control signal CLK. The first terminal of the tenth transistor M10 can be connected to the first node N1, and the second terminal of the tenth transistor M10 can be connected to the third node N3. The control terminal of the tenth transistor M10 can be used to receive the clock control signal CLK. The first terminal of the second transistor M2 can be connected to the first node N1, and the second terminal of the second transistor M2 can be connected to the fourth node N4. The control terminal of the second transistor M2 can be used to receive the clock control signal CLK. The second transistor M2 and the tenth transistor M10 are of the same type, while the type of the eighth transistor M8 is different from the types of the second transistor M2 and the tenth transistor M10. For example, the eighth transistor M8 can be an N-type field-effect transistor, and the second transistor M2 and the tenth transistor M10 can be P-type field-effect transistors. When the clock control signal CLK is low, the eighth transistor M8 is turned off, so that the sensing circuit has no ground path. The second transistor M2 and the tenth transistor M10 are turned on, transmitting the high-level first voltage signal VDD of the first node N1 to the third node N3 and the fourth node N4, so that both input terminals of the latch circuit 130 obtain high-level signals, and the latch circuit 130 maintains the data signal of the antifuse array latched at the previous moment. It is understood that in other embodiments, the first output control circuit 120 and the second output control circuit 140 may also have other circuit structures. Based on other circuit structures, the second output control circuit 140 may transmit the charging signal of the first node N1 to the third node N3 and the fourth node N4 when the clock control signal CLK is at the second level, and the first output control circuit 120 may turn on the second node N2 and the ground terminal when the clock control signal CLK is at the first level. This disclosure is not limited thereto.

[0051] like Figure 2As shown in this exemplary embodiment, the reading circuit 100 may further include a level adjustment circuit 113. The level adjustment circuit 113 can be connected to the fifth node N5 and the sixth node N6. The level adjustment circuit 113 can adjust the voltages of the fifth node N5 and the sixth node N6 according to the clock control signal CLK. The level adjustment circuit 113 can be implemented using transistors. For example, the level adjustment circuit 113 may include a ninth transistor M9. The first terminal of the ninth transistor M9 can be connected to the fifth node N5, the second terminal of the ninth transistor M9 can be connected to the sixth node N6, and the control terminal of the ninth transistor M9 can be used to receive a first voltage signal VDD. Specifically, the ninth transistor M9 can adjust the voltages of the fifth node N5 and the sixth node N6 when the clock control signal CLK decreases from high to low. Specifically, when the clock control signal CLK is high, due to a rising edge, all nodes of the read circuit 100 reach a stable state. Taking the signal level of the first signal terminal Vminus of the comparator circuit 110 as higher than the signal level of the second signal terminal Vplus, in the stable state, the fifth node N5 is at an intermediate level, and the sixth node N6 is low. When the clock control signal CLK becomes low, the second transistor... Transistor M2 and the tenth transistor M10 are turned on to charge each node of the readout circuit 100. Because there is a potential difference between the first and second terminals of the ninth transistor M9, the fourth transistor M4 and the fifth transistor M5 are turned on at different degrees, resulting in different charging speeds at both ends of the ninth transistor M9. The ninth transistor M9 can balance the charging speeds at both ends, so that when the next clock control signal CLK changes from low to high, the voltage levels at both ends of the ninth transistor M9, i.e., the fifth node N5 and the sixth node N6, are basically the same, thus completing the voltage regulation of the fifth node N5 and the sixth node N6. Of course, in other embodiments, the level adjustment circuit 113 can also have other circuit structures. Based on other circuit structures, the level adjustment circuit 113 can adjust the voltages of the fifth node N5 and the sixth node N6 according to the clock control signal CLK.

[0052] It should be noted that the antifuse array readout circuit 100 provided in this disclosure can have low current consumption, which can save power consumption of the antifuse array, greatly reduce the load on the power supply, and ensure stable power supply output signal. The following is an example... Figure 2 Taking the circuit structure shown as an example, the current consumption of the reading circuit 100 is illustrated.

[0053] like Figure 2As shown in this exemplary embodiment, the read circuit 100 consumes current only when the clock control signal CLK changes (i.e., rising or falling edge). When the clock control signal CLK is a stable low or high level, there is only leakage current. Specifically, when the clock control signal CLK is low, because the eighth transistor M8 is off, the power supply path to ground of the read circuit 100 is disconnected, and there is only leakage current in the read circuit 100, thus greatly reducing the power consumption of the read circuit 100. When the clock control signal CLK is high, the second transistor M2 and the tenth transistor M10 are off. As can be seen from the above analysis, when the clock control signal CLK reaches a stable high level, the third transistor M3 and the fourth transistor M4 in the comparison circuit 110 are off (or the first transistor M1 and the fifth transistor M5 are off, depending on the signal comparison result of the first signal terminal Vminus and the second signal terminal Vplus), disconnecting the two paths from the power supply to ground. Thus, when the clock control signal CLK is a stable high level, there is also no path from the power supply to ground, thus saving the overall power consumption of the read circuit 100.

[0054] Figure 3 This is a schematic diagram of the readout circuit of an antifuse array in related technologies. Figure 3 In the antifuse array shown, the read circuit 100 consists of comparators and latches. Typically, the power consumption of a single comparator is about 50μA. If all comparators in the antifuse array are enabled at the same time, the current consumed by a 36-column × 16-row antifuse array is about 50uA × 16 × 36 × 2 = 58mA. This will put a great burden on the power supply. Excessive current will cause the power supply voltage to be unstable, or even cause the entire circuit to fail to work properly.

[0055] The read circuit provided in this exemplary embodiment consumes an average current of 20–33 nA when the clock control signal CLK is low. Multiplying this by the number of read circuits 100 in the antifuse array, the total current consumed is approximately 23.04–38.02 uA. When the clock control signal CLK is high, the average current consumed is 185 nA. Multiplying this by the number of read circuits 100 in the antifuse array, the total current consumed is approximately 213.12 uA. It can be seen that the current consumed by the read circuit 100 of the antifuse array provided in this disclosure is much smaller than... Figure 3 The conventional read circuit shown consumes only 58mA of current, which can greatly save the power consumption of the antifuse array, significantly reduce the load on the power supply, and ensure a stable output of the power supply signal.

[0056] Furthermore, the reading circuit provided in this exemplary embodiment occupies a smaller area on the circuit board than... Figure 3The reading circuit shown occupies about 3% less area, which helps to optimize the size of the antifuse array and the memory formed by the antifuse array, and improves the applicability of the antifuse array and the memory formed therefrom.

[0057] like Figure 1 As shown in this exemplary embodiment, the antifuse array may further include a programming control circuit 400, which can program the selected antifuse memory cell in response to a programming control signal Zadd. For example, the programming control circuit 400 may include a twelfth transistor M12. The control terminal of the twelfth transistor M12 receives the programming control signal Zadd. The first terminal of the twelfth transistor M12 is connected to the data port of the antifuse array (i.e., the first signal terminal Vminus of the comparator circuit 110), and the second terminal receives a first set voltage VSS. The twelfth transistor M12 may be an N-type field-effect transistor, and the first set voltage VSS may be a low-level voltage signal. When the programming control signal Zadd is high, the twelfth transistor M12 is turned on, and the first set voltage VSS at the second terminal of the twelfth transistor M12 is transmitted to one end of the selected antifuse memory cell. A high voltage is applied to the gate of the antifuse memory cell by Fsbln, causing the gate oxide dielectric of the antifuse memory cell to break down. The antifuse memory cell is then programmed, and correspondingly, the antifuse memory cell presents a low-resistance state. It should be understood that in other embodiments, the programming control circuit 400 may have other circuit structures, and this disclosure is not limited thereto.

[0058] like Figure 1As shown in this exemplary embodiment, the antifuse array may further include a pre-charge circuit 300, which is correspondingly configured with the read circuit 100. The pre-charge circuit 300 is connected to the first signal terminal Vminus of the comparator circuit 110. The pre-charge circuit 300 can pre-charge the first signal terminal Vminus of the comparator circuit 110 before the clock control signal CLK becomes the first level. Specifically, the pre-charge circuit 300 is configured one-to-one with the antifuse array, and is connected to the first signal terminal Vminus of the comparator circuit 110. The pre-charge circuit 300 can pre-charge the first signal terminal Vminus of the comparator circuit 110 before the comparator circuit 110 is enabled, charging the first signal terminal Vminus to a high level. For example, the pre-charge circuit 300 may include an eleventh transistor M11. The control terminal of the eleventh transistor M11 receives the pre-charge control signal Pre-charge, the first terminal is connected to the pre-charge signal VDD, and the second terminal is connected to the first signal terminal Vminus of the comparator circuit 110. The eleventh transistor M11 can be a P-type field-effect transistor, and the pre-charge signal VDD can be a high-level signal. When the pre-charge control signal Pre-charge is low, the eleventh transistor M11 turns on, transmitting the high-level pre-charge signal VDD to the first signal terminal Vminus of the comparator circuit 110, charging the first signal terminal Vminus of the comparator circuit 110 to a high level. It is understood that in other embodiments, when the second signal terminal Vplus of the comparator circuit 100 is connected to the data port of the antifuse array, the pre-charge circuit 300 is connected to the second signal terminal Vplus of the comparator circuit 100. Furthermore, in other embodiments, the pre-charge circuit 300 may have other circuit structures, and this disclosure is not limited thereto.

[0059] In this exemplary embodiment, after the data signal is output from the data port for a certain period of time, the clock control signal CLK is changed from a second level to a first level (from low level to high level). This ensures that when the read circuit 100 reads data F_Data, the data signal at the data port is already stable, guaranteeing that the comparator circuit 110 can accurately sense the data stored in the antifuse array, thereby outputting the correct first sensing signal S1 to the third node N3 and a stable second sensing signal S2 to the fourth node N4. In some embodiments of this disclosure, the clock control signal CLK can transition from a low level to a high level signal after a delay of 10ns to 100ns (e.g., 10ns, 20ns, 30ns, 40ns, 50ns, 60ns, 70ns, 80ns, 90ns, 100ns) after the pre-charge control signal Pre-charge ends.

[0060] Figure 4This is a schematic diagram of the structure of a programmable non-volatile memory according to one embodiment of the present disclosure, as shown below. Figure 4 As shown, this disclosure also provides a programmable non-volatile memory, which may include the antifuse array described in any of the embodiments of this disclosure above. It is understood that... Figure 1 Equivalent to Figure 5 A schematic diagram of the structure of an antifuse array.

[0061] In this exemplary embodiment, adjacent antifuse arrays 100 can reuse one array selection sub-signal RdSel_n, meaning that one array selection sub-signal RdSel_n can activate multiple columns of antifuse arrays 100. For example, Figure 5 This is a schematic diagram illustrating the multiplexing of array selection sub-signals according to one embodiment of the present disclosure, as shown below. Figure 5As shown, the memory may include M columns of antifuse arrays 100. The antifuse array 100 located in the m-th column (Segment_m) and the antifuse array 100 located in the (m+1)-th column (Segment_m+1) multiplexes the same array selection sub-signal RdSel_n. The antifuse array 100 located in the m-th column (Segment_m) and the antifuse array 100 located in the (m+2)-th column (Segment_m+2) use two different array selection sub-signals RdSel_n and RdSel_n+1. Only one array selection sub-signal RdSel_n is valid at any given time, where m is an odd number less than M. A valid array selection sub-signal RdSel_n means that the array selection sub-signal RdSel_n can select a set of antifuse arrays. This means that, starting from the first column, two adjacent columns of antifuse arrays 100 form a group, and the same array selection sub-signal RdSel_n activates a group of antifuse arrays 100. For example, if the memory includes 36 columns of antifuse array 100, then the first column (Segment_1) of antifuse array 100 can share the same array select sub-signal RdSel_1 with the second column (Segment_2) of antifuse array 100, the third column (Segment_3) of antifuse array 100 and the fourth column (Segment_4) of antifuse array 100 can share the same array select sub-signal RdSel_2, the fifth column (Segment_5) of antifuse array 100 can share the same array select sub-signal RdSel_3 with the sixth column (Segment_6) of antifuse array 100, and so on. The 35th column (Segment_35) of antifuse array 100 and the 36th column (Segment_36) of antifuse array 100 can share the same array select sub-signal RdSel_18. Of course, in other embodiments, the array selection sub-signal RdSel_n can also have other multiplexing methods. For example, three antifuse arrays 100 can be multiplexed into a group using the same array selection sub-signal RdSel_n. That is, the antifuse arrays 100 in the first column (Segment_1), the second column (Segment_2), and the third column (Segment_3) can multiplex the same array selection sub-signal RdSel_1, the antifuse arrays 100 in the fourth column (Segment_4), the fifth column (Segment_5), and the sixth column (Segment_6) can multiplex the same array selection sub-signal RdSel_2, and so on. This disclosure is not limited to this.

[0062] like Figure 1 , Figure 4As shown in this exemplary embodiment, the memory may further include multiple output circuits 20. Each output circuit 20 is connected to the read circuit 100 in a row of antifuse arrays and receives the array selection signal RdSel_n. One output circuit 20 is connected to the read circuit 100 in a row of antifuse arrays and outputs the data F_Data read from one of the selected antifuse arrays in that row. Thus, the antifuse memory cell status data F_Data read by that row of antifuse arrays will only be output when the array selection sub-signal RdSel_n of an antifuse array is high. The output circuit 20 may include one or more output sub-circuits. Figure 6 This is a schematic diagram of the output circuit according to one embodiment of the present disclosure, such as... Figure 6 As shown, the output circuit 20 includes an output sub-circuit 201. At this time, each antifuse array in the same row is connected to the output sub-circuit 201. The output sub-circuit 201 outputs the data F_Data read by the reading circuit 100 according to the array selection signal RdSel_n.

[0063] Figure 7 This is a schematic diagram of the output circuit according to another embodiment of the present disclosure, such as... Figure 7 As shown, the output circuit 20 may include two output sub-circuits, such as a first output sub-circuit 201 and a second output sub-circuit 202. This structure is equivalent to the read circuit 100 of the odd-numbered antifuse array being connected to the first output sub-circuit 201, and the read circuit 100 of the even-numbered antifuse array being connected to the second output sub-circuit 202. If the selected antifuse storage cell is located in an even-numbered column of the antifuse array, the data F_Data of that antifuse storage cell is output only through the second output sub-circuit 202, without going through the first output sub-circuit 201. Similarly, the data F_Data of the antifuse storage cell located in an odd-numbered column of the antifuse array is output only through the first output sub-circuit 201, without going through the second output sub-circuit 202. Therefore, when both an even-numbered column and an odd-numbered column of the antifuse array are selected simultaneously, the data F_Data of the odd-numbered column can be output through the first output sub-circuit 201, and the data F_Data of the even-numbered column can be output through the second output sub-circuit 202. Obviously, this output circuit 20 can save the data F_Data transmission time, improve the data F_Data transmission speed, and reduce the attenuation of data F_Data during transmission.

[0064] It is understandable that when the output circuit 20 includes only one output sub-circuit 201, the output circuit 20 can only output one bit of data F_Data at a time. If the output circuit 20 includes two output sub-circuits 201, the output circuit 20 can output two bits of data F_Data at a time. It can be seen that by setting two output sub-circuits 201, the output efficiency of data F_Data can be improved.

[0065] Of course, in other embodiments, the output circuit 20 may also include three or more output sub-circuits, which can be set according to the data transmission speed, data storage method and data volume. For example, the output circuit 20 may include three output sub-circuits 201, wherein the first column (Segment_1) antifuse array read circuit 100, the fourth column (Segment_4) antifuse array read circuit 100, the seventh column (Segment_7) antifuse array read circuit 100... are connected to the first output sub-circuit 201, the second column (Segment_2) antifuse array read circuit 100, the fifth column (Segment_5) antifuse array read circuit 100, the eighth column antifuse array read circuit 100... are connected to the second output sub-circuit 202, the third column (Segment_3) antifuse array read circuit 100, the sixth column (Segment_6) antifuse array read circuit 100, the ninth column antifuse array read circuit 100... are connected to the third output sub-circuit 203, and so on. Similarly, the output circuit 20 includes multiple output sub-circuits, which can improve the data output efficiency of the antifuse array.

[0066] Figure 8 This is a schematic diagram of the structure of an output sub-circuit according to an embodiment of the present disclosure, as shown below. Figure 8As shown, the output sub-circuit may include a transmission circuit 2012 and multiple selection circuits 2011. Each selection circuit 2011 is connected to a read circuit 100, and each selection circuit 2011 can output the data F_Data read by the read circuit 100 in response to an array selection sub-signal RdSel_n. The transmission circuit 2012 is connected between the output terminals of the multiple selection circuits 2011 and the data port, and the transmission circuit 2012 can transmit the data F_Data output by the selection circuits 2011 to the data port. For example, the selection circuit 2011 may include an AND gate circuit 21, and the transmission circuit 2012 may include multiple cascaded OR gate circuits 22. One input terminal of the AND gate circuit 21 is connected to the output terminal of the read circuit 100, the other input terminal receives the array selection sub-signal RdSel_n, and the output terminal is connected to the other input terminal of the OR gate circuit 22. The first input terminal of each OR gate circuit 22 is connected to the output terminal of the corresponding selection circuit 2011. The second input terminal of the first OR gate circuit 22 is grounded. The output terminal of the last OR gate circuit 22 is connected to the data port. The output terminal of the previous OR gate circuit 22 is connected to the second input terminal of the next OR gate circuit 22.

[0067] For example, the memory includes a 36-column × 16-row antifuse array, and the output circuit 20 has Figure 5The circuit structure shown, taking one row of antifuse arrays as an example, has an OR gate 22 connected to the read circuit 100 of the first column (Segment_1) antifuse array as the first stage of the transmission circuit 2012 in the first output sub-circuit 201, an OR gate 22 connected to the read circuit 100 of the third column (Segment_3) antifuse array as the second stage of the transmission circuit 2012, and so on. If the first column (Segment_1) antifuse array is selected and the stored data F_Data is high (i.e., the selected antifuse memory cell is programmed), then the first stage selection circuit 2011 in the first output sub-circuit 201 outputs a high level, the other selection circuits 2011 all output a low level, each stage of the transmission circuit 2012 outputs a high level, and the first output sub-circuit 201 finally outputs a high-level signal, outputting the programming status of the selected antifuse memory cell in the first column (Segment_1) antifuse array. Alternatively, if the first column (Segment_1) antifuse array is selected and the stored data F_Data is low (i.e., the selected antifuse memory cell is not programmed), then the first stage selection circuit 2011 in the first output sub-circuit 201 outputs a low level, and the other selection circuits 2011 also output a low level. Each stage of the transmission circuit 2012 outputs a low level, and the first output sub-circuit 201 finally outputs a low-level signal, outputting the unprogrammed state of the selected antifuse memory cell in the first column (Segment_1) antifuse array. Alternatively, if the third column (Segment_3) antifuse array is selected and the stored data F_Data is high (i.e., the selected antifuse memory cell is programmed), then the second-stage selection circuit 2011 in the first output sub-circuit 201 outputs a high level, the other selection circuits 2011 all output a low level, the first stage of the transmission circuit 2012 outputs a low level, the second to the last stage of the transmission circuit 2012 all output a high level, and the first output sub-circuit 201 finally outputs a high-level signal, outputting the programming status of the selected antifuse memory cell in the third column (Segment_3) antifuse array.

[0068] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the generality of this disclosure and include, but are not disclosed herein, common knowledge or customary techniques in the art. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

Claims

1. An antifuse array, characterized in that, The antifuse array includes a readout circuit connected to the data port of the antifuse array. The readout circuit includes: A comparator circuit, connected to a second node, a third node, and a fourth node, and having a first signal terminal and a second signal terminal, wherein the first signal terminal or the second signal terminal is connected to the data port, the comparator circuit is configured to respond to the signal of the second node when the clock control signal is at a first level, output a first sensing signal to the third node and output a second sensing signal to the fourth node based on the comparison result of the signals of the first signal terminal and the second signal terminal; A first output control circuit is connected to a second node and a ground terminal. The first output control circuit is configured to turn on the second node and the ground terminal when the clock control signal is at a first level. A latching circuit, connected to the third node and the fourth node, is configured to output the data stored in the antifuse array based on the first sensing signal and the second sensing signal. The latching circuit includes a first NAND gate and a second NAND gate. The first input terminal of the first NAND gate is connected to the third node, and the second input terminal of the first NAND gate is connected to the output terminal of the second NAND gate. The first input terminal of the second NAND gate is connected to the fourth node, and the second input terminal of the second NAND gate is connected to the output terminal of the first NAND gate. The latching circuit outputs the data stored in the antifuse array through the output terminal of the first NAND gate or through the output terminal of the second NAND gate. The reading circuit also includes: A second output control circuit is connected to the first node, the third node, and the fourth node. The second output control circuit is configured to transmit the charging signal of the first node to the third node and the fourth node when the clock control signal is at the second level, wherein the first level of the clock control signal is out of phase with the second level. Specifically, when the clock control signal CLK is at a stable first level and a stable second level, the comparison circuit is disconnected from ground in both cases.

2. The antifuse array according to claim 1, characterized in that, The comparison circuit includes: A comparison unit is connected to the second node, the fifth node, and the sixth node. The comparison unit has a first signal terminal and a second signal terminal. The first signal terminal is connected to the data port, and the second signal terminal is used to receive a preset reference signal. The comparison unit is configured to compare the data signal of the data port with the preset reference signal, and adjust the voltage values ​​of the fifth node and the sixth node according to the comparison result in response to the signal of the second node. A signal amplification unit is connected to the fifth node, the sixth node, the third node, the fourth node, and the first node. The signal amplification unit is configured to amplify the voltage difference between the fifth node and the sixth node, and output the first induced signal to the third node and the second induced signal to the fourth node.

3. The antifuse array according to claim 2, characterized in that, The comparison unit includes: The sixth transistor has its first terminal connected to the fifth node and its second terminal connected to the second node. The control terminal of the sixth transistor receives the preset reference signal. A seventh transistor, wherein the first terminal of the seventh transistor is connected to the sixth node, the second terminal of the seventh transistor is connected to the second node, and the control terminal of the seventh transistor is connected to the data port; The sixth transistor and the seventh transistor are of the same type.

4. The antifuse array according to claim 3, characterized in that, Both the sixth transistor and the seventh transistor are N-type field-effect transistors.

5. The antifuse array according to claim 2, characterized in that, The signal amplification unit includes: A fourth transistor, wherein the first terminal of the fourth transistor is connected to the third node, the second terminal of the fourth transistor is connected to the fifth node, and the control terminal of the fourth transistor is connected to the fourth node; The fifth transistor has its first terminal connected to the fourth node, its second terminal connected to the sixth node, and its control terminal connected to the third node. A first transistor, wherein a first terminal of the first transistor is connected to the first node, a second terminal of the first transistor is connected to the third node, and a control terminal of the first transistor is connected to the fourth node; A third transistor, wherein a first terminal of the third transistor is connected to the first node, a second terminal of the third transistor is connected to the fourth node, and a control terminal of the third transistor is connected to the third node; The fourth transistor and the fifth transistor are of the same type, and the first transistor and the third transistor are of the same type.

6. The antifuse array according to claim 5, characterized in that, The fourth and fifth transistors are N-type field-effect transistors; the first and third transistors are P-type field-effect transistors.

7. The antifuse array according to claim 6, characterized in that, The second output control circuit includes: The tenth transistor has a first terminal connected to the first node, a second terminal connected to the third node, and a control terminal receiving the clock control signal. The second transistor has a first terminal connected to the first node and a second terminal connected to the fourth node. The control terminal of the second transistor receives the clock control signal. The second transistor and the tenth transistor are of the same type.

8. The antifuse array according to claim 7, characterized in that, The first output control circuit includes: The eighth transistor has its first terminal connected to the second node and its second terminal connected to ground. The control terminal of the eighth transistor receives the clock control signal. The second transistor and the eighth transistor are of different types.

9. The antifuse array according to claim 8, characterized in that, The eighth transistor is an N-type field-effect transistor, while the second transistor and the tenth transistor are both P-type field-effect transistors.

10. The antifuse array according to claim 1, characterized in that, The reading circuit also includes: A level adjustment circuit, connected to the fifth node and the sixth node, is configured to adjust the voltage of the fifth node and the sixth node according to the clock control signal.

11. The antifuse array according to claim 10, characterized in that, The level adjustment circuit includes: The ninth transistor has its first terminal connected to the fifth node and its second terminal connected to the sixth node. The control terminal of the ninth transistor receives a first voltage signal.

12. The antifuse array according to claim 1, characterized in that, After the data signal is output from the data port, the clock control signal changes from the second level to the first level.

13. The antifuse array according to claim 2, characterized in that, Also includes: A pre-charge circuit is provided corresponding to the read circuit. The pre-charge circuit is connected to the first signal terminal of the comparison circuit. The pre-charge circuit is configured to pre-charge the first signal terminal of the comparison circuit before the clock control signal is at the first level.

14. A programmable non-volatile memory, characterized in that, Includes the antifuse array as described in any one of claims 1-13.

15. The programmable non-volatile memory according to claim 14, characterized in that, The memory also includes: Multiple output circuits, each of which is connected to the read circuit in a row of the antifuse array and receives an array selection signal, the output circuit being configured to output the data read by the read circuit according to the array selection signal.

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