A memory and a method for manufacturing the same, a storage system

Abstract

The application discloses a memory, a preparation method thereof and a memory system. A stack layer in a stepped structure is first formed in a step region, then a first sacrificial layer and a second sacrificial layer are sequentially covered on the stepped structure, the second sacrificial layer is removed after the interlayer sacrificial layer is replaced by a gate layer, the first sacrificial layer is removed to form a third cavity on each step after the second sacrificial layer is removed, then a stop layer is filled in the third cavity, and finally a word line contact penetrating through the stop layer is formed. A second cavity is formed at the position of the second sacrificial layer in the embodiment of the application, and then the second cavity can be used to etch the first sacrificial layer to form the third cavity. The etching process can greatly increase the thickness of the third cavity, that is, the thickness of the stop layer can be greatly increased, and then the word line contact can be easily stopped on each layer of the gate layer, that is, the process window of the word line contact is improved.

Description

Technical Field

[0001] This invention relates generally to the field of electronic devices, and more specifically to a memory, a method for its fabrication, and a storage system. Background Technology

[0002] In 3D NAND, contact holes are typically formed first on the steps, and then conductive material is filled into the contact holes to form word line contacts. The etching of the contact holes needs to stop on the gate layer so that the word line contacts make contact with each gate layer.

[0003] As the number of 3D NAND layers increases, the etching process for contact holes becomes increasingly difficult. For example, it is difficult to stop the etching process on each gate layer, which can easily cause through-holes, resulting in word line contacts connecting to the gate layer below, leading to leakage and defects.

[0004] Improving the etching process for contact holes is a problem that urgently needs to be solved. Summary of the Invention

[0005] The purpose of this invention is to provide a memory and its manufacturing method and storage system, which aims to improve the process window for forming word line contacts.

[0006] In a first aspect, embodiments of the present invention provide a memory, comprising:

[0007] Provide substrate;

[0008] A stacked layer is formed on the substrate, the stacked layer comprising a plurality of stacked pairs, each stacked pair comprising an interlayer insulating layer and an interlayer sacrificial layer, the stacked layer comprising a step region, the plurality of stacked pairs being in a step structure in the step region;

[0009] A first sacrificial layer and a second sacrificial layer are sequentially covered on the stepped structure;

[0010] Remove the interlayer sacrificial layer and the second sacrificial layer to form a first cavity and a second cavity, respectively;

[0011] A gate layer is deposited in the first cavity and the second cavity to replace the interlayer sacrificial layer with a gate layer;

[0012] Remove the gate layer located in the second cavity;

[0013] The first sacrificial layer is etched through the second cavity to form a third cavity including the second cavity;

[0014] The third cavity is filled with a stop layer;

[0015] Word line contacts are formed that penetrate the stop layer and extend to the gate layer in each step.

[0016] Furthermore, the first sacrificial layer is made of the same material as the interlayer insulating layer, and the second sacrificial layer is made of the same material as the interlayer sacrificial layer.

[0017] Furthermore, the thickness of the second sacrificial layer is greater than the thickness of the interlayer sacrificial layer.

[0018] Furthermore, the first sacrificial layer has a horizontal platform and longitudinal sidewalls at each step; the method for fabricating the memory also includes:

[0019] The second sacrificial layer located on the longitudinal sidewall of the first sacrificial layer is removed to form a spacer region;

[0020] A filler insulating layer is covered on the first sacrificial layer and the second sacrificial layer, the filler insulating layer filling the spacer region.

[0021] Furthermore, the filling insulating layer is made of the same material as the first sacrificial layer.

[0022] Furthermore, prior to the step of removing the interlayer sacrificial layer and the first sacrificial layer, the method for fabricating the memory further includes:

[0023] A gate line slot is formed that extends through the stacked layers, and the gate line slot extends along a first direction.

[0024] Furthermore, the step of removing the first sacrificial layer through the second cavity includes:

[0025] The first sacrificial layer, a portion of the filling insulating layer, and a portion of the interlayer insulating layer are etched through the gate line gaps and the second cavity to form the third cavity including the second cavity.

[0026] Furthermore, the material of the stop layer is silicon nitride or polycrystalline silicon.

[0027] Furthermore, in each of the stacked pairs, the interlayer insulating layer is located on the interlayer sacrificial layer; the step of forming a word line contact through the stop layer includes:

[0028] Contact holes are formed by etching the filling insulating layer and the stop layer at each step, with the bottom of the contact holes located in the stop layer;

[0029] The stop layer and the interlayer insulating layer at the bottom of the contact hole are further etched to make the contact hole contact the gate layer in each step;

[0030] The contact hole is filled with conductive material.

[0031] Secondly, embodiments of the present invention provide a method for fabricating a memory, comprising:

[0032] Semiconductor layer;

[0033] A stacked structure includes a plurality of stacked pairs stacked on the semiconductor layer, each of the stacked pairs including an interlayer insulating layer and a gate layer, the stacked structure including a step region, and the plurality of stacked pairs having a step structure in the step region;

[0034] A stop layer is located on each step of the stepped structure, and the stop layer has a stop layer sidewall located at the edge of each step;

[0035] Word line contacts penetrate the stop layer and extend to the gate layer in each step;

[0036] The sidewall of the stop layer protrudes from the sidewall of each step.

[0037] Furthermore, the material of the stop layer is silicon nitride or polycrystalline silicon.

[0038] Furthermore, the thickness of the stop layer is greater than the thickness of the gate layer.

[0039] Furthermore, the memory also includes:

[0040] A dielectric layer covering the stepped structure and the stop layer;

[0041] The dielectric layer and the interlayer insulating layer are made of the same material.

[0042] Furthermore, the memory also includes:

[0043] The grid line slot structure penetrates the stacked structure and extends along a first direction.

[0044] Furthermore, the interlayer insulating layer has a groove at the junction with the gate line slot structure, the gate line slot structure fills the groove, and it intersects with the gate layer, the stop layer and the dielectric layer.

[0045] Thirdly, embodiments of the present invention provide a storage system, including:

[0046] The memory as described in any one of items 10-15 above;

[0047] A controller, electrically connected to the memory, is used to control the memory to store data.

[0048] The beneficial effects of this invention are as follows: It provides a memory and its fabrication method and memory system. First, a stacked layer with a stepped structure is formed in the step region. Then, a first sacrificial layer and a second sacrificial layer are sequentially covered on the step structure. After replacing the interlayer sacrificial layer with a gate layer, the second sacrificial layer is removed. After removing the second sacrificial layer, the first sacrificial layer can be removed to form a third cavity located on each step. Next, a stop layer is filled into the third cavity, and finally, word line contacts penetrating the stop layer are formed. In this invention, the second cavity is formed at the location of the second sacrificial layer. The second cavity can then be used to etch the first sacrificial layer to form the third cavity. The etching process can greatly increase the thickness of the third cavity, that is, it can greatly increase the thickness of the stop layer, thereby making it easier for the word line contacts to stop on each gate layer, thus improving the process window of the word line contacts. Attached Figure Description

[0049] The technical solution and other beneficial effects of the present invention will become apparent from the following detailed description of specific embodiments of the invention, in conjunction with the accompanying drawings.

[0050] Figure 1 This is a schematic flowchart of the method for fabricating a memory according to an embodiment of the present invention;

[0051] Figures 2-16 This is a schematic diagram of the structure of the memory provided in the embodiment of the present invention during the manufacturing process;

[0052] Figure 8a yes Figure 8 A schematic diagram of the cross-sectional structure of the memory at point A-A1;

[0053] Figure 9a yes Figure 9 A schematic diagram of the cross-sectional structure of the memory at point B-B1;

[0054] Figure 10a yes Figure 10 A schematic diagram of the cross-sectional structure of the memory at point C-C1;

[0055] Figure 11a yes Figure 11 A schematic diagram of the cross-sectional structure of the memory at point D-D1;

[0056] Figure 12a yes Figure 12 A schematic diagram of the cross-sectional structure of the memory at point E-E1;

[0057] Figure 14a yes Figure 14 A schematic diagram of the cross-sectional structure of the memory at F-F1;

[0058] Figure 15a yes Figure 15 A schematic diagram of the cross-sectional structure of the memory at G-G1;

[0059] Figure 16a yes Figure 16 A schematic diagram of the cross-sectional structure of the memory at H-H1;

[0060] Figure 17 This is a schematic diagram of the structure of the memory provided in an embodiment of the present invention;

[0061] Figure 17a yes Figure 17 A schematic diagram of the cross-sectional structure of the memory at I-I1;

[0062] Figure 18 This is a schematic diagram of the storage system provided in an embodiment of the present invention. Detailed Implementation

[0063] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0064] It should be understood that although the terms first, second, etc., may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of the invention.

[0065] It should be understood that when a component is said to be "on" or "connected" to another component, it can be directly on or connected to the other component, or there may be an inserted component. Other terms used to describe relationships between components should be interpreted in a similar manner.

[0066] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and contact layers (where contacts, interconnects, and one or more dielectric layers are formed).

[0067] This paper uses a Cartesian coordinate system (X, Y, and Z) to represent the cross-section of the memory in various directions, where the XY plane is parallel to the substrate and the Z direction is perpendicular to the substrate.

[0068] It should be noted that the illustrations provided in the embodiments of the present invention are only schematic representations of the basic concept of the present invention. Although the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component can be arbitrarily changed in actual implementation, and the layout of the components may also be more complex.

[0069] The memory in this embodiment of the invention can be a wafer or a three-dimensional memory. Three-dimensional memory can be applied to communication products, consumer electronics, automotive products, aerospace products, artificial intelligence products, or big data, etc. Consumer electronics include, but are not limited to, mobile phones, computers, tablets, cameras, smart glasses, or gaming products, etc.

[0070] Please see Figure 1 , Figure 1 This is a schematic flowchart illustrating the method for fabricating a memory according to an embodiment of the present invention. Please also refer to... Figures 2-16 , Figures 2-16 This is a schematic diagram of the structure of the memory provided in the embodiment of the present invention during the manufacturing process. Figures 2-16 The image shows the XZ cross-section of the memory, which is fabricated using the following steps S1-S9.

[0071] Please see Figure 1 Steps S1-S2 and Figure 2 .

[0072] Step S1: Provide substrate 10.

[0073] The substrate 10 can be a semiconductor substrate, such as silicon (Si), germanium (Ge), SiGe substrate, silicon on insulator (SOI), or germanium on insulator (GOI). The semiconductor substrate can also be a substrate containing other elemental semiconductors or compound semiconductors, and can also be a multilayer structure, such as Si / SiGe.

[0074] Step S2: A stacked layer 20 is formed on the substrate 10. The stacked layer 20 includes a plurality of stacked pairs. Each stacked pair includes an interlayer insulating layer 21 and an interlayer sacrificial layer 22. The stacked layer 20 includes a step region. The plurality of stacked pairs have a step structure in the step region.

[0075] In one embodiment, an isolation insulating layer 11 (e.g., silicon oxide) may be deposited on a substrate 10 first, and then an interlayer sacrificial layer 22 and an interlayer insulating layer 21 may be deposited alternately on the isolation insulating layer 11. One interlayer sacrificial layer and one interlayer insulating layer 21 may constitute a stack pair, and the resulting stacked layer 20 may include multiple stack pairs. The stacked layer 20 may include a core region (not shown) and a step region adjacent to the core region. Figure 1 Only the step region is shown in the image. Then, the multiple stacked layers located in the step region are etched step by step to form a structure like... Figure 2 The stepped structure is shown. An exemplary material for the interlayer insulating layer 21 may be silicon oxide, and an exemplary material for the interlayer sacrificial layer 22 may be silicon nitride.

[0076] Please see Figure 1 Step S3 and Figures 3-4 .

[0077] Step S3: Sequentially cover the stepped structure with a first sacrificial layer 30 and a second sacrificial layer 40.

[0078] like Figure 3 As shown, a first sacrificial layer 30 can be deposited on the stepped structure using a deposition process, such as... Figure 4As shown, a second sacrificial layer 40 is then deposited on the first sacrificial layer 30. Deposition methods include, but are not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD), and physical vapor deposition (PVD). In this embodiment, the first sacrificial layer 30 is made of the same material as the interlayer insulating layer 21, and the second sacrificial layer 40 is made of the same material as the interlayer sacrificial layer 22; that is, the first sacrificial layer 30 can be made of silicon oxide, and the second sacrificial layer 40 can be made of silicon nitride. In this embodiment, the thickness of the second sacrificial layer 40 is greater than the thickness of the interlayer sacrificial layer 22.

[0079] like Figure 4 As shown, the first sacrificial layer 30 has a horizontal platform surface 31 and longitudinal sidewalls 32 at each step. In one embodiment, after step S3, please refer to... Figures 5-6 The method for fabricating this memory may further include: 1) as follows Figure 5 As shown, the second sacrificial layer 40 located on the longitudinal sidewall 32 of the first sacrificial layer 30 is removed to form a spacer region 41; 2) as Figure 6 As shown, a filling insulating layer 50 is covered on the first sacrificial layer 30 and the second sacrificial layer 40, the filling insulating layer 50 filling the spacer region 41, and the filling insulating layer 50 may be made of the same material as the first sacrificial layer 30 (e.g., silicon oxide); 3) as Figure 6 As shown, the filled insulating layer 50 is subjected to chemical mechanical polishing (CMP) to planarize the surface and expose the second sacrificial layer 40.

[0080] After forming the filled insulating layer 50 and performing CMP, as Figure 7 As shown, a gate line slot 60 is formed through the stacked layer 20, and the gate line slot 60 extends along a first direction. Figure 7 The image shows a cross-section of the memory in the YZ direction, where the cross-section precisely cuts through the second sacrificial layer 40. The first direction can be the X direction, meaning the gate line slot 60 extends along the X direction.

[0081] Please see Figure 1 Step S4 in Figure 8 and Figure 8a , Figure 8a yes Figure 8 The schematic diagram of the cross-sectional structure of the memory at A-A1 also shows the YZ section.

[0082] Step S4: Remove the interlayer sacrificial layer 22 and the second sacrificial layer 40 to form the first cavity 221 and the second cavity 401, respectively.

[0083] After the gate line gap 60 is formed, step S4 is performed, allowing etchant to enter through the gate line gap 60 and etch the interlayer sacrificial layer 22 and the second sacrificial layer 40. Since the interlayer sacrificial layer 22 and the second sacrificial layer 40 are made of the same material (e.g., silicon nitride), and the first sacrificial layer 30 and the interlayer insulating layer 21 are made of the same material (e.g., silicon oxide), the interlayer sacrificial layer 22 and the second sacrificial layer 40 can be removed by controlling the etch selectivity ratio of silicon nitride and silicon oxide. After the interlayer sacrificial layer 22 is removed, a first cavity 221 is formed; after the second sacrificial layer 40 is etched, a second cavity 401 is formed.

[0084] Please see Figure 1 Step S5 in the process Figure 9 and Figure 9a , Figure 9a yes Figure 9 The schematic diagram of the cross-sectional structure of the memory at B-B1 shows the YZ section.

[0085] Step S5: Deposit a gate layer 23 in the first cavity 221 and the second cavity 401 to replace the interlayer sacrificial layer 22 with the gate layer 23.

[0086] Since the thickness of the second sacrificial layer 40 is greater than the thickness of the interlayer sacrificial layer 22, the thickness of the second cavity 401 is greater than the thickness of the first cavity 221. Therefore, after depositing the gate layer 23, it can be ensured that the first cavity 221 is filled with the gate layer 23, while the second cavity 401 is not filled with the gate layer 23.

[0087] In one embodiment, the gate layer 23 can be composed of a combination of multiple film layers, such as a barrier layer (e.g., aluminum oxide), an adhesion layer (e.g., titanium nitride), and a conductive layer (e.g., tungsten metal) deposited sequentially. The barrier layer prevents metal atoms in the conductive layer from diffusing outwards, and the adhesion layer increases the adhesion between the conductive layer and the barrier layer. It is understood that the upper surface of the first sacrificial layer 30 consists of the barrier layer, the adhesion layer, and the conductive layer sequentially. After the interlayer sacrificial layer 22 is replaced by the gate layer 23, the interlayer insulating layer 21 and the gate layer 23 form a stacked structure 20a.

[0088] Please see Figure 1 Step S6 in Figure 10 and Figure 10a , Figure 10a yes Figure 10 The schematic diagram of the cross-sectional structure of the memory at C-C1 shows the YZ section.

[0089] Step S6: Remove the gate layer 23 located in the second cavity 401.

[0090] After depositing the gate layer 23, the gate layer 23 is etched back to remove it from the second cavity 401. Simultaneously, a portion of the gate layer 23 in the first cavity 221 is also etched. Therefore, the gate layer 23 in the first cavity 221 is recessed a certain distance away from the interlayer insulating layer 21 and away from the gate line gap 60. The etch back can be performed using wet etching, where the etching solution enters the second cavity 401 from the gate line gap 60. Since the etching solution contacts all surfaces of the gate layer 23 in the second cavity 401 but only the sides of the gate layer 23 in the first cavity 221, the gate layer 23 in the second cavity 401 can be completely removed, while the sides of the gate layer 23 in the first cavity 221 are partially removed.

[0091] When the gate layer 23 is a combination of multiple film layers (e.g., a barrier layer, an adhesive layer, and a conductive layer deposited sequentially), when removing the gate layer 23, the conductive layer is removed first, followed by the adhesive layer and the barrier layer in sequence.

[0092] Please see Figure 1 Step S7 in Figure 11 and Figure 11a , Figure 11a yes Figure 11 The schematic diagram of the cross-sectional structure of the memory at point D-D1 shows the YZ section.

[0093] Step S7: Etch the first sacrificial layer 30 through the second cavity 401 to form a third cavity 402 including the second cavity 401.

[0094] Since the second cavity 401 exposes the first sacrificial layer 30, the etchant can enter the second cavity 401 from the gate line gap 60 and contact the first sacrificial layer 30. Because in this embodiment, the first sacrificial layer 30, the interlayer insulating layer 21, and the filling insulating layer 50 are made of the same material (e.g., all are silicon oxide), all surfaces of the silicon oxide exposed by the first cavity 221 and the gate line gap 60 are etched simultaneously, forming a third cavity 402 that is essentially an enlargement of the second cavity 401. Therefore, the interlayer insulating layer 21 is recessed inward relative to the gate layer 23, away from the gate line gap 60; that is, the interlayer insulating layer 21 has a groove 211 at its junction with the gate line gap 60.

[0095] The main purpose of step S7 is to remove the first sacrificial layer 30 located between the filling insulating layer 50 and the stacked layer 20, so that the gap between the filling insulating layer 50 and the stacked layer 20 reaches the required thickness, and therefore the stop layer formed subsequently can also reach the required thickness. The greater the thickness of the first sacrificial layer 30, the greater the thickness of the stop layer formed after removal, thus greatly increasing the thickness of the stop layer, and also arbitrarily controlling the thickness of the stop layer. The greater the thickness of the stop layer, the easier it is for the subsequent etching of the contact holes to stop on each gate layer 23, thereby greatly improving the process window of the contact holes.

[0096] Please see Figure 1 Step S8 in Figure 12 and Figure 12a , Figure 12a yes Figure 12 The schematic diagram of the cross-sectional structure of the memory at E-E1 shows the YZ section.

[0097] Step S8: Fill the third cavity 402 with a stop layer 70.

[0098] A stop layer 70 is deposited in the third cavity 402. The material of the stop layer 70 can be silicon nitride or polycrystalline silicon.

[0099] Please see Figure 13 After filling the stop layer 70, the method for fabricating the memory further includes: filling the gate line gap 60 with a dielectric layer (e.g., silicon oxide) or sequentially filling with a dielectric layer and a conductive layer (e.g., polysilicon) to form a gate line gap structure 61, wherein the gate line gap structure 61 fills the groove 211.

[0100] Please see Figure 1 Step S9 in Figure 14 and Figure 14a , Figure 15 and Figure 15a as well as Figure 16 and Figure 16a . Figure 14a yes Figure 14 The schematic diagram of the cross-sectional structure of the memory at F-F1 shows the YZ section. Figure 15a yes Figure 15 A schematic diagram of the cross-sectional structure of the memory at point G-G1. Figure 16a yes Figure 16 A schematic diagram of the cross-sectional structure of the memory at H-H1.

[0101] Step S9: Form word line contacts 80 that penetrate the stop layer 70 and extend to the gate layer 23 in each step.

[0102] In one embodiment, the interlayer insulating layer 21 in each of the stack pairs is located on the interlayer sacrificial layer 22. The step of forming the word line contact 80 may include: 1) as... Figure 14 and Figure 14a As shown, contact holes 81 are formed by etching the filling insulating layer 50 and the stop layer 70 at each step. Figure 14a Only one contact hole 81 is shown, the bottom of which is located in the stop layer 70; 2) as Figure 15 and Figure 15a As shown, the stop layer 70 and the interlayer insulating layer 21 at the bottom of the contact hole 81 are further etched to make the contact hole 81 contact the gate layer 23 in each step; 3) as Figure 16 and Figure 16a As shown, conductive material is filled into the contact hole 81 to form a word line contact 80.

[0103] During the etching of contact holes 81, the stop layer 70 allows all contact holes 81 to stop in the stop layer 70 first. Then, only a short etching (or punching) is needed to stop each contact hole 81 on its respective gate layer 23. Therefore, the stop layer 70 makes it easy for the etching of contact holes 81 to stop on each gate layer 23, which can improve the process window of contact holes 81.

[0104] In one embodiment, the interlayer sacrificial layer in each stack pair is located on the interlayer insulating layer (i.e., the interlayer sacrificial layer is exposed at the step), and in the fabrication method, the interlayer sacrificial layer is deposited again on the interlayer sacrificial layer at each step to increase the thickness of the interlayer sacrificial layer. Subsequently, in the replacement process, the interlayer sacrificial layer is replaced with a gate layer (e.g., tungsten), which can increase the thickness of the gate layer at the step, thereby increasing the process window for contact hole etching. However, studies have found that this fabrication method makes it easy for tungsten residue to form at the corners of the gate line gaps when etching, resulting in word line leakage. Moreover, this method is also difficult to increase the thickness of the interlayer sacrificial layer at the step, posing a significant process challenge.

[0105] The memory fabrication method provided in this embodiment of the invention first forms a first sacrificial layer 30 and a second sacrificial layer 40 sequentially on a stepped structure. Then, after replacing the interlayer sacrificial layer 22 with a gate layer 23, the second sacrificial layer 40 is removed. Removing the second sacrificial layer 40 creates a second cavity 401, which can then be used to remove the first sacrificial layer 30 to form a third cavity 402. This method removes the first sacrificial layer 30 and the second sacrificial layer 40 on the step and fills the stop layer 70. Therefore, this embodiment of the invention can control the thickness of the stop layer 70 formed on the step by adjusting the thickness of the first sacrificial layer 30 and the second sacrificial layer 40, and by controlling the removal process of the first sacrificial layer 30 and the second sacrificial layer 40. Thus, this fabrication method can greatly increase the thickness of the stop layer 70 on the step, thereby greatly improving the process window of the contact hole 81. Compared to the fabrication method in the above embodiment, the fabrication method provided in this embodiment of the invention does not require increasing the thickness of the gate layer 23 on the step, is simpler in process, and has fewer challenges, thus avoiding tungsten residue.

[0106] Please see Figure 17 and Figure 17a , Figure 17 This is a schematic diagram of the structure of the memory provided in an embodiment of the present invention. Figure 17a yes Figure 17 A schematic diagram of the cross-sectional structure of the memory at I-I1.

[0107] like Figure 17 As shown, the memory 100 includes a semiconductor layer 10', an isolation insulating layer 11 on the semiconductor layer 10', and a stacked structure 20a on the isolation insulating layer 11. The semiconductor layer 10' may include a polysilicon layer, and the stacked structure 20a includes multiple stacked pairs, each of which includes an interlayer insulating layer 21 and a gate layer 23. The stacked structure 20a includes a step region, and the multiple stacked pairs are arranged in a step structure in the step region, that is, each stacked pair covers a portion of the stacked pair below it, and the bottom stacked pair covers a portion of the isolation insulating layer 11.

[0108] The memory 100 also includes a stop layer 70 located on each step of the stepped structure. The stop layer 70 is made of silicon nitride or polysilicon, and its thickness is greater than that of the gate layer 23. In this embodiment, the stop layer 70 has stop layer sidewalls located at the edges of each step, and these sidewalls protrude from the sidewalls of each step; in other words, the stop layer 70 on each step extends in the X direction beyond the platform of that step.

[0109] In other embodiments, the stop layer 70 on each step may be located entirely on the platform of the step, i.e., it does not extend beyond the platform of each step in the X direction.

[0110] The memory 100 also includes word line contacts 80 extending through the stop layer 70 in the Z direction, the word line contacts 80 extending to the gate layer 23 in each step.

[0111] The memory 100 further includes a dielectric layer 90 covering the stepped structure and the stop layer 70. The dielectric layer 90 and the interlayer insulating layer 21 are made of the same material (e.g., both are silicon oxide). The stop layers 70 on each step are isolated from each other by the dielectric layer 90.

[0112] like Figure 17a As shown, the memory 100 also includes a gate line slot structure 61 extending through the stacked structure 20a along the Z direction, the gate line slot structure 61 extending along a first direction (X). The interlayer insulating layer 21 has a groove 211 at its junction with the gate line slot structure 61, the gate line slot structure 61 filling the groove 211 and junction with the gate layer 23, the stop layer 70 and the dielectric layer 90.

[0113] The memory 100 provided in this embodiment of the invention has a stop layer 70 on the step of the stacked structure 20a, which makes it easier for the word line contact 80 to stop on each gate layer 23, thereby improving the process window of the word line contact 80.

[0114] Please see Figure 18 , Figure 18 This is a schematic diagram of the structure of a storage system provided in an embodiment of the present invention. The storage system 200 includes a memory 201 and a controller 202. The memory 201 can be the memory in any of the above embodiments. The controller 202 is electrically connected to the memory 201 and is used to control the memory 201 to store data. The memory 201 can perform data storage operations based on the control of the controller 202.

[0115] In some implementations, the storage system may be implemented as a Universal Flash Storage (UFS) device, a Solid State Drive (SSD), a Multimedia Card in the form of MMC, eMMC, RS-MMC, and Micro MMC, a Secure Digital Card in the form of SD, Mini SD, and Micro SD, a PCMCIA card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a High Speed ​​PCI (PCI-E) type storage device, a Compact Flash (CF) card, a Smart Media Card, or a Memory Stick, etc.

[0116] The memory 201 includes: a semiconductor layer; a stacked structure including a plurality of stacked pairs of structures stacked on the semiconductor layer, each of the stacked pairs of structures including an interlayer insulating layer and a gate layer, the stacked structure including a step region, the plurality of stacked pairs of structures being a step structure in the step region; a stop layer located on each step of the step structure, the stop layer having a stop layer sidewall located at the edge of each step; word line contacts penetrating the stop layer and extending to the gate layer in each step; wherein the stop layer sidewall protrudes from the sidewall of each step.

[0117] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of the present invention; those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for fabricating a memory, characterized in that, include: Provide substrate; A stacked layer is formed on the substrate, the stacked layer comprising a plurality of stacked pairs, each stacked pair comprising an interlayer insulating layer and an interlayer sacrificial layer, the stacked layer comprising a step region, the plurality of stacked pairs being in a step structure in the step region; A first sacrificial layer and a second sacrificial layer are sequentially covered on the stepped structure; Remove the interlayer sacrificial layer and the second sacrificial layer to form a first cavity and a second cavity, respectively; A gate layer is deposited in the first cavity and the second cavity to replace the interlayer sacrificial layer with a gate layer; Remove the gate layer located in the second cavity; The first sacrificial layer is etched through the second cavity to form a third cavity including the second cavity; The third cavity is filled with a stop layer; Word line contacts are formed that penetrate the stop layer and extend to the gate layer in each step.

2. The method for fabricating a memory according to claim 1, characterized in that, The first sacrificial layer is made of the same material as the interlayer insulating layer, and the second sacrificial layer is made of the same material as the interlayer sacrificial layer.

3. The method for fabricating a memory according to claim 1, characterized in that, The thickness of the second sacrificial layer is greater than the thickness of the interlayer sacrificial layer.

4. The method for fabricating a memory according to claim 1, characterized in that, The first sacrificial layer has a horizontal platform and longitudinal sidewalls at each step; the method for fabricating the memory further includes: The second sacrificial layer located on the longitudinal sidewall of the first sacrificial layer is removed to form a spacer region; A filler insulating layer is covered on the first sacrificial layer and the second sacrificial layer, the filler insulating layer filling the spacer region.

5. The method for fabricating a memory according to claim 4, characterized in that, The filling insulating layer is made of the same material as the first sacrificial layer.

6. The method for fabricating a memory according to claim 4, characterized in that, Before the step of removing the interlayer sacrificial layer and the first sacrificial layer, the method for fabricating the memory further includes: A gate line slot is formed that extends through the stacked layers, and the gate line slot extends along a first direction.

7. The method for fabricating a memory according to claim 6, characterized in that, The step of removing the first sacrificial layer through the second cavity includes: The first sacrificial layer, a portion of the filling insulating layer, and a portion of the interlayer insulating layer are etched through the gate line gaps and the second cavity to form the third cavity including the second cavity.

8. The method for fabricating a memory according to claim 1, characterized in that, The material of the stop layer is silicon nitride or polycrystalline silicon.

9. The method for fabricating a memory according to claim 4, characterized in that, In each of the stack pairs, the interlayer insulating layer is located on the interlayer sacrificial layer; The step of forming word line contacts that penetrate the stop layer includes: Contact holes are formed by etching the filling insulating layer and the stop layer at each step, with the bottom of the contact holes located in the stop layer; The stop layer and the interlayer insulating layer at the bottom of the contact hole are further etched to make the contact hole contact the gate layer in each step; The contact hole is filled with conductive material.

10. A memory, characterized in that, include: Semiconductor layer; A stacked structure includes a plurality of stacked pairs stacked on the semiconductor layer, each of the stacked pairs including an interlayer insulating layer and a gate layer, the stacked structure including a step region, and the plurality of stacked pairs having a step structure in the step region; A stop layer is located on each step of the stepped structure, and the stop layer has a stop layer sidewall located at the edge of each step; Word line contacts penetrate the stop layer and extend to the gate layer in each step; The stop layer sidewall protrudes from the sidewall of each step. In the extending direction of the gate layer, the stop layer and the gate layer located in the same layer include a dielectric portion, which contacts the sidewall of the gate layer.

11. The memory according to claim 10, characterized in that, The material of the stop layer is silicon nitride or polycrystalline silicon.

12. The memory according to claim 10, characterized in that, The thickness of the stop layer is greater than the thickness of the gate layer.

13. The memory according to claim 10, characterized in that, The memory also includes: A dielectric layer covering the stepped structure and the stop layer; The dielectric layer and the interlayer insulating layer are made of the same material.

14. The memory according to claim 13, characterized in that, The memory also includes: The grid line slot structure penetrates the stacked structure and extends along a first direction.

15. The memory according to claim 14, characterized in that, The interlayer insulating layer has a groove at the junction with the gate line slot structure, the gate line slot structure fills the groove, and it intersects with the gate layer, the stop layer and the dielectric layer.

16. A storage system, characterized in that, include: The memory as described in any one of claims 10-15; A controller, electrically connected to the memory, is used to control the memory to store data.

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