Semiconductor structure

Abstract

The application discloses a semiconductor structure, comprising: a semiconductor substrate; and a logic unit with a logic function, comprising: a plurality of first transistors, each of the plurality of first transistors comprising a first gate electrode; a second transistor comprising a second gate electrode; a third transistor located in the active region, comprising a third gate electrode; and a first isolation structure and a second isolation structure, wherein the first isolation structure, the second isolation structure and the first gate electrode have a first length in the first direction, the second gate electrode and the third gate electrode have a second length in the first direction, and the second length is shorter than the first length. The first transistor is separated from the first isolation structure and the second isolation structure by using the second transistor and the third transistor, so that the above-mentioned structure of the application has a smaller area and higher efficiency under the condition that the semiconductor structure or the standard unit can normally work and run.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a semiconductor structure. Background Technology

[0002] Integrated circuits (ICs) have become increasingly important. Applications using ICs are used by millions of people. These applications include mobile phones, smartphones, tablets, laptops, PDAs, wireless email terminals, MP3 audio and video players, and portable wireless network browsers. ICs increasingly include powerful and efficient on-board data storage and logic circuits for signal control and processing.

[0003] As integrated circuits become smaller and more compact, the chip area increases as the number of standard cells used in integrated circuits increases. Therefore, there is a need for standard cells that offer smaller area and higher efficiency. Summary of the Invention

[0004] In view of this, the present invention provides a semiconductor structure to solve the above problems.

[0005] According to a first aspect of the present invention, a semiconductor structure is disclosed, comprising:

[0006] Semiconductor substrates; and

[0007] A logic unit, having a logic function, includes: a plurality of first transistors in an active region above a semiconductor substrate, each of the plurality of first transistors including a first gate electrode extending along a first direction; a second transistor located in the active region, including a second gate electrode extending along the first direction; a third transistor located in the active region, including a third gate electrode extending along the first direction; and a first isolation structure and a second isolation structure located at opposite edges of the active region and extending along the first direction.

[0008] The first gate electrode is disposed between the first isolation structure and the second isolation structure, the second gate electrode is disposed between the first gate electrode and the first isolation structure, and the third gate electrode is disposed between the first gate electrode and the second isolation structure.

[0009] The first isolation structure, the second isolation structure, and the first gate electrode have a first length in the first direction, and the second gate electrode and the third gate electrode have a second length in the first direction, wherein the second length is shorter than the first length.

[0010] According to a second aspect of the present invention, a semiconductor structure is disclosed, comprising:

[0011] Semiconductor substrates; and

[0012] A logic unit having a first logic function and a second logic function includes: at least one first transistor in an active region above a semiconductor substrate, including a first gate electrode extending along a first direction, wherein the first transistor is configured to perform the first logic function; at least one second transistor in the active region, including a second gate electrode extending along the first direction, wherein the second transistor is configured to perform the second logic function; a first isolation structure disposed at a first edge of the active region and extending along the first direction; and a second isolation structure disposed at a second edge of the active region and extending along the first direction.

[0013] The first gate electrode is disposed between the first isolation structure and the second gate electrode, and the second gate electrode is disposed between the first gate electrode and the second isolation structure.

[0014] The first edge of the active region is positioned opposite to the second edge of the active region.

[0015] According to a third aspect of the present invention, a semiconductor structure is disclosed, comprising:

[0016] Semiconductor substrates; and

[0017] A logic unit, having logic functions, includes: a plurality of P-type transistors located in a first active region above the semiconductor substrate, each of the plurality of P-type transistors including a first gate electrode extending along the first direction; a plurality of N-type transistors located in a second active region above the semiconductor substrate, wherein each of the plurality of N-type transistors shares the first gate electrode with its respective P-type transistor; a first isolation structure and a second isolation structure located at opposite edges of the first active region and opposite edges of the second active region, and extending along the first direction; and a first transistor located in the first active region and between the first isolation structure and the P-type transistor. The transistor includes a second gate extending along the first direction; a second transistor located in the first active region and between the second isolation structure and the P-type transistor, including a third gate electrode extending along the first direction; a third transistor located in the second active region and between the first isolation structure and the N-type transistor, wherein the first transistor and the third transistor share a second gate; and a fourth transistor located in the second active region and between the second isolation structure and the N-type transistor, wherein the second transistor and the fourth transistor share a third gate electrode, wherein the P-type transistor and the N-type transistor are used to perform logic functions.

[0018] The semiconductor structure of the present invention includes: a semiconductor substrate; and a logic unit having a logic function, comprising: a plurality of first transistors in an active region above the semiconductor substrate, each of the plurality of first transistors including a first gate electrode extending along a first direction; a second transistor located in the active region including a second gate electrode extending along the first direction; a third transistor located in the active region including a third gate electrode extending along the first direction; and a first isolation structure and a second isolation structure located at opposite edges of the active region and extending along the first direction, wherein the first gate electrode is disposed between the first isolation structure and the second isolation structure, the second gate electrode is disposed between the first gate electrode and the first isolation structure, and the third gate electrode is disposed between the first gate electrode and the second isolation structure, wherein the first isolation structure, the second isolation structure and the first gate electrode have a first length in the first direction, the second gate electrode and the third gate electrode have a second length in the first direction, and the second length is shorter than the first length. In this way, the first transistor can be isolated from the first isolation structure and the second isolation structure using the second transistor and the third transistor, thereby avoiding or reducing the influence of the first isolation structure and the second isolation structure on the first transistor. Therefore, the structure of the present invention has a smaller area and higher efficiency while ensuring that the semiconductor structure or standard cell can work and operate normally. Attached Figure Description

[0019] Figure 1 A simplified diagram illustrating a cell array of an IC according to some embodiments of the present invention is shown.

[0020] Figure 2 Illustrations of some embodiments according to the present invention are shown. Figure 1 A simplified diagram of a row in a cell array.

[0021] Figure 3A A simplified diagram illustrating a logic unit according to some embodiments of the present invention is shown.

[0022] Figure 3B The semiconductor structure of a logic cell according to some embodiments of the present invention is shown along... Figure 3A The cross-sectional view of line A-AA in the diagram.

[0023] Figure 3C The following are some embodiments of the invention. Figure 3A A cross-sectional view of the semiconductor structure of the logic cell with line B-BB in the diagram.

[0024] Figure 4 A simplified diagram illustrating a logic unit according to some embodiments of the present invention is shown.

[0025] Figure 5 A diagram illustrating the relationship between cell delay and diffusion edge extension according to some embodiments of the present invention is shown.

[0026] Figure 6 A simplified diagram illustrating a logic unit according to some embodiments of the present invention is shown.

[0027] Figure 7A A simplified diagram illustrating a logic unit according to some embodiments of the present invention is shown.

[0028] Figure 7B The semiconductor structure of a logic cell according to some embodiments of the present invention is shown along... Figure 7A A cross-sectional view of line C-CC in the diagram.

[0029] Figure 7C The following are some embodiments of the invention. Figure 7A A cross-sectional view of the semiconductor structure of the line D-DD logic unit.

[0030] Figure 8 A simplified diagram illustrating a logic unit according to some embodiments of the present invention is shown.

[0031] Figure 9 A simplified diagram illustrating a logic unit according to some embodiments of the present invention is shown.

[0032] Figure 10A A simplified diagram illustrating a logic unit according to some embodiments of the present invention is shown.

[0033] Figure 10B Some embodiments of the invention are shown along Figure 10A A cross-sectional view of the semiconductor structure of the logic cell E-EE in the diagram.

[0034] Figure 11 A simplified diagram illustrating a logic unit according to some embodiments of the present invention is shown.

[0035] Figure 12 A simplified diagram illustrating a logic unit according to some embodiments of the present invention is shown.

[0036] Figure 13A A simplified diagram illustrating a logic unit according to some embodiments of the present invention is shown.

[0037] Figure 13B The following are some embodiments of the invention shown. Figure 13A A cross-sectional view of the semiconductor structure of the logic cell with line F-FF in the diagram.

[0038] Figure 14A simplified diagram illustrating a logic unit according to some embodiments of the present invention is shown.

[0039] Figure 15 A simplified diagram illustrating a logic unit according to some embodiments of the present invention is shown.

[0040] Figure 16 A simplified diagram illustrating a logic unit according to some embodiments of the present invention is shown.

[0041] Figure 17 A simplified diagram illustrating a logic unit according to some embodiments of the present invention is shown.

[0042] Figure 18 A simplified diagram illustrating a group logic unit according to some embodiments of the present invention is shown.

[0043] Figure 19 A simplified diagram illustrating a group logic unit according to some embodiments of the present invention is shown.

[0044] Figure 20 A simplified diagram illustrating a group logic unit according to some embodiments of the present invention is shown.

[0045] Figure 21 A simplified diagram illustrating a group logic unit according to some embodiments of the present invention is shown. Detailed Implementation

[0046] In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings, which form part of the invention, and which illustrate specific preferred embodiments in which the invention can be practiced. These embodiments have been described in sufficient detail to enable those skilled in the art to practice them, and it should be understood that other embodiments may be utilized, and mechanical, structural, and procedural changes may be made, without departing from the spirit and scope of the invention. Therefore, the following detailed description should not be construed as limiting, and the scope of the embodiments of the invention is defined only by the appended claims.

[0047] It will be understood that although the terms “first,” “second,” “third,” “primary,” “secondary,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another. Therefore, without departing from the teachings of the inventive concept, the first or primary element, component, region, layer, or portion discussed below may be referred to as a second or secondary element, component, region, layer, or portion.

[0048] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “under,” “above,” and “above” may be used herein to describe the relationship of an element or feature to it. Another element or feature is shown in the figure. In addition to the orientation described in the figure, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly. Additionally, it will be understood that when a “layer” is referred to as being “between” two layers, it can be the only layer between the two layers, or there may be one or more intermediate layers.

[0049] The terms “about,” “roughly,” and “about” generally mean a range of ±20%, ±10%, ±5%, ±3%, ±2%, ±1%, or ±0.5% of a specified value. The specified values ​​in this invention are approximate. Unless otherwise specified, the specified values ​​include the meanings of “about,” “roughly,” and “about.” The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular terms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise.

[0050] It will be understood that when an “element” or “layer” is referred to as being “on,” “connected to,” “coupled to,” or “adjacent to” another element or layer, it can be directly on, connected to, coupled to, or adjacent to the other element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being “directly on,” “directly connected to,” “directly coupled to,” or “immediately adjacent to” another element or layer, there are no intermediate elements or layers.

[0051] Note: (i) the same features will be represented by the same reference numerals throughout the figures and will not necessarily be described in detail in every figure in which they appear, and (ii) a series of figures may show different aspects of a single item, each of which is associated with various reference labels that may appear throughout the series or only in selected figures of the series.

[0052] Figure 1A simplified diagram illustrating a cell array 100 of an IC according to some embodiments of the present invention is shown. The cell array 100 includes a plurality of logic cells 10. In some embodiments, the logic cells 10 are standard cells (e.g., INV (inverter), AND, OR, NAND, NOR, Flip-Flop, SCAN, etc.), combinations thereof, or specific (custom) logic function cells. Furthermore, the logic functions among the logic cells 10 can be the same or different. Additionally, each logic cell 10 includes a plurality of transistors. In some embodiments, logic cells 10 corresponding to the same function or operation may have the same circuit configuration but different semiconductor structures and / or different layouts. Figure 1 In this layout, the logic units 10 have the same unit height H1 (e.g., along the Y direction). Furthermore, the logic units 10 may have the same or different unit widths (e.g., along the X direction). It should be noted that the number and configuration of the logic units 10 are merely examples and are not intended to limit the invention.

[0053] In some embodiments, the transistors in the logic unit 10 are selected from planar transistors, fin field effect transistors (FinFETs), vertical gate all around (GAA), horizontal GAA, nanowires, nanosheets, or combinations thereof.

[0054] Figure 2 Illustrations of some embodiments according to the present invention are shown. Figure 1 A simplified diagram of a row or column in a cell array 100. The cell array 100 may be part of or a component of a semiconductor structure. Logic cells 10_1, 10_2, and 10_3 are arranged in the same row and located between power line 20 (e.g., VDD line or first power line) and ground line 30 (e.g., VSS line or second power line). Furthermore, the outer boundary of each of the logic cells 10_1, 10_2, and 10_3 is shown using dashed lines. Logic cells 10_1, 10_2, and 10_3 have the same cell height H1. Figure 1In the cell array 100, logic cells 10 in the same row are electrically isolated from each other by isolation structures (or regions). In other words, the active region of each logic cell 10 is separated from the active regions (or active areas) of adjacent logic cells 10 by isolation structures. In some embodiments, the isolation structure may be a diffusion break (DB) structure. In some embodiments, the isolation structure may be shallow trench isolation (STI). In some embodiments, the isolation structure may be a dielectric-base dummy gate. Compared to continuous diffusion logic cells, logic cells 10_1, 10_2, and 10_3 have smaller cell areas (e.g., a 10% reduction in area) due to their smaller cell height and narrower power / ground lines.

[0055] In logic cell 10_1, gate structures 210_1 and 210_2 extending along the Y direction form P-type transistors P11 and P12 in the active region 110_1 of the N-type well region NW, and N-type transistors N11 and N12 in the active region 120_1 of the P-type well region PW. In logic cell 10_2, gate structures 210_3 to 210_6 extending along the Y direction form P-type transistors P21 to P24 in the active region 110_2 of the N-type well region NW, and P-type transistors P21 to P24 in the active region 120_2 of the P-type well region PW. In logic cell 10_3, gate structures 210_7 and 210_8 extending along the Y direction form P-type transistors P31 and P32 in the active region 110_3 of the N-type well region NW, and N-type transistors N31 and N32 in the N-type well region NW in the active region 120_3 of the P-type well region PW. For simplicity, detailed descriptions of gate structures 210_1 to 210_8, such as the gate dielectric, gate electrode, and corresponding source / drain regions, will be omitted. In this document, the gate structure may also be referred to as the gate or gate electrode.

[0056] P-type transistors P11 and P12 and N-type transistors N11 and N12 are configured to perform a first logic function of logic unit 10_1. P-type transistors P21 to P24 and N-type transistors N21 to N24 are configured to perform a second logic function of logic unit 10_2. P-type transistors P31 and P32 and N-type transistors N31 and N32 are configured to perform a third logic function of logic unit 10_3. In some embodiments, the first, second, and third logic functions are different. For example, logic unit 10_1 is an inverter (NOT gate), logic unit 10_2 is a NAND gate, and logic unit 10_3 is a NOR gate. In some embodiments, the first, second, and third logic functions are the same. For example, logic units 10_1, 10_2, and 10_3 are inverters with different drive strengths.

[0057] exist Figure 2 In this configuration, isolation structures 215_1 and 215_2 are arranged within the boundary of logic unit 10_1, isolation structures 215_2 and 215_3 are arranged within the boundary of logic unit 10_2, and isolation structures 215_3 and 215_4 are arranged within the boundary of logic unit 10_3. In other words, the active regions 110_1 and 120_1 of logic unit 10_1 are separated (or isolated) from the active regions 110_2 and 120_2 of logic unit 10_2 by isolation structure 215_2. Furthermore, the active regions 110_2 and 120_2 of logic unit 10_2 are separated (or isolated) from the active regions 110_3 and 120_3 of logic unit 10_2 by isolation structure 215_3.

[0058] In logic cells 10_1 to 10_3, gate structures are arranged between isolation structures with a fixed pitch PH. For example, gate structures 210_3 to 210_6 are arranged sequentially from isolation structure 215_2 to isolation structure 215_3 according to the pitch PH. Furthermore, the pitch between isolation structure 215_2 and gate structure 210_2 is equal to the pitch between isolation structure 215_2 and gate structure 210_3, that is, the pitch between them is also pitch PH.

[0059] In some embodiments, gate structures 210_1 to 210_8 and isolation structures 215_1 to 215_4 have the same length (e.g., H1) in the Y direction. In some embodiments, gate structures 210_1 to 210_8 and isolation structures 215_1 to 215_4 have the same width in the X direction. Furthermore, gate structures 210_1 to 210_8 and isolation structures 215_1 to 215_4 are formed below and partially covered by power lines 20 and ground lines 30. The cell array 100 may also include power lines 20 and ground lines 30. When forming the cell array, the power lines 20 and ground lines 30 of each logic cell may be aligned to join together.

[0060] In some embodiments, each of the gate structures 210_1 to 210_8 may be continuous poly, and each of the isolation structures 215_1 to 215_4 may be continuous poly on a diffusion edge.

[0061] Figure 3A A simplified diagram illustrating a logic unit 10A according to some embodiments of the present invention is shown. The logic unit 10A is capable of providing specific (or custom, tailored) logic functions with small cell delays. The logic unit 10A is arranged between a power line 20 and a ground line 30 and has a cell height H1. Furthermore, the outer boundary of the logic unit 10A is shown using dashed lines.

[0062] In logic cell 10A, gate structures 210a to 210d extending along the Y direction form P-type transistors P1 to P4 in the active region 110 of the N-type well region NW. Furthermore, gate structures 210a to 210d form N-type transistors N1 to N4 in the active region 120 of the P-type well region PW. The P-type transistors P1 to P4 and the N-type transistors N1 to N4 are configured to perform specific logic functions of logic cell 10A.

[0063] and Figure 2Compared to logic units 10_1, 10_2, and 10_3, logic unit 10A further includes tie-gate transistors T1 and T2. Each of the tie-gate transistors T1 and T2 is a dummy P-type transistor, which has a source region and a drain region both coupled to its gate. Gate structures 210e and 210f extending along the Y direction form the tie-gate transistors T1 and T2 in the active region 110 of the N-type well region NW. It should be noted that gate structures 210e and 210f only extend above the N-type well region NW and do not extend above the P-type well region PW. Therefore, gate structures 210e and 210f are shorter than gate structures 210a to 210d. In this embodiment of the invention, gate structures 210e and 210f are shorter than gate structures 210a and 210d, therefore, gate structures 210e and 210f are not actually gate structures of the transistors (transistors T1 and T2) used for logic functions. Furthermore, transistors T1 and T2 are dummy transistors and do not perform logic functions. They are used to separate isolation structures 215a and 215b from transistors P1-P4 located between transistors T1 and T2, thereby avoiding or reducing the negative impact of diffusion stress on transistors P1-P4 and ensuring normal operation of the transistors. In this embodiment, isolation structures 215a and 215b extending along the Y direction are arranged within the boundary of logic unit 10A. The diffusion stress of isolation structure 215a has a more severe negative impact on PMOS, but almost no negative impact on NMOS (NMOS transistors, such as N-type transistors N1 to N4). In the above design of this embodiment, gate structures 210e and 210f only extend above the N-type well region NW and not above the P-type well region PW. Dielectric base-gate structures 217a and 217b are located above the P-type well region PW. Therefore, the embodiments of the present invention employ targeted design to avoid redundant design and redundant circuit layout. This allows for more remaining space above the P-type well region PW, reducing space occupation. The reserved space can be used for the layout of other circuits, improving design flexibility. Of course, in other embodiments, gate structures 210e and 210f can also extend above the P-type well region PW, and can be freely designed as needed. Furthermore, when gate structures 210e and 210f extend above the P-type well region PW, they can be electrically connected to the ground line 30 in a manner similar to (or other ways) connecting gate structures 217a and 217b to the power supply line 20. Additionally, as follows: Figure 6 As shown, this case can also adopt... Figure 6 The design shown includes the connection of gate transistors T3 and T4, which can be referred to in the following description.

[0064] exist Figure 3AIn the active region 110, connection features 220a to 220g extending along the Y direction are located above the active region 110. Connection features 220a to 220g are formed in the same layer above the active region 110. In some embodiments, one of each connection feature 220a to 220g is a contact for connecting the source / drain regions of a transistor. Furthermore, connection features 230a to 230f are located in the logic cell 10A. Connection features 230a to 230f are formed above connection features 220a to 220g. In some embodiments, each of connection features 230a to 230f is a via for connecting a corresponding contact or contact point (e.g., a source / drain contact). Furthermore, connection features 235a and 235b are located in the logic cell 10A. Connection features 235a and 235b, as well as connection features 230a to 230f, are formed in the same layer. In some embodiments, each of connection features 235a and 235b is a via (e.g., a gate contact) for connecting a corresponding gate structure. Furthermore, the materials of connection features 235a and 235b, connection features 230a to 230f, and connection features 220a to 220g are selected from Ti, TiN, TaN, Co, Ru, Pt, Ni, W, Al, Cu, or combinations thereof. In some embodiments, connection features 235a and 235b, connection features 230a to 230f, and connection features 220a to 220g are formed of the same material. In some embodiments, connection features 235a and 235b, connection features 230a to 230f, and connection features 220a to 220g are formed of different materials.

[0065] Isolation structures 215a and 215b extending in the Y direction are arranged within the boundary of logic cell 10A. Gate structures 210a to 210d are surrounded (or sandwiched in between) by isolation structures 215a and 215b. Gate structure 210e is disposed (or inserted) between isolation structure 215a and gate structure 210a, and gate structure 210f is disposed (or inserted) between isolation structure 215b and gate structure 210d. In this embodiment, N-type transistor N1 shares gate structure 210a with P-type transistor P1, N-type transistor N2 shares gate structure 210b with P-type transistor P2, N-type transistor N3 shares gate structure 210c with P-type transistor P3, and N-type transistor N4 shares gate structure 210d with P-type transistor P4. Therefore, each N-type transistor shares a gate structure with its corresponding P-type transistor.

[0066] In logic cell 10A, gate structures 210a to 210f are arranged between isolation structures 215a and 215b with a fixed pitch PH. For example, gate structures 210e, 210a to 210d and 210f are arranged sequentially from isolation structure 215a to isolation structure 215b according to the pitch PH.

[0067] The active regions 110 and 120 of the logic unit 10A are defined by isolation structures 215a and 215b along the X direction. For example, isolation structure 215a is located at the left edge of the active regions 110 and 120, while isolation structure 215b is located at the right edge of the active regions 110 and 120. In other words, isolation structures 215a and 215b are located at the opposite edges of the active regions 110 and 120. By inserting gate structure 210e (i.e., connecting gate transistor T1), gate structure 210a (i.e., P-type transistor P1) is moved away from the left edge of the active region 110. Therefore, the diffusion destructive stress (diffusion stress) at the left edge of the active region 110 is avoided, which would reduce the saturation drain current (Idsat) of P-type transistor P1, especially for P-type transistors with SiGe channels. Furthermore, by inserting gate structure 210f (i.e., connecting gate transistor T2), gate structure 210d (i.e., P-type transistor P4) is moved away from the right edge of the active region 110. Therefore, avoiding the diffusion-induced destructive stress at the right edge of the active region 110 reduces the saturation drain current (Idsat) of the P-type transistor P4, especially for P-type transistors with SiGe channels.

[0068] In logic cell 10A, a dielectric base gate structure 217a extending in the Y direction is disposed between gate structure 210a and isolation structure 215a and above active region 120. Furthermore, a dielectric base gate structure 217b extending in the Y direction is disposed between gate structure 210d and isolation structure 215b and above active region 120. It is noteworthy that dielectric base gate structures 217a and 217b extend only above P-type well region PW and not above N-type well region NW. Therefore, dielectric base gate structures 217a and 217b are shorter than gate structures 210a to 210d. In some embodiments, dielectric base gate structures 217a and 217b and gate structures 210e and 210f have the same length. Dielectric base gate structures 217a and 217b can be used to space transistors.

[0069] In some embodiments, dielectric base gate structures 217a and 217b are formed at the interface between the N-type well region NW and the P-type well region PW by performing a cut-metal gate (CMG) process or a cut-poly (CPO) process on gate structures 210e and 210f, which have the same length as the gate structures 210a to 210d. Then, the gate features of the gate structures 210e and 210f above the P-type well region are replaced with a dielectric substrate material.

[0070] Figure 3B The semiconductor structure of logic cell 10A according to some embodiments of the present invention is shown along Figure 3A The cross-sectional view of line A-AA in the diagram. Please refer to it together. Figure 3A and 3B An N-type well region NW is formed above a substrate (not shown). In some embodiments, the substrate is a Si substrate. In some embodiments, the substrate material is selected from bulk silicon, SiP, SiGe, SiC, SiPC, Ge, SOI-Si, SOI-SiGe, III-VI materials, or combinations thereof. In some embodiments, the N-type well region NW is an N-type substrate. A semiconductor fin (or fin sheet) 200a is formed on the N-type well region NW. Furthermore, isolation structures 215a and 215b are arranged on the left and right edges of the semiconductor fin 200a.

[0071] Connection feature 220a is formed between isolation structure 215a and gate structure 210e, and the source region 205a of gate transistor T1 is coupled to power line 20 through connection feature 220a and connection feature 230a. Connection feature 220b is formed between gate structures 210e and 210a, and the common source / drain region (source / drain region) 205b of gate transistor T1 and P-type transistor P1 is coupled to power line 20 through connection feature 220b and connection feature 230b. Connection feature 220c is formed between gate structures 210a and 210b, and the common source / drain region 205c of P-type transistors P1 and P2 is coupled to interconnect structure (not shown) through connection feature 220c.

[0072] Connection feature 220g is formed between isolation structure 215b and gate structure 210f, and the source region 205g of gate transistor T2 is coupled to power line 20 via connection feature 220g and connection feature 230e. Connection feature 220f is formed between gate structures 210d and 210f, and the common source / drain region (source / drain region) 205f of gate transistor T2 and P-type transistor P4 is coupled to power line 20 via connection feature 220f and connection feature 230d. Connection feature 220e is formed between gate structures 210c and 210d, and the common source / drain region 205e of P-type transistors P3 and P4 is coupled to interconnect structure (not shown) via connection feature 220e.

[0073] Connection feature 220d is formed between gate structures 210b and 210c, and the common source / drain region (source / drain region) 205d of P-type transistors P2 and P3 is connected to power line 20 via connection feature 220d and connection feature 230c. Furthermore, connection feature 220d is also coupled to a metal line 240 extending in the X direction via connection feature 230f. Metal line 240 is coupled to gate structures 210e and 210f via connection features 235a and 235b, respectively. In some embodiments, metal line 240, power line 20, and ground line 30 are formed in the same metal line. Metal line 240 is electrically connected to power line 20.

[0074] For the gate transistor T1, for example, the source region (or drain region) 205a is coupled to the power line 20 via connection features 220a and 230a. Furthermore, the drain region (correspondingly, or source region) 205b is coupled to the power line 20 via connection features 220b and 230b. Additionally, the gate structure 210e is coupled to the power line 20 via metal line 240 and connection features 220d, 230c, 230f, and 235a. Similarly, for the gate transistor T2, the source region 205g is coupled to the power line 20 via connection features 220g and 230e. Furthermore, the drain region 205f is coupled to the power line 20 via connection features 220f and 230d. Additionally, the gate structure 210f is coupled to the power line 20 via metal line 240 and connection features 220d, 230c, 230f, and 235b. Therefore, the drain, gate, and source regions (source regions) of gate transistors T1 and T2 are coupled to the power line 20 through a first-type interconnect structure formed by metal lines 240 and corresponding connection features (e.g., 235a, 235b). In other words, the gate transistors T1 and T2 cannot provide specific logic functions for the logic cell 10A.

[0075] Figure 3C The following are some embodiments of the invention shown. Figure 3AA cross-sectional view of the semiconductor structure of logic cell 10A along line B-BB. (See also: [link to reference]). Figure 3A and 3C A semiconductor fin 200b is formed on the P-type well region PW. Furthermore, isolation structures 215a and 215b are disposed on the left and right edges of the semiconductor fin 200b. For simplicity, the connection features of the source / drain regions connecting N-type transistors N1 to N4 are omitted.

[0076] exist Figure 3C In this configuration, a dielectric substrate dummy gate 217a is formed between gate structure 210a and isolation structure 215a, and a dielectric substrate dummy gate 217b is formed between gate structure 210d and isolation structure 215b. The lower surfaces of isolation structures 215a and 215b are lower than the lower surfaces of the dielectric substrate dummy gates 217a and 217b. Furthermore, the depth of isolation structures 215a and 215b is greater than the depth of the dielectric substrate dummy gates 217a and 217b. In some embodiments, the upper surfaces of the dielectric substrate dummy gates 217a and 217b are flush with the upper surfaces of the isolation structures 215a and 215b. In some embodiments, isolation structures 215a and 215b are formed by STI (Surface Mount Technology), and the upper surfaces of isolation structures 215a and 215b are flush with the lower surfaces of the dielectric substrate dummy gates 217a and 217b. The dielectric base dummy gates 217a and 217 can be made of dielectric material, such as the same material as the isolation structure 215a.

[0077] Figure 4 A simplified diagram illustrating a logic cell 10B according to some embodiments of the present invention is shown. The outer boundary of the logic cell 10B is shown by dashed lines. The semiconductor structure of the logic cell 10B is similar to... Figure 3A The semiconductor structure of the logic unit 10A, and Figure 4 and Figure 3A The difference lies in that logic cell 10B includes more gate-connecting transistors T1_1 to T1_3 and more gate-connecting transistors T2_1 to T2_3. For simplicity, the connection characteristics of the source / drain regions of the transistors are omitted.

[0078] exist Figure 4In this configuration, gate structures 210e_1 to 210e_3 are disposed between gate structure 210a and isolation structure 215a above active region 110, and gate structures 210f_1 to 210f_3 are disposed between gate structure 210d and isolation structure 215b above active region 110. Furthermore, dielectric substrate gate structures 217a_1 to 217a_3 are disposed between gate structure 210a and isolation structure 215a above active region 120, and dielectric substrate gate structures 217b_1 to 217b_3 are disposed between gate structure 210d and isolation structure 215b above active region 120. Additionally, extended metal lines 240 are connected to gate structures 210e_1 to 210e_3 and 210f_1 to 210f_1 respectively via connecting features 235a_1 to 235a_3 and 235b_1 to 235b_1.

[0079] It should be noted that the number of gate structures 210e_1 to 210e_3 and 210f_1 to 210f_3, and the corresponding dielectric substrate gate structures 217a_1 to 217a_3 and 217b_1 to 217b_3, are merely illustrative examples and are not intended to limit the invention. In some embodiments, the number of gate structures 210e_1 to 210e_3 or 210f_1 to 210f_3 is greater than the number of gate structures 210a to 210d, which achieves better isolation and further reduces the impact of isolation structures 215a and 215b on transistors with logic functions. Of course, it is not necessarily better to have more gate transistors (e.g., gate transistor T1); the number can be freely set as needed. In some embodiments, the number of gate structures 210e_1 to 210e_3 or 210f_1 to 210f_3 is equal to the number of gate structures 210a to 210d. In some embodiments, the number of gate structures 210e_1 to 210e_3 or 210f_1 to 210f_3 is less than the number of gate structures 210a to 210d.

[0080] Because the distance between P-type transistor P1 and isolation structure 215a and the distance between P-type transistor P4 and isolation structure 215b are increased, logic cell 10B can provide the specific logic functions of logic cell 10A with a smaller cell delay. Therefore, it is more effective to avoid the diffusion-induced destructive stress at the edges of the active region 110 from reducing the saturation drain current (Idsat) of the transistors in logic cell 10A, especially the saturation drain currents of P-type transistors P1 and P4.

[0081] Figure 5A diagram illustrating the relationship between cell delay and diffusion edge extension according to some embodiments of the present invention is shown. By inserting more connected gate transistors, as the diffusion edge extension increases (i.e., the gate structure of the connected gate transistors increases), the cell delay of the logic cell (e.g., the delay time from input to output) decreases. The arrangement of connected gate transistors reduces the cell delay caused by interference from the edge-located isolation structures on transistors P1 and P4.

[0082] Figure 6 A simplified diagram illustrating a logic cell 10C according to some embodiments of the present invention is shown. The outer boundary of the logic cell 10C is indicated by dashed lines. The semiconductor structure of the logic cell 10C is similar to... Figure 3A The semiconductor structure of the logic unit 10A is similar, while Figure 6 and Figure 3A The difference lies in that logic cell 10C also includes connection gate transistors T3 and T4 located above the active region 120. For simplicity, the connection characteristics of the source / drain regions of the connection transistors are omitted.

[0083] exist Figure 6 In the logic cell 10C, gate structure 210g is disposed between gate structure 210a and isolation structure 215a, and gate structure 210h is disposed between gate structure 210d and isolation structure 215b above active region 120. No dielectric base gate structure is provided in the logic cell 10C. Furthermore, metal line 242 is coupled to gate structures 210g and 210h via connection features 235c and 235d, respectively. Similarly, metal line 242 is also coupled to ground line 30 via connection feature 230g and corresponding connection features (not shown), such as the contact of the common source / drain regions of N-type transistors N2 and N3. Furthermore, the source and drain regions of gate transistors T3 and T4 are coupled to ground line 30 via corresponding features (not shown). Therefore, each of gate transistors T3 and T4 forms a dummy N-type transistor, with its source and drain regions coupled to its gate.

[0084] Logic cell 10C is able to provide a specific logic function delay for logic cell 10A with a smaller cell d because it uses more gate-connecting transistors (e.g., transistors T3 and T4). Therefore, the diffusion-induced destructive stress at the edges of the active regions 110 and 120 is less likely to reduce the saturation drain current (Idsat) of the transistors in logic cell 10C, particularly P-type transistors P1 and P4 and N-type transistors N1 and N4.

[0085] Figure 7AA simplified diagram illustrating a logic unit 10D according to some embodiments of the present invention is shown. The outer boundary of the logic unit 10D is indicated by dashed lines. The logic unit 10D is capable of providing similar... Figure 3A The specific logic function of logic unit 10A. The semiconductor structure of logic unit 10D and... Figure 3A The semiconductor structure of logic unit 10A is similar to that of logic unit 10A. Figure 7A and Figure 3A The difference lies in that the drain, gate, and source regions of the gate transistors T1 and T2 are coupled to the power line 20 via a second type of interconnect structure. For simplicity, the connection features of the source / drain regions of the transistors are omitted.

[0086] Figure 7B The semiconductor structure of the logic cell 10D according to some embodiments of the present invention is shown along... Figure 7A The cross-sectional view of line C-CC in the diagram. Please refer to the reference diagram. Figure 7A and Figure 7B The gate structure 210e of the gate transistor T1 is coupled to a metal line 240a extending in the X direction via a connection feature 235a, and the metal line 240a is further coupled to a metal line 320a extending in the Y direction via a connection feature 310a. Furthermore, the gate structure 210f of the gate transistor T2 is coupled to a metal line 240b extending in the X direction via a connection feature 235b, and the metal line 240b is further coupled to a metal line 320b extending in the Y direction via a connection feature 310c. Metal lines 240a and 240b are formed in a first metal layer, and metal lines 320a and 320b are formed in a second metal layer above the first metal layer. Furthermore, metal lines 240a and 240b are separated or spaced apart. Furthermore, the lengths of metal lines 240a and 240b are less than twice the pitch PH. Compared to Figures 3A-3B The connection path or connection method shown for connecting the drain, gate, and source regions of gate transistors T1 and T2 to the power supply line 20. Figures 7A-7B This diagram illustrates another connection path or method for connecting the metal line 240 to the drain, gate, and source regions of the gate transistors T1 and T2. Therefore, different connection paths or methods can be freely selected according to wiring requirements or design specifications, improving design flexibility. Figures 3A-3B The connection path or connection method shown for connecting the drain, gate, and source regions of gate transistors T1 and T2 to the power supply line 20 can also be called a first-type interconnect structure. Figures 7A-7B This illustrates another connection path or connection method for connecting the drain, gate, and source regions of gate transistors T1 and T2 to the power line 20, which can also be called a second type of interconnect structure.

[0087] Figure 7CThe following are some embodiments of the invention shown. Figure 7A The image shows a cross-sectional view of the semiconductor structure of the 10D logic unit in the D-DD line. Please also refer to... Figure 7A and Figure 7C For example, the source region 205a of the gate transistor T1 is coupled to the metal line 244a extending in the X direction via connection features 220a and 230j, and the drain region 205b of the gate transistor T1 is connected to the metal line 244a via connection features 220b and 230h. Furthermore, the source region (or drain region) 205g of the gate transistor T2 is connected to the metal line 244b extending in the X direction via connection features 220g and 230k, and the drain region (correspondingly, the source region) 205f of the gate transistor T2 is coupled to the metal line 244b via connection features 220f and 230i.

[0088] In logic cell 10D, metal line 244a is further coupled to metal line 320a via connection feature 310b, and metal line 244b is further coupled to metal line 320b via connection feature 310d. Therefore, the drain, gate, and source regions of gate transistor T1 are coupled to power line 20 via a second-type interconnect structure 50D_1 formed by metal lines 240a, 320a, and 244a and their respective connection features. Furthermore, the drain, gate, and source regions of gate transistor T2 are coupled to power line 20 via a second-type interconnect structure 50D_2 formed by metal lines 240b, 320b, and 244b and their respective connection features. In some embodiments, the second-type interconnect structures 50D_1 and 50D_2 are mirror-image in the X-direction in the layout (i.e., the second-type interconnect structures 50D_1 and 50D_2 are axially symmetrical, for example, the axis extending along the Y-direction and located at the middle position of logic cell 10D).

[0089] Figure 8 A simplified diagram illustrating a logic cell 10E according to some embodiments of the present invention is shown. The outer boundary of the logic cell 10E is shown by dashed lines. The semiconductor structure of the logic cell 10E is similar to... Figure 7A The semiconductor structure of the logic unit 10D is similar, while Figure 8 and Figure 7A The difference is that logic cell 10E includes more gate transistors T1_1 to T1_3 and more gate transistors T2_1 to T2_3.

[0090] exist Figure 8In this configuration, extended metal lines 240a are connected to gate structures 210e_1 to 210e_3 via connection features 235a_1 to 235a_3, respectively. Extended metal lines 240b are connected to gate structures 210f_1 to 210f_3 of gate transistors T2_1 to T2_3 via connection features 235b_1 to 235b_3, respectively. Furthermore, extended metal lines 244a are coupled to the source / drain regions of gate transistors T1_1 to T1_3 via connection features 230j_1 to 230j_3 and 230h. Extended metal lines 244b are coupled to the source / drain regions of gate transistors T2_1 to T2_3 via connection features 230k_1 to 230k_3 and 230i.

[0091] Because the distance between P-type transistor P1 and isolation structure 215a and the distance between P-type transistor P4 and isolation structure 215b are increased, logic cell 10E can provide the specific logic function of logic cell 10D with a small cell delay. Therefore, it is more effective to avoid the diffusion damage stress at the left and right edges of the active region 110 from reducing the saturation drain current (Idsat) of the transistors in logic cell 10E, especially the saturation drain current of P-type transistors P1 and P4.

[0092] Figure 9 A simplified diagram illustrating a logic cell 10F according to some embodiments of the present invention is shown. The outer boundary of the logic cell 10F is shown using dashed lines. The semiconductor structure of the logic cell 10F is similar to... Figure 7A The semiconductor structure of the logic unit 10D, and Figure 9 and Figure 7A The difference is that logic cell 10F also includes connection gate transistors T3 and T4 above the active region 120.

[0093] exist Figure 9 In this configuration, the drain, gate, and source regions of gate transistor T3 are coupled to ground line 30 via a second-type interconnect structure 50D_3. Furthermore, the drain, gate, and source regions of gate transistor T4 are coupled to ground line 30 via a second-type interconnect structure 50D_4. Therefore, each of gate transistors T3 and T4 forms a dummy N-type transistor, with its source and drain regions both coupled to its gate. In some embodiments, second-type interconnect structures 50D_1 and 50D_3 are mirror images in the X-direction, while second-type interconnect structures 50D_2 and 50D_4 are mirror images in the X-direction (i.e., second-type interconnect structures 50D_1 and 50D_3 are symmetrical along the Y-axis, and second-type interconnect structures 50D_2 and 50D_4 are symmetrical along the Y-axis).

[0094] Logic cell 10F is able to provide the specific logic functions of logic cell 10D with small cell delays because it uses more gate-connecting transistors (e.g., transistors T3 and T4). Therefore, it is more likely that the diffusion-induced destructive stress at the edges of the active regions 110 and 120 will reduce the saturation drain current (Idsat) of the transistors in logic cell 10F, especially the saturation drain current of P-type transistors P1 and P4 and N-type transistors N1 and N4.

[0095] Figure 10A A simplified diagram illustrating a logic unit 10G according to some embodiments of the present invention is shown. The outer boundary of the logic unit 10G is shown using dashed lines. The logic unit 10G is capable of providing similar... Figure 3A The specific logic function of logic unit 10A. The semiconductor structure of logic unit 10G and... Figure 3A The semiconductor structure of logic unit 10A is similar to that of logic unit 10A. Figure 10A and Figure 3A The difference lies in that the drain, gate, and source regions of gate transistors T1 and T2 are coupled to power line 20 through a third interconnect structure (third type interconnect structure). For simplicity, the connection characteristics of the source / drain regions of the transistors are omitted. Compared to... Figures 3A-3B The first type of interconnect structure shown connects the drain, gate, and source regions of gate transistors T1 and T2 to power line 20. Figures 7A-7B Another type of interconnect structure is shown, in which the drain, gate, and source regions of gate transistors T1 and T2 are connected to the power line 20. Figures 10A-10B This invention illustrates yet another connection path or method for connecting the drain, gate, and source regions of gate transistors T1 and T2 to the power line 20, which can also be referred to as a third type of interconnect structure. Therefore, in this invention, different connection paths or methods can be freely selected according to wiring requirements or design specifications, improving design flexibility.

[0096] Figure 10B The semiconductor structure of the logic cell 10G according to some embodiments of the present invention is shown along... Figure 10A Please refer to the cross-sectional view of line E-EE. Figure 10A and Figure 10BThe gate structure 210e of the gate transistor T1 is connected to the metal line 240a via connection feature 235a, and the gate structure 210f of the gate transistor T2 is coupled to the metal line 240b via connection feature 235b. The metal line 240a extends in the X direction between the isolation structure 215a and the gate structure 210a, while the metal line 240b extends in the X direction between the isolation structure 215b and the gate structure 210d. The source region 205a of the gate transistor T1 is connected to the metal line 240a via connection features 220a and 230j, and the drain region 205b of the gate transistor T1 is connected to the metal line 240a via connection features 220b and 230h. Furthermore, the source region 205g of the gate transistor T2 is connected to the metal line 240b via connection features 220g and 230k, and the drain region 205f of the gate transistor T2 is connected to the metal line 240b via connection features 220f and 230i. Therefore, the drain, gate, and source regions of the gate transistor T1 are connected to the power supply line 20 via a third-type interconnect structure 50G_1 formed by metal line 240a and corresponding connection features. The drain, gate, and source regions of the gate transistor T2 are coupled to the power supply line 20 via a third-type interconnect structure 50G_2 formed by metal line 240b and corresponding connection features.

[0097] In some embodiments, the third type interconnect structures 50G_1 and 50G_2 are mirrored in the X direction. In some embodiments, the space or spacing between connection features 230b, 230j, 230i, and 230k and connection features 235a and 235b is determined according to process rules.

[0098] Figure 11 A simplified diagram illustrating a logic cell 10H according to some embodiments of the present invention is shown. The outer boundary of the logic cell 10H is indicated by dashed lines. The semiconductor structure of the logic cell 10H is... Figure 10A The semiconductor structure of the logic unit 10G is similar, and Figure 11 and Figure 10A The difference is that logic unit 10H includes more gate transistors T1_1 to T1_3 and more gate transistors T2_1 to T2_3.

[0099] exist Figure 11In this configuration, extended metal lines (extended metal lines) 240a are connected to gate structures 210e_1 to 210e_3 via connection features 235a_1 to 235a_3, respectively. Extended metal lines 240b are connected to gate structures 210f_1 to 210f_3 of gate transistors T2_1 to T2_3 via connection features 235b_1 to 235b_3, respectively. Furthermore, extended metal lines 240a are also connected to the source / drain regions of gate transistors T1_1 to T1_3 via connection features 230j_1 to 230j_3 and 230h. Extended metal lines 240b are also coupled to the source / drain regions of gate transistors T2_1 to T2_3 via connection features 230k_1 to 230k_3 and 230i.

[0100] Logic cell 10H can provide the specific logic functions of logic cell 10G with a smaller cell delay because the distance between P-type transistor P1 and isolation structure 215a and the distance between P-type transistor P4 and isolation structure 215b are increased. Therefore, it is more effective to avoid the diffusion damage stress at the left and right edges of the active region 110 from reducing the saturation drain current (Idsat) of the transistors in logic cell 10H, especially the saturation drain current of P-type transistors P1 and P4.

[0101] Figure 12 A simplified diagram illustrating a logic cell 10I according to some embodiments of the present invention is shown. The outer boundary of the logic cell 10I is shown using dashed lines. The semiconductor structure of the logic cell 10I is similar to... Figure 10A The logic unit has a 10G semiconductor structure, and Figure 12 and Figure 10A The difference is that logic unit 10I also includes connection gate transistors T3 and T4 above the active region 120.

[0102] exist Figure 12 In this configuration, the drain, gate, and source regions of gate transistor T3 are coupled to ground line 30 via a third-type interconnect structure 50G_3. Similarly, the drain, gate, and source regions of gate transistor T4 are coupled to ground line 30 via a third-type interconnect structure 50G_4. Therefore, each of gate transistors T3 and T4 forms a dummy N-type transistor, with its source and drain regions both coupled to its gate. In some embodiments, the third-type interconnect structures 50G_1 and 50G_3 are mirror images in the X-direction, and the third-type interconnect structures 50G_2 and 50G_4 are mirror images in the X-direction.

[0103] Logic cell 10I is able to provide the specific logic functions of logic cell 10G with a smaller cell delay because it uses more gate-connecting transistors (e.g., transistors T3 and T4). Therefore, it is more likely to avoid the diffusion destructive stress at the left and right edges of the active regions 110 and 120 from reducing the saturation leakage current (Idsat) of the transistors in logic cell 10I, especially the saturation leakage current of P-type transistors P1 and P4 and N-type transistors N1 and N4.

[0104] Figure 13A A simplified diagram illustrating a logic unit 10J according to some embodiments of the present invention is shown. The outer boundary of the logic unit 10J is indicated by dashed lines. The logic unit 10J is capable of providing similar... Figure 3A The specific logic function of logic unit 10A. The semiconductor structure of logic unit 10J and... Figure 3A The semiconductor structure of logic unit 10A is similar to that of logic unit 10A. Figure 13A and Figure 3A The difference lies in that the drain, gate, and source regions of gate transistors T1 and T2 are coupled to power line 20 via a fourth type of interconnect structure. For simplicity, the connection characteristics of the source / drain regions of the transistors are omitted. Compared to... Figures 3A-3B The first type of interconnect structure shown connects the drain, gate, and source regions of gate transistors T1 and T2 to power line 20. Figures 7A-7B Another type of interconnect structure is shown, in which the drain, gate, and source regions of gate transistors T1 and T2 are connected to the power line 20. Figures 10A-10B The diagram shows a third type of interconnect structure in which the drain, gate, and source regions of gate transistors T1 and T2 are connected to power line 20. Figures 13A-13B This invention illustrates another connection path or method for connecting the drain, gate, and source regions of gate transistors T1 and T2 to power line 20, which can also be referred to as a fourth type of interconnect structure. Therefore, in this invention, different connection paths or methods can be freely selected according to wiring requirements or design specifications, improving design flexibility. In embodiments of this invention, different types of interconnect structures can be used in a single logic unit. For example, a single logic unit can use a first type of interconnect structure, a second type of interconnect structure, a third type of interconnect structure, and so on. For example, in... Figure 10AIn the example shown, the drain, gate, and source regions of gate transistors T1 and T2 are all connected to the power line 20 via a third type of interconnect structure. However, the present invention could be configured such that, for example, the drain, gate, and source regions of gate transistor T1 are connected to the power line 20 via a third type of interconnect structure, and the drain, gate, and source regions of gate transistor T2 are connected to the power line 20 via a first type of interconnect structure. Alternatively, it could be configured such that the drain, gate, and source regions of gate transistor T1 are connected to the power line 20 via a second type of interconnect structure, and the drain, gate, and source regions of gate transistor T2 are connected to the power line 20 via a fourth type of interconnect structure, and so on.

[0105] Therefore, when using the first type of interconnect structure (such as...) Figures 3A-3B As shown), the gate region of the gate transistor T1 is connected to the drain and source regions of the electrically connected gate transistor T1 via connection feature 235a, metal line 240, connection features 230f, 220d, 230c, power line 20, and connection features 230b, 220b, 230a, 220a, etc. The gate region of the gate transistor T2 is connected to the drain and source regions of the electrically connected gate transistor T2 in a similar manner. The connection features 235a, metal line 240, connection features 230f, 220d, 230c, power line 20, and connection features 230b, 220b, 230a, 220a, etc., can be referred to as the first type of interconnection structure. Correspondingly, when using the second type of interconnection structure (such as...) Figures 7A-7B As shown), the gate region of the gate transistor T1 is electrically connected to the drain and source regions of the gate transistor T1 via connection feature 235a, metal line 240a, connection feature 310a, metal line 320a, connection feature 310b, metal line 244a, and connection feature 230h. The gate region of the gate transistor T2 is similarly connected to the drain and source regions of the gate transistor T2. Connection feature 235a, metal line 240a, connection feature 310a, metal line 320a, connection feature 310b, metal line 244a, and connection feature 230h can be referred to as the second type of interconnection structure. Correspondingly, when using a third type of interconnection structure (such as...) Figures 10A-10B As shown), the gate region of the gate transistor T1 is connected to the drain and source regions of the gate transistor T1 via connection feature 235a, metal line 240a, connection feature 230j, 230h, etc., and the gate region of the gate transistor T2 is connected to the drain and source regions of the electrically connected gate transistor T2 in a similar manner; wherein connection feature 235a, metal line 240a, connection feature 230j, 230h, etc. can be referred to as a third type of interconnection structure. Correspondingly, when using a third type of interconnection structure (such as...) Figures 13A-13BAs shown, the gate region of the gate transistor T1 is electrically connected to the drain and source regions of the gate transistor T1 through connection features 330a, 220a, 220b, etc., and the gate region of the gate transistor T2 is connected to the drain and source regions of the gate transistor T2 in a similar manner; among them, connection features 330a, 220a, 220b, etc. can be called the fourth connection structure.

[0106] Therefore, the present invention can be configured such that, for example, the gate region of gate transistor T1 can be electrically connected to the drain and source regions of gate transistor T1 through a first connection structure, and the gate region of gate transistor T2 can be electrically connected to the drain and source regions of gate transistor T2 through a second connection structure. Alternatively, it can be configured such that the gate region of gate transistor T1 can be electrically connected to the drain and source regions of gate transistor T1 through a second connection structure, and the gate region of gate transistor T2 can be electrically connected to the drain and source regions of gate transistor T2 through a third connection structure. Alternatively, the gate region of gate transistor T1 can be electrically connected to the drain and source regions of gate transistor T1 through a fourth connection structure, and the gate region of gate transistor T2 can be electrically connected to the drain and source regions of gate transistor T2 through a third connection structure, and so on, and other methods. Therefore, the method of electrically connecting the gate region of gate transistor T1 to the drain and source regions of gate transistor T1 can be called the first single-connection structure, and the method of electrically connecting the gate region of gate transistor T1 to the drain and source regions of gate transistor T1 can be called the second single-connection structure. The first single-connection structure can be any one of the first, second, third, and fourth connection structures, and the second single-connection structure can also be any one of the first, second, third, and fourth connection structures. The first and second single-connection structures can be the same or different, and the specific design can be modified as needed to meet different wiring and design requirements. The first and second single-connection structures can be the same for ease of manufacturing.

[0107] Figure 13B The semiconductor structure of logic cell 10J according to some embodiments of the present invention is shown. Figure 13A The cross-sectional view of line F-FF in the diagram. Refer to the diagram together. Figure 13A and 13BThe source region 205a of the gate transistor T1 is coupled to the connection feature 220a, and the drain region 205b of the gate transistor T1 is coupled to the connection feature 220b. The gate structure 210e of the gate transistor T1 is coupled to the connection features 220a and 220b via the connection feature 330a extending in the X direction. Furthermore, the source region 205g of the gate transistor T2 is coupled to the connection feature 220g, and the drain region 205f of the gate transistor T2 is coupled to the connection feature 220f. The gate structure 210f of the gate transistor T2 is coupled to the connection features 220f and 220g via the connection feature 330b extending in the X direction. In some embodiments, the connection feature 330a is formed over the connection features 220a and 220b and the gate structure 210e using one or more process steps, and the connection feature 330b is formed over the connection features 220f and 220g and the gate structure 210f. Furthermore, connection feature 330a contacts connection features 220a and 220b and gate structure 210e, and connection feature 330b contacts connection features 220f and 220g and gate structure 210f. Therefore, the drain, gate, and source regions of the gate transistor T1 are coupled to the power line 20 via a fourth type interconnect structure 50J_1 formed by a single connection feature 330a. The drain, gate, and source regions of the gate transistor T2 are coupled to the power line 20 via a fourth type interconnect structure 50J_2 formed by a single connection feature 330b. In some embodiments, the fourth type interconnect structures 50J_1 and 50J_2 are mirror images in the X direction.

[0108] Figure 14 A simplified diagram illustrating a logic cell 10K according to some embodiments of the present invention is shown. The outer boundary of the logic cell 10K is shown using dashed lines. The semiconductor structure of the logic cell 10K is similar to... Figure 13A The logic unit 10J has a semiconductor structure, and Figure 14 and Figure 13A The difference is that logic cell 10K includes more gate-connecting transistors T1_1 to T1_3 and more gate-connecting transistors T2_1 to T2_3.

[0109] exist Figure 14 In the process, the extended connection feature 330a is coupled to the gate structures 210e_1 to 210e_3 and the corresponding source / drain regions of the gate transistors T1_1 to T1_3. The extended metal line 330b is connected to the gate structures 210f_1 to 210f_3 and the corresponding source / drain regions of the gate transistors T2_1 to T2_3.

[0110] With the increased distance between P-type transistor P1 and isolation structure 215a, and between P-type transistor P4 and isolation structure 215b, logic cell 10K can provide the specific logic functions of logic cell 10G with a smaller cell delay. Therefore, it is more effective to avoid the diffusion-induced destructive stress at the edges of the active region 110 reducing the saturation drain current (Idsat) of the transistors in logic cell 10K, especially the saturation drain currents of P-type transistors P1 and P4.

[0111] Figure 15 A simplified diagram illustrating a logic cell 10L according to some embodiments of the present invention is shown. The outer boundary of the logic cell 10L is shown using dashed lines. The semiconductor structure of the logic cell 10L is similar to... Figure 13A The logic unit 10J has a semiconductor structure, and Figure 15 and Figure 13A The difference is that the logic unit 10L also includes the connection gate transistors T3 and T4 above the active region 120.

[0112] exist Figure 15 In this configuration, the drain, gate, and source regions of gate transistor T3 are coupled to ground line 30 via a fourth-type interconnect structure 50J_3. Similarly, the drain, gate, and source regions of gate transistor T4 are coupled to ground line 30 via a fourth-type interconnect structure 50J_4. Therefore, each of gate transistors T3 and T4 forms a dummy N-type transistor, with its source and drain regions both coupled to its gate. In some embodiments, the fourth-type interconnect structures 50J_1 and 50J_3 are mirror images in the X-direction, and the fourth-type interconnect structures 50J_2 and 50J_4 are mirror images in the X-direction.

[0113] Because more gate-connecting transistors (e.g., transistors T3 and T4) are used, logic cell 10L is able to provide the specific logic functions of logic cell 10J with a smaller cell delay. Therefore, the diffusion-induced destructive stress at the edges of the active regions 110 and 120 is less likely to reduce the saturation drain current (Idsat) of the transistors in logic cell 10L, especially the saturation drain currents of P-type transistors P1 and P4 and N-type transistors N1 and N4.

[0114] Figure 16 A simplified diagram illustrating a logic unit 10M according to some embodiments of the present invention is shown. The outer boundary of the logic unit 10M is shown using dashed lines. The logic unit 10M is capable of providing similar... Figure 3A The specific logic function of logic unit 10A. The semiconductor structure of logic unit 10M and... Figure 3A The semiconductor structure of the logic unit 10A is similar, while Figure 16 and Figure 3AThe difference lies in that gate structures 210e and 210f are replaced by gate structures 210g and 210h, respectively.

[0115] Gate structures 210g and 210h extending along the Y direction form the gate transistors T1 and T2 in the active region 110 of the N-type well region NW. Furthermore, gate structures 210g and 210h extending along the Y direction form transistors C1 and C2 in the active region 120 of the P-type well region PW. It should be noted that gate structures 210g and 210h, as well as gate structures 210a to 210d, have the same length (e.g., equal to the cell height H1). For simplicity, the connection features of the source / drain regions of the transistors are omitted. In this embodiment, transistor C1 shares gate structure 210g with transistor T1, N-type transistor N1 shares gate structure 210a with P-type transistor P1, N-type transistor N2 shares gate structure 210b with P-type transistor P2, and transistor C2 shares gate structure 210h with transistor T2. Therefore, each N-type transistor shares a gate structure with its corresponding P-type transistor.

[0116] and Figure 3A Compared to the gate structures 210e and 210f of logic cell 10A, gate structures 210g and 210h extend in the Y direction and reach above the P-type well region PW. Therefore, logic cell 10M also includes transistors C1 and C2. Each of transistors C1 and C2 is a dummy N-type transistor, with both its source and drain regions coupled to ground line 30. Furthermore, gate structures 210g and 210h are coupled to power line 20 via a first-type interconnect structure formed by metal lines 240 and corresponding connection features (e.g., 235a and 235b). Therefore, each of transistors C1 and C2 acts as a capacitor (e.g., a decoupling capacitor or bypass capacitor) between power line 20 and ground line 30, thereby providing a more stable power supply and reducing noise for logic cell 10M.

[0117] Figure 17 A simplified diagram illustrating a logic cell 10N according to some embodiments of the present invention is shown. The outer boundary of the logic cell 10N is indicated by dashed lines. The semiconductor structure of the logic cell 10N is similar to... Figure 16 The logic unit has a 10M semiconductor structure, and Figure 17 and Figure 16 The difference is that the logic unit 10N includes more gate-connecting transistors T1_1 to T1_3 and more gate-connecting transistors T2_1 to T2_3, as well as more transistors C1_1 to C1_3 and more transistors C2_1 to C2_3.

[0118] exist Figure 17In this embodiment, gate structures 210g_1 to 210g_3 are disposed between gate structure 210a and isolation structure 215a, and gate structures 210h_1 to 210h_3 are disposed between gate structure 210d and isolation structure 215b. Furthermore, extended metal lines 240 are coupled to gate structures 210g_1 to 210g_3 and 210h_1 to 210h_3 respectively via corresponding connection features 235a_1 to 235a_3 and 235b_1 to 235b_3. It should be noted that the number of gate structures 210g_1 to 210g_3 and 210h_1 to 210h_3 is merely an example and is not intended to limit the invention.

[0119] Due to the increased distance between P-type transistor P1 and isolation structure 215a, and between P-type transistor P4 and isolation structure 215b, logic cell 10N can provide the specific logic functions of logic cell 10M with a smaller cell delay. Therefore, the diffusion-induced destructive stress at the edges of the active regions 110 and 120 is better avoided, which would reduce the saturation drain current (Idsat) of the transistors in logic cell 10N, especially the saturation drain currents of P-type transistors P1 and P4 and N-type transistors N1 and N4.

[0120] Figure 18 A simplified diagram illustrating a group logic unit 10_GP1 according to some embodiments of the present invention is shown. Figure 18 In this configuration, logic unit 10_4 includes a P-type transistor P41 and an N-type transistor N41 configured to perform a fourth logic function. A gate structure 210_11 extending along the Y direction forms the P-type transistor P41 in the active region 110_4 of the N-type well region NW and the N-type transistor N41 in the active region 120_4 of the P-type well region PW. Logic unit 10_5 includes P-type transistors P51 and P52 and N-type transistors N51 and N52 for performing a fifth logic function. Gate structures 210_12 and 210_13 extending along the Y direction form P-type transistors P51 and P52 in the active region 110_5 of the N-type well region NW and N-type transistors N51 and N52 in the active region 120_5 of the P-type well region PW. In some embodiments, the fourth logic function is the same as the fifth logic function. In some embodiments, the fourth logic function is different from the fifth logic function.

[0121] In logic cell 10_4, isolation structures 215_5 and 215_6 are formed within the boundary of logic cell 10_4 to define active regions 110_4 and 120_4. In logic cell 10_5, isolation structures 215_7 and 215_8 are formed within the boundary of logic cell 10_5 to define active regions 110_5 and 120_5. Active regions 110_4 and 120_4 are separate from active regions 110_5 and 120_5.

[0122] exist Figure 18 In this configuration, logic cells 10_4 and all logic cells 10_5 are merged into group logic cell 10_GP1. Group logic cell 10_GP1 provides fourth and fifth logic functions with relatively small cell delays. Group logic cell 10_GP1 is arranged between power line 20 and ground line 30 and has a cell height H1. Furthermore, the outer boundary of group logic cell 10_GP1 is shown using dashed lines.

[0123] The grouped logic unit 10_GP1 is divided into a first sub-unit GP1_1 and a second sub-unit GP1_2. In the first sub-unit GP1_1, the gate structure 210i extending along the Y direction forms a P-type transistor P5 in the active region 110 and an N-type transistor N5 in the active region 120. The P-type transistor P5 and the N-type transistor N5 are used to perform a fourth function. In other words, the first sub-unit GP1_1 serves as logic unit 10_4. In the second sub-unit GP1_2, the gate structures 210k and 210l extending along the Y direction form P-type transistors P6 and P7 in the active region 110 and N-type transistors N6 and N7 in the active region 120. The P-type transistors P6 and P7 and the N-type transistors N6 and N7 are configured to perform a fifth logic function. In other words, the second sub-unit GP1_2 serves as logic unit 10_5.

[0124] In the grouped logic unit 10_GP1, gate structures 210j and 210m extending in the Y direction are arranged between gate structures 210i and 210k. Furthermore, gate structures 210j and 210m are located at the interface between the first sub-unit GP1_1 and the second sub-unit GP1_2. The lengths of gate structures 210j and 210m are shorter than the lengths of gate structures 210i, 210k, and 210l.

[0125] Gate structure 210m forms a P-type transistor B1 in active region 110, and gate structure 210j forms an N-type transistor B2 in active region 120. In the grouped logic unit 10_GP1, the source regions of P-type transistor B1 and P-type transistor P6 share a common source / drain region, and the source regions of P-type transistor B1 and P-type transistor P5 share a common source / drain region. Further, the drain regions of N-type transistor B2 and N-type transistor N6 share a common source / drain region, and the source regions of N-type transistor B2 and N-type transistor N5 share a common source / drain region. In some embodiments, the source and drain regions of P-type transistor B1 are connected to power line 20. In some embodiments, the source and drain regions of N-type transistor B2 are connected to ground line 30. As described above, gate structures 210i to 210l are arranged between isolation structures 215a and 215b with a fixed spacing PH.

[0126] In some embodiments, the gate structure 210m is coupled to the power line 20 via the connection feature 235e. Therefore, the P-type transistor B1 is a dummy transistor whose source and drain regions are both coupled to its gate, meaning that the P-type transistor B1 is independent of the fourth and fifth logic functions.

[0127] In some embodiments, the gate structure 210j is coupled to the ground line 30 via the connection feature 235f. Therefore, the N-type transistor B2 is a dummy transistor whose source and drain regions are both coupled to its gate, meaning that the N-type transistor B2 is independent of the fourth and fifth logic functions.

[0128] Because the distance between P-type transistor P5 and isolation structure 215b is increased (compared to the distance between P-type transistor P41 and isolation structure 215_6), the first sub-unit GP1_1 in the group logic unit 10_GP1 can provide the fourth logic function of logic unit 10_4 with a smaller unit delay. Similarly, because the distance between P-type transistor P6 and isolation structure 215a is increased (compared to the distance between P-type transistor P51 and isolation structure 215_7), the second sub-unit GP1_2 in the group logic unit 10_GP1 can provide the fifth logic function of logic unit 10_5 with a smaller unit delay. It should be noted that the number of sub-units in the group logic unit 10_GP1 is used as an example and is not intended to limit the invention.

[0129] Figure 19 A simplified diagram illustrating a group logic unit 10_GP2 according to some embodiments of the present invention is shown. The outer boundary of the group logic unit 10_GP2 is shown using dashed lines. The semiconductor structure of the group logic unit 10_GP2 is similar to... Figure 18 The semiconductor structure of the group logic unit 10_GP1, Figure 19 and Figure 18 The difference is that the group logic unit 10_GP2 also includes the gate connection transistor T1 in the first sub-unit GP2_1 and the gate connection transistor T2 in the second sub-unit GP2_2.

[0130] exist Figure 19 In the active region 110, the gate structure 210e extending along the Y direction forms the gate transistor T1, and the gate structure 210f extending along the Y direction forms the gate transistor T2. It should be noted that gate structures 210e and 210f only extend above the N-type well region NW, and not above the P-type well region PW. Therefore, gate structures 210e and 210f are shorter than gate structures 210i, 210k, and 210l.

[0131] Furthermore, a dielectric substrate gate structure 217a extending in the Y direction is disposed between the gate structure 210i and the isolation structure 215a, and above the active region 120. Additionally, a dielectric base gate structure 217b extending in the Y direction is disposed between the gate structure 210i and the isolation structure 215b, and above the active region 120. It should be noted that the dielectric base gate structures 217a and 217b only extend above the P-type well region PW, and not above the N-type well region NW. Therefore, the dielectric base gate structures 217a and 217b are shorter than the gate structures 210i, 210k, and 210i.

[0132] exist Figure 19 In this configuration, the drain, gate, and source regions of gate transistors T1 and T2 are coupled to power line 20 via a first-type interconnect structure formed by metal line 240 and corresponding interconnect features (e.g., interconnect features 235a, 235b, and 230f). In some embodiments, N-type gate transistors (e.g., N-type gate transistors) can be used in the group logic unit 10_GP2. Figure 6 (connecting gate transistors T3 and T4). In some embodiments, such as Figure 16 As shown, the group logic unit 10_GP2 also includes transistors C1 and C2 in the active region 120. In some embodiments, by inserting more connection gate transistors (e.g., between the gate structure 210e and the isolation structure 215a and between the gate structure 210f and the isolation structure 215b) Figure 4 The group logic unit 10_GP2 (connecting gate transistors T1_1 to T1_3 and connecting gate transistors T2_1 to T2_3) can provide fourth and fifth logic functions with smaller cell delays.

[0133] In some embodiments, the drain region, gate region, and source region of the gate transistors T1 and T2 are coupled to the power line 20 via a second type of interconnect structure, such as... Figure 7A , 7B As shown in 8 and 9.

[0134] In some embodiments, the drain region, gate region, and source region of the gate transistors T1 and T2 are coupled to the power line 20 via a third type of interconnect structure, such as... Figure 10A , 10B As shown in 11 and 12.

[0135] In some embodiments, the drain region, gate region, and source region of the gate transistors T1 and T2 are coupled to the power line 20 via a fourth type of interconnect structure, such as... Figure 13A , 13B As shown in 14 and 15.

[0136] Figure 20A simplified diagram illustrating a group logic unit 10_GP3 according to some embodiments of the present invention is shown. Figure 20 In this diagram, logic units 10_4 and 10_5 are combined into a grouped logic unit 10_GP3. Grouped logic unit 10_GP3 provides fourth and fifth logic functions with small cell delays. Furthermore, the outer boundary of grouped logic unit 10_GP3 is shown using dashed lines.

[0137] The grouped logic unit 10_GP3 is divided into a first subunit GP3_1 and a second subunit GP3_2. The first subunit GP3_1 includes a P-type transistor P5 and an N-type transistor N5, and serves as logic unit 10_4. The second subunit GP3_2 includes P-type transistors P6 and P7 and N-type transistors N6 and N7, and serves as logic unit 10_5.

[0138] The semiconductor structure of the group logic unit 10_GP3 is similar to Figure 18 The semiconductor structure of the group logic unit 10_GP1, Figure 20 and Figure 18 The difference is that the group logic unit 10_GP3 does not include the gate structure 210j (e.g. Figure 18 (As shown). P-type transistors P5 and P6 share a common source / drain region, and N-type transistors N5 and N6 also share a common source / drain region. Therefore, with... Figure 18 Compared to the packet logic unit 10_GP1, the packet logic unit 10_GP3 has a smaller area. It should be noted that the number of sub-units in the packet logic unit 10_GP3 is used as an example and is not intended to limit the invention. Specifically, as... Figure 18 As shown, when logic units 10_4 and 10_5 are combined, the electrode polarity of the source / drain region (source / drain regions of P-type transistor P41 and N-type transistor N41) of logic unit 10_4 near the isolation structure 215_6 is opposite to the electrode polarity of the source / drain region (source / drain regions of P-type transistor P51 and N-type transistor N51) of logic unit 10_5 near the isolation structure 215_7. For example, if the source region (source region of P-type transistor P41 and N-type transistor N41) of logic unit 10_4 near the isolation structure 215_6, then the drain region (drain region of P-type transistor P51 and N-type transistor N51) of logic unit 10_5 near the isolation structure 215_7. Figure 18In the example shown, after merging logic cells 10_4 and 10_5, isolation structures 215_6 and 215_7 are replaced by gate structures 210m and 210j. Therefore, the merged grouped logic cell 10_GP1 can reduce the negative impact of isolation structures 215_6 and 215_7 on transistors P5, N5, P6, N6, P7, and N7. Furthermore, in one embodiment, after merging logic cells 10_4 and 10_5, the position of gate structure 210j can still be occupied by the same material as the isolation structures (isolation structures 215_6 / 215_7). This is because the isolation structures have almost no negative impact on NMOS transistors, so the formation of gate structure 210j can be omitted. Figure 18 The examples shown are different, in Figure 20 In the example shown, when logic unit 10_4 and logic unit 10_5 are combined, the electrode polarity of the source / drain region of logic unit 10_4 near the isolation structure 215_6 is the same as the electrode polarity of the source / drain region of logic unit 10_5 near the isolation structure 215_7. For example, if the source region is on the side of logic unit 10_4 near the isolation structure 215_6, then the source region is also on the side of logic unit 10_5 near the isolation structure 215_7. Figure 20 In the example shown, after merging logic unit 10_4 and logic unit 10_5, isolation structures 215_6 and 215_7 are removed. Therefore, the merged grouped logic unit 10_GP1 can reduce the negative impact of isolation structures 215_6 and 215_7 on transistors P5, N5, P6, N6, P7, and N7.

[0139] Figure 21 A simplified diagram illustrating a group logic unit 10_GP4 according to some embodiments of the present invention is shown. The outer boundary of the group logic unit 10_GP4 is shown using dashed lines. The semiconductor structure of the group logic unit 10_GP4 is similar to... Figure 20 The semiconductor structure of the group logic unit 10_GP3 is similar. Figure 21 and Figure 20 The difference is that the group logic unit 10_GP4 also includes the gate connection transistor T1 in the first sub-unit GP4_1 and the gate connection transistor T2 in the second sub-unit GP4_2.

[0140] exist Figure 21 In this configuration, the drain, gate, and source regions of gate transistors T1 and T2 are coupled to power line 20 via a first-type interconnect structure formed by metal line 240 and corresponding interconnect features (e.g., interconnect features 235a, 235b, and 230f). In some embodiments, N-type gate transistors (e.g., N-type gate transistors) can be used in the group logic unit 10_GP4. Figure 6 (Connecting gate transistors T3 and T4). In some embodiments, the group logic unit 10_GP4 also includes transistors C1 and C2 in the active region 120, such as... Figure 16 As shown. In some embodiments, by inserting more connection gate transistors (e.g., between gate structure 210e and isolation structure 215a and between gate structure 210f and isolation structure 215b) Figure 4 The group logic unit 10_GP4 (which connects gate transistors T1_1 to T1_3 and gate transistors T2_1 to T2_3) can provide fourth and fifth logic functions with smaller cell delays.

[0141] In some embodiments, the drain region, gate region, and source region of the gate transistors T1 and T2 are coupled to the power line 20 through a second type of interconnect structure, such as... Figure 7A , 7B As shown in 8 and 9.

[0142] In some embodiments, the drain, gate, and source regions of gate transistors T1 and T2 are coupled to power line 20 via a third (type) interconnect structure, such as... Figure 10A , 10B As shown in 11 and 12.

[0143] In some embodiments, the drain region, gate region, and source region of the gate transistors T1 and T2 are coupled to the power line 20 via a fourth type of interconnect structure, such as... Figure 13A , 13B As shown in 14 and 15.

[0144] In this embodiment, a semiconductor structure for logic cells that reduces latency is provided. By inserting a connection gate transistor at the boundary of the logic cell requiring high-speed operation, the diffusion edge is extended to alleviate diffusion breakage stress. Therefore, the saturation drain current (Idsat) of the transistors in the logic cell (e.g., the transistor between the two connection gate transistors) does not decrease, thereby improving the operation or running speed of the logic cell.

[0145] Those skilled in the art will readily observe that numerous modifications and alterations can be made to the apparatus and method while maintaining the teachings of this invention. Therefore, the foregoing disclosure should be interpreted as being limited only by the scope and limits of the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: Semiconductor substrate; as well as A logic unit, having a logic function, includes: a plurality of first transistors in a first active region above a semiconductor substrate, each of the plurality of first transistors including a first gate electrode extending along a first direction; a second transistor located in the first active region and including a second gate electrode extending along the first direction; a third transistor located in the first active region and including a third gate electrode extending along the first direction; and a first isolation structure and a second isolation structure located at opposite edges of the first active region and extending along the first direction. The first gate electrode is disposed between the first isolation structure and the second isolation structure, the second gate electrode is disposed between the first gate electrode and the first isolation structure, and the third gate electrode is disposed between the first gate electrode and the second isolation structure. The first isolation structure, the second isolation structure, and the first gate electrode have a first length in the first direction, and the second gate electrode and the third gate electrode have a second length in the first direction, wherein the second length is shorter than the first length; The first transistor is used to perform logic functions. The second and third transistors are dummy transistors. The drain, source, and gate of the second and third transistors are coupled to a VDD power line extending along a second direction, which is perpendicular to the first direction.

2. The semiconductor structure as described in claim 1, characterized in that, Also includes: The fourth transistor, located in the second active region above the semiconductor substrate, includes a fourth gate electrode extending along the first direction; The fifth transistor, located in the second active region above the semiconductor substrate, includes a fifth gate electrode extending along the first direction; The fourth and fifth transistors are dummy transistors, and the fourth and fifth gate electrodes are dielectric substrate gate structures or electrically connected to the ground line.

3. The semiconductor structure as described in claim 1, characterized in that, The second gate electrode and the third gate electrode are coupled to the source region of one of the plurality of first transistors via the same metal line extending along a second direction, and the second direction is perpendicular to the first direction.

4. The semiconductor structure as described in claim 1, characterized in that, The source and drain regions of the second transistor are coupled to a first metal line extending along a second direction, and the first metal line is coupled to the second gate electrode through a second metal line extending in the first direction and a third metal line extending in the second direction, wherein the second direction is perpendicular to the first direction, and the first metal line and the third metal line are formed in the same metal layer below the second metal line.

5. The semiconductor structure as described in claim 1, characterized in that, The second gate electrode is connected to the drain and source regions of the second transistor via a first metal line extending along the second direction between the first isolation structure and the first gate electrode, and the third gate electrode is coupled to the drain and source regions of the third transistor via a second metal line extending along the second direction between the second isolation structure and the first gate electrode, wherein the second direction is perpendicular to the first direction.

6. The semiconductor structure as described in claim 1, characterized in that, The second gate electrode is coupled to the drain and source regions of the second transistor through a first single-connection structure, and the third gate electrode is coupled to the drain and source regions of the third transistor through a second single-connection structure.

7. The semiconductor structure as described in claim 1, characterized in that, The first isolation structure, the second gate electrode, the third gate electrode, and the second isolation structure are arranged sequentially at a fixed interval.

8. A semiconductor structure, characterized in that, include: Semiconductor substrate; as well as A logic unit having a first logic function and a second logic function includes: at least one first transistor in an active region above a semiconductor substrate, including a first gate electrode extending along a first direction, wherein the first transistor is configured to perform the first logic function; at least one second transistor in the active region, including a second gate electrode extending along the first direction, wherein the second transistor is configured to perform the second logic function; a first isolation structure disposed at a first edge of the active region and extending along the first direction; and a second isolation structure disposed at a second edge of the active region and extending along the first direction. The first gate electrode is disposed between the first isolation structure and the second gate electrode, and the second gate electrode is disposed between the first gate electrode and the second isolation structure. The first edge of the active region is disposed opposite to the second edge of the active region; the logic unit further includes: The first dummy transistor, in the active region, includes a fourth gate electrode extending along the first direction; and The second dummy transistor includes a fifth gate electrode extending along the first direction in the active region. The fourth gate electrode is disposed between the first isolation structure and the first gate electrode, and the fifth gate electrode is disposed between the second isolation structure and the second gate electrode. The fourth gate electrode and the fifth gate electrode are shorter than the first gate electrode and the second gate electrode in the first direction.

9. The semiconductor structure as described in claim 8, characterized in that, This logic unit also includes: The third transistor, in the active region, includes a third gate electrode extending along the first direction. The first gate electrode and the second gate electrode are separated by the third gate electrode. The third transistor is a virtual transistor that is independent of the first logic function and the second logic function. The third gate electrode is shorter than the first gate electrode and the second gate electrode in the first direction.

10. The semiconductor structure as described in claim 8, characterized in that, The first transistor and the second transistor share a common source region.

11. The semiconductor structure as described in claim 8, characterized in that, The first isolation structure, the first gate electrode, the second gate electrode, and the second isolation structure are arranged sequentially at a fixed interval, wherein the first isolation structure, the first gate electrode, the second gate electrode, and the second isolation structure have the same length.

12. The semiconductor structure as described in claim 8, characterized in that, The fourth gate electrode and the fifth gate electrode are connected to the source region of the first transistor or the second transistor via the same metal line extending along a second direction, and the second direction is perpendicular to the first direction.

13. The semiconductor structure as described in claim 8, characterized in that, The source and drain regions of the first dummy transistor are connected to a first metal line extending along a second direction, and the first metal line is connected to the fourth gate electrode via a second metal line extending in the first direction and a third metal line extending in the second direction, wherein the second direction is perpendicular to the first direction, and the first metal line and the third metal line are formed in the same metal layer below the second metal line.

14. The semiconductor structure as claimed in claim 8, characterized in that, The fourth gate electrode is connected to the drain and source regions of the first dummy transistor via a first metal line extending in a second direction between the first isolation structure and the first gate electrode. The fifth gate electrode is coupled to the drain and source regions of the second dummy transistor via a second metal line extending in a second direction between the second isolation structure and the second gate electrode, wherein the second direction is perpendicular to the first direction.

15. The semiconductor structure as described in claim 8, characterized in that, The fourth gate electrode is connected to the drain and source regions of the first dummy transistor via a first single-connection structure, and the fifth gate electrode is connected to the drain and source regions of the second dummy transistor via a second single-connection structure, wherein the second direction is perpendicular to the first direction.

16. A semiconductor structure, characterized in that, include: Semiconductor substrate; as well as A logic unit, having logic functions, includes: a plurality of P-type transistors located in a first active region above the semiconductor substrate, each of the plurality of P-type transistors including a first gate electrode extending along a first direction; a plurality of N-type transistors located in a second active region above the semiconductor substrate, wherein each of the plurality of N-type transistors shares a first gate electrode with its respective P-type transistor; a first isolation structure and a second isolation structure located at opposite edges of the first active region and opposite edges of the second active region, and extending along the first direction; and a first transistor located in the first active region and between the first isolation structure and the P-type transistor. The transistor includes a second gate extending along the first direction; a second transistor located in the first active region and between the second isolation structure and the P-type transistor, including a third gate electrode extending along the first direction; a third transistor located in the second active region and between the first isolation structure and the N-type transistor, wherein the first transistor and the third transistor share a second gate; and a fourth transistor located in the second active region and between the second isolation structure and the N-type transistor, wherein the second transistor and the fourth transistor share a third gate electrode, wherein the P-type transistor and the N-type transistor are used to perform logic functions; Each of the first transistor and the second transistor is a dummy transistor, and the second gate electrode, drain region and source region of the first transistor and the third gate electrode, drain region and source region of the second transistor are all coupled to a VDD power line extending in a second direction, wherein the second direction is perpendicular to the first direction. The drain and source regions of the third and fourth transistors are coupled to a ground line extending in the second direction, such that each of the third and fourth transistors acts as a capacitor between the power line and the ground line.

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