Decoupling capacitor for semiconductor devices

Abstract

Systems, methods, and apparatus, including computer programs encoded on a computer storage medium, for decoupling capacitors for semiconductor devices are provided. An embodiment provides that the decoupling capacitors are electrically coupled to a power bus.

Description

Technical Field

[0001] This disclosure generally relates to memory devices, and more specifically, to decoupling capacitors for semiconductor devices. Background Technology

[0002] Memory is commonly implemented in electronic systems such as computers, mobile phones, and handheld devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory requires power to maintain its data and can include random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), and synchronous dynamic random access memory (SDRAM). Non-volatile memory provides permanent data by retaining the stored data when no power is supplied and can include NAND flash memory, NOR flash memory, nitride read-only memory (NROM), phase-change memory (e.g., phase-change random access memory), resistive memory (e.g., resistive random access memory), crosspoint memory, ferroelectric random access memory (FeRAM), or the like.

[0003] Memory devices can be used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information can be stored by programming different states of the memory device. For example, a binary memory device can store one of two states typically represented by logic 1 or logic 0. In other devices, more than two states can be stored. To access the stored information, components of the device can read or sense at least one stored state in the memory device. To access information, components of the device can write to or program the states in the memory device. Summary of the Invention

[0004] In one aspect, this disclosure relates to a memory device including a decoupling capacitor, the memory device comprising: a vertically stacked array of memory cells having horizontally oriented access lines and vertically oriented digital lines, including: memory capacitor access means coupled to a respective memory capacitor; horizontally oriented access lines coupled to the gate of the memory capacitor access means; vertically oriented digital lines coupled to the memory capacitor access means; and a decoupling capacitor coupled to a power bus, wherein the decoupling capacitor is vertically separated from the memory capacitors.

[0005] In another aspect, this disclosure relates to a memory device including a decoupling capacitor, the memory device comprising: a vertically stacked array of memory cells having vertically oriented access lines and horizontally oriented digital lines, comprising: memory capacitor access means coupled to corresponding memory capacitors; vertically oriented access lines coupled to the gates of the memory capacitor access means; horizontally oriented digital lines electrically coupled to the memory capacitor access means; decoupling capacitors horizontally separated from memory capacitors in the same layer; and a power bus, wherein the decoupling capacitors are electrically coupled to the power bus.

[0006] In another aspect, this disclosure relates to a method for forming a decoupling capacitor for a vertically stacked array of memory cells, the method comprising: forming a first vertical layer and a second vertical layer, wherein each of the first vertical layer and the second vertical layer includes a corresponding memory cell containing a storage capacitor; forming a third vertical layer, wherein the third vertical layer includes a corresponding memory cell containing a decoupling capacitor; and forming a power bus, wherein the power bus is electrically coupled to the memory cells on the third layer via conductive vertical lines.

[0007] In another aspect, this disclosure relates to a method for forming a decoupling capacitor for a vertically stacked array of memory cells, the method comprising: forming a plurality of vertical layers, each of said plurality of vertical layers including a respective memory cell containing a storage capacitor and a respective memory cell containing a decoupling capacitor; and forming a power bus, wherein said power bus is electrically coupled to the memory cell containing the decoupling capacitor via a respective horizontal digital line. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of a portion of a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0009] Figure 2 This is a diagram of a portion of a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0010] Figure 3 This is a diagram of a portion of a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0011] Figure 4 This is a diagram of a portion of the unit cells according to several embodiments of the present disclosure.

[0012] Figure 5 This is a cross-sectional view of a portion of a semiconductor device according to several embodiments of the present disclosure.

[0013] Figure 6 This is a block diagram of an apparatus according to several embodiments of the present disclosure. Detailed Implementation

[0014] Embodiments of this disclosure describe decoupling capacitors for semiconductor devices. Semiconductor devices include several conductive paths that can be used to distribute power. In some examples, the voltage along a conductive path may drop (e.g., decrease or diminish) in response to the voltage or current demand of individual components of the semiconductor device. If a conductive path experiences a relatively large drop, the conductive path may not be able to provide sufficient voltage or current to the components of the semiconductor device to enable proper operation. The decoupling capacitors disclosed herein can be coupled to a power bus to help reduce or eliminate the drop and help maintain voltage across a range of operating conditions. For example, the decoupling capacitor can advantageously provide additional charge (e.g., voltage) to the power bus during periods of high demand. This can provide improved operating characteristics for the semiconductor device.

[0015] The figures in this document follow a numbering convention, where the first few digits correspond to the figure number and the remaining digits identify the elements or components within the figure. Similar elements or components between different figures can be identified by using similar digits. For example, reference digit 103 may refer to... Figure 1 Component "03" in the text, and similar components in Figure 2 The element may be referred to as 203. Multiple similar elements within a figure may be designated by a reference numeral followed by a hyphen and another number or letter. Such similar elements may be generally referred to without hyphens and additional numbers or letters. For example, elements 103-1 and 103-2 or other similar elements may be generally referred to as 103. It should be understood that the elements shown in the various embodiments herein may be added, interchanged, and / or eliminated to provide several additional embodiments of this disclosure. Furthermore, it should be understood that the scale and relative dimensions of the elements provided in the figures are intended to illustrate embodiments of this disclosure and should not be considered as intended to be limiting.

[0016] Figure 1 This is a schematic diagram of a portion of a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure. Figure 1 The illustration shows a circuit diagram of a cell array of a portion of a three-dimensional (3D) semiconductor memory device according to an embodiment of the present disclosure. Figure 1The cell array can have multiple sub-cell arrays 101-1, 101-2, ..., 101-N. Sub-cell arrays 101-1, 101-2, ..., 101-N can have various configurations. For example, sub-cell arrays 101-1, 101-2, ..., 101-N can be arranged along a second direction (D2) 105. Each of the sub-cell arrays (e.g., sub-cell array 101-2) can contain multiple access lines 107-1, 107-2, ..., 107-Q (which may also be called word lines). Furthermore, each of the sub-cell arrays (e.g., sub-cell array 101-2) can contain multiple digital lines 103-1, 103-2, ..., 103-Q (which may also be called bit lines, data lines, or sensing lines). Figure 1 In this embodiment, access lines 107-1, 107-2, ..., 107-Q are described as extending in a first direction (D1) 109 and digital lines 103-1, 103-2, ..., 103-Q are described as extending in a third direction (D3) 111; however, the embodiments are not limited thereto. The first direction (D1) 109 and the second direction (D2) 105 can be considered as being in a horizontal (“XY”) plane. The third direction (D3) 111 can be considered as being in a vertical (“Z”) plane. Therefore, according to several embodiments described herein and as Figure 1 As described herein, the digital lines 103-1, 103-2, ..., 103-Q extend in a vertical direction (e.g., third direction (D3) 111); however, the embodiments are not limited thereto. For example, according to several embodiments described herein, the digital lines 103-1, 103-2, ..., 103-Q may extend in a horizontal direction (e.g., direction (D1) 109).

[0017] As mentioned, the embodiments are not limited to Figure 1 The schematic diagram is shown below. One or more embodiments specify that digital lines 103-1, 103-2, ..., 103-Q may extend in a first direction (D1) 109 and access lines 107-1, 107-2, ..., 107-Q may extend in a third direction (D3) 111. Therefore, one or more embodiments specify that digital lines 103-1, 103-2, ..., 103-Q may extend in a horizontal direction and access lines 107-1, 107-2, ..., 107-Q may extend in a vertical direction.

[0018] A memory cell (e.g., 110) may include access means (e.g., transistors) and memory nodes located at the intersections of each access line 107-1, 107-2, ..., 107-Q and each digital line 103-1, 103-2, ..., 103-Q. The memory cell can be written to or read from using the access lines 107-1, 107-2, ..., 107-Q and the digital lines 103-1, 103-2, ..., 103-Q. Figure 1As shown, access lines 107-1, 107-2, ..., 107-Q can be connected along the horizontal rows of memory cells in each sub-cell array 101-1, 101-2, ..., 101-N, and digital lines 103-1, 103-2, ..., 103-Q can be connected along the vertical columns of memory cells in each sub-cell array 101-1, 101-2, ..., 101-N. A memory cell (e.g., 110) can be located between an access line (e.g., 107-2) and a digital line (e.g., 103-2). Each memory cell can be uniquely addressed by a combination of access lines 107-1, 107-2, ..., 107-Q and digital lines 103-1, 103-2, ..., 103-Q.

[0019] Access lines 107-1, 107-2, ..., 107-Q may be or include conductive patterns (e.g., metal lines) disposed on and spaced apart from the substrate. Figure 1 As shown, access lines 107-1, 107-2, ..., 107-Q may extend in a first direction (D1) 109. Access lines 107-1, 107-2, ..., 107-Q in a sub-cell array (e.g., 101-2) may be spaced apart from each other in a vertical direction (e.g., in a third direction (D3) 111). However, the embodiments are not limited thereto.

[0020] Digital lines 103-1, 103-2, ..., 103-Q may be or be contained in the direction perpendicular to the substrate (e.g., on the third direction (D3)111) (as shown). Figure 1 (As shown in the diagram) Extended conductive patterns (e.g., metal lines). Digital lines in a sub-cell array (e.g., 101-2) may be spaced apart from each other in a first direction (D1) 109. However, the embodiments are not limited thereto.

[0021] The gate of a memory cell (e.g., memory cell 110) may be connected to an access line (e.g., 107-2), and a first conductive node (e.g., a first source / drain region) of an access means (e.g., a transistor) of memory cell 110 may be connected to a digital line (e.g., 103-2). Each of the memory cells (e.g., memory cell 110) may be connected to a storage node (e.g., a capacitor). A second conductive node (e.g., a second source / drain region) of an access means (e.g., a transistor) of memory cell 110 may be connected to a storage node (e.g., a capacitor). Although the references to the first and second source / drain regions are used herein to denote two separate and distinct source / drain regions, it is not intended that the source / drain regions referred to as "first" and / or "second" source / drain regions have a single meaning. It is only desirable that one of the source / drain regions is connected to a digital line (e.g., 103-2) and the other is connected to a storage node.

[0022] Figure 2 This is a diagram of a portion of a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure. Figure 2 As shown, the vertical three-dimensional (3D) memory comprises a vertically oriented stack of memory cells in array 220.

[0023] The vertically oriented stacking of memory cells can be manufactured such that each cell is formed on one of multiple vertical levels (e.g., tiers). For example... Figure 2 As described, array 220 includes a first layer 222-1, a second layer 222-2, a third layer 222-3, and a fourth layer 222-4; however, the embodiment is not limited to a specific number of layers. For example, the array may contain fewer than four or more than four layers. Vertical layers are arranged (e.g., stacked) in a vertical direction (e.g., a third direction (D3) 211).

[0024] like Figure 2 As shown, each of the multiple vertical hierarchies contains several units, including storage nodes. For example, hierarchy 222-1 specifically includes units directly coupled to access line 207-1; hierarchy 222-2 specifically includes units directly coupled to access line 207-2; hierarchy 222-3 specifically includes units directly coupled to access line 207-3; and hierarchy 222-4 specifically includes units directly coupled to access line 207-4. Unit 224 of hierarchies 222-1, 222-2, and 222-3 includes capacitors that can be called storage capacitors 224. Unit 219 of hierarchy 222-4 and other units in hierarchy 4 include capacitors that can be called decoupling capacitors. Figure 2 As shown, the cell 219 containing the decoupling capacitor is perpendicularly separated from the cell 224 containing the storage capacitor. In other words, the cell 219 containing the decoupling capacitor extends in a third direction (D3) 211 compared to the cell 224 containing the storage capacitor.

[0025] like Figure 2 The image shows storage capacitors in vertical digital lines 203-1, 203-2, 203-3, and 203-4, and conductive interconnect layers 222-1, 222-2, and 222-3. For example... Figure 2 As shown, access lines 207-1, 207-2, 207-3, and 207-4 are interconnected with cells associated with specific access lines.

[0026] like Figure 2As shown, cell 219, which includes the decoupling capacitor of layer 4 222-4, is not electrically interconnected via vertical digital lines 203-1, 203-2, 203-3, and 203-4. Non-conductive vertical lines 218-1, 218-2, 218-3, and 218-4 are formed between cell 219 containing the decoupling capacitor and the corresponding vertically aligned cell 224 containing the storage capacitor. The non-conductive vertical lines 218-1, 218-2, 218-3, and 218-4 specify that cell 219 containing the decoupling capacitor is electrically isolated from cells 224 containing storage capacitors in lower layers (e.g., layers 222-1, 221-2, and 222-3).

[0027] The non-conductive vertical lines 218-1, 218-2, 218-3, and 218-4 are formed of non-conductive materials. Examples of non-conductive materials include dielectric materials, such as oxide materials (e.g., SiO2) and nitride materials (e.g., silicon nitride (Si3N4)), as well as other non-conductive materials.

[0028] like Figure 2 As shown, power bus 231 may be positioned above (e.g., formed on) the vertically oriented stack of memory cells. Power bus 231 may be a conductive material, such as a metal. Figure 2 As shown, the power bus 231 is vertically separated (e.g., above) from the unit 219 containing the decoupling capacitor and the unit 224 containing the storage capacitor. In other words, the power bus 231 extends further in a third direction (D3) 211 than the unit 219 containing the decoupling capacitor and the unit 224 containing the storage capacitor.

[0029] Unit 219, containing decoupling capacitors, is electrically coupled to power bus 231 via conductive vertical lines 226-1, 226-2, 226-3, and 226-4. Because unit 219, containing decoupling capacitors, is electrically coupled to power bus 231, the decoupling capacitors help reduce or eliminate voltage drops and help maintain voltage across a range of operating conditions. Although Figure 2 Not explicitly stated, but the power bus can be electrically coupled to several components, such as decoders, sense amplifiers, etc., that can be used to access memory cells associated with, for example, reading and / or writing data. Decoupling capacitors can be used to prevent, for example, a drop in the power supply signal of the Vdd and / or Vss signals.

[0030] The conductive vertical lines 226-1, 226-2, 226-3, and 226-4 may comprise titanium. In some embodiments, the conductive vertical line 226 may comprise titanium nitride (TiN). In some embodiments, the conductive vertical line 226 may comprise ruthenium (Ru). In some embodiments, the conductive vertical line 226 may be tungsten (W). However, the embodiments are not limited thereto.

[0031] Figure 3 This is a diagram of a portion of a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure. Figure 3 As shown, the vertical three-dimensional (3D) memory comprises a vertically oriented stack of memory cells in array 320.

[0032] The vertically oriented stacking of memory cells can be manufactured such that each cell is formed on one of multiple vertical levels (e.g., tiers). For example... Figure 3 As described, array 320 may include layers 322-1, 322-2, 322-3, and 322-4; however, the embodiments are not limited to a specific number of layers. For example, the array may contain fewer than or more than four layers. Vertical layers are arranged (e.g., stacked) in a vertical direction (e.g., a third direction (D3) 311).

[0033] like Figure 3 As shown, array 320 includes horizontal digital lines 303-1, 303-2, 303-3, 303-4 of cells with conductive interconnects respectively associated with specific digital lines, and vertical access lines 307-1, 307-2, 307-3, 307-4 of cells with conductive interconnects respectively associated with specific access lines.

[0034] like Figure 3 As shown, the power bus 331 can be formed on a vertically oriented stack of memory cells. For example, a cell electrically coupled to the power bus via corresponding horizontal digital lines 303-1, 303-2, 303-3, 303-4 is called cell 319 containing decoupling capacitors. A cell not electrically coupled to the power bus is called cell 324 containing storage capacitors.

[0035] like Figure 3 As shown, horizontal digital lines 303-1, 303-2, 303-3, and 303-4 are electrically coupled to a power bus 331. Horizontal digital lines 303-1, 303-2, 303-3, and 303-4 are coplanar and form a planar slice 322 containing an array 320 of cells 319 containing decoupling capacitors from layers 322-1, 322-2, 322-3, and 322-4. The cells 319 containing decoupling capacitors in the planar slice 322 are horizontally separated from the cells 324 containing storage capacitors; cells 324 are not in the same layer of the planar slice 322. Although... Figure 3 The planar slice 322 is described as being positioned at the end of the array 320, but the embodiment is not limited thereto. For example, the planar slice 322 may be positioned in the inner portion of the array 320, such that a cell containing a decoupling capacitor in a particular layer is positioned between cells containing a storage capacitor in the same layer.

[0036] One or more embodiments specify that each vertical access line in the planar slice 322 is continuously activated, for example, causing the access device coupled thereto to be "on". Maintaining each vertical access line in the planar slice 322 in an active state (e.g., continuously on) ensures that each cell 319 containing a decoupling capacitor in the planar slice 322 is actively coupled to the corresponding horizontal digital line 303.

[0037] As mentioned, the power bus 331 can be formed on a vertically oriented stack of memory cells. Figure 3 As shown, the power bus 331 may include a first vertical portion 327, a second vertical portion 328, and a horizontal portion 329, wherein the first vertical portion 327 and the second vertical portion 328 are electrically coupled to (e.g., in contact with) the horizontal portion 329. Figure 3 As shown, the first vertical portion 327 and the second vertical portion 328 each extend in a third direction (D3) 311, and the horizontal portion 329 extends in a first direction (D1) 309. For example... Figure 3 As shown, a portion of the power bus 331 is coplanar with the horizontal digital lines 303-1, 303-2, 303-3, and 303-4. For example... Figure 3 As shown, a portion of the power bus 331 is horizontally separated from unit 319, which contains decoupling capacitors, and horizontally separated from unit 324, which contains storage capacitors, at the same level. For example... Figure 3 As shown, a portion of the power bus 331 is vertically separated from the unit 319 containing the decoupling capacitor and from the unit 324 containing the storage capacitor at the same level.

[0038] Figure 4 This is a diagram of a portion of the unit cells according to several embodiments of the present disclosure. Figure 4 A more detailed description of memory cells according to some embodiments of the present disclosure (e.g., in) Figure 1 The unit cells of the vertically stacked array (e.g., within the sub-cell array 101-2) of the sub-cell array 101-2 Figure 1 (Memory unit 110 in the middle). For example Figure 4 As shown, the first and second source / drain regions 421 and 423 can be impurity-doped regions of the lateral access device 430. The first and second source / drain regions can be separated by a channel 425 formed in the semiconductor material body (e.g., the body region) of the lateral access device 430. The first and second source / drain regions 421 and 423 can be formed by n-type or p-type dopants doped in the body region. The embodiments are not limited thereto.

[0039] For example, for an n-type conductive transistor structure, the body region of the lateral access device 430 may be formed of a lightly doped p-type (p-) semiconductor material. In one embodiment, the body region and the channel 425 separating the first and second source / drain regions 421 and 423 may comprise a lightly doped p-type (e.g., low dopant concentration (p-)) polysilicon material including boron (B) atoms as impurity dopants to the polysilicon. The first and second source / drain regions 421 and 423 may also comprise metals and / or metal composites formed using atomic layer deposition processes, containing ruthenium (Ru), molybdenum (Mo), nickel (Ni), titanium (Ti), copper (Cu), highly doped degenerate semiconductor materials, and / or indium oxide (In₂O₃) or indium tin oxide (In₂O₃). 2-x Sn x At least one of O3). However, the embodiments are not limited to these examples. As used herein, degenerate semiconductor materials are intended to mean semiconductor materials (e.g., polycrystalline silicon) containing highly doped materials with significant interactions between dopants (e.g., phosphorus (P), boron (B), etc.). In contrast, non-degenerate semiconductors contain moderate doping, where the dopant atoms are well separated from each other in the semiconductor host lattice and their interactions are negligible.

[0040] In this example, the first and second source / drain regions 421 and 423 may contain highly doped, n-type conductive impurities (e.g., highly doped (n+)) doped within the first and second source / drain regions 421 and 423. In some embodiments, the highly doped, n-type conductive first and second drain regions 421 and 423 may contain a high concentration of phosphorus (P) atoms deposited therein. However, the embodiments are not limited to this example. In other embodiments, the access device 430 (e.g., a transistor) may be of p-type conductive construction, in which case the conductivity type of the impurity (e.g., the dopant) will be reversed.

[0041] like Figure 4 As shown in the example embodiment, the first source / drain region 421 may occupy the upper portion of the body of the lateral access device 430. For example, the first source / drain region 421 may have a bottom surface within the body of the lateral access device 430 that is vertically positioned in a third direction (D3) 411 higher than the bottom surface of the body of the lateral access device 430. Therefore, the transistor 430 may have a body portion located below the first source / drain region 421 and electrically in contact with, for example, body contacts. Furthermore, as Figure 4As shown in the example embodiments, access line 407 may be disposed on a top surface opposite and coupled to channel region 425, separated from it by gate dielectric 404. Gate dielectric material 404 may comprise, for example, a high-k dielectric material, silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. Embodiments are not limited thereto. For example, in the high-k dielectric material example, gate dielectric material 404 may comprise one or more of the following: hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobium iron ore, etc. One or more embodiments specify that gate dielectric 404 includes silicon dioxide (SiO2) material, aluminum oxide (Al2O3) material, high dielectric constant (k) (e.g., high-k) dielectric material, and / or combinations thereof.

[0042] like Figure 4 As shown in the example embodiment, a digital line can extend vertically to a horizontally oriented access device 430 (e.g., a transistor horizontally conducted between the first and second source / drain regions 421 and 423) adjacent to the sidewall of the first source / drain region 421 in a third direction (D3) 411. In this embodiment, the vertically oriented digital line 403-1 is asymmetrically adjacent and electrically contacts the first source / drain region 421. The digital line 403-1 may be asymmetrically formed to reverse, for example, the space of the body contact in the channel region 425.

[0043] Figure 5 This is a cross-sectional view of a portion of a semiconductor device according to several embodiments of the present disclosure. Figure 5 In the example embodiment shown, alternating layers of first dielectric material 530-1, 530-2, ..., 530-N, semiconductor material 532-1, 532-2, ..., 532-N, and second dielectric material 533-1, 533-2, ..., 533-N are formed in a vertical stack on the working surface of semiconductor substrate 500. However, the embodiments are not limited to this example and may include more or fewer repeated iterations.

[0044] like Figure 5 The description indicates that the semiconductor device may include a power bus 531. The power bus 531 may be positioned above (e.g., formed on) a vertically oriented stack of memory cells. The power bus 531 is vertically separated from (e.g., above) the cell 519 containing a decoupling capacitor and the cell 524 containing a storage capacitor. Although Figure 5 Not shown in the diagram, but the power bus 531 may contain several vertical sections, such as those related to... Figure 3 Discussion.

[0045] like Figure 5 The description states that the conductive vertical line 526 can couple the unit 519, which contains a decoupling capacitor, to the power bus 531. Furthermore, the non-conductive vertical line 518 can specify that the unit 219, which contains a decoupling capacitor, is electrically isolated from the unit 224, which contains a storage capacitor in a lower level.

[0046] Although Figure 5 Not shown, but the material can be separated from the substrate 500 by an insulating material. In one embodiment, the first dielectric material 530 can be deposited to have a thickness ranging from 20 nanometers (nm) to 60 nm, for example, a vertical height in a third direction (D3). In one embodiment, the semiconductor material 532 can be deposited to have a thickness ranging from 20 nm to 100 nm, for example, a vertical height. In one embodiment, the second dielectric material 533 can be deposited to have a thickness ranging from 10 nm to 30 nm, for example, a vertical height. However, the embodiments are not limited to these examples.

[0047] In some embodiments, the first dielectric materials 530-1, 530-2, ..., 530-N may be interlayer dielectrics (ILDs). By way of example and not limitation, the first dielectric materials 530-1, 530-2, ..., 530-N may include oxide materials, such as SiO2. In another example, the first dielectric materials 530-1, 530-2, ..., 530-N may include silicon nitride (Si3N4) material (also referred to herein as “SiN”). In yet another example, the first dielectric materials 530-1, 530-2, ..., 530-N may include silicon oxycarbide (SiO2). x C y In another example, the first dielectric material 530-1, 530-2, ..., 530-N may comprise silicon oxynitride (SiO2). x N y) Materials (also referred to herein as "SiON") and / or combinations thereof. Examples are not limited to these instances.

[0048] In some embodiments, semiconductor materials 532-1, 532-2, ..., 532-N may comprise silicon (Si) material in a polycrystalline and / or amorphous state. Semiconductor materials 532-1, 532-2, ..., 532-N may be lightly doped p-type (p-) silicon materials. Semiconductor materials 532-1, 532-2, ..., 532-N may be formed by using a low concentration of vapor-phase doped boron atoms (B) as an impurity dopant to form lightly doped p-type (p-) silicon materials. Lightly doped p-type (p-) silicon materials may be polycrystalline silicon materials. However, the embodiments are not limited to these examples.

[0049] In some embodiments, the second dielectric materials 533-1, 533-2, ..., 533-N may be interlayer dielectrics (ILDs). By way of example, and not limitation, the second dielectric materials 533-1, 533-2, ..., 533-N may include nitride materials. The nitride material may be silicon nitride (Si3N4) material (also referred to herein as “SiN”). In another example, the second dielectric materials 533-1, 533-2, ..., 533-N may include silicon oxycarbide (SiOC) material. In yet another example, the second dielectric materials 533-1, 533-2, ..., 533-N may comprise silicon oxynitride (SiON) and / or combinations thereof. The embodiments are not limited to these examples. However, according to embodiments, the second dielectric materials 533-1, 533-2, ..., 533-N may be selected to differ in material or composition from the first dielectric material.

[0050] like Figure 5 As shown, the semiconductor device may include a gate dielectric material 504. The gate dielectric material 504 can be selected from various dielectric materials. A conductive material 507 may be deposited on the gate dielectric material 504. The conductive material 507 may be intertwined with the gate dielectric material 504 and indistinguishable from it.

[0051] In some embodiments, the conductive material 507 may include one or more of the following: doped semiconductors, such as doped silicon, doped germanium, etc.; conductive metal nitrides, such as titanium nitride, tantalum nitride, etc.; metals, such as tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.; and / or metal semiconductor compounds, such as tungsten silicide, cobalt silicide, titanium silicide, etc.; and / or some other combination thereof. The conductive material 507, wound together with the gate dielectric material 504, may form access lines (also referred to as word lines) opposite the channel region. Several embodiments specify that the access lines are horizontally oriented access lines extending in direction (D1) 509, for example, in / out of the page, such as... Figure 5 This is explained in the text. However, the embodiments are not limited thereto. Several embodiments specify that the access line is a vertically oriented access line.

[0052] like Figure 5 As shown, a semiconductor material 595, such as a highly doped semiconductor material, can be utilized. In some embodiments, the highly doped semiconductor material 595 may be a metal, such as tungsten (W). However, the embodiments are not limited thereto. In some embodiments, the highly doped semiconductor material 595 may be a highly doped (e.g., p-type highly doped (p+)) semiconductor material that can be deposited into the second vertical opening. In this example, the highly doped semiconductor material 595 may be a highly doped p-type (p+) silicon material. The highly doped p-type (p+) silicon material 595 may be a polycrystalline silicon material. In some embodiments, the highly doped semiconductor material 595 may be a highly doped p-type (p+) silicon-germanium (SiGe) material.

[0053] Several embodiments specify that a dielectric material 574 may be used. The dielectric material 574 may be in direct contact with the conductive material 507 and the lightly doped semiconductor material 532. However, the embodiments are not limited to this example.

[0054] The embodiments specify that the semiconductor device may include a first source / drain region 521. One or more embodiments specify that the first source / drain region 521 may be formed by vapor-phase doping, for example by doping a portion of a semiconductor material 532. In some embodiments, the first source / drain region may be adjacent to the channel region.

[0055] The embodiments specify that the semiconductor device may include a second source / drain region 523. As further discussed herein, a horizontally oriented capacitor cell having a bottom electrode may be deposited into a horizontal opening to make electrical contact with the second source / drain region 523.

[0056] The embodiments specify that the semiconductor device may include a first electrode material 561, which may be referred to as the bottom electrode. The first electrode material 561 may be coupled to a second source / drain region 523 of the horizontal access device. Although the references to the first and second source / drain regions are used herein to refer to two separate and distinct source / drain regions, it is not intended that the source / drain regions referred to as "first" and / or "second" source / drain regions have a single meaning. It is only desirable that one of the source / drain regions is connected to a digital line and the other is connected to a memory node.

[0057] One or more embodiments specify that dielectric material 563 may be deposited on first electrode material 561. Second electrode material 556 (e.g., top electrode) may be deposited on dielectric material 563. Figure 5 As shown, the top electrode 556 can be shared by several memory nodes, such as cell 519 containing decoupling capacitors of layers 522-4 and cell 524 containing storage capacitors of layers 522-1, 522-2, and 522-4. The top electrode 556 can be coupled to a common electrode plane, such as (for example) a ground plane. Figure 5 As shown, the decoupling capacitor of unit 519 and the storage capacitor of unit 524 extend horizontally in the second direction (D2) in the drawing plane, and can therefore be referred to as horizontally oriented storage nodes.

[0058] like Figure 5 As shown, dielectric material 574 can contact the main contact 595 of the horizontally oriented access device 530 (e.g., highly doped p-type (p+) silicon material).

[0059] like Figure 5 As shown, conductive material 503 can be formed into vertical digital lines 503. For example... Figure 5As shown, a vertical digital line 503 extending in direction (D3) 511 is electrically coupled to a first source / drain region 521 of a cell 524 containing a storage capacitor. However, the embodiments are not limited thereto. As previously mentioned, one or more embodiments specify that the digital line 503 is horizontal and the access line 507 is vertical; such semiconductor devices can be manufactured using various processing steps. Figure 5 As shown, conductive material 503 contacts (e.g., terminates vertically at) a non-conductive vertical line 518.

[0060] In some embodiments, the conductive material 503 may be formed of a silicide. In some embodiments, the conductive material 503 may include a titanium material. In some embodiments, the conductive material 503 may include a titanium nitride (TiN) material. In some embodiments, the conductive material 503 may include a ruthenium (Ru) material. In some embodiments, the conductive material may be tungsten (W). However, the embodiments are not limited thereto.

[0061] Although Figure 5 Not explicitly stated, but provided in one or more embodiments, the vertical digital line 503 may pass through the substrate 500 to the underlying interconnect metal layer, such that the vertical digital line 503 may be connected to the underlying CMOS and interconnect layers beneath the substrate 500. Compared to some other configurations, the connection to the underlying metal layer provides a shorter path for the vertical digital line 503 to the CMOS circuitry beneath the substrate 500.

[0062] Figure 6 This is a block diagram of an apparatus according to several embodiments of the present disclosure. Figure 6 This is a block diagram of a device in the form of a computing system 650 including a memory device 651, according to several embodiments of the present disclosure. As used herein, for example, the memory device 651, the memory array 653, and / or the host 602 may also be individually considered as a "device". According to embodiments described herein, the memory device 651 may include at least one memory array 653, wherein memory cells having digital lines and body contacts are formed.

[0063] In this example, system 650 includes a host 602 coupled to memory device 651 via interface 654. Computing system 650 can be a personal laptop, desktop computer, digital camera, mobile phone, memory card reader, or Internet of Things (IoT) enabled device, as well as various other types of systems. Host 602 may include several processing resources capable of accessing memory 651, such as one or more processors, microprocessors, or some other type of control circuitry system. System 650 may include a separate integrated circuit, or both host 602 and memory device 651 may be on the same integrated circuit. For example, host 602 may be a system controller for a memory system including multiple memory devices 651, wherein system controller 652 provides access to the respective memory devices 651 through another processing resource (e.g., a central processing unit (CPU)).

[0064] exist Figure 6 In the example shown, host 602 is responsible for executing the operating system (OS) and / or various applications (e.g., processes) that can be loaded onto it (e.g., loaded onto it from memory device 651 via controller 652). The OS and / or various applications can be loaded from memory device 651 by providing access commands from host 602 to memory device 651, including access to data of the OS and / or various applications. Host 602 can also access data used by the OS and / or various applications by providing access commands to memory device 651 to retrieve data for executing the OS and / or various applications.

[0065] For clarity, system 650 has been simplified to focus on features particularly relevant to this disclosure. Memory array 653 may be a DRAM array, comprising at least one memory cell having digital lines and body contacts formed according to the techniques described herein. For example, memory array 653 may be an unshielded DL 4F2 array, such as a 3D-DRAM memory array. Array 653 may include memory cells arranged in rows coupled via word lines (which may be referred to herein as access lines or select lines) and columns coupled via digital lines (which may be referred to herein as sense lines or data lines). Although Figure 6 The illustration shows a single array 653, but the embodiments are not limited thereto. For example, the memory device 651 may include several arrays 653, such as several memory banks of DRAM cells.

[0066] Memory device 651 includes an address circuitry 606 for latching address signals provided via interface 654. The interface may include, for example, a physical interface employing a suitable protocol, such as a data bus, address bus, and command bus, or a combined data / address / command bus. This protocol may be custom or proprietary, or interface 654 may employ a standardized protocol, such as Peripheral Component Interconnect High Speed ​​(PCIe), Gen-Z, CCIX, or the like. Address signals are received and decoded by row decoder 608 and column decoder 612 to access memory array 653. Data can be read from memory array 653 by sensing voltage and / or current changes on a sensing line using sensing circuitry 655. Sensing circuitry 655 may include, for example, a sense amplifier capable of reading and latching a page (e.g., a row) of data from memory array 653. I / O circuitry 657 can be used for bidirectional data communication with host 602 via interface 654. Read / write circuitry 613 is used to write data to or read data from memory array 653. As an example, circuit system 613 may include various drivers, latching circuit systems, etc.

[0067] The control circuitry system 652 decodes signals provided by the host 602. These signals may be commands provided by the host 602. These signals may include chip enable signals, write enable signals, and address latch signals, which are used to control operations performed on the memory array 653, including data read operations, data write operations, and data erase operations. In various embodiments, the control circuitry system 652 is responsible for executing instructions from the host 602. The control circuitry system 652 may include a state machine, a sequencer, and / or some other type of control circuitry system, which may be implemented in hardware, firmware, or software, or any combination of the three. In some instances, the host 602 may be a controller external to the memory device 651. For example, the host 602 may be a memory controller coupled to the processing resources of a computing device.

[0068] The term "semiconductor" can refer to, for example, a material, a wafer, or a substrate, and includes any substrate semiconductor structure. "Semiconductor" should be understood to include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin-film transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon supported by a substrate semiconductor structure, and other semiconductor structures. Furthermore, when referring to the semiconductor in the foregoing description, prior process steps may have been used to form regions / junctions in the substrate semiconductor structure, and the term "semiconductor" may include an underlying material containing such regions / junctions.

[0069] As used herein, “several” or “a certain amount” of something may refer to one or more such things. For example, “several” or “a certain amount” of memory cells may refer to one or more memory cells. “A certain amount” of something is intended to be two or more. As used herein, performing multiple actions simultaneously refers to actions that at least partially overlap within a specific time period. As used herein, the term “coupling” may include electrical coupling, direct coupling and / or direct connection without intermediary elements (e.g., by direct physical contact), indirect coupling and / or connection using intermediary elements, or wireless coupling. The term “coupling” may further include two or more elements that cooperate or interact with each other (e.g., in a causal relationship). An element coupled between two elements may be between the two elements and may be coupled to each of the two elements.

[0070] It should be recognized that the term "vertical" describes a change from "completely" vertical due to variations in routine manufacturing, measurement, and / or assembly, and that what a person skilled in the art generally understands means by the term "vertical." For example, vertical may correspond to the z-direction. As used herein, when a particular element is "adjacent" to another element, the particular element may cover the other element, may be above or laterally to the other element, and / or may be in direct physical contact with the other element. Laterally to may refer to, for example, a horizontal direction that may be perpendicular to the z-direction (e.g., the y-direction or x-direction).

[0071] Although specific embodiments have been illustrated and described herein, those skilled in the art will understand that arrangements calculated to achieve the same results may be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of the various embodiments of this disclosure. It should be understood that the foregoing description has been carried out in an illustrative rather than restrictive manner. Those skilled in the art will understand, upon review of the foregoing description, combinations of the above embodiments and other embodiments not explicitly described herein. The scope of the various embodiments of this disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of the various embodiments of this disclosure should be determined by reference to the appended claims and the full scope of their equivalents.

Claims

1. A memory device (651) comprising a decoupling capacitor, the memory device comprising: A vertically stacked array of memory cells (220, 653), the array having horizontally oriented access lines (107-1, 107-2, ..., 107-Q, 207-1, 207-2, 207-3, 207-4, 407) and vertically oriented digital lines (103-1, 103-2, ..., 103-Q, 203-1, 203-2, 203-3, 203-4, 403-1, 503), comprising: Storage capacitor access devices (430, 530) are coupled to the corresponding storage capacitor (524); A horizontally oriented access line coupled to the gate of the storage capacitor access device; A vertically oriented digital line coupled to the storage capacitor access device; Non-conductive vertical lines (218-1, 218-2, 218-3, 218-4, 518) are located between the decoupling capacitor and the corresponding vertically aligned storage capacitor; and A decoupling capacitor (519) coupled to a power bus (231, 531), wherein the decoupling capacitor is perpendicularly separated from the storage capacitor.

2. The memory device of claim 1, further comprising conductive vertical lines (226-1, 226-2, 226-3, 226-4, 526) between the decoupling capacitor and the power bus, wherein the conductive vertical lines electrically couple the decoupling capacitor to the power bus.

3. The memory device of claim 1, wherein the power bus is perpendicularly separated from the decoupling capacitor or the storage capacitor or both.

4. The memory device according to any one of claims 1 to 3, wherein the decoupling capacitor is formed on a first vertical layer (222-4, 522-4), and the storage capacitor is formed on several other vertical layers (221-1, 221-2, 221-3, 522-1, 522-2, 522-3).

5. A method for forming a decoupling capacitor for a vertically stacked array of memory cells (220, 653), the method comprising: A first vertical layer (222-2, 522-2) and a second vertical layer (222-3, 522-3) are formed, wherein the first vertical layer and the second vertical layer each include a corresponding memory cell (224, 524) containing a storage capacitor; A third vertical layer (222-4, 522-4) is formed, wherein the third vertical layer includes corresponding memory cells (219, 519) containing decoupling capacitors; A power bus (231, 531) is formed, wherein the power bus is electrically coupled to the memory cells on the third vertical level via conductive vertical lines (226-1, 226-2, 226-3, 226-4, 526); and Non-conductive vertical lines (218-1, 218-2, 218-3, 218-4, 518) are formed between the second vertical level and the third vertical level to electrically isolate the memory cell containing the storage capacitor from the memory cell containing the decoupling capacitor.

6. The method of claim 5, wherein the power bus is vertically separated from the decoupling capacitor and the storage capacitor.

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