Semiconductor device

Abstract

Embodiments provide a semiconductor device capable of obtaining a desired output voltage from a resistance element with high reliability. The semiconductor device of the present embodiment includes a first-conductivity-type semiconductor substrate. A first-impurity-diffusion layer of a second conductivity type is provided in a surface region of the semiconductor substrate. A resistance element includes a second-impurity-diffusion layer of the first conductivity type, which is provided inside the first-impurity-diffusion layer in the surface region of the semiconductor substrate. In a transistor, a gate is connected to an input of the resistance element, a source is connected to the first-impurity-diffusion layer, and a drain is connected to a voltage source having a higher voltage than the input. A current source is connected to the source.

Description

[0001] [Related Applications]

[0002] This application enjoys priority to Japanese Patent Application No. 2021-3038 (filed on January 12, 2021). This application includes all contents of the basic application by reference to that basic application. Technical Field

[0003] This embodiment relates to a semiconductor device. Background Technology

[0004] NAND (Not-And) flash memory and other semiconductor devices sometimes feature a structure with an array of memory cells positioned above CMOS (Complementary Metal Oxide Semiconductor) circuitry to achieve miniaturization. In CMOS circuits, the power supply circuitry sometimes includes a voltage divider circuit containing an impurity diffusion layer.

[0005] However, when a forward bias voltage is applied between the impurity diffusion layer and the substrate based on the change in the input voltage of the resistive element of the voltage divider circuit, there is a concern that the required output voltage may not be obtained from the voltage divider circuit. In this case, the reliability of the CMOS circuit will decrease. Summary of the Invention

[0006] The implementation provides a highly reliable semiconductor device capable of obtaining the required voltage from a voltage divider circuit.

[0007] The semiconductor device of this embodiment includes a semiconductor substrate of a first conductivity type. A first impurity diffusion layer of a second conductivity type is disposed on the surface region of the semiconductor substrate. The resistive element includes a second impurity diffusion layer of the first conductivity type, which is disposed inside the first impurity diffusion layer in the surface region of the semiconductor substrate. In the transistor, the gate is connected to the input portion of the resistive element, the source is connected to the first impurity diffusion layer, and the drain is connected to a voltage source with a voltage higher than that of the input portion. A current source is connected to the source. Attached Figure Description

[0008] Figure 1A This is a schematic perspective view illustrating a semiconductor memory device according to the first embodiment.

[0009] Figure 1B This is a schematic top view representing a laminated volume.

[0010] Figure 2A This is a schematic cross-sectional view illustrating a three-dimensional storage unit.

[0011] Figure 2B This is a schematic cross-sectional view illustrating a three-dimensional storage unit.

[0012] Figure 3 This is a schematic top view illustrating the semiconductor memory device of the first embodiment.

[0013] Figure 4 It is a cross-sectional view showing a portion of the CMOS circuitry located beneath the memory cell array.

[0014] Figure 5 yes Figure 4 The equivalent circuit diagram of the resistor voltage divider circuit shown is shown.

[0015] Figure 6A This is a graph representing the operation of a resistor divider circuit without a transistor Tr.

[0016] Figure 6B This is a graph showing the operation of the resistor divider circuit in this embodiment.

[0017] Figure 7 This is a schematic cross-sectional view showing an example of the configuration of the resistor voltage divider circuit in the second embodiment.

[0018] Figure 8 This is a circuit diagram illustrating an example of the configuration of the resistor voltage divider circuit in the third embodiment. Detailed Implementation

[0019] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. These embodiments do not limit the present invention. The drawings are schematic or conceptual, and the proportions of the parts are not necessarily the same as actual proportions. In the specification and drawings, the same reference numerals are used for elements described above with respect to the accompanying drawings, and detailed descriptions are omitted where appropriate.

[0020] (First Embodiment)

[0021] Figure 1A This is a schematic perspective view illustrating the semiconductor memory device 100a according to the first embodiment. Figure 1B This is a schematic top view representing laminate 2. In this specification, the lamination direction of laminate 2 is defined as the Z direction. A direction that intersects or is orthogonal to the Z direction is defined as the Y direction. A direction that intersects or is orthogonal to both the Z and Y directions is defined as the X direction. Figure 2A and Figure 2B These are schematic cross-sectional views illustrating a three-dimensional storage unit. Figure 3 This is a schematic top view illustrating the semiconductor memory device 100a according to the first embodiment.

[0022] like Figures 1A to 3As shown, the semiconductor memory device 100a of the first embodiment can be a non-volatile memory with memory cells having a three-dimensional structure. However, this embodiment can also be applied to semiconductor devices other than semiconductor memory devices.

[0023] The semiconductor memory device 100a includes a substrate 1, a laminate 2, a deep slit ST (plate-like portion 3), a shallow slit SHE (plate-like portion 4), and a plurality of columnar portions CL.

[0024] The substrate 1 includes a substrate 10, an interlayer insulating film 11, a conductive layer 12, and a semiconductor portion 13. The interlayer insulating film 11 is disposed on the substrate 10. The conductive layer 12 is disposed on the interlayer insulating film 11. The semiconductor portion 13 is disposed on the conductive layer 12.

[0025] Substrate 10 is a semiconductor substrate, such as a silicon substrate. Silicon (Si) has a conductivity type, for example, p-type. A device separation region 10i is provided on the surface region of substrate 10, for example. The device separation region 10i is, for example, an insulating region containing silicon oxide, and an active region AA is defined on the surface region of substrate 10. The source and drain regions of transistor Tr are provided in the active region AA. Transistor Tr constitutes the peripheral circuitry (CMOS (Complementary Metal Oxide Semiconductor) circuit) of non-volatile memory. The CMOS circuitry is disposed below the buried source layer BSL and on substrate 10. An interlayer insulating film 11, for example, contains silicon oxide (SiO2) to insulate transistor Tr. A wiring 11a is provided within the interlayer insulating film 11. Wiring 11a is a wiring electrically connected to transistor Tr. The conductive layer 12 contains a conductive metal, such as tungsten (W). The semiconductor portion 13 contains, for example, silicon. Silicon has a conductivity type, for example, n-type. A portion of the semiconductor portion 13 may also contain undoped silicon.

[0026] The conductive layer 12 and the semiconductor portion 13 are electrically connected as an integral first conductive film, serving as a memory cell array. Figure 1B The common source electrode (buried source layer) of 2m functions. Therefore, the conductive layer 12 and / or the semiconductor part 13 are also referred to as the buried source layer BSL.

[0027] The stacked layer 2 is disposed above the substrate 10 and is located in the Z direction relative to the conductive layer 12 and the semiconductor portion 13 (buried source layer BSL). The stacked layer 2 is composed of multiple electrode films 21 and multiple insulating layers 22 alternately stacked along the Z direction. The electrode films 21 contain conductive metals, such as tungsten. The insulating layers 22 contain, for example, silicon oxide. The insulating layers 22 insulate the electrode films 21 from each other. The number of electrode films 21 and insulating layers 22 is arbitrary. The insulating layer 22 may also be an air gap, for example. An insulating film 2g is provided between the stacked layer 2 and the conductive portion 13, for example. The insulating film 2g contains, for example, silicon oxide (SiO2). The insulating film 2g may also contain a high dielectric with a relative permittivity higher than that of silicon oxide. The high dielectric is, for example, a metal oxide.

[0028] The electrode film 21 includes at least one source-side selected gate (SGS), multiple word lines (WL), and at least one drain-side selected gate (SGD). The source-side selected gate (SGS) is the gate electrode of the source-side selected transistor (STS). The word lines (WL) are the gate electrodes of the memory cells (MC). The drain-side selected gate (SGD) is the gate electrode of the drain-side selected transistor (STD). The source-side selected gate (SGS) is disposed in the lower region of the stacked layer 2. The drain-side selected gate (SGD) is disposed in the upper region of the stacked layer 2. The lower region refers to the region of the stacked layer 2 closest to the substrate portion 1, and the upper region refers to the region of the stacked layer 2 furthest from the substrate portion 1. The word lines (WL) are disposed between the source-side selected gate (SGS) and the drain-side selected gate (SGD).

[0029] Among the multiple insulating layers 22, the thickness in the Z direction of the insulating layer 22 that insulates the source-side select gate SGS from the word line WL can, for example, be thicker than the thickness in the Z direction of the insulating layer 22 that insulates the word lines WL from each other. Furthermore, a cover insulating film (not shown) can be provided above the uppermost insulating layer 22 furthest from the substrate portion 1. The cover insulating film may, for example, comprise silicon oxide.

[0030] Semiconductor memory device 100a has multiple memory cells MC connected in series between a source-side selection transistor STS and a drain-side selection transistor STD. The structure of the source-side selection transistor STS, memory cells MC, and drain-side selection transistor STD connected in series is called a "memory string" or "NAND string". The memory string is connected to a bit line BL, for example, via a contact Cb. The bit line BL is positioned above the stack 2 and extends in the Y direction.

[0031] Multiple deep slits ST and multiple shallow slits SHE are respectively provided within the laminate 2. The deep slits ST extend in the X direction, penetrating the laminate 2 from its upper end to the matrix 1, and are disposed within the laminate 2. The plate-like portion 3 is disposed within the deep slits ST. Figure 1BThe plate-shaped portion 3, for example, includes at least an insulating material. This insulating material is, for example, silicon oxide. The plate-shaped portion 3 may also include a conductive material that is electrically insulated from the laminate 2 by the insulating material and electrically connected to the buried source layer BSL. The shallow slit SHE extends in the X direction, from the upper end of the laminate 2 to the middle of the laminate 2. A plate-shaped portion 4 is provided, for example, within the shallow slit SHE. Figure 1B Plate-shaped portion 4 is, for example, silicon oxide.

[0032] like Figure 1B As shown, the stacked matrix 2 includes a stepped portion 2s and a memory cell array 2m. The stepped portion 2s is disposed at the edge of the stacked matrix 2. The memory cell array 2m is sandwiched or surrounded by the stepped portion 2s. A deep slit ST extends from the stepped portion 2s at one end of the stacked matrix 2, through the memory cell array 2m, to the stepped portion 2s at the other end of the stacked matrix 2. A shallow slit SHE is disposed at least in the memory cell array 2m.

[0033] like Figure 3 As shown, the storage cell array 2m includes a cell region and a tap region. The stepped section 2s includes a staircase region. Figure 3 The joint area may be located, for example, between the unit area and the stepped area. Figure 3 Although not illustrated, the connector area can also be located between the unit areas. The stepped area is an area with multiple wirings 37a. The connector area is an area with wirings 37b and 37c. Wirings 37a to 37c extend, for example, in the Z direction. Wirings 37a are electrically connected, for example, to the electrode film 21. Wiring 37b is electrically connected, for example, to the conductive layer 12. Wiring 37c is electrically connected, for example, to wiring 11a.

[0034] Figure 1B The portion of the stack 2 sandwiched between two plate-shaped portions 3 is called a block. A block, for example, constitutes the smallest unit of data erasure. A plate-shaped portion 4 is disposed within the block. The stack 2 between the plate-shaped portions 3 and 4 is called a finger. The drain-side select gate SGD is separated by each finger. Therefore, when writing and reading data, one finger within the block can be selected via the drain-side select gate SGD.

[0035] Multiple columnar portions CL are respectively disposed within memory vias MH, which are disposed within the stacked layer 2. Each columnar portion CL extends along the Z-direction from the upper end of the stacked layer 2, penetrating the stacked layer 2 and being disposed within the stacked layer 2 and the buried source layer BSL. Each columnar portion CL includes a semiconductor body 210, a memory film 220, and a core layer 230. Each columnar portion CL includes a core layer 230 disposed at its center, a semiconductor body 210 disposed around the core layer 230, and a memory film 220 disposed around the semiconductor body 210. The semiconductor body 210 is electrically connected to the buried source layer BSL. The memory film 220 has a charge trapping portion between the semiconductor body 210 and the electrode film 21. Multiple columnar portions CL, selected one by one from each finger portion, are connected to a common bit line BL via a contact Cb. The columnar portions CL are respectively disposed, for example, in a cell region (Cell) Figure 3 ).

[0036] like Figure 2A and Figure 2B As shown, the shape of the memory hole MH in the XY plane is, for example, a circle or an ellipse. A barrier insulating film 21a, forming part of the memory film 220, may also be provided between the electrode film 21 and the insulating layer 22. The barrier insulating film 21a is, for example, a silicon oxide film or a metal oxide film. An example of a metal oxide is aluminum oxide. A barrier film 21b may also be provided between the electrode film 21 and the insulating layer 22, and between the electrode film 21 and the memory film 220. For example, if the electrode film 21 is tungsten, the barrier film 21b may be, for example, a multilayer structure of titanium nitride and titanium. The barrier insulating film 21a suppresses charge tunneling from the electrode film 21 to the memory film 220 side. The barrier film 21b improves the adhesion between the electrode film 21 and the barrier insulating film 21a.

[0037] The semiconductor body 210 is, for example, a bottomed cylindrical shape. The semiconductor body 210 contains, for example, silicon. The silicon is, for example, polycrystalline silicon formed by crystallizing amorphous silicon. The semiconductor body 210 is, for example, undoped silicon. Alternatively, the semiconductor body 210 may also be p-type silicon. The semiconductor body 210 serves as the channel for the drain-side select transistor (STD), the memory cell (MC), and the source-side select transistor (STS). The semiconductor body 210 is electrically connected to the buried source layer (BSL).

[0038] In the memory film 220, the portion other than the blocking insulating film 21a is disposed between the inner wall of the memory hole MH and the semiconductor body 210. The memory film 220 is, for example, cylindrical. A plurality of memory cells MC have storage regions between the semiconductor body 210 and the electrode film 21, which serves as the word line WL, and are stacked in the Z direction. The memory film 220 includes, for example, a covering insulating film 221, a charge trapping film 222, and a tunnel insulating film 223. The semiconductor body 210, the charge trapping film 222, and the tunnel insulating film 223 each extend in the Z direction.

[0039] An insulating cover 221 is disposed between the insulating layer 22 and the charge trapping film 222. The insulating cover 221 may contain, for example, silicon oxide. When the sacrificial film (not shown) is replaced with the electrode film 21 (replacement step), the insulating cover 221 protects the charge trapping film 222 from etching. The insulating cover 221 can also be removed between the electrode film 21 and the memory film 220 during the replacement step. In this case, as... Figure 2A and Figure 2B As shown, a barrier insulating film 21a is provided, for example, between the electrode film 21 and the charge trapping film 222. Alternatively, the insulating film 221 may be omitted if the electrode film 21 is not formed using a replacement step.

[0040] A charge trapping film 222 is disposed between the barrier insulating film 21a, the cover insulating film 221, and the tunnel insulating film 223. The charge trapping film 222 may contain, for example, silicon nitride, and has trapping portions within it for trapping charges. The portion of the charge trapping film 222 sandwiched between the electrode film 21 (which serves as the word line WL) and the semiconductor body 210 constitutes a charge trapping section, forming the storage region of the memory cell MC. The threshold voltage of the memory cell MC varies depending on whether there is charge in the charge trapping section or the amount of charge trapped in the charge trapping section. Thus, the memory cell MC stores information.

[0041] A tunnel insulating film 223 is disposed between the semiconductor substrate 210 and the charge trapping film 222. The tunnel insulating film 223 may comprise, for example, silicon oxide, or a mixture of silicon oxide and silicon nitride. The tunnel insulating film 223 acts as a potential barrier between the semiconductor substrate 210 and the charge trapping film 222. For example, when electrons are injected from the semiconductor substrate 210 into the charge trapping section (writing operation), and when holes are injected from the semiconductor substrate 210 into the charge trapping section (erasing operation), the electrons and holes respectively pass through the potential barrier of the tunnel insulating film 223 (tunneling).

[0042] The core layer 230 is embedded within the internal space of the cylindrical semiconductor body 210. The core layer 230 is, for example, columnar in shape. The core layer 230 contains, for example, silicon oxide and is insulating.

[0043] Figure 3Multiple columnar portions CLHR are respectively disposed within holes HR, which are disposed within the laminate 2. The holes HR extend along the Z-direction from the upper end of the laminate 2, penetrating the laminate 2 and extending into the laminate 2 and the semiconductor portion 13. Each columnar portion CLHR includes at least an insulator 5. The insulator 5 is, for example, silicon oxide. Alternatively, each columnar portion CLHR may have the same structure as the columnar portion CL. Each columnar portion CLHR is disposed, for example, in the staircase region and the tap region. The columnar portion CLHR functions as a support member for maintaining the gaps formed in the staircase region and the tap region when the sacrificial film (not shown) is replaced with the electrode film 21 (replacement step). Multiple columnar portions CLC4 are formed within the tap region, insulating film 32, and insulating film 31 of the laminate 2. Each columnar portion CLC4 includes a wiring 37c. The wiring 37c is electrically insulated from the laminate 2 by an insulator 36c. Wiring 37c is electrically connected to either wiring 11a or the other.

[0044] In a top-view layout, the columnar portion CL, i.e., the memory hole MH, is arranged in a hexagonal, densest configuration between two adjacent slits ST in the Y direction. For example... Figure 3 As shown, the shallow slit SHE is arranged to overlap a portion of the columnar portion CL. The columnar portion CL located below the shallow slit SHE does not constitute a memory cell.

[0045] Figure 1A The semiconductor portion 13 includes, for example, an n-type semiconductor layer 131, an n-type semiconductor layer 132, and an n-type or undoped semiconductor layer 133. Semiconductor layer 131 is connected to the conductive layer 12. Semiconductor layer 132 is connected to both semiconductor layer 131 and the semiconductor body 210. For example, semiconductor layer 132 extends to the portion of the memory film 220 that has been removed and is connected to the semiconductor body 210. Furthermore, semiconductor layer 132 is arranged to surround the semiconductor body 210 in an XY top view. Semiconductor layer 133 is connected to semiconductor layer 132.

[0046] The semiconductor memory device 100a further includes a semiconductor section 14. The semiconductor section 14 is located between the stacked layer 2 and the semiconductor section 13. The semiconductor section 14 includes a semiconductor layer 134. The semiconductor layer 134 is disposed within the insulating layer 22, between the insulating layer 22b closest to the semiconductor section 13 and the insulating film 2g. The conductivity type of the semiconductor layer 134 is, for example, n-type. The semiconductor layer 134 functions, for example, as a source-side select gate (SGS).

[0047] Figure 4 This is a cross-sectional view showing a portion of the CMOS circuitry located below the 2m memory cell array. Figure 4 An example of a resistor voltage divider circuit 300 used in power supplies, etc., is shown. Figure 5 yes Figure 4 The equivalent circuit diagram of the resistor voltage divider circuit 300 shown is shown.

[0048] The resistor divider circuit 300 includes a semiconductor substrate 310, an STI (Sallow Trench Isolation) 305, multiple well diffusion layers 321 to 323, multiple resistor elements R1 to R3, a transistor Tr, a current source CS, and wiring layers 340 to 344.

[0049] Semiconductor substrate 310, for example, uses p-type semiconductor substrates fabricated as first conductivity type. - A type of silicon substrate. A Sallow Trench Isolation (STI) 305, serving as a component isolation region, is provided on the surface region of the semiconductor substrate 310. The area outside the STI 305 is defined as the active region. The STI 305 may be an insulating film such as silicon oxide.

[0050] n - The n-type well diffusion layers 321-323, serving as the first impurity diffusion layers of the second conductivity type, are disposed in the active region of the surface area of ​​the semiconductor substrate 310. Multiple well diffusion layers 321-323 are formed, for example, by introducing n-type impurities such as arsenic and phosphorus into the surface region of the semiconductor substrate 310. Furthermore, n... - p - of" - " indicates a relatively low impurity concentration, n" + p + of" + "Indicates a relatively high concentration of impurities."

[0051] Resistive elements R1 to R3 include a second impurity diffusion layer as the first conductivity type. + P-type impurity diffusion layers are formed. Resistive elements R1 to R3 are respectively disposed correspondingly to well diffusion layers 321 to 323 within the surface region of the semiconductor substrate 310. Therefore, well diffusion layers 321 to 323 are respectively disposed around the resistive elements R1 to R3, and the well diffusion layers 321 to 323 are disposed between the resistive elements R1 to R3 and the semiconductor substrate 310. The resistive elements R1 to R3 are formed, for example, by introducing p-type impurities such as boron into the surface region of the semiconductor substrate 310.

[0052] Multiple resistors R1 to R3 are connected in series between the input section IN and the ground GND, which serves as a low-voltage source, via wiring layers 341 to 343, forming a chain resistor. The number of resistors R1 to R3 connected in series can be arbitrary. The potential of the ground GND is, for example, Vss.

[0053] Figure 4The diagram schematically illustrates wiring layers 340-344, which comprise multiple wiring layers disposed on a conductor substrate 310. The multiple wiring layers in the multiple wiring layers may use conductive metals such as copper. Interlayer insulating films, such as silicon oxide films, are provided between the wiring layers of the multiple wiring layers.

[0054] Resistive element R1 is disposed within the well diffusion layer 321, with one end connected to the input section IN and the gate electrode G of transistor Tr. The other end of resistive element R1 is connected to one end of resistive element R2 and the well diffusion layer 322 via wiring layer 341.

[0055] Resistive element R2 is disposed within the well diffusion layer 322, with one end of resistor R2 connected to the other end of resistor R1 and the well diffusion layer 322. The other end of resistor R2 is connected to one end of resistor R3 and the well diffusion layer 323 via wiring layer 342.

[0056] Resistor R3 is disposed within the well diffusion layer 323, with one end of resistor R3 connected to the other end of resistor R2 and the well diffusion layer 323. The other end of resistor R3 is connected to ground GND via wiring layer 343.

[0057] Transistor Tr is, for example, an n-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Furthermore, transistor Tr is a depletion-mode transistor with a negative threshold voltage. For example, the threshold voltage of transistor Tr can be set to -Vt. An n-type impurity, for example, can be introduced into the channel region CH of transistor Tr. Impurities can also be introduced into the gate electrode G to make transistor Tr depletion-mode.

[0058] The gate electrode G of transistor Tr is connected to the input section IN and one end of the resistor element R1 via wiring layer 340. The drain D of transistor Tr is n + A type-n impurity diffusion layer is connected to the voltage source VS. The source S of transistor Tr is n... + A type-type impurity diffusion layer is connected to a constant current source CS and a well diffusion layer 321 via a wiring layer 344. The constant current source CS is connected between the source S of transistor Tr and ground GND. The constant current source CS allows a specific current to flow from transistor Tr to ground GND.

[0059] like Figure 5 As shown, the series-connected resistors R1 to R3 are used to generate the voltage required to divide the input voltage Vinput. For example, the voltage Vinput is used as output OUT1. The node voltage between resistors R1 and R2 is used as output OUT2. The node voltage between resistors R2 and R3 is used as output OUT3.

[0060] At this time, transistor Tr functions as a source follower circuit. It changes the source voltage S by following the voltage Vinput of the input portion IN of the gate electrode G. When the voltage of the gate G of transistor Tr is Vinput, the voltage of the source S of transistor Tr is Vinput + |Vt|. That is, since transistor Tr is a depletion-type transistor with a negative threshold voltage, Vinput + |Vt| can be applied to the well diffusion layer 321 surrounding the resistor element R1. Therefore, a bias voltage (Vinput + |Vt|) higher than the absolute value of the threshold voltage Vinput of the input portion IN is applied to the well diffusion layer 321. In this way, transistor Tr functions as a bias circuit that applies a bias voltage (Vinput + |Vt|) to the well diffusion layer 321. On the other hand, the voltage Vinput of the input portion IN is applied to one end of the resistor element R1 via the wiring layer 340. Therefore, by providing transistor Tr, the voltage (Vinput + Vt) of the well diffusion layer 321 is maintained at a voltage |Vt| that is higher than the absolute value of the threshold voltage of transistor Tr than the voltage Vinput applied to the resistive element R1. Thus, the voltage at n... - Type 321 trap diffusion layer and p + A reverse bias voltage is applied to the pn junction of the resistor element R1, but no forward bias voltage is applied. Therefore, leakage current flowing from resistor element R1 to the well diffusion layer 321 can be suppressed, and the current from the input section IN can flow through resistor element R1 and wiring layer 341 to resistor element R2. As a result, resistor element R1 can fully function as a voltage divider resistor element.

[0061] For example, even if the voltage Vinput at the input section IN drops sharply from 9 volts to 3 volts, the voltage of the well diffusion layer 321 will follow Vinput from (9+Vt) volts to (3+Vt) volts. Therefore, the voltage of the well diffusion layer 321 is maintained at a level higher than the voltage of the resistive element R1 by |Vt|. In this way, even if the voltage Vinput at the input section IN drops sharply, a forward bias will not be applied to the pn junction between the well diffusion layer 321 and the resistive element R1. This suppresses leakage current from the resistive element R1 to the well diffusion layer 321, allowing the resistive element R1 to function fully as a voltage divider resistor, thus improving the reliability of the semiconductor memory device 100a.

[0062] In the first embodiment, transistor Tr is connected only to the well diffusion layer 321, which is biased by a voltage (Vinput + |Vt|). This well diffusion layer 321 corresponds to the resistor R1 connected to the input section IN (closest to the input section IN). No bias circuit (transistor) is provided in the well diffusion layers 322 and 323. This is because, among resistors R1 to R3, resistor R1 receives the largest voltage change (e.g., V1-V2) from the input section IN. Since resistors R2 and R3 are subjected to voltages divided (OUT2, OUT3), the voltage change at the input side of resistors R2 and R3 is smaller than the voltage change at the input side of resistor R1.

[0063] Furthermore, when using the resistor divider circuit 300 in an analog circuit, the resistance ratio of resistors R1 to R3 is sometimes important. In this case, it is necessary to suppress the voltage dependence of the resistance values ​​of resistors R1 to R3. The voltage dependence of the resistor depends on the voltage applied to n. - Type 321 trap diffusion layer and p + The magnitude of the reverse bias voltage at the pn junction of the resistor element R1. When a reverse bias voltage is applied to the pn junction, a depletion layer is generated at the pn junction. The resistance values ​​of resistor elements R1 to R3 are determined by the pn junction voltage. + The amount of depletion layer extended in the resistor elements R1 to R3 increases. Therefore, it is preferable to suppress not only leakage current, but also the change in resistance value of resistor elements R1 to R3 caused by reverse bias voltage.

[0064] Therefore, in this embodiment, the voltage of the well diffusion layers 321-323 is increased by the absolute value of the threshold voltage |Vt| compared to the voltage Vinput. Thus, while avoiding a forward bias state at the pn junction, a minimum required reverse bias voltage is applied to the pn junction, and changes in the resistance of resistors R1-R3 are suppressed. In other words, the resistance values ​​of resistors R1-R3 do not change significantly due to changes in the voltage Vinput. Therefore, the resistor divider circuit 300 of this embodiment is also advantageous for analog circuits.

[0065] Figure 6A This is a graph representing the operation of a resistor divider circuit without a transistor Tr. The vertical axis represents the voltage Vinput, the voltage Vwell1 of the well diffusion layer 321, or the voltage Vr1 of the resistive element R1. The horizontal axis represents time.

[0066] Assuming Figure 6AAs shown, without transistor Tr, that is, without source follower circuitry, the well diffusion layer 321 is connected to the input section IN. Consequently, the voltage Vwell1 of the well diffusion layer 321 becomes almost the same as the voltage Vinput of the input section IN. In this case, when the voltage Vinput decreases from V1 to V2 (V2 < V1) (t0~t2), the voltage Vwell1 of the well diffusion layer 321 decreases from V1 to V2 along with the voltage Vinput of the input section IN. At this time, the voltage Vr1 of the resistor element R1 begins to decrease with a delay from the point when the voltage Vinput of the input section IN begins to decrease. Therefore, as shown during the period t1~t3, the voltage Vr1 of the resistor element R1 is sometimes greater than the voltage Vinput, i.e., the voltage Vwell1 of the well diffusion layer 321. In this case, a forward bias is applied to the pn junction between the well diffusion layer 321 and the resistor element R1, and leakage current flows from the resistor element R1 to the well diffusion layer 321. In addition, whether a forward bias voltage is applied to the pn junction between the well diffusion layer 321 and the resistive element R1 also depends on the slope of the voltage Vinput change or the magnitude of the voltage Vinput change at the input section IN.

[0067] Figure 6B This is a graph illustrating the operation of the resistor voltage divider circuit 300 in this embodiment. In this embodiment, as described above, utilizing the source follower function of transistor Tr, the voltage Vwell1 of the well diffusion layer 321 is set to be higher than the input voltage Vinput by a factor of |Vt| of transistor Tr (Vinput + |Vt|). Therefore, even if the input voltage Vinput decreases from V1 to V2 (t0 to t2), the voltage Vwell1 of the well diffusion layer 321 will decrease from (V1 + |Vt|) to (V2 + |Vt|). Thus, since the voltage Vwell1 of the well diffusion layer 321 is higher than the input voltage Vinput by |Vt|, the voltage Vwell1 is always maintained above the voltage Vr1 of the resistor element R1. Therefore, no forward bias is applied to the pn junction between the well diffusion layer 321 and the resistor element R1, suppressing leakage current from the resistor element R1 to the well diffusion layer 321. As a result, the resistor divider circuit 300 of this embodiment can output the required output voltages OUT1 to OUT3 from the resistor elements R1 to R3.

[0068] In addition, when the voltage Vinput changes significantly and its slope is large, it is sufficient to increase the absolute value of the threshold voltage |Vt| of the transistor Tr accordingly, so that the pn junction between the well diffusion layer 321 and the resistive element R1 is not subjected to a forward bias voltage.

[0069] (Second Implementation)

[0070] Figure 7 This is a schematic cross-sectional view showing an example of the configuration of the resistor voltage divider circuit 300 according to the second embodiment. According to the second embodiment, STI305 is omitted.

[0071] Although STI305 is not provided, since the well diffusion layers 321-323 are sufficiently electrically separated, there is no need to specifically provide STI305. Therefore, the layout area of ​​the resistor divider circuit 300 can be reduced. Other configurations in the second embodiment can be the same as the corresponding configurations in the first embodiment. Therefore, the second embodiment can achieve the same effects as the first embodiment.

[0072] (Third Implementation)

[0073] Figure 8 This is a circuit diagram showing an example of the configuration of the resistor voltage divider circuit 300 in the third embodiment. In the third embodiment, a bias circuit is provided not only in the well diffusion layer 321 closest to the input section IN, but also in the well diffusion layers 322 and 323 immediately following the well diffusion layer 321 (transistors Tr2 and Tr3).

[0074] Since the transistor Tr1 connected to the well diffusion layer 321 has the same configuration as the transistor Tr in the first embodiment, its description is omitted.

[0075] The gate electrode G of transistor Tr2 is connected between resistors R1 and R2. The drain D of transistor Tr2 is n. + A type-n impurity diffusion layer is connected to the voltage source VS. The source S of transistor Tr2 is n... + A type of impurity diffusion layer is connected to the constant current source CS and the well diffusion layer 322.

[0076] Transistor Tr2 functions as a source follower circuit. Transistor Tr2 is also a depletion-type transistor with a negative threshold voltage. Therefore, the well diffusion layer 322 surrounding resistor R2 is subjected to a bias voltage (OUT2 voltage + |Vt2|) that is absolutely higher than the threshold voltage. In this way, transistor Tr functions as a bias circuit that applies a bias voltage to the well diffusion layer 321.

[0077] On the other hand, a voltage of OUT2 is applied to one end of the resistor element R2. Therefore, by providing the transistor Tr2, the voltage of the well diffusion layer 322 is maintained at a voltage (OUT2 voltage + |Vt2|) that is higher than the voltage applied to the resistor element R2 by an absolute value exceeding the threshold voltage of the transistor Tr2. This suppresses the application of a forward bias voltage to the pn junction between the well diffusion layer 322 and the resistor element R2. Consequently, leakage current flowing from the resistor element R2 to the well diffusion layer 322 is suppressed, allowing the resistor element R2 to function effectively as a voltage divider resistor.

[0078] The gate electrode G of transistor Tr3 is connected between resistors R2 and R3. The drain D of transistor Tr3 is n. + A type-n impurity diffusion layer is connected to the voltage source VS. The source S of transistor Tr3 is n... + A type of impurity diffusion layer is connected to the constant current source CS and the well diffusion layer 323.

[0079] Transistor Tr3 also functions as a source follower circuit. Transistor Tr3 is also a depletion-type transistor with a negative threshold voltage. Therefore, the well diffusion layer 323 surrounding resistor R3 is subjected to a bias voltage (OUT3 voltage +|Vt3|) that is absolutely higher than the threshold voltage. In this way, transistor Tr3 functions as a bias circuit that applies a bias voltage to the well diffusion layer 323.

[0080] On the other hand, a voltage of OUT3 is applied to one end of the resistor element R3. Therefore, by providing the transistor Tr3, the voltage of the well diffusion layer 323 is maintained at a voltage (OUT3 voltage + |Vt3|) that is higher than the voltage applied to the resistor element R3 by an absolute value exceeding the threshold voltage of the transistor Tr3. This suppresses the application of a forward bias voltage to the pn junction between the well diffusion layer 323 and the resistor element R3. Consequently, leakage current flowing from the resistor element R3 to the well diffusion layer 323 is suppressed, and the resistor element R3 can function fully as a voltage divider resistor.

[0081] Transistors Tr1 to Tr3 can be depletion-type transistors, and their threshold voltages can be the same or different from each other.

[0082] For example, the third embodiment is more effective when the voltages of the outputs OUT2 and OUT3 change significantly as the voltage Vinput of the input section IN changes.

[0083] In addition, if the voltage of output OUT2 changes significantly with the change of the voltage of input IN Vinput, but the voltage of output OUT3 changes less significantly, transistor Tr3 can be omitted, and only transistors Tr1 and Tr2 can be set.

[0084] In the described embodiment, the transistor Tr uses an n-type depletion-type transistor. However, by changing the conductivity of the semiconductor substrate 310, the well diffusion layers 321-323, and the resistive elements R1-R3, and reversing the relationship between the voltages Vinput, Vsup, and ground GND, the transistor Tr can also use a p-type depletion-type transistor.

[0085] Several embodiments of the present invention have been described, but these embodiments are merely examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included not only in the scope or spirit of the invention, but also in the scope of the invention as described in the claims and its equivalents.

[0086] [Explanation of Symbols]

[0087] 100a Semiconductor Memory Device

[0088] 300Ω resistor voltage divider circuit

[0089] 310 Semiconductor Substrate

[0090] 305 STI

[0091] 321-323 Trap diffusion layer

[0092] Resistor elements R1 to R3

[0093] Tr transistor

[0094] CS current source

[0095] 340-344 wiring layers.

Claims

1. A semiconductor device comprising: Semiconductor substrate of the first conductivity type; A first impurity diffusion layer of the second conductivity type is disposed on the surface region of the semiconductor substrate; A first resistive element includes a second impurity diffusion layer of a first conductivity type and has an input portion, the first resistive element being disposed in the first impurity diffusion layer of the second conductivity type; The second resistive element includes a third impurity diffusion layer of a first conductivity type that is separated from the first impurity diffusion layer of the second conductivity type; A transistor, outside the first impurity diffusion layer of the second conductivity type and the third impurity diffusion layer of the first conductivity type, and comprising: The gate is connected to the input section. The source electrode is connected to the first impurity diffusion layer of the second conductivity type, and The drain is connected to a voltage source with a voltage higher than that of the input section; and A current source, connected to the source electrode; in The first resistor element and the second resistor element are connected in series between the input section and the output section, and the voltage of the output section is lower than the voltage of the voltage source.

2. The semiconductor device of claim 1, wherein the transistor comprises a field-effect transistor.

3. The semiconductor device of claim 1, wherein the semiconductor device comprises a memory device.

4. The semiconductor device according to claim 3, further comprising: A stack comprising alternating layers of insulating and conductive layers disposed above the transistor.

5. The semiconductor device of claim 4, wherein the insulating layer comprises silicon oxide and the conductive layer comprises tungsten.

6. The semiconductor device according to claim 1, further comprising: An interlayer insulating film is disposed on the transistor, the first resistive element, and the second resistive element.

7. The semiconductor device of claim 6, wherein the interlayer insulating film comprises silicon oxide.

8. The semiconductor device according to claim 6, further comprising: Wiring is disposed in the interlayer insulating film and electrically connected to the transistor.

9. The semiconductor device of claim 1, wherein the transistor is a depletion-type transistor.

10. The semiconductor device of claim 9, wherein the transistor has a negative threshold voltage.

11. The semiconductor device according to claim 1 or 9, wherein the first resistive element and the second resistive element are disposed on the surface region of the semiconductor substrate.

12. The semiconductor device according to claim 11, further comprising: shallow trench isolation between the first resistive element and the second resistive element.

13. The semiconductor device according to claim 11, further comprising: a plurality of transistors configured to bias the first resistive element and the second resistive element respectively.

14. The semiconductor device according to claim 1 or 9, wherein the source and drain of the transistor are of a second conductivity type.

15. The semiconductor device according to claim 1 or 9, wherein the voltage of the first impurity diffusion layer of the second conductivity type is higher than the voltage of the input portion by an absolute value of the threshold voltage of the transistor.

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