Integrated chip and method of forming the same

Abstract

In some embodiments, the present embodiments relate to an integrated chip including a gate electrode disposed over a substrate and a gate dielectric layer disposed over the gate electrode. The gate dielectric layer includes a ferroelectric material. An active structure is disposed over the gate dielectric layer, and the active structure includes a semiconductor material. A source contact and a drain contact are disposed over the active structure. A capping structure is disposed over the active structure and between the source contact and the drain contact, wherein the capping structure includes a first metallic material.

Description

Technical Field

[0001] The embodiments of the present invention relate to semiconductor technology, and particularly to integrated chips and methods for forming the same. Background Technology

[0002] Many modern electronic devices incorporate non-volatile memory. Non-volatile memory is electronic memory that can store data even when power is off. A promising candidate for next-generation non-volatile memory is ferroelectric random-access memory (FeRAM). Ferroelectric RAM has a relatively simple structure and is compatible with the fabrication processes of complementary metal-oxide-semiconductor (CMOS) logic and thin-film transistors. Summary of the Invention

[0003] In some embodiments, an integrated chip is provided, the integrated chip including a gate electrode disposed above a substrate; a gate dielectric layer disposed above the gate electrode, the gate dielectric layer comprising a ferroelectric material; an active structure disposed above the gate dielectric layer, the active structure comprising a semiconductor material; a source contact and a drain contact disposed above the active structure; and a cover structure disposed above the active structure and between the source contact and the drain contact, wherein the cover structure comprises a first metal material.

[0004] In some other embodiments, an integrated chip is provided, the integrated chip including a gate electrode disposed above a substrate; a gate dielectric layer disposed above the gate electrode, wherein the gate dielectric layer comprises a ferroelectric material; an active structure disposed above the gate dielectric layer; a source contact and a drain contact disposed above the active structure; and a cover structure disposed above the active structure and between the source contact and the drain contact, wherein the cover structure comprises a first metal material having a higher affinity for oxygen than the metal in the active structure.

[0005] In other embodiments, a method for forming an integrated chip is provided, the method comprising forming a gate electrode over a substrate; forming a gate dielectric layer over the gate electrode, the gate dielectric layer comprising a ferroelectric material; forming an active structure over the gate dielectric layer; forming a first metal layer over the active structure; removing a peripheral portion of the first metal layer to form a cover structure over the active structure; and forming a source contact and a drain contact over the active structure, wherein the cover structure is laterally disposed between the source contact and the drain contact. Attached Figure Description

[0006] The embodiments of the present invention can be better understood from the following detailed description and accompanying drawings. It should be noted that, according to industry standard practice, the various features shown in the drawings are not necessarily drawn to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity.

[0007] Figure 1 This diagram shows a cross-sectional view of some embodiments of a field-effect transistor (FET) ferroelectric random access memory (FeRAM) device, which includes a cover structure disposed above an active structure, wherein the bottom layer of the active structure includes a cocktail layer.

[0008] Figure 2 Enlarged cross-sectional schematic diagrams showing some embodiments of the microstructure of the hybrid layer.

[0009] Figure 3 This diagram shows a cross-sectional view of some other embodiments of a field-effect transistor ferroelectric random access memory device, which includes a cover structure disposed above an active structure, wherein the bottom layer of the active structure includes a hybrid layer.

[0010] Figure 4 and Figure 5 This diagram shows a cross-sectional view of some embodiments of a field-effect transistor ferroelectric random access memory device, which includes a cover structure disposed above an active structure.

[0011] Figure 6 The diagram shows a cross-sectional view of some embodiments of an integrated chip, which includes a field-effect transistor ferroelectric random access memory device having a cover structure disposed above an active structure and the field-effect transistor ferroelectric random access memory device being embedded in an interconnect structure.

[0012] Figure 7-20 Various views and schematic diagrams showing some embodiments of a method for forming a cover structure over the active structure of a field-effect transistor ferroelectric random access memory device.

[0013] Figure 21 Display corresponding to Figure 6-20 The flowchart shows some embodiments of a method for forming a cover structure over the active structure of a field-effect transistor ferroelectric random access memory device.

[0014] Explanation of reference numerals in the attached figures:

[0015] 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000A, 1100A, 1200A, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000: Schematic cross-section

[0016] 102: Base

[0017] 104: Dielectric layer

[0018] 106: Gate electrode

[0019] 108: Gate dielectric layer

[0020] 110: Active Structure

[0021] 110b: Lowest level

[0022] 110t: Top layer

[0023] 110s: Top surface

[0024] 112: Hybrid Layer

[0025] 114: First Active Layer

[0026] 116: Interconnect dielectric layer

[0027] 118: Source / Drain Contact

[0028] 120: Second Active Layer

[0029] 122: Covering Structure

[0030] 124: First metal layer

[0031] 128: Diffusion Zone

[0032] 202: First Materials Zone

[0033] 204: Second Material Zone

[0034] 302: Massive basal layer

[0035] 304: Active basal layer

[0036] 326: Second metal layer

[0037] 402: Lower part

[0038] 502: Third Active Layer

[0039] 602: Interconnection Structure

[0040] 604a: First Field-Effect Transistor Ferroelectric Random Access Memory Device

[0041] 604b: Second Field-Effect Transistor Ferroelectric Random Access Memory Device

[0042] 606: Etching Stop Layer

[0043] 608: Interconnector

[0044] 618: Interconnection Point

[0045] 901: Wafer Clamp

[0046] 902: Housing

[0047] 908: First Gas Inlet Pipeline

[0048] 910: First container shell

[0049] 912: Inert gas source

[0050] 914: Second gas inlet pipeline

[0051] 916: Oxygen source

[0052] 918: Second container shell

[0053] 919: Gas outlet pipeline

[0054] 920: First precursor substrate

[0055] 922: First solid precursor

[0056] 924: Second precursor substrate

[0057] 926: Second solid precursor

[0058] 928: Third precursor substrate

[0059] 930: Third solid precursor

[0060] 932: Third container shell

[0061] 934: Arrow

[0062] 936: Door Structure

[0063] 1000B, 1000C, 1100B, 1200B: Timing Diagram

[0064] 1002: Remarks

[0065] 1004: Step One

[0066] 1006: Step Two

[0067] 1008: Step Three

[0068] 1010: Step Four

[0069] 1012: Step Five

[0070] 1014: Step Six

[0071] 1302: First continuous metal layer

[0072] 1304: Second continuous metal layer

[0073] 1402: Mask structure

[0074] 1802: Opening

[0075] 2100: Method

[0076] 2102, 2104, 2106, 2108, 2110, 2112: Actions

[0077] A: Square

[0078] t1: First thickness

[0079] t2: Second thickness

[0080] t3: Third thickness Detailed Implementation

[0081] It is important to understand that the following disclosure provides many different embodiments or examples for implementing different components of the provided subject. Specific examples of the various components and their arrangements are described below to simplify the description of the disclosure. Of course, these are merely examples and are not intended to limit the invention. For example, the following disclosure describes forming a first component on or above a second component, indicating that it includes embodiments where the formed first component and the second component are in direct contact, as well as embodiments where additional components may be formed between the first component and the second component, so that the first component and the second component may not be in direct contact. Furthermore, different examples in the disclosure may use repeated reference numerals and / or words. These repeated numerals or words are for simplification and clarity purposes and are not intended to limit the relationships between the various embodiments and / or the described appearance structures.

[0082] Furthermore, to facilitate the description of the relationship between one element or component and another element(s)(s) in the accompanying drawings, spatially related terms such as "below," "under," "lower," "above," "upper," and similar terms may be used. In addition to the orientations shown in the drawings, spatially related terms also cover different orientations of the device during use or operation. The device may also be otherwise positioned (e.g., rotated 90 degrees or located in other orientations), and the descriptions using the spatially related terms will be interpreted accordingly.

[0083] A thin-film transistor (TFT) is a field-effect transistor (FET) containing an active structure. When a sufficient signal (e.g., voltage, current) is applied to the source, drain, and gate structures of the TFT, the active structure is "turned on," allowing moving charge carriers to pass through it. In some examples, the active structure comprises a transparent semiconductor material, such as indium gallium zinc oxide (IGZO), amorphous silicon, or other materials suitable for optical applications. In a bottom-gate TFT, the gate electrode is located below the active structure, and the source and drain contacts are located above it. A gate dielectric layer separates the gate electrode from the active structure. In some examples, the gate dielectric layer comprises a ferroelectric material, making the TFT function as a ferroelectric random access memory (FeRAM) device. Because the crystal structure of the ferroelectric material changes when an electric field is present, the ferroelectric layer can store data values ​​based on reversible switching between polarization states.

[0084] To form a field-effect transistor ferroelectric random access memory device, a ferroelectric layer is formed above the gate electrode. Next, an active structure is formed above the ferroelectric layer, and source and drain contacts are formed above the active structure. In some embodiments, depending on which materials of the active structure directly contact the gate dielectric layer, defects such as oxygen vacancies and surface states (i.e., excess charge) may exist at the interface between the active structure and the gate dielectric layer, which can reduce carrier mobility in the active structure. Furthermore, since the top surface of the active structure is exposed to air in the surrounding environment, these defects can form on the top surface of the active structure. These defects on the top surface of the active structure may also include oxygen vacancies and surface states, which can increase electron scattering and reduce carrier mobility.

[0085] Various embodiments of the present invention relate to forming a cover structure above the active structure and between the source and drain contacts to reduce defects at the top surface of the active structure and increase the carrier mobility of the active structure, thereby improving the overall performance of the field-effect transistor ferroelectric random access memory device. In some such embodiments, the top layer of the active structure includes a first metal oxide material with high bonding energy, which reduces oxygen vacancies at the top surface of the active structure. Furthermore, in some embodiments, the cover structure includes one or more metal materials with strong oxidizing capabilities, which reduces oxygen vacancies at the top surface of the active structure. Furthermore, in some embodiments, the bottom layer of the active structure may include a mixture of a first metal oxide material and a second metal oxide material, such that the first and second metal oxide materials directly contact the ferroelectric layer to increase carrier mobility and reduce surface states at the interface between the active structure and the ferroelectric layer. As defects in the active structure (e.g., oxygen vacancies, surface states, weakly bonded oxygen) are reduced, the carrier mobility of the active structure increases, which increases the switching speed and reliability of the field-effect transistor ferroelectric random access memory device.

[0086] Figure 1 A cross-sectional schematic diagram 100 shows some embodiments of a field-effect transistor (FET) ferroelectric random access memory (FeRAM) device, which includes a cover structure disposed above an active structure.

[0087] Figure 1 A cross-sectional schematic diagram 100 includes a gate electrode 106 disposed above a substrate 102. In some embodiments, a dielectric layer 104 is disposed between the gate electrode 106 and the substrate 102. In some embodiments, a gate dielectric layer 108 is disposed above the gate electrode 106. In these embodiments, the gate dielectric layer 108 includes a ferroelectric material configured to store data states by changing crystal structure orientation, thereby exposing resistance to different voltage biases.

[0088] In some embodiments, an active structure 110 is disposed above a gate dielectric layer 108. In some embodiments, the active structure 110 includes a semiconductor material that can be "turned on" when a sufficient bias voltage is applied to the active structure 110 to form a channel region for moving charge carriers. The channel region for charge carriers can be controlled to read data from or write data to the gate dielectric layer 108. In some embodiments, the bottom layer 110b of the active structure 110 includes a hybrid layer 112 (the hybrid layer 112 includes a mixture of a first material and a second material) and a first active layer 114 disposed above the hybrid layer 112 (the first active layer 114 includes a third material different from the first and second materials). In some embodiments, the active structure 110 includes a stack of alternating hybrid layers 112 and first active layers 114.

[0089] In some embodiments, the source / drain contact 118 is disposed above the active structure 110. In some embodiments, the source / drain contact 118 is disposed in the interconnect dielectric layer 116 and extends through the interconnect dielectric layer 116 to contact the top layer 110t of the active structure 110.

[0090] In some embodiments, the first, second, and third materials of the active structure 110 are metal oxides. In some embodiments, the third material of the first active layer 114 comprises a more crystalline material than the first and second materials. Therefore, the first active layer 114 is spaced apart from the gate dielectric layer 108; otherwise, the interface between the third material of the first active layer 114 and the gate dielectric layer 108 would be too rough and have potential adhesion and structural problems on the gate dielectric layer 108. In some embodiments, the first material of the hybrid layer 112 comprises a stronger and more negative bond energy than the second material. In some embodiments, the bond energy may depend on the Ellingham diagram of the metal oxides, which shows the relationship between the Gibbs free energy of various metal oxides and temperature.

[0091] Because the first material has a stronger bond energy, there are fewer defects (e.g., oxygen vacancies) and fewer surface states (i.e., excess charge) at the interface between the first material of the hybrid layer 112 and the gate dielectric layer 108. In some embodiments, the second material of the hybrid layer 112 has a higher mobility than the first material of the hybrid layer 112 due to the weaker bond energy and the increase in metal ions. Therefore, the mobile charge carriers at the interface between the hybrid layer 112 and the gate dielectric layer 108 can have a higher mobility. For these reasons, in some embodiments, the hybrid layer 112 comprises a mixture of the first and second materials to reduce defects, but also to increase the carrier mobility at the interface between the bottom layer 110b of the active structure 110 and the gate dielectric layer 108, thereby increasing the reliability and switching speed of the field-effect transistor ferroelectric random access memory device.

[0092] In some embodiments, the top layer 110t of the active structure 110 includes a second active layer 120, which includes the first material but does not include a second or third material due to the high bond energy of the first material. In some such embodiments, the high bond energy of the first material reduces defects such as oxygen vacancies at the top surface 110s of the active structure 110. In some embodiments, the top layer 110t of the active structure 110 is disposed directly above one of the hybrid layers 112. Furthermore, a cover structure 122 is disposed above the active structure 110 and between the source / drain contacts 118 to reduce defects such as surface states and oxygen vacancies at the top surface 110s of the active structure 110. In some embodiments, the cover structure 122 extends through the interconnect dielectric layer 116 to contact the active structure 110.

[0093] In some embodiments, the overlay structure 122 includes a first metal layer 124, which comprises a first metallic material. In some embodiments, the first metallic material of the first metal layer 124 comprises one or more metals with strong oxidizing properties. In other words, the first metallic material has a high affinity for oxygen. In some embodiments, the oxygen affinity can be determined by a metal oxide Ellingham plot, which shows the relationship between the Gibbs free energy of formation of various metal oxides and temperature; metal oxides with a large negative Gibbs free energy indicate that the metal has a high affinity for oxygen. In some embodiments, the Gibbs free energy can be measured by X-ray photoluminescence spectroscopy, X-ray fluorescence, photoluminescence, or some other suitable measurement technique.

[0094] In some embodiments, the first metal layer 124 has a higher affinity for oxygen or a larger negative Gibbs free energy on the Ellingham diagram compared to the metal oxide material of the active structure 110. Therefore, when the first metal layer 124 is formed directly above the top layer 110t of the active structure 110, the first metal material can diffuse into the active structure 110 and bond with the weakly bonded oxygen of the active structure 110 to reduce defects in the active structure 110 (e.g., oxygen vacancies, surface states, weakly bonded oxygen) and increase the carrier mobility of the active structure 110. In some such embodiments, a diffusion region 128 may be disposed in the upper region of the active structure 110 and below the first metal layer 124 of the overlay structure 122, the first metal layer 124 comprising the first metal material with bonded oxygen.

[0095] Therefore, in some embodiments, the overlay structure 122 reduces defects (e.g., oxygen vacancies, surface states, weakly bonded oxygens) near the topmost surface 110s of the active structure 110 to increase the carrier mobility of the active structure 110, thereby increasing the switching speed of the entire field-effect transistor ferroelectric random access memory device. With the increased switching speed, the field-effect transistor ferroelectric random access memory device can be "turned on" more quickly because mobile charge carriers can move more easily through the active structure. Therefore, data can be stored more easily and reliably to or from the gate dielectric layer 108.

[0096] Figure 2 Enlarged cross-sectional schematic diagram 200 showing some embodiments of the microstructure of the hybrid layer. In some embodiments, cross-sectional schematic diagram 200 corresponds to... Figure 1 Block A.

[0097] As shown in the cross-sectional schematic diagram 200, in some embodiments, the hybrid layer 112 includes a first material region 202 and a second material region 204. In some embodiments, the second material region 204 is embedded in the first material region 202. In other embodiments, the first material region 202 may be embedded in the second material region 204. However, in some embodiments, the hybrid layer 112 comprises a mixture of the first material and the second material, and the enlarged cross-sectional schematic diagram 200 shows the first material region 202 including the first material and the second material region 204 including the second material.

[0098] In some embodiments, the first material includes gallium oxide, hafnium oxide, zirconium oxide, titanium oxide, aluminum oxide, tantalum oxide, strontium oxide, barium oxide, scandium oxide, magnesium oxide, lanthanum oxide, gadolinium oxide, or some other suitable metal oxide. In some embodiments, the second material includes indium oxide, tin oxide, arsenic oxide, zinc oxide, or the like. In some embodiments, the third material includes zinc oxide. Thus, for example, in some embodiments, the first material includes gallium oxide, the second material includes indium oxide, and the third material includes zinc oxide, such that the active structure includes indium gallium zinc oxide (IGZO), which is a semiconductor material. In some other embodiments, the active structure ( Figure 1 The active structure 110 may include a semiconductor material formed by a combination of tin gallium zinc oxide, indium hafnium zinc oxide, or some other suitable first, second and third materials.

[0099] In some such embodiments, the first material region 202 is substantially amorphous, and the second material region 204 is substantially amorphous. Because the first material region 202 and the second material region 204 are amorphous, the amount of material between the mixed layer 112 and the gate dielectric layer can be reduced. Figure 1 The roughness and electron scattering at the interface between the gate dielectric layer 108. Furthermore, in some embodiments, since the first material region 202 and the second material region 204 are in direct contact with the gate dielectric layer (… Figure 1 The gate dielectric layer 108 can reduce defects and increase carrier mobility, which can increase the "on" current and switching speed of the field-effect transistor ferroelectric random access memory device.

[0100] Figure 3 A cross-sectional schematic diagram 300 shows some other embodiments of a field-effect transistor ferroelectric random access memory device, which includes a cover structure disposed above an active structure.

[0101] In some embodiments, substrate 102 includes silicon overlaid on an insulating substrate, such that dielectric layer 104 is disposed between bulk substrate layer 302 and active substrate layer 304. In some embodiments, the top layer 110t of active structure 110 is located directly above one of the first active layers 114. It should be understood that active structure 110 may include a layer larger than... Figure 3 Show more or fewer layers.

[0102] In some embodiments, the gate dielectric layer 108 has a first thickness t1 in the range of, for example, about 5 nm to about 20 nm. In some embodiments, the active structure 110 may have a second thickness t2 in the range of, for example, about 5 nm to about 15 nm. In some embodiments, each hybrid layer 112, the first active layer 114, and / or the second active layer 120 has a third thickness t3 in the range of, for example, about 5 nm to about 20 nm. With the agreement In some embodiments, the ratio of the first material to the second material in the hybrid layer 112 is in the range from about 0.1 to about 0.99.

[0103] In some embodiments, the gate electrode 106 may comprise, for example, titanium nitride, aluminum, tungsten, copper, or some other suitable conductive material. In some embodiments, the gate dielectric layer 108 comprises a ferroelectric material, such as strontium bismuth tantalate, lead zirconium titanate, zinc hafnium oxide, zirconium hafnium oxide, doped hafnium oxide, or the like. In some embodiments, the gate electrode 106 may have a thickness in the range of, for example, about 10 nm to about 20 nm. In some embodiments, the source / drain contact 118 may comprise, for example, aluminum, tungsten, copper, tantalum, titanium, or some other suitable conductive material.

[0104] Furthermore, in some embodiments, the cover structure 122 comprises aluminum, calcium, scandium, yttrium, niobium, tantalum, chromium, iron, titanium, silicon, hafnium, zirconium, titanium, strontium, barium, magnesium, lanthanum, gadolinium, combinations thereof, and / or some other suitable metal or semiconductor material having strong oxidizing properties (i.e., high affinity for oxygen). In some embodiments, the cover structure 122 has a thickness of, for example, approximately With the agreement Within the range between. In some embodiments, the overlay structure 122 further includes a second metal layer 326, which comprises a second metal material different from the first metal material of the first metal layer 124. For example, in some embodiments, the first metal layer 124 may comprise calcium, and the second metal layer 326 may comprise aluminum. In some such embodiments, the diffusion region 128 of the active structure 110 may comprise calcium oxide. In some embodiments, the first metal layer 124 is a single layer formed by atomic layer deposition (ALD). In some other embodiments, the first metal layer 124 comprises multiple layers of the same material formed by atomic layer deposition. In some embodiments, the second metal layer 326 is a single layer formed by atomic layer deposition. In some other embodiments, the second metal layer 326 comprises multiple layers of the same material formed by atomic layer deposition. However, in some embodiments, the overlay structure 122 includes one or more layers and / or alloys of metallic material configured to directly contact the topmost surface 110s of the active structure 110 to reduce defects in the active structure 110 (e.g., oxygen vacancies, surface states, weakly bonded oxygen) and improve the performance of the field-effect transistor ferroelectric random access memory device.

[0105] Figure 4 A cross-sectional schematic diagram 400 shows some embodiments of a field-effect transistor ferroelectric random access memory device, which includes a cover structure located above an active structure.

[0106] In some embodiments, the active structure 110 includes a mixture of a first material, a second material, and a third material over the substrate 102. Therefore, in some embodiments, the active structure 110 includes a lower portion 402 without a defining layer. In some other embodiments, the lower portion 402 may include a single semiconductor material, such as silicon. In some embodiments, a second active layer 120 is disposed directly above the lower portion 402 of the active structure 110 and includes the first material. In some embodiments, the lower portion 402 is disposed directly above the gate dielectric layer 108. In some other embodiments, a hybrid layer ( Figure 1 The hybrid layer 112 can be disposed between the lower part 402 of the active structure 110 and the gate dielectric layer 108.

[0107] In some embodiments, the diffusion region 128 of the active structure 110 extends below the top layer 110t of the active structure 110. In some other embodiments, the diffusion region 128 extends into the top layer 110t, but does not extend below the top layer 110t of the active structure 110 (see [reference]). Figure 3 ).

[0108] Furthermore, in some embodiments, the top surface of the cover structure 122 is narrower than the bottom surface of the cover structure 122. In some such embodiments, the cover structure 122 may be formed by a deposition process and a subsequent patterning process prior to the formation of the interconnect dielectric layer 116.

[0109] Figure 5 A cross-sectional schematic diagram 500 shows some other embodiments of a field-effect transistor ferroelectric random access memory device, which includes a cover structure located above an active structure.

[0110] In some embodiments, the active structure 110 includes a stack of a first active layer 114, a second active layer 120, and a third active layer 502 over the gate dielectric layer 108. In some such embodiments, the first active layer 114, the second active layer 120, and the third active layer 502 may be arranged, for example, with the first active layer 114 disposed over the second active layer 120, and the third active layer 502 disposed over the first active layer 114. It should be understood that, with Figure 5 The different arrangements of the first active layer 114, the second active layer 120, and the third active layer 502 shown are also within the scope of this embodiment of the invention.

[0111] In some embodiments, the first active layer 114 may include a third material, the second active layer 120 may include a first material, and the third active layer 502 may include a second material. In other words, in some embodiments, no layer of the active structure 110 includes a mixture of metal oxides; instead, each layer of the active structure 110 includes a single metal oxide. In some other embodiments, the bottom layer 110b of the active structure 110 may include a hybrid layer (…). Figure 1 A hybrid layer 112 is used to increase carrier mobility at the interface between the active structure 110 and the gate dielectric layer 108.

[0112] In some embodiments, the top layer 110t of the active structure 110 includes a second active layer 120, which includes a first material. In some embodiments, the top layer 110t of the active structure 110 is disposed directly above one of the first active layers 114 or directly above one of the third active layers 502.

[0113] Furthermore, in some embodiments, the top surface of the cover structure 122 is wider than the bottom surface of the cover structure 122. In some such embodiments, the cover structure 122 can be formed by a patterning process and a subsequent deposition process after the interconnect dielectric layer 116 is formed.

[0114] Figure 6 A cross-sectional schematic diagram 600 shows some embodiments of an integrated chip, including a field-effect transistor ferroelectric random access memory device embedded in an interconnect structure.

[0115] In some embodiments, field-effect transistor ferroelectric random access memory (FETs) are disposed in an interconnect structure 602, which is disposed above a substrate 102. In some such embodiments, FETs (e.g., a first FET ferroelectric random access memory device 604a and a second FET ferroelectric random access memory device 604b) are disposed in a back-end-of-line (BEOL) portion of an integrated chip, wherein the back-end portion of the integrated chip is disposed above a front-end-of-line (FEOL) portion of the integrated chip. In some embodiments, FETs (e.g., a first FET ferroelectric random access memory device 604a and a second FET ferroelectric random access memory device 604b) are electrically coupled to means in the front-end portion of the integrated chip. In some embodiments, the front end portion of the integrated chip includes at least one transistor disposed in and / or above the substrate 102, such as a metal-oxide-semiconductor field-effect transistor (MOSFET), a fin field-effect transistor (finFET), a gate all-around field-effect transistor (GAAFET), or some other type of transistor device.

[0116] In some embodiments, the interconnect structure 602 includes interconnect points 618 and interconnect lines 608 disposed in the interconnect dielectric layer 116 and the etch stop layer 606. In some embodiments, the interconnect points 618 and interconnect lines 608 may include, for example, aluminum, tungsten, copper, tantalum, titanium, or some other suitable conductive material. In some embodiments, the interconnect dielectric layer 116 may include, for example, nitrides (e.g., silicon nitride, silicon oxynitride), carbides (e.g., silicon carbide), oxides (e.g., silicon oxide), borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), low dielectric constant oxides (e.g., carbon-doped oxides, SiCOH), or the like. In some embodiments, the etch stop layer 606 may include, for example, silicon carbide, silicon nitride, or some other suitable dielectric material.

[0117] like Figure 6As shown, a first field-effect transistor ferroelectric random access memory device 604a and a second field-effect transistor ferroelectric random access memory device 604b are disposed in an interconnect structure 602. In some embodiments, an interconnection point 618 is disposed above and coupled to the active structure 110, such that the interconnection point 618 serves as the source / drain contact of the field-effect transistor ferroelectric random access memory device. Figure 5 (Source / drain contact 118). In some embodiments, as shown in the first field-effect transistor ferroelectric random access memory device 604a, the gate electrode 106 is disposed above one of the interconnects 608. In other embodiments, the gate electrode 106 may be disposed above one of the interconnects 618. In some embodiments, as shown in the second field-effect transistor ferroelectric random access memory device 604b, the gate electrode 106 is omitted, and the gate dielectric layer 108 is disposed directly above one of the interconnects 608 of the interconnect structure 602.

[0118] In some embodiments, the cover structure 122 is not directly coupled to either the interconnect 608 or the interconnect point 618. In some other embodiments, the cover structure 122 may be coupled to either the interconnect 608 or the interconnect point 618 to ground the cover structure 122. In some such other embodiments, grounding the cover structure 122 may improve the switching capability of the gate dielectric layer 108 between polarization states for memory storage.

[0119] In some embodiments, since the field-effect transistor ferroelectric random access memory devices (e.g., the first field-effect transistor ferroelectric random access memory device 604a and the second field-effect transistor ferroelectric random access memory device 604b) have small vertical dimensions, the field-effect transistor ferroelectric random access memory devices can be integrated into the interconnect structure 602 of the integrated chip, and the field-effect transistor ferroelectric random access memory devices can be controlled through the network of interconnect lines 608 and interconnection points 618 of the interconnect structure 602 to store data in the gate dielectric layer 108.

[0120] Figure 7-20 Various views and cross-sectional schematic diagrams 700-2000 illustrating some embodiments of a method for forming a field-effect transistor ferroelectric random access memory (FET) device, the FET device including a cover structure disposed above an active structure to reduce defects in the active structure and increase the switching speed and reliability of the overall FET device. Although Figure 7-20 The description concerns the method, but it should be understood that... Figure 7-20 The displayed structure is not limited to this method, but exists independently as a structure independent of the method.

[0121] like Figure 7As shown in the cross-sectional schematic diagram 700, in some embodiments, a gate electrode 106 is formed over a substrate 102. In various embodiments, the substrate 102 may include any type of semiconductor body (e.g., silicon / complementary metal-oxide-semiconductor body, SiGe, silicon-on-insulator), such as a semiconductor wafer or one or more grains on a wafer, and any other type of semiconductor and / or epitaxial layers formed on the semiconductor and / or other associated elements. In some other embodiments, the substrate 102 may include a transparent material, such as glass for optical applications. Figure 7 In the cross-sectional schematic diagram 700, the substrate 102 is a silicon-on-insulator (SOI) substrate including a dielectric layer 104 disposed above a bulk substrate layer 302 and below an active substrate layer 304. In some such embodiments, the bulk substrate layer 302 and the active substrate layer 304 may comprise, for example, silicon, germanium, or some other suitable semiconductor material. In some embodiments, the dielectric layer 104 includes silicon dioxide, silicon oxynitride, or some other suitable dielectric layer.

[0122] In some embodiments, the gate electrode 106 is formed on the substrate 102 by a deposition process (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), direct current electrosputtering, etc.). In some embodiments, the gate electrode 106 comprises titanium nitride, aluminum, tungsten, copper, or some other suitable conductive material. In some embodiments, the gate electrode 106 has a thickness in the range of, for example, about 10 nm to about 20 nm.

[0123] like Figure 8 As shown in the cross-sectional schematic diagram 800, in some embodiments, a gate dielectric layer 108 is formed above the gate electrode 106. In some embodiments, the gate dielectric layer 108 is formed by atomic layer deposition in a cavity at a temperature ranging from, for example, about 200°C to about 400°C. In some other embodiments, the gate dielectric layer 108 is formed by other deposition processes (e.g., physical vapor deposition, chemical vapor deposition, etc.). In some embodiments, the gate dielectric layer 108 comprises a ferroelectric material, such as strontium bismuth tantalate, lead zirconium titanate, hafnium zinc oxide, hafnium zirconium oxide, doped hafnium oxide, or the like. For example, in some embodiments, the gate dielectric layer 108 comprises hafnium zirconium oxide, wherein the atomic ratio of hafnium to zirconium is about 1 to 1. In some embodiments, the gate dielectric layer 108 has a first thickness t1 ranging from, for example, about 5 nm to about 20 nm.

[0124] like Figure 9As shown in the cross-sectional schematic diagram 900, in some embodiments, the substrate 102 is transferred onto a wafer chuck 901 within a reaction chamber defined by the housing 902. In some embodiments, the reaction chamber is an atomic layer deposition (ALD) chamber, a low-pressure vessel, and / or the like. In some embodiments, respectively in Figure 7 and Figure 8 During the formation of the gate electrode 106 and / or the gate dielectric layer 108, the substrate 102 is already in the reaction chamber. In some embodiments, a first gas inlet line 908 passes through the housing 902, such that a precursor container defined by a container housing (e.g., a first container housing 910, a second container housing 918, a third container housing 932) is coupled to the reaction chamber via the first gas inlet line 908. In some embodiments, a second gas inlet line 914 passes through the housing 902, such that an oxygen source 916 can enter the reaction chamber. In some embodiments, a gas outlet line 919 passes through the housing 902, such that various gases can exit the reaction chamber during the deposition process.

[0125] In some embodiments, a first precursor container defined by a first container housing 910, a second precursor container defined by a second container housing 918, and a third precursor container defined by a third container housing 932 are coupled to a first gas inlet line 908 and an inert gas source 912. In other embodiments, more or fewer than three precursor containers may be coupled to a reaction chamber. In some embodiments, the inert gas source 912 may be “connected” to allow inert gas to enter one or more precursor containers to activate the precursor in each precursor container, allowing precursor gas to enter the reaction chamber through the first gas inlet line 908 to form a layer on the gate dielectric layer 108. In some embodiments, each precursor container includes a gate structure 936, which can be controlled to open or close via control circuitry, as indicated by arrow 934, to allow or prevent inert gas from entering the precursor container from the inert gas source 912, respectively.

[0126] In some embodiments, a first precursor container includes a first precursor substrate 920, which holds a first solid precursor 922 in a recess. In some embodiments, a second precursor container includes a second precursor substrate 924, which holds a second solid precursor 926 in a recess. In some embodiments, a third precursor container includes a third precursor substrate 928, which holds a third solid precursor 930 in a recess. In some embodiments, the first solid precursor 922, the second solid precursor 926, and the third solid precursor 930 each include a solid precursor corresponding to a specific material of a layer to be formed on the gate dielectric layer 108 to form an active structure over the gate dielectric layer 108.

[0127] For example, in some embodiments, the active structure formed on the gate dielectric layer 108 includes a combination of a first material, a second material, and a third material. In some embodiments, a first solid precursor 922 corresponds to the first material, a second solid precursor 926 corresponds to the second material, and a third solid precursor 930 corresponds to the third material. In other embodiments, the first solid precursor 922 may correspond to a mixture of solid precursors corresponding to the first and second materials, the second solid precursor 926 may correspond to the first material, and the third solid precursor 930 may correspond to the third material. In other embodiments, the first solid precursor 922 may correspond to a mixture of solid precursors corresponding to the first, second, and third materials, the second solid precursor 926 may correspond to the first material, and the third solid precursor 930 may be omitted. In other embodiments, more than three precursor containers may be coupled to the housing 902.

[0128] It should be understood that various methods can be used to form an active structure over the gate dielectric layer 108, and each method can use different combinations of solid precursors in the precursor container. Figures 10A-10C The first and second methods correspond to forming an active structure above the gate dielectric layer 108. Figure 11A and 11B This corresponds to the third method of forming an active structure above the gate dielectric layer 108. Figure 12A and 12B This corresponds to the fourth method of forming an active structure above the gate dielectric layer 108. Therefore, the method can be derived from... Figure 9 Proceed to Figure 10A and 10B ; or from Figure 9 Proceed to Figure 10A and 10C , and thus omit Figure 10B; or from Figure 9 Proceed to Figure 11A and 11B , and thus omit Figures 10A-10C ; or from Figure 9 Proceed to Figure 12A and 12B , and thus omit Figure 10A-11B .

[0129] Furthermore, Figure 10A-12B The method shown demonstrates the formation of an active structure over the gate dielectric layer 108 via atomic layer deposition (ALD). However, it should be understood that in other embodiments, the active structure may be formed over the gate dielectric layer 108 by other deposition methods, such as chemical vapor deposition, physical vapor deposition, or similar methods.

[0130] like Figure 10A As shown in the cross-sectional schematic diagram 1000A, in some embodiments, an atomic layer deposition process is performed to form an active structure 110 over the gate dielectric layer 108, wherein the active structure 110 includes a stack of a hybrid layer 112 and a first active layer 114, the hybrid layer 112 comprising a mixture of a first material and a second material, and the first active layer 114 comprising a third material. In some such embodiments, the bottom layer 110b of the active structure 110 includes one layer of the hybrid layer 112. Furthermore, in some embodiments, the top layer 110t of the active structure 110 includes a second active layer 120, the second active layer 120 comprising the first material but not including the second or third material.

[0131] In some such embodiments, the first, second, and third materials of the active structure 110 are metal oxides. In some such embodiments, the first solid precursor 922, the second solid precursor 926, and the third solid precursor 930 may each comprise a first metal, a second metal, and a third metal corresponding to the first, second, and third materials of the active structure 110, respectively. For example, in some embodiments, the first material may include gallium, hafnium, zirconium, titanium, aluminum, tantalum, strontium, barium, scandium, magnesium, lanthanum, gadolinium, or some other suitable metal. In some embodiments, where the first material includes gallium, the first precursor of the first solid precursor 922 may include, for example, Ga(C2H5)3, Ga(NMe)3, Ga(C5H7O2)3, GaCp*, Ga(CH3)3, Ga2(NMe2)6, or some other suitable solid precursor including gallium.

[0132] In some embodiments, the second material includes indium, tin, zinc, arsenic, or some other suitable metal. In some such embodiments, where the second material includes indium, the second solid precursor 926 may include, for example, trimethylindium, triethylindium, InCp(C5H5In), InCA-1(C8H...24 InNSi2), DADI(C7H) 18 InN) or some other suitable solid precursor including indium. In some other embodiments, the third material includes zinc or some other metal. In some embodiments, the third solid precursor 930 includes, for example, Zn(CH3COO)2, diethylzinc, dimethylzinc, zinc acetate, (CH3)Zn(OCH(CH3)2) or some other suitable solid precursor.

[0133] Figure 10B Timing diagram 1000B shows some embodiments of a first method for forming an active structure 110 over a gate dielectric layer 108, wherein a first solid precursor 922 corresponds to a first material, a second solid precursor 926 corresponds to a second material, and a third solid precursor 930 corresponds to a third material. (The last part, "in conjunction with...", appears to be a fragment and doesn't need a direct translation.) Figure 10A Cross-sectional schematic diagram 1000A description Figure 10B .

[0134] In some embodiments, to form the active structure 110, a hybrid layer 112 is first formed over the gate dielectric layer 108. In some such embodiments, the hybrid layer 112 comprises a mixture of a first material and a second material. Therefore, in some embodiments, according to Figure 10B Note 1002 and Figure 10B In the timing diagram 1000B, step 1004 of the method firstly includes simultaneously activating the first solid precursor 922 and the second solid precursor 926. In some embodiments, the first solid precursor 922 and the second solid precursor 926 are activated by “turning on” an inert gas source 912. Furthermore, in some embodiments, the door structure 936 on the first container housing 910 and the second container housing 918 is “opened” while the door structure 936 on the third container housing 932 is “closed”, such that inert gas is introduced from the inert gas source 912, activating the first solid precursor 922 and the second solid precursor 926, but not activating the third solid precursor 930. In some embodiments, the inert gas source 912 includes, for example, nitrogen, argon, hydrogen, a combination of the foregoing, or some other suitable gas.

[0135] Furthermore, in some embodiments, an inert gas source 912 activates the first solid precursor 922 and the second solid precursor 926, and in step two 1006 of the method, an oxygen source 916 is "connected" to introduce oxygen vapor into the reaction chamber. In some embodiments, the oxygen source 916 may include water. In some such embodiments, the oxygen vapor from the oxygen source 916 reacts with the precursor mixture vapor of the first solid precursor 922 and the second solid precursor 926 in the reaction chamber to form a mixed layer 112 by atomic layer deposition on the gate dielectric layer 108. In some such embodiments, the mixed layer 112 comprises a mixture of the first and second materials, which is a metal oxide.

[0136] In some embodiments, then in step three 1008, by closing the door structure 936 connecting the first container housing 910 and the second container housing 918, the door structure 936 of the third container housing 932 is opened, and the inert gas source 912 is "connected" to activate the third solid precursor 930. In some such embodiments, the inert gas from the inert gas source 912 reacts with the third solid precursor 930, and the precursor gas enters the reaction chamber. Next, in step four 1010 of the method, the oxygen source 916 is "connected" to introduce oxygen vapor into the reaction chamber. In some such embodiments, the oxygen vapor reacts with the precursor vapor of the third solid precursor 930 to form the first active layer 114 over the mixed layer 112 by atomic layer deposition. In some embodiments, by repeating steps one 1004, two 1006, three 1008, and four 1010 multiple times, a stack of the mixed layer 112 and the first active layer 114 is formed over the gate dielectric layer 108.

[0137] In some embodiments, the topmost layer 110t of the active structure 110 includes a second active layer 120 composed of a first material (but without a second or third material), therefore, in some embodiments, Figure 10B The method proceeds to step five 1012, in which the door structures 936 of the second container shell 918 and the third container shell 932 are closed, the door structure 936 of the first container shell 910 is opened, and the inert gas source 912 is "connected" to activate the first solid precursor 922. Furthermore, in step six 1014 of the method, the oxygen source 916 is "connected" to introduce oxygen vapor into the reaction chamber. In some such embodiments, the oxygen vapor reacts with the precursor vapor of the first solid precursor 922 to form a second active layer 120 by atomic layer deposition over the mixed layer 112 and the first active layer 114.

[0138] In some embodiments, byproducts of the reaction between precursor vapor and oxygen vapor may be discharged through gas outlet line 919. In some embodiments, the gas pulses of steps one 1004, two 1006, three 1008, four 1010, five 1012, and six 1014 may each have a time period, for example, ranging from about 1 millisecond to about 20 minutes. Furthermore, in some embodiments, except for the activation of the first solid precursor 922 and the second solid precursor 926 in step one 1004, the gas pulses of steps one 1004, two 1006, three 1008, four 1010, five 1012, and six 1014 do not overlap with each other. In some other embodiments, steps one 1004, two 1006, three 1008, four 1010, five 1012, and six 1014 may partially overlap with each other. For example, in some other embodiments, step two 1006 may begin before the inert gas source 912 used in step one 1004 is completely "blocked".

[0139] Because the first material of the hybrid layer 112 has strong bond energy, there are fewer defects (e.g., oxygen vacancies) at the interface between the first material of the hybrid layer 112 and the gate dielectric layer 108, resulting in fewer surface states (i.e., excess charge). In some embodiments, the second material of the hybrid layer 112 has a greater mobility than the first material of the hybrid layer 112 due to the weaker bond energy and the increase in metal ions in the second material. Therefore, mobile charge carriers can have a higher mobility at the interface between the hybrid layer 112 and the gate dielectric layer 108. Thus, the bottom layer 110b of the active structure 110 includes the hybrid layer 112, which contains a mixture of the first and second materials to reduce defects, but also to increase the charge mobility at the interface between the bottom layer 110b of the active structure 110 and the gate dielectric layer 108.

[0140] Furthermore, the second active layer 120 includes a first material having a higher bond energy than the second and third materials. By forming the second active layer 120 as the top layer 110t of the active structure 110, defects (e.g., surface states, oxygen vacancies) at the top surface of the active structure 110 are reduced.

[0141] Figure 10C A timing diagram 1000C shows some embodiments of a second method for forming an active structure 110 over a gate dielectric layer 108, wherein a first solid precursor 922 corresponds to a precursor mixture of a first material and a second material, a second solid precursor 926 corresponds to the first material, and a third solid precursor 930 corresponds to the third material. (The last part, "in conjunction with...", appears to be a fragment and doesn't need a direct translation.) Figure 10A Cross-sectional schematic diagram 1000A description Figure 10C .

[0142] In some other embodiments, the first solid precursor 922 corresponds to the precursor mixture, which corresponds to the first and second materials of the mixing layer 112. In some embodiments, the ratio of the first precursor corresponding to the first material to the second precursor corresponding to the second material is, for example, in the range of about 0.01 to about 0.99. Therefore, in some embodiments, step 1004 of the method includes activating the solid precursor mixture by opening the door structure 936 of the first container housing 910, closing the door structures 936 of the second container housing 918 and the third container housing 932, and “connecting” the inert gas source 912. The inert gas from the inert gas source 912 then reacts with the solid precursor mixture, causing the precursor mixture vapor to enter the reaction chamber. In some embodiments, Figure 10C The method proceeds to step two 1006, in which the oxygen source 916 is "connected" so that oxygen vapor reacts with the precursor mixture vapor in the reaction chamber to form a mixed layer 112 on the gate dielectric layer 108 by atomic layer deposition.

[0143] In some embodiments, steps three 1008, four 1010, five 1012, and six 1014 include... Figure 10B The methods described are the same or similar steps.

[0144] like Figure 11A As shown in the cross-sectional schematic diagram 1100A, in some other embodiments, the active structure 110 formed above the gate dielectric layer 108 includes a stack of a first active layer 114, a second active layer 120, and a third active layer 502. The first active layer 114 includes a third material, the second active layer 120 includes a first material, and the third active layer 502 includes a second material. In some such embodiments, the bottom layer 110b of the active structure 110 may include one of the first active layer 114, the second active layer 120, and the third active layer 502. In some embodiments, the top layer 110t of the active structure 110 includes one layer of the second active layer 120, which includes the first material.

[0145] Figure 11B show Figure 11A The timing diagram 1100B of some embodiments of the third method for forming an active structure 110 over the gate dielectric layer 108, shown in the cross-sectional schematic diagram 1100A, indicates that a first solid precursor 922 in a first precursor container may correspond to a first material, a second solid precursor 926 in a second precursor container may correspond to a second material, and a third solid precursor 930 may correspond to a third material. (The last sentence appears to be incomplete and possibly refers to a different topic.) Figure 11A Cross-sectional schematic diagram 1100A description Figure 11B .

[0146] As shown in timing diagram 1100B, in some embodiments, step one 1104 of the method includes “turning on” an inert gas source 912 to activate a first solid precursor 922 associated with a first material of one layer of the second active layer 120. In some embodiments, step two 1106 of the method includes turning on an oxygen source 916 such that oxygen vapor reacts with the first precursor vapor of step one 1104 to form one layer of the second active layer 120 over the gate dielectric layer 108 by atomic layer deposition. In some embodiments, the method proceeds to step three 1108, wherein the inert gas source 912 is turned on to activate a second solid precursor 926 associated with one layer of the third active layer 502. In some embodiments, step four 1110 of the method includes turning on an oxygen source 916 such that oxygen vapor reacts with the second precursor vapor of step three 1108 to form one layer of the third active layer 502 over one layer of the second active layer 120 by atomic layer deposition.

[0147] In some embodiments, the method proceeds to step five 1112, wherein an inert gas source 912 is "connected" to activate a third solid precursor 930 associated with a third material of one of the first active layers 114. In some embodiments, step six 1114 of the method includes connecting an oxygen source 916 such that oxygen vapor reacts with the third precursor vapor of step five 1112 to form one of the first active layers 114 by atomic layer deposition over one of the third active layers 502. In some embodiments, steps one 1104, two 1106, three 1108, four 1110, five 1112, and six 1114 are repeated to form a stack of the first active layer 114, the second active layer 120, and the third active layer 502 over the gate dielectric layer 108. Then, in some embodiments, Figure 11B The method includes steps seven 1116 and eight 1118 to form the top layer 110t of the active structure 110, which includes the second active layer 120. Therefore, in some embodiments, steps seven 1116 and eight 1118 include the same or similar steps as steps one 1104 and 1106 for forming the second active layer 120.

[0148] like Figure 12A As shown in the cross-sectional schematic diagram 1200A, in some embodiments, the active structure 110 formed above the gate dielectric layer 108 includes a lower portion 402, which contains a mixture of a first material, a second material, and a third material above the gate dielectric layer 108. Therefore, in some embodiments, the active structure 110 includes a lower portion 402 without a defining layer. Furthermore, in some embodiments, a second active layer 120 comprising the first material is formed above the lower portion 402, such that the active structure 110 includes the second active layer 120 disposed above the lower portion 402.

[0149] Figure 12B show Figure 12A The timing diagram 1200B, shown in the cross-sectional schematic diagram 1200A, illustrates some embodiments of the fourth method for forming an active structure 110 over the gate dielectric layer 108, wherein a first solid precursor 922 in a first precursor container may correspond to a first material, a second solid precursor 926 in a second precursor container may correspond to a second material, and a third solid precursor 930 may correspond to a third material. (The last sentence appears to be incomplete and possibly refers to a different topic.) Figure 12A Cross-sectional schematic diagram 1200A description Figure 12B .

[0150] like Figure 12B As shown in the timing diagram 1200B, in some embodiments, step one 1204 of the method includes "turning on" an inert gas source 912 to simultaneously activate a first solid precursor 922, a second solid precursor 926, and a third solid precursor 930. Next, in step two 1206 of the method, an oxygen source 916 is "turned on" so that oxygen vapor reacts with the precursor mixture vapor from step one 1204 to form the lower portion 402 of the active structure 110 by atomic layer deposition. In some embodiments, steps one 1204 and two 1206 are repeated multiple times to increase the thickness of the lower portion 402. In some embodiments, after forming the lower portion 402 of the active structure, the method proceeds to step three 1208, where the inert gas source 912 is turned on to activate the first solid precursor 922, but the second solid precursor 926 or the third solid precursor 930 is not activated. Furthermore, in some embodiments, the method proceeds to step 1210, in which the oxygen source 916 is "connected" so that oxygen vapor reacts with the second mixture vapor from step 1208 to form a second active layer 120 above the lower portion 402 of the active structure 110.

[0151] therefore, Figures 10A to 12B Various methods can be shown to form the active structure 110 over the gate dielectric layer 108. It should be understood that other related methods and / or Figure 10A-12B Combinations of methods are also within the scope of embodiments of the present invention.

[0152] In some embodiments, the method proceeds to forming a cover structure over the active structure. Figure 13-16 The first method of forming a covering structure above the active structure 110 is shown, while Figure 17-20 This illustrates a second method for forming a cover structure over the active structure 110. Therefore, in some embodiments, after forming the active structure 110 over the gate dielectric layer 108, the method can proceed to... Figure 13 or Figure 17 (and thus omitted) Figure 13-16 (Steps).

[0153] like Figure 13 As shown in the cross-sectional schematic diagram 1300, in some embodiments, a first continuous metal layer 1302 is formed over the active structure 110. In some embodiments, the first continuous metal layer 1302 comprises a first metallic material having a higher affinity for oxygen than the metal in the active structure 110. Therefore, in some embodiments, the first metallic material is different from the metal in the active structure 110. In some embodiments, the first continuous metal layer 1302 may comprise, for example, aluminum, calcium, scandium, yttrium, niobium, tantalum, chromium, iron, titanium, silicon, hafnium, zirconium, titanium, strontium, barium, magnesium, lanthanum, gadolinium, combinations thereof, and / or some other suitable metal or semiconductor material having strong oxidizing properties (i.e., high affinity for oxygen). In some embodiments, the first continuous metal layer 1302 is formed using an atomic layer deposition (ALD) process and may be formed in the same ALD reaction chamber used to form the active structure 110. For example, in some embodiments, the first continuous metal layer 1302 may be formed by “connecting” an inert gas source (e.g., Figure 9 An inert gas source 912 is used to activate the precursor associated with the first metallic material during an atomic layer deposition process. In other embodiments, the first continuous metallic layer 1302 may be formed using a deposition process different from atomic layer deposition, such as physical vapor deposition, chemical vapor deposition, sputtering, or some other suitable process.

[0154] In some embodiments, when the first continuous metal layer 1302 is formed using an atomic layer deposition process, if the first continuous metal layer 1302 comprises aluminum, the precursor used may include, for example, Al(CH-3)3 or some other precursors comprising aluminum. In some embodiments, when the first continuous metal layer 1302 is formed using an atomic layer deposition process, if the first continuous metal layer 1302 comprises calcium, the precursor used may include, for example, Ca(OCC(CH3)3CHCOC(CH3)3))2, calcium phosphate (2,2,6,6-tetramethyl-3,5-heptanediol) or some other precursors comprising calcium.

[0155] In some embodiments, a second continuous metal layer 1304 is then formed over the first continuous metal layer 1302. In some embodiments, the second continuous metal layer 1304 may comprise the same or similar material as the first continuous metal layer 1302. In other embodiments, the second continuous metal layer 1304 is omitted. In some embodiments, the second continuous metal layer 1304 is formed using the same deposition process as the first continuous metal layer 1302, such as atomic layer deposition, physical vapor deposition, chemical vapor deposition, sputtering, or similar methods. In some embodiments, the second continuous metal layer 1304 may be formed by “connecting” an inert gas source (e.g., ...). Figure 9An inert gas source 912 is used to activate the precursor associated with the second metallic material through an atomic layer deposition process. In some embodiments, the thicknesses of the first continuous metal layer 1302 and the second continuous metal layer 1304 may be, for example, approximately [missing information]. to approximately Within the range between.

[0156] like Figure 14 As shown in the cross-sectional schematic diagram 1400, in some embodiments, a mask structure 1402 is formed over a first continuous metal layer 1302 and a second continuous metal layer 1304. In some embodiments, the mask structure 1402 is formed using photolithography and removal (e.g., etching) processes. In some embodiments, the mask structure 1402 includes a photoresist material or a hard mask material.

[0157] like Figure 15 As shown in the cross-sectional schematic diagram 1500, in some embodiments, a removal process is performed based on the mask structure 1402 to remove the first continuous metal layer and the second continuous metal layer. Figure 14 The peripheral portions of the first continuous metal layer 1302 and the second continuous metal layer 1304 are used to form a cover structure 122 over the active structure 110. The cover structure 122 includes the first metal layer 124 and a second metal layer 326 disposed above the first metal layer 124. In some embodiments, Figure 15 The removal process includes wet etching or dry etching. In some embodiments, due to Figure 15 Due to the residual effect of the removal process, the upper surface of the second metal layer 326 is narrower than the lower surface of the first metal layer 124.

[0158] like Figure 16 As shown in the cross-sectional schematic diagram 1600, in some embodiments, a thermal annealing process is performed. In some embodiments, the thermal annealing process is carried out in the cavity at a temperature in the range of, for example, about 400°C to about 700°C. In some embodiments, after the thermal annealing process, a diffusion region 128 is formed in the topmost layer 110t of the active structure 110. In some embodiments, the diffusion region 128 comprises a metal oxide made of a first metallic material of the capping structure 122 and oxygen. In some such embodiments, during the thermal annealing process, the first metallic material can diffuse into the active layer and bond with weakly bonded oxygen in the active structure 110 because the first metallic material has a higher affinity for oxygen than the metal in the active structure 110. Therefore, the capping structure 122 helps reduce defects (e.g., oxygen vacancies, surface states, weakly bonded oxygen) in the active structure 110 to improve the performance of the field-effect transistor ferroelectric random access memory device.

[0159] In some embodiments, after a thermal annealing process, source / drain contacts 118 are formed on either side of the overlay structure 122 above the active structure 110. In some embodiments, the source / drain contacts 118 are formed in the interconnect dielectric layer 116 above the active structure 110 through various steps, including deposition processes (e.g., physical vapor deposition, chemical vapor deposition, atomic layer deposition, sputtering, etc.), removal processes (e.g., wet etching, dry etching, chemical mechanical planarization (CMP), etc.), and / or patterning processes (e.g., photolithography / etching). In some other embodiments, the source / drain contacts 118 are formed first, followed by the formation of the interconnect dielectric layer 116 between the source / drain contacts 118 and above the active structure 110.

[0160] In some embodiments, the interconnect dielectric layer 116 comprises, for example, nitrides (e.g., silicon nitride, silicon oxynitride), carbides (e.g., silicon carbide), oxides (e.g., silicon oxide), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low dielectric constant oxides (e.g., carbon-doped oxides, SiCOH), or the like. In some embodiments, the source / drain contacts 118 comprise, for example, aluminum, tungsten, copper, tantalum, titanium, or some other suitable conductive material.

[0161] Furthermore, in some embodiments, a voltage terminal is coupled to the gate electrode 106 and the source / drain contact 118. In some embodiments, the overlay structure 122 is grounded. In other embodiments, the overlay structure 122 is not grounded or coupled to any voltage terminal. However, in some embodiments, Figure 16 The resulting structure is a thin-film transistor (TFT), which is also a field-effect transistor (FET) ferroelectric random access memory (FeRAM) device. In some such embodiments, when a sufficient signal (e.g., current, voltage) is applied to the source / drain junction 118 and the gate electrode 106, a channel region can be formed in the active structure 110 to read memory from or write memory to the gate dielectric layer 108. In some embodiments, a capping structure 122 disposed directly above the gate dielectric layer 108 and directly above the active structure 110 and the hybrid layer 112 helps reduce defects (e.g., surface states, oxygen vacancies, weakly bonded oxygen) in the active structure 110 (and thus the channel region), thereby increasing the switching speed and reliability of the entire FET ferroelectric random access memory device.

[0162] Figure 17-20 Cross-sectional schematic diagrams 1700-2000 show some alternative steps in forming a covering structure 122 above the active structure 110.

[0163] like Figure 17 As shown in the cross-sectional schematic diagram 1700, in some embodiments, an interconnect dielectric layer 116 is first formed above the active structure 110.

[0164] like Figure 18 As shown in the cross-sectional schematic diagram 1800, in some embodiments, the interconnect dielectric layer 116 is patterned to form openings 1802 in the interconnect dielectric layer 116 to expose the active structure 110. In some embodiments, the openings 1802 in the interconnect dielectric layer 116 are formed by various steps, including deposition processes (e.g., physical vapor deposition, chemical vapor deposition, atomic layer deposition, sputtering, spin coating, etc.), patterning processes (e.g., photolithography / etching), and removal processes (e.g., wet etching, dry etching).

[0165] like Figure 19 As shown in the cross-sectional schematic diagram 1900, in some embodiments, a first metal layer 124 is formed in an opening 1802 of the interconnect dielectric layer 116. In some embodiments, the first metal layer 124 partially fills the opening 1802, while in some other embodiments, the first metal layer 124 completely fills the opening 1802. In some embodiments, the first metal layer 124 is formed by a deposition process (e.g., physical vapor deposition, chemical vapor deposition, atomic layer deposition, sputtering, etc.) and a subsequent removal process (e.g., etching, chemical mechanical polishing).

[0166] like Figure 20 As shown in the cross-sectional schematic diagram 2000, in some embodiments, at the opening ( Figure 19 A second metal layer 326 is formed over the first metal layer 124 in the opening 1802 to form a cover structure 122 over the active structure 110. In some embodiments, a thermal annealing process is performed to form a diffusion region 128 of the active structure 110. Next, in some embodiments, source / drain contacts 118 are formed in the interconnect dielectric layer 116.

[0167] In some other embodiments, the interconnect dielectric layer 116 is patterned to form openings for the source / drain contacts 118 before the second metal layer 326 is formed over the first metal layer 124. In some embodiments, the openings for the source / drain contacts 118 and the openings in the interconnect dielectric layer 116 are then ( Figure 19 A second metallic material is formed in the opening 1802 to form the source / drain contact 118 and the second metallic layer 326. In these embodiments, the source / drain contact 118 and the second metallic layer 326 may include the second metallic material. Furthermore, in some such embodiments, a thermal annealing process for forming the diffusion region 128 may be performed before or after the deposition of the second metallic material.

[0168] In some embodiments, since the covering structure 122 is formed in the opening of the interconnect dielectric layer 116 ( Figure 19 In the opening 1802), the covering structure 122 can therefore have a top surface that is wider than the bottom surface. Furthermore, in some embodiments, because the covering structure 122 is formed in the opening (…), Figure 19 In the opening 1802), compared to other embodiments, the removal process can cause less damage to the top layer 110t of the active structure 110, wherein the first metal layer 124 is formed before the interconnect dielectric layer 116 is formed, such as Figure 13-16 As shown.

[0169] However, in some embodiments, the overlay structure 122 helps reduce defects (e.g., surface states, oxygen vacancies, weakly bonded oxygen) in the active structure 110 and increases the switching speed and reliability of the entire field-effect transistor ferroelectric random access memory device.

[0170] Figure 21 Flowcharts showing some embodiments of a method 2100 for forming a field-effect transistor ferroelectric random access memory device are shown. Method 2100 includes providing a cover structure over an active structure to reduce defects in the active structure and increase the switching speed and reliability of the entire field-effect transistor ferroelectric random access memory device.

[0171] Although method 2100 is described below as a series of actions or events, it should be understood that the order of these actions or events shown should not be construed as limiting. For example, some actions may occur in a different order and / or simultaneously with other events or actions not shown and / or described herein. Furthermore, not all shown actions are required to perform one or more aspects or embodiments described herein. Moreover, one or more actions described herein may be performed in one or more separate actions and / or stages.

[0172] In action 2102, a gate electrode is formed over the substrate. Figure 7 A cross-sectional schematic diagram 700 shows some embodiments of the corresponding action 2102.

[0173] In action 2104, a gate dielectric layer comprising a ferroelectric material is formed above the gate electrode. Figure 8 A cross-sectional schematic diagram 800 shows some embodiments of the corresponding action 2104.

[0174] In action 2106, an active structure is formed above the gate dielectric layer. Figure 10A A cross-sectional schematic diagram 1000A shows some embodiments of the corresponding action 2106.

[0175] In action 2108, a first metal layer is formed above the active structure. Figure 13A cross-sectional schematic diagram 1300 shows some embodiments of the corresponding action 2108.

[0176] In action 2110, the peripheral portion of the first metal layer is removed to form a cover structure over the active structure. Figure 15 A cross-sectional schematic diagram 1500 shows some embodiments of the corresponding action 2110.

[0177] In action 2112, a source contact and a drain contact are formed above the active structure, wherein the cover structure is laterally positioned between the source contact and the drain contact. Figure 16 A cross-sectional schematic diagram 1600 shows some embodiments of the corresponding action 2112.

[0178] Therefore, the embodiments of the present invention relate to a method in which an active structure is formed above a ferroelectric layer and a cover structure is formed above the active structure to reduce defects in the active structure and optimize the charge mobility of the active structure to increase the switching speed and reliability of the entire field-effect transistor ferroelectric random access memory device.

[0179] Therefore, in some embodiments, the present invention relates to an integrated chip, the integrated chip comprising: a gate electrode disposed above a substrate; a gate dielectric layer disposed above the gate electrode, the gate dielectric layer comprising a ferroelectric material; an active structure disposed above the gate dielectric layer, the active structure comprising a semiconductor material; a source contact and a drain contact disposed above the active structure; and a cover structure disposed above the active structure and between the source contact and the drain contact, wherein the cover structure comprises a first metal material.

[0180] In some other embodiments, the active structure includes a stack of alternatingly stacked mixed layers and a stack of a plurality of first active layers, wherein the mixed layers include a mixture of a first material and a second material, wherein the plurality of first active layers include a third material different from the first material and the second material, wherein the bottom layer of the active structure is one of the mixed layers, and wherein the top layer of the active structure is disposed above the stack of alternatingly stacked mixed layers and a stack of a plurality of first active layers, and the top layer of the active structure includes the first material.

[0181] In some other embodiments, the active structure includes a stack of a plurality of first active layers, a plurality of second active layers, and a plurality of third active layers, wherein the plurality of first active layers include a first metal oxide material, the plurality of second active layers include a second metal oxide material, and the plurality of third active layers include a third metal oxide material.

[0182] In some other embodiments, the covering structure includes a first layer and a second layer disposed above the first layer, the first layer including a first metal material and the second layer including a second metal material.

[0183] In some other embodiments, the overlay structure is grounded.

[0184] In some other embodiments, the first metallic material has a higher affinity for oxygen than the material of the active structure.

[0185] In some other embodiments, the active structure includes a lower portion comprising a mixture of a first material, a second material, and a third material, and the active structure includes an upper portion disposed above the lower portion, the upper portion comprising the first material.

[0186] In some other embodiments, the covering structure directly contacts the diffusion region of the active structure, wherein the diffusion region includes a first metallic material and a first material.

[0187] In other embodiments, embodiments of the present invention relate to an integrated chip, the integrated chip comprising: a gate electrode disposed above a substrate; a gate dielectric layer disposed above the gate electrode, wherein the gate dielectric layer comprises a ferroelectric material; an active structure disposed above the gate dielectric layer; a source contact and a drain contact disposed above the active structure; and a cover structure disposed above the active structure and between the source contact and the drain contact, wherein the cover structure comprises a first metal material, the first metal material having a higher affinity for oxygen than the metal in the active structure.

[0188] In some other embodiments, the active structure includes a first material, a second material different from the first material, and a third material different from the first and second materials, wherein the first and second materials directly contact the gate dielectric layer, wherein the third material is spaced apart from the gate dielectric layer by the first and second materials, and wherein the overlay structure directly contacts the first material but does not contact the second or third material.

[0189] In some other embodiments, the covering structure includes a first layer and a second layer disposed above the first layer, the first layer including a first metallic material and the second layer including a second metallic material, wherein the first layer directly contacts the diffusion region of the active structure, and wherein the diffusion region includes the first metallic material and oxygen.

[0190] In some other embodiments, the covering structure comprises a mixture of a first metallic material and a second metallic material.

[0191] In some other embodiments, the integrated chip further includes: an interconnect via disposed below the gate electrode and coupled to the gate electrode; a first interconnect disposed above the source contact and coupled to the source contact; a second interconnect disposed above the drain contact and coupled to the drain contact; and an interconnect dielectric structure surrounding the interconnect via, the first interconnect, the second interconnect, the source contact, the drain contact, and the cover structure.

[0192] In some other embodiments, the overlay structure is grounded.

[0193] In some other embodiments, the top layer of the active structure comprises gallium oxide, and the bottom layer of the active structure comprises a mixture of gallium oxide and indium oxide.

[0194] In other embodiments, the present invention relates to a method comprising: forming a gate electrode over a substrate; forming a gate dielectric layer over the gate electrode, the gate dielectric layer comprising a ferroelectric material; forming an active structure over the gate dielectric layer; forming a first metal layer over the active structure; removing a peripheral portion of the first metal layer to form a cover structure over the active structure; and forming a source contact and a drain contact over the active structure, wherein the cover structure is laterally disposed between the source contact and the drain contact.

[0195] In some other embodiments, the step of forming the active structure includes: simultaneously activating two precursors to form a mixed layer over a gate dielectric layer, such that the mixed layer comprises a mixture of a first material and a second material; forming a first active layer over the mixed layer, the first active layer comprising a third material different from the first and second materials; and repeating the steps of forming the mixed layer and the first active layer to form a stack of a plurality of mixed layers and a plurality of first active layers stacked alternately over the gate dielectric layer; and forming a topmost active layer over the stack of the plurality of mixed layers and the plurality of first active layers, the topmost active layer comprising the first material.

[0196] In some other embodiments, the method further includes: forming a second metal layer over the first metal layer; and removing a peripheral portion of the second metal layer, wherein the covering structure includes the first metal layer and the second metal layer.

[0197] In some other embodiments, the first metal layer is formed using a solid precursor and an atomic layer deposition process.

[0198] In some other embodiments, the method further includes performing a thermal annealing process after the formation of the first metal layer and before the formation of the source and drain contacts.

[0199] The foregoing outlines the features of numerous embodiments, enabling those skilled in the art to better understand the embodiments of the present invention from various perspectives. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the inventive concept and scope of the present invention. Various changes, substitutions, or modifications can be made to the embodiments of the present invention without departing from the inventive concept and scope of the present invention.

Claims

1. An integrated chip, comprising: A gate electrode is disposed above a substrate; A gate dielectric layer is disposed above the gate electrode, and the gate dielectric layer includes a ferroelectric material; An active structure is disposed above the gate dielectric layer, and the active structure includes a semiconductor material; A source contact and a drain contact are disposed above the active structure; as well as A covering structure is disposed above the active structure and between the source terminal and the drain terminal, wherein the covering structure includes a first metal material, wherein the covering structure is in contact with a diffusion region of the active structure, and the diffusion region includes the first metal material and a first material of the active structure.

2. The integrated chip of claim 1, wherein the active structure comprises a stack of alternatingly stacked hybrid layers and a plurality of first active layers, wherein the hybrid layers comprise a mixture of a first material and a second material, wherein the plurality of first active layers comprise a third material different from the first material and the second material, wherein a bottom layer of the active structure is one of the hybrid layers, and wherein a top layer of the active structure is disposed above the stack of alternatingly stacked hybrid layers and a plurality of first active layers, and the top layer of the active structure comprises the first material.

3. The integrated chip of claim 1, wherein the active structure comprises a stack of a plurality of first active layers, a plurality of second active layers and a plurality of third active layers, the plurality of first active layers comprising a first metal oxide material, the plurality of second active layers comprising a second metal oxide material, and the plurality of third active layers comprising a third metal oxide material.

4. The integrated chip as claimed in claim 1, wherein the overlay structure includes a first layer and a second layer disposed above the first layer, the first layer including the first metal material, and the second layer including a second metal material.

5. The integrated chip of claim 1, wherein the overlay structure is grounded.

6. The integrated chip of claim 1, wherein the first metal material has a higher affinity for oxygen than the material of the active structure.

7. The integrated chip of claim 1, wherein the active structure includes a lower portion comprising a mixture of the first material, a second material, and a third material, and wherein the active structure includes an upper portion disposed above the lower portion, the upper portion comprising the first material.

8. An integrated chip, comprising: A gate electrode is disposed above a substrate; A gate dielectric layer is disposed above the gate electrode, wherein the gate dielectric layer includes a ferroelectric material; An active structure is disposed above the gate dielectric layer; A source contact and a drain contact are disposed above the active structure; as well as A covering structure is disposed above the active structure and between the source terminal and the drain terminal, wherein the covering structure includes a first metal material, the first metal material having a higher affinity for oxygen than the metal in the active structure, wherein the covering structure is in contact with a diffusion region of the active structure, and the diffusion region includes the first metal material and a first material of the active structure.

9. The integrated chip of claim 8, wherein the active structure includes the first material, a second material different from the first material, and a third material different from the first material and the second material, wherein the first material and the second material directly contact the gate dielectric layer, wherein the third material is spaced apart from the gate dielectric layer by the first material and the second material, and wherein the overlay structure directly contacts the first material but does not contact the second material or the third material.

10. The integrated chip of claim 8, wherein the overlay structure includes a first layer and a second layer disposed above the first layer, the first layer including the first metal material, the second layer including a second metal material, wherein the first layer directly contacts a diffusion region of the active structure, and wherein the diffusion region includes the first metal material and oxygen.

11. The integrated chip of claim 8, wherein the overlay structure comprises a mixture of the first metal material and a second metal material.

12. The integrated chip of claim 8, further comprising: An interconnect via is disposed below the gate electrode and coupled to the gate electrode; A first interconnect line is disposed above the source contact and coupled to the source contact; A second interconnect line is disposed above the drain contact and coupled to the drain contact; as well as An interconnect dielectric structure surrounding the interconnect via, the first interconnect line, the second interconnect line, the source contact, the drain contact, and the cover structure.

13. The integrated chip of claim 8, wherein the overlay structure is grounded.

14. The integrated chip of claim 8, wherein a top layer of the active structure comprises gallium oxide, and a bottom layer of the active structure comprises a mixture of gallium oxide and indium oxide.

15. A method for forming an integrated chip, comprising: A gate electrode is formed over a substrate; A gate dielectric layer is formed above the gate electrode, and the gate dielectric layer includes a ferroelectric material. An active structure is formed above the gate dielectric layer; A first metal layer is formed above the active structure; A peripheral portion of the first metal layer is removed to form a cover structure over the active structure, wherein the cover structure is in contact with a diffusion region of the active structure, and the diffusion region includes a first metal material of the cover structure and a first material of the active structure. as well as A source contact and a drain contact are formed above the active structure, wherein the covering structure is laterally disposed between the source contact and the drain contact.

16. The method for forming an integrated chip as claimed in claim 15, wherein the step of forming the active structure includes: By simultaneously activating two precursors, a hybrid layer is formed above the gate dielectric layer, such that the hybrid layer comprises a mixture of the first material and a second material; A first active layer is formed above the hybrid layer, the first active layer comprising a third material that is different from the first material and the second material; as well as The steps of forming the hybrid layer and the first active layer are repeated to form a stack of multiple hybrid layers and multiple first active layers that are stacked alternately on top of the gate dielectric layer; as well as A topmost active layer is formed above the stack of the plurality of hybrid layers and the plurality of first active layers, the topmost active layer comprising the first material.

17. The method for forming an integrated chip as described in claim 15, further comprising: A second metal layer is formed above the first metal layer; and Remove a peripheral portion of the second metal layer, wherein the covering structure includes the first metal layer and the second metal layer.

18. The method of forming an integrated chip as claimed in claim 15, wherein the first metal layer is formed by using a solid precursor and an atomic layer deposition process.

19. The method for forming an integrated chip as described in claim 15, further comprising: A thermal annealing process is performed after the formation of the first metal layer and before the formation of the source and drain contacts.

Images