有限RAM系统中的逻辑到物理转译技术

By introducing L2P mapping technology with host cache into the memory system, the performance problem caused by L2P table update latency is solved, the efficiency of random write operations is improved, and system performance and user experience are enhanced.

CN114761931BActive Publication Date: 2026-07-17MICRON TECHNOLOGY INC
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
MICRON TECHNOLOGY INC
Filing Date
2020-09-24
Publication Date
2026-07-17

AI Technical Summary

Technical Problem

Existing memory systems suffer from performance degradation due to L2P table update latency when handling random write operations, and the increased internal memory cost is unacceptable.

Method used

The L2P mapping technology using host cache is used to deliver the translation table to the host and update the L2P table using the physical address provided by the host, thereby reducing the controller's direct reference to the translation table and improving memory access efficiency.

Benefits of technology

By reducing L2P table update latency, the random write performance of the storage system is improved, thereby enhancing overall system efficiency and user experience.

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Abstract

本文公开用于更高效地执行针对存储器装置的随机写入操作的装置及技术。在实例中，一种操作快闪存储器装置的方法可包含：在快闪存储器装置处从主机接收写入请求，所述写入请求包含第一逻辑块地址及写入数据；将所述写入数据保存到具有第一物理地址的所述快闪存储器装置的位置；当与所述写入请求相关联的写入数据量高于阈值时，在第一模式中操作所述存储器装置；当写入数据量低于所述阈值时，在第二模式中操作所述快闪存储器装置；及将所述写入数据量与所述阈值进行比较。
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