Semiconductor device with bonding pads and interlayer passivation layer and method of manufacturing the same

Abstract

A method of forming a sandwich passivation layer (405) on a semiconductor device (400) including a bond pad (404) is provided. The method includes forming a first layer (406) over a surface of the semiconductor device (400), removing a portion of the first layer (406) to expose a surface of the bond pad (404), forming a second layer (407) over the first layer (406) and the surface of the bond pad (404), and forming a third layer (408) over the second layer (407), wherein the surface of the bond pad (404) is not in contact with the first layer (406) or the third layer (408).

Description

Technical Field

[0001] This disclosure relates to a method and apparatus for reducing corrosion of aluminum bonding pads in semiconductor devices, and more particularly, but not exclusively, to a method for forming an interlayer passivation layer on a semiconductor device including bonding pads and a semiconductor device including bonding pads and an interlayer passivation layer. Background Technology

[0002] This disclosure relates to a method and apparatus for reducing bonding pad corrosion in semiconductor devices. Corrosion defects in aluminum or aluminum-copper (Al-Cu) interconnects and bonding pads are a significant problem in back-end-of-line (BEOL) semiconductor processing.

[0003] Figure 1 illustrates an example of a prior art semiconductor device 100 with a single bonding pad 103. A top dielectric layer 102 is formed over a semiconductor substrate 101. A top metal layer is then formed on the top dielectric layer and etched to form metal interconnects and bonding pads 103. A passivation layer 104 is then formed over the top metal layer including the bonding pads 103.

[0004] The passivation layer 104 can be formed during a dual passivation process. First, a silicon oxide layer 104a is formed, followed by a silicon nitride layer 104b. Both layers can be deposited by chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD). The passivation layer 104 is then etched to form an opening above the bonding pad 103.

[0005] During back-to-the-loop (BEOL) semiconductor device 100 processing, a metal bond is formed on bonding pads 103 to attach the semiconductor device 100 to, for example, wires, contacts, devices, or circuit boards. Any corrosion of the bonding pads 103 can effectively hinder a high-quality bond. Corrosion of the bonding pads 103 can lead to failure of the semiconductor device 100 due to poor metal bonding formed with them.

[0006] In the prior art, techniques have been developed to reduce corrosion of the bonding pad surface due to the presence of fluorine. These techniques include the use of plasma, deionized water containing carbon dioxide, or a combination of wet and dry etching processes.

[0007] The purpose of this disclosure is to provide a method and apparatus for reducing bonding pad corrosion in semiconductor devices, or at least to provide a useful alternative. Summary of the Invention

[0008] In embodiments, this disclosure overcomes the aforementioned problems by providing a sandwich passivation layer for the semiconductor device. This arrangement reduces corrosion of the bonding pads. Specifically, it reduces corrosion of the bonding pads due to contamination on the surface of the semiconductor device. More specifically, this arrangement reduces corrosion caused by the combination of chlorine (Cl-) or fluorine (F-) with O and OH elements trapped on the tetraethyl orthosilicate (TEOS)-based oxide film.

[0009] Both dry and wet etching processes, as well as the manufacturing environment, can lead to contamination of semiconductor devices with molecules such as chlorine (Cl-) and fluorine (F-). If these molecules come into contact with moisture (such as OH-), they can form acids that can cause corrosion of the bonding pads (see [link to documentation]). Figure 2a ).

[0010] The copper-added aluminum metallization film used for bonding pads can exhibit highly localized pitting corrosion in the presence of moisture. This localized aluminum corrosion is caused by the electrolytic erosion of aluminum around the Al₂Cuθ phase particles, which in turn effectively hinders high-quality wire bonding (see [link to documentation]). Figure 2b ).

[0011] For optical semiconductor devices, the use of nitride films (such as plasma-enhanced nitride films (PESiN)) is unsuitable because they are optically incompatible. Conformality is an indicator of the ability of a film deposition process to coat the undercut recessed surface as well as the top and sidewall surfaces. PESiN processes are typically non-conformal, resulting in an increase in the number of large voids within the film structure. These voids can affect the refractive index of the passivation layer and thus the optical performance of the semiconductor device.

[0012] The use of PEOX in a dual passivation process has its limitations. If PEOX is used as the first passivation layer in a dual passivation process, delamination failures of the semiconductor device may occur after the alloying and assembly stages in BEOL. Furthermore, using PEOX as the second layer in a dual passivation process is undesirable because PEOX is a non-conformal film, which can lead to sagging, poor step coverage, and voids within the film.

[0013] Therefore, in the manufacture of optical semiconductor devices, oxide layers such as plasma-enhanced tetraethyl orthosilicate (PETEOS) are used as two layers in the dual passivation process.

[0014] However, PETEOS is more effective than other materials used for passivation layers (such as PESiN or SiO2 (glass)) at capturing moisture and particles from environments containing chemical molecules (such as Cl-). The structure of the TEOS membrane contains -O, -H, and -OH groups that can capture chloride (Cl-), such as... Figure 3As shown in the diagram. Depending on the process conditions for forming a PETEOS-based membrane, the membrane can have more -O, -H, or -OH bonds with water on its surface. These molecules have temporary bonds, such as dipole-dipole interactions / van der Waals forces, which cause molecules to be trapped on the surface.

[0015] PETEOS exhibits high wettability due to its low contact angle with water. Specifically, the contact angle between PETEOS and water is 0 degrees. Therefore, the surface of the PETEOS film can trap moisture, as well as chloride or fluoride elements, from the environment or manufacturing processes (such as etching). The presence of these molecules on the surface of the PETEOS film can lead to acid formation. If this acid comes into contact with the bonding pads, bonding pad corrosion may occur.

[0016] In one example, Cl- and moisture on the surface of the PETEOS film can combine to form hydrochloric acid (HCl) that corrodes the bonding pads.

[0017] Plasma-enhanced silicon nitride (PESIN) has a contact angle of 38.04 degrees with water. Therefore, the level of bonding pad corrosion experienced in semiconductor devices with a nitride layer in the passivation layer is less than that experienced in devices with a passivation layer of PETEO only. Consequently, this corrosion problem is more common in optical semiconductor devices using PETEO in both layers of a dual passivation process.

[0018] Moisture cannot be completely removed from the environment. It can only be controlled, for example, by using an alloying process or an N2 box. Therefore, other means are needed to reduce the moisture content of the PETEOS layer.

[0019] To address this failure mechanism, a sandwich passivation layer is provided. According to one aspect of this disclosure, a method for forming a sandwich passivation layer on a semiconductor device including bonding pads is provided, the method comprising:

[0020] A first layer is formed above the surface of the semiconductor device;

[0021] Remove a portion of the first layer to expose the surface of the bonding pads;

[0022] A second layer is formed above the first layer and the bonding pads; and

[0023] A third layer is formed above the second layer;

[0024] The surface of the bonding pad does not contact the first or third layer in order to reduce corrosion of the bonding pad caused by molecules trapped on the surface of the first or third layer.

[0025] Therefore, embodiments of this disclosure provide a sandwich passivation layer that reduces corrosion of the bonding pads by ensuring that the surface of the bonding pads does not contact the first or third layer and is not exposed to molecules trapped on the surfaces of the first and third layers. The surface of the bonding pads is effectively separated from the first and third layers. In embodiments, the molecules include chlorine or fluorine. In embodiments, the molecules include moisture molecules, such as OH.

[0026] In an embodiment, forming the first layer may include forming the first layer on an initial layer formed on a semiconductor device, and removing a portion of the first layer may further include removing a portion of the initial layer to expose the surface of the bonding pads (404). Optionally, the initial layer may be thinner than the first layer. In an embodiment, the height (or thickness) of the initial layer may be less than 500 Å. In an embodiment, the height (or thickness) of the first layer may be equal to the height (or thickness) of the aluminum (Al) top metal layer or the bonding pads. For example, if the Al layer has a height of 4 kA, the first layer may have a height of 4 kA.

[0027] In an embodiment, the method may further include removing a portion of the third and second layers to expose the surface of the bonding pads. This allows for metal-to-metal contact with the surface of the bonding pads.

[0028] In this embodiment, the wettability of the first and third layers can be higher than that of the second layer. As a result, the trapping of molecules and moisture on the surface of the second layer is less than that of the first or third layer. This leads to reduced corrosion of the bonding pads.

[0029] Optionally, the first, second, and third layers may be formed of one or more optically compatible materials used in optical semiconductor devices. Optionally, the first, second, and / or third layers may have high conformality.

[0030] In this embodiment, the first and third layers are formed by plasma-enhanced TEOS (PETEOS).

[0031] In this embodiment, the second layer may be formed of plasma-enhanced oxide (PEOX). PEOX has a different structure than PETEOS, including fewer -O and -OH groups. This reduces temporary bonding, such as dipole-dipole interactions / van der Waals forces between Cl- and -H / -O or -OH elements on the surface of the SiO2 film formed by PEOX. This prevents moisture, as well as Cl- and F- elements, from being trapped on the surface and causing corrosion of the bonding pads.

[0032] By providing a PEOX layer between the first and second layers, some of the drawbacks of known passivation layers can be avoided.

[0033] PEOX layers can have a height of less than 1000A.

[0034] PEOX has a water contact angle of 52.18 degrees, thus exhibiting lower wettability than the first and third layers.

[0035] Furthermore, PEOX is optically compatible when used in optical semiconductor devices because it is conformal.

[0036] In this embodiment, the semiconductor device may be an optical device.

[0037] In this embodiment, the third layer may have a low deposition rate. Specifically, the third layer may be formed at a deposition rate of 500 Å / min or lower. The lower deposition rate establishes good film density and reduces failures or effects due to stress.

[0038] During the formation of the sandwich passivation layer, the first, second, and third layers of the sandwich passivation layer can be formed in the same chamber and / or using the same equipment. This process reduces the need for additional etching and / or masking processes.

[0039] According to a second aspect of this disclosure, a semiconductor device is provided, comprising:

[0040] Bonding pads; and

[0041] Interlayer passivation layer, the interlayer passivation layer comprising:

[0042] First layer;

[0043] The second layer on the first layer; and

[0044] The third layer above the second layer;

[0045] The surface of the bonding pad does not contact the first or third layer in order to reduce corrosion of the bonding pad caused by molecules trapped on the surface of the first or third layer.

[0046] In one embodiment, the first layer is formed on an initial layer formed on a semiconductor device, and the surface of the bonding pads does not contact the initial layer (404).

[0047] In one embodiment, the device also includes openings in the third and second layers that expose the surfaces of the bonding pads 404.

[0048] In this embodiment, the wettability of the first and third layers can be higher than that of the second layer. Therefore, less molecules and moisture are trapped on the surface of the second layer compared to the first or third layer. This results in reduced corrosion of the bonding pads.

[0049] Optionally, the first, second, and third layers may be formed of one or more optically compatible materials used in optical semiconductor devices. Optionally, the first, second, and / or third layers may have high conformality.

[0050] In this embodiment, the first and third layers are formed of plasma-enhanced TEOS (PETEOS). This material is commonly used in optical semiconductor devices due to its conformability and therefore good optical properties.

[0051] In this embodiment, the second layer may be formed of plasma-enhanced oxide (PEOX). PEOX has a different structure than PETEOS, including fewer -O and -OH groups. This reduces temporary bonding, such as dipole-dipole interactions / van der Waals forces between Cl- and -H / -O or -OH elements on the surface of the SiO2 film formed by PEOX. This prevents moisture, as well as Cl- and F- elements, from being trapped on the surface and causing corrosion of the bonding pads.

[0052] PEOX has a water contact angle of 52.18 degrees, thus exhibiting lower wettability than the first and third layers.

[0053] Furthermore, PEOX is optically compatible when used in optical semiconductor devices because it is conformal.

[0054] In this embodiment, the semiconductor device may be an optical device.

[0055] In one embodiment, the PEOX layer may have a low deposition rate. In another embodiment, the second layer may be formed at a deposition rate of 500 Å / min or lower. In yet another embodiment, the second layer may be formed at a deposition rate of 500 Å / min.

[0056] The process of forming the interlayer passivation layer can be an in-situ chamber process. Therefore, the formation of the interlayer passivation layer will not affect any etching process.

[0057] Compared with these known methods for preventing corrosion, the method and apparatus disclosed herein for reducing corrosion of aluminum bonding pads in semiconductor devices have the following advantages:

[0058] 1. This method and equipment effectively reduce corrosion of bonding pads caused by chlorine.

[0059] 2. The conformal properties of PEOX mean that sandwich passivation layers can be used in optical semiconductor devices.

[0060] 3. Improved BEOL output by reducing corrosion of bonding pads and thus reducing equipment failures.

[0061] 4. In the formation of the interlayer passivation layer, the first, second, and third layers are formed in the same chamber and / or using the same equipment. Optionally, the initial layer may also be formed in the same chamber or using the same equipment.

[0062] 5. This method and apparatus can utilize the low deposition rate of the third layer.

[0063] Finally, the method and semiconductor device disclosed herein utilize a novel approach, at least because they provide an interlayer passivation layer for reducing bonding pad corrosion. Attached Figure Description

[0064] Some embodiments of this disclosure will now be described by way of example only and with reference to the accompanying drawings, in which:

[0065] Figure 1 illustrates a semiconductor device known in the prior art.

[0066] Figure 2a The image shows pad corrosion found at the bonding pads in X-ray cross-section (XSEM) during failure mode analysis.

[0067] Figure 2b The failure mechanism of aluminum bonding pad corrosion is shown.

[0068] Figure 3 The contamination of the PETEOS film in the passivation layer is shown.

[0069] Figure 4a A semiconductor device according to this disclosure is shown.

[0070] Figure 4b A semiconductor device according to this disclosure is shown.

[0071] Figure 4c A semiconductor device according to this disclosure is shown.

[0072] Figure 4d A semiconductor device according to this disclosure is shown.

[0073] Figure 5 The method according to this disclosure is shown.

[0074] Figure 6 The method according to this disclosure is shown. Detailed Implementation

[0075] Generally, this disclosure provides a sandwich or composite passivation layer to reduce corrosion of bonding pads in semiconductor devices. The sandwich passivation layer includes a first layer, a third layer, and a second layer between the first and third layers. This reduces corrosion of the bonding pads caused by molecules trapped on the surface of the first or third layer.

[0076] Some examples of solutions are given in the attached figures.

[0077] Figure 4a A semiconductor device 400 according to an embodiment of the present disclosure is illustrated. The semiconductor device 400 includes a semiconductor substrate 401 on which a device layer 402 providing a device structure is formed. In an embodiment, the device structure is an optical structure. For example, the device structure may be a light-emitting diode or a photodiode. The device layer 402 also includes any interconnect layers required to enable connection to portions of the device structure.

[0078] An initial layer 403 is formed above the device layer 402. The initial layer 403 may be a top dielectric layer. In an embodiment, the initial layer is formed of PETEOS.

[0079] The bonding pad 404 may be made of an aluminum-copper (Al-Cu) composite material. The surface of the bonding pad 404 defines an area on the surface of a top metal layer for forming a metal bond to, for example, a wire, contact, device, or circuit board.

[0080] A sandwich passivation layer 405 is formed above the initial layer. The sandwich passivation layer 405 includes a first layer 406, a second layer 407 above the surfaces of the first layer 406 and the bonding pads 404, and a third layer 408 above the second layer 407. Figure 4a It can be seen that the surface of the bonding pad 404 does not contact the first layer 406 or the third layer 407.

[0081] refer to Figure 4a and Figure 5 The method for generating the interlayer passivation layer is described in detail below.

[0082] In step S501, a first layer 406 is formed over the initial layer 403, covering the bonding pads 404. The first layer 406 is formed using a CVD process or a PECVD process. The deposition rate (A / min) of the first layer 406 will depend on the thickness of the metal layer 404. In an embodiment, the deposition rate is in the range of 2000 to 8000 A / min. In an embodiment, the first layer 406 is formed from PETEOS.

[0083] In step S502, a portion of the first layer 406 is removed to form an opening above the bonding pad 404. In this embodiment, this is achieved through an etching process. However, it will be apparent to those skilled in the art that other techniques, such as chemical mechanical polishing (CMP), can be used.

[0084] In step S503, a second layer 407 is formed over the surfaces of the first layer 406 and the bonding pads 404. The second layer 407 is formed using a CVD process or a PECVD process. The deposition rate (A / min) of the second layer can be less than 500 A / min. In an embodiment, the second layer 407 has less wettability than the first layer 406. In an embodiment, the second layer 407 is formed of PEOX.

[0085] In step S504, a third layer 408 is formed on the second layer 407. The third layer is formed using a CVD process or a PECVD process. In an embodiment, the second layer 407 has less wettability than the third layer 408. In an embodiment, the third layer 408 is formed from PETEOS.

[0086] refer to Figure 6 In an embodiment, the method may include additional steps. Optionally, an initial layer 403 may be formed on the semiconductor device 400 before the formation of the first layer 406 (S601). Thus, in S602, the first layer 406 is formed on the initial layer 403, and in S603, a portion of the first layer 406 and the initial layer 403 are removed to expose the bonding pads 404.

[0087] Steps S604 and S605 are equivalent to S503 and S504 above.

[0088] In step S606, a portion of the third layer 408 and the second layer 407 is removed to form an opening above the bonding pad 404 and expose the surface of the bonding pad 404, as shown. Figure 4b As shown. In this embodiment, this is achieved through an etching process. However, it will be apparent to those skilled in the art that other techniques, such as chemical mechanical polishing (CMP), can be used.

[0089] Alternatively, the interlayer passivation layer 405 can then be etched or subjected to CMP, such that a much thinner second layer 407 remains on the surface of the bonding pad 404, as... Figure 4c and Figure 4d As shown. This thinner second layer 407 will protect the surface of the bonding pad 404 until metal contact is required. An additional removal step is required to remove the thinner second layer 407 before metal contact can be formed on the surface of the bonding pad 404.

[0090] The embodiments disclosed herein can be used in many different semiconductor manufacturing applications, including optical devices, in the optical equipment industry and other industries.

[0091] List of reference numerals in the attached diagram:

[0092] 100 Semiconductor Equipment

[0093] 101 Semiconductor Substrate

[0094] 102 Top Dielectric Layer

[0095] 103 Bonding Pads

[0096] 104 passivation layer

[0097] 104a silicon dioxide

[0098] 104b silicon nitride

[0099] 400 Semiconductor Equipment

[0100] 401 Semiconductor Substrate

[0101] 402 Equipment Layer

[0102] 403 Initial Layer

[0103] 404 bonding pads

[0104] 405 Interlayer Passivation Layer

[0105] 406 First Floor

[0106] 407 Second Floor

[0107] 408 Third Floor

[0108] Those skilled in the art will understand that positional terms such as “up,” “along,” and “side” in the foregoing description and appended claims are used with reference to conceptual illustrations such as those shown in the accompanying drawings. These terms are used for ease of reference but are not intended to be restrictive. Therefore, these terms should be understood to refer to objects when positioned as shown in the accompanying drawings.

[0109] Although this disclosure has been described with reference to preferred embodiments as described above, it should be understood that these embodiments are merely illustrative and the claims are not limited to those embodiments. In view of the content of this disclosure, those skilled in the art will be able to make modifications and substitutions, which are considered to fall within the scope of the appended claims. Each feature disclosed or shown in this specification may be incorporated in any embodiment, either alone or in any suitable combination with any other feature disclosed or shown herein.

Claims

1. A method for forming an interlayer passivation layer (405) on a semiconductor device (400) including bonding pads (404), the method comprising: A first layer (406) is formed above the surface of the semiconductor device (400); Remove a portion of the first layer (406) to expose the surface of the bonding pad (404); A second layer (407) is formed above the first layer (406) and on the exposed surface of the bonding pad (404); and A third layer (408) is formed above the second layer (407); The surface of the bonding pad (404) does not contact the first layer (406) or the third layer (408), and the wettability of the first layer (406) and the third layer (408) is higher than that of the second layer (407).

2. The method of claim 1, wherein forming the first layer (406) includes forming the first layer (406) on an initial layer (403) formed on the semiconductor device (400), wherein removing a portion of the first layer (406) further includes removing a portion of the initial layer to expose the surface of the bonding pad (404), and wherein the surface of the bonding pad (404) is not in contact with the initial layer (403).

3. The method of claim 1, further comprising removing a portion of the third layer (408) and the second layer (407) to expose the surface of the bonding pad.

4. The method according to claim 1, wherein the first layer (406) and the third layer (408) are formed by plasma-enhanced TEOS (PETEOS).

5. The method according to claim 1, wherein the second layer (407) is formed of plasma-enhanced oxide (PEOX).

6. The method according to claim 1, further wherein the semiconductor device (400) is an optical device.

7. The method of claim 1, wherein the third layer (408) is formed at a deposition rate of 500 Å / min or lower.

8. The method of claim 1, wherein the first layer, the second layer and the third layer are formed using the same equipment.

9. A semiconductor device (400), comprising: Joining pads (404); as well as Intercalated passivation layer (405), the intercalated passivation layer (405) includes: First floor (406); The second layer (407) on the first layer (406); and The third layer (408) above the second layer; The surface of the bonding pad (404) does not contact the first layer (406) or the third layer (408), and The second layer is in direct contact with at least a portion of the surface of the bonding pad, and the wettability of the first layer (406) and the third layer (408) is higher than that of the second layer (407).

10. The device according to claim 9, wherein the first layer (406) is formed on an initial layer (403) formed on the semiconductor device (400), and wherein the surface of the bonding pad (404) does not contact the initial layer (403).

11. The device of claim 9, further comprising openings in the third layer (408) and the second layer (407) to expose the surface of the bonding pad (404).

12. The device according to claim 9, wherein the first layer (406) and the third layer (408) are formed by plasma-enhanced TEOS (PETEOS).

13. The device according to claim 9, wherein the second layer (407) is formed of plasma-enhanced oxide (PEOX).

14. The device according to claim 9, further wherein the semiconductor device (400) is an optical device.

15. The device of claim 9, wherein the third layer (408) is formed at a deposition rate of 500 Å / min or less.

16. The device of claim 9, wherein the first layer, the second layer and the third layer are formed using the same equipment.

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