Semiconductor Package

Abstract

A heat sink (3) is provided on the upper surface of the cooling plate (1) via an insulating layer (2). A semiconductor chip (4) is provided on the heat sink (3). A molding resin (10) encapsulates the upper surface of the cooling plate (1), the heat sink (3) and the semiconductor chip (4). The insulating layer (2) does not extend further to the side than the heat sink (3). A groove (11) is provided on the upper surface of the cooling plate (1) below the outer periphery of the heat sink (3). The insulating layer (2) is provided in a manner suspended above the groove (11).

Description

Technical Field

[0001] The present invention relates to a semiconductor package used in a power control device or the like. Background Art

[0002] A semiconductor package is being used in which a heat sink is provided on a cooling plate via an insulating layer. Currently, in order to ensure the insulation distance between the cooling plate and the heat sink, the area of ​​the insulating layer is increased so that the insulating layer extends to the side of the heat sink (for example, see Patent Document 1).

[0003] Patent Document 1: Japanese Patent Application Publication No. 2014-183058 Summary of the invention

[0004] As the area of ​​the insulating layer increases, the area of ​​the cooling plate also increases, which causes a problem that the size of the semiconductor package increases.

[0005] The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor package that can ensure insulation and be downsized.

[0006] The semiconductor package involved in the present invention is characterized in that it comprises: a cooling plate; a heat sink, which is arranged on the upper surface of the cooling plate via an insulating layer; a semiconductor chip, which is arranged on the heat sink; and a molding resin, which encapsulates the upper surface of the cooling plate, the heat sink and the semiconductor chip, the insulating layer does not extend further to the side than the heat sink, and a groove is provided on the upper surface of the cooling plate below the outer periphery of the heat sink, and the insulating layer is provided in a manner suspended above the groove.

[0007] Effects of the Invention

[0008] In the present invention, the insulating layer does not extend further to the side than the heat sink, so it is not necessary to increase the area of ​​the cooling plate. In addition, a groove is provided on the upper surface of the cooling plate below the outer peripheral portion of the heat sink. The insulating layer is provided in a manner suspended above the groove. Thus, the insulation distance between the cooling plate and the heat sink can be ensured. Thus, the size of the semiconductor package can be miniaturized while ensuring insulation. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a cross-sectional view showing the semiconductor package according to the first embodiment.

[0010] Figure 2 It is a top view showing the upper surface of the cooling plate.

[0011] Figure 3 It is a plan view showing a state where a heat sink and the like are installed on the cooling plate.

[0012] Figure 4 is a cross-sectional view showing a semiconductor package according to a comparative example.

[0013] Figure 5 It is a cross-sectional view showing a semiconductor package according to the second embodiment.

[0014] Figure 6 It is a cross-sectional view showing a semiconductor package according to the third embodiment.

[0015] Figure 7 It is a cross-sectional view showing a semiconductor package according to a fourth embodiment.

[0016] Figure 8 It is a cross-sectional view showing a semiconductor package according to the fifth embodiment.

[0017] Fig. 9 is a cross-sectional view showing a cooling plate having a groove portion without a tapered portion.

[0018] Fig.10 It is a cross-sectional view showing a semiconductor package according to the sixth embodiment.

[0019] Fig.11 It is a cross-sectional view showing a semiconductor package according to the seventh embodiment.

[0020] Fig.12 It is a cross-sectional view showing a semiconductor package according to the eighth embodiment. DETAILED DESCRIPTION

[0021] The semiconductor package according to the embodiment will be described with reference to the drawings. The same reference numerals are used for the same or corresponding components, and duplicate description may be omitted.

[0022] Implementation Method 1

[0023] Figure 1 1 is a cross-sectional view showing a semiconductor package according to Embodiment 1. The cooling plate 1 is a pin fin type having a plurality of heat dissipation fins on the lower surface side. The cooling plate 1 is made of a metal such as copper or aluminum. A heat sink 3 is provided on the upper surface of the cooling plate 1 via an insulating layer 2. The heat sink 3 is made of a metal such as copper and has electrical conductivity. The insulating layer 2 is an epoxy resin filled with a filler. The thickness of the insulating layer 2 is about 0.15 mm to 0.2 mm.

[0024] A semiconductor chip 4 is provided on the heat sink 3. The semiconductor chip 4 is an IGBT, a MOSFET, a diode, etc. The lower surface electrode of the semiconductor chip 4 is bonded to the heat sink 3 via solder 5. The heat generated by the semiconductor chip 4 is conducted to the cooling plate 1 via the solder 5, the heat sink 3, and the insulating layer 2.

[0025] The lead 6 is bonded to the upper surface electrode of the semiconductor chip 4 by solder 7. The lead 8 is bonded to the heat sink 3 by solder 9. The mold resin 10 encapsulates the upper surface of the cooling plate 1, the heat sink 3, the semiconductor chip 4, and a part of the leads 6 and 8. The mold resin 10 is an epoxy resin. The mold resin 10 is filled in the groove 11 of the cooling plate 1.

[0026] The heat sink 3 is an insulating layer integrated heat sink. When viewed from above, the outer shape of the insulating layer 2 is the same as the outer shape of the heat sink 3. That is, the area of ​​the insulating layer 2 is the same as the area of ​​the heat sink 3. Therefore, the insulating layer 2 does not extend further to the side than the heat sink 3.

[0027] A groove 11 is provided on the upper surface of the cooling plate 1 below the outer periphery of the heat sink 3. The depth of the groove 11 is about 0.5 mm to 1.0 mm. The width of the groove 11 is about 2.0 mm to 3.0 mm. The insulating layer 2 is provided so as to be suspended above the groove 11. The length of the insulating layer 2 suspended above the groove 11 is about 1.0 mm to 1.5 mm.

[0028] Figure 2 It is a top view showing the upper surface of the cooling plate. Figure 3 1 is a plan view showing a state where a heat sink and the like are installed on the cooling plate. The groove 11 is provided in a quadrangular frame shape so as to surround the entire periphery of the heat sink 3. However, the groove 11 may be provided so as to surround only a portion of the heat sink 3.

[0029] Next, the effects of the present embodiment will be described in comparison with a comparative example. Figure 4 1 is a cross-sectional view showing a semiconductor package according to a comparative example. In the comparative example, the groove 11 is not provided on the upper surface of the cooling plate 1. Therefore, in order to ensure the insulation distance between the cooling plate 1 and the heat sink 3, the area of ​​the insulating layer 2 is increased so that the insulating layer 2 extends further to the side than the heat sink 3. In conjunction with this, there is a problem that the size of the semiconductor package increases due to the increase in the area of ​​the cooling plate 1.

[0030] In contrast, in the present embodiment, the insulating layer 2 does not extend further to the side than the heat sink 3. Therefore, the area of ​​the insulating layer 2 is small, and thus it is not necessary to increase the area of ​​the cooling plate 1. In addition, a groove 11 is provided on the upper surface of the cooling plate 1 below the outer periphery of the heat sink 3. The insulating layer 2 is provided so as to be suspended above the groove 11. Thus, the insulation distance between the cooling plate 1 and the heat sink 3 can be ensured. Thus, the insulation can be ensured and the size of the semiconductor package can be miniaturized.

[0031] Implementation Method 2

[0032] Figure 51 is a cross-sectional view showing a semiconductor package according to Embodiment 2. A notch 12 is provided on the side surface of the heat sink 3. By utilizing the notch 12, the heat sink 3 can be easily transported during manufacturing. The other structures and effects are the same as those of Embodiment 1.

[0033] Implementation 3

[0034] Figure 6 1 is a cross-sectional view showing a semiconductor package according to Embodiment 3. A tapered portion 13 inclined toward the center of the cooling plate 1 is provided on the side surface outside the groove portion 11. During resin encapsulation, the molding resin 10 is injected from the upper side of the tapered portion 13. The molding resin 10 flows along the tapered portion 13, so that the molding resin 10 easily flows into the groove portion 11. Other structures and effects are the same as those of Embodiment 1.

[0035] Implementation 4

[0036] Figure 7 2 is a cross-sectional view of a semiconductor package according to Embodiment 4. A dimple 14 is provided on the upper surface of the cooling plate 1 in an area other than the contact surface with the insulating layer 2. The depth of the dimple 14 is about 0.1 mm and the size is about φ0.25 mm. By providing the dimple 14, the adhesion between the cooling plate 1 and the molding resin 10 is improved. In addition, the dimple 14 is not provided on the contact surface with the insulating layer 2, so that heat dissipation can be ensured. Furthermore, the dimple 14 may be provided only in the groove portion 11. Other structures and effects are the same as those of Embodiment 1.

[0037] Implementation method 5

[0038] Figure 8 1 is a cross-sectional view showing a semiconductor package according to Embodiment 5. A tapered portion 15 is provided on the inner side surface of the groove portion 11 . Fig. 9 1 is a cross-sectional view showing a cooling plate having a groove without a tapered portion. When the groove 11 without the tapered portion 15 is formed by cutting, burrs 16 may be generated at the end of the groove 11. Since the inner part of the groove 11 is the mounting part of the insulating layer 2 and the heat sink 3, the presence of burrs 16 will hinder the mounting. In contrast, by providing the tapered portion 15 on the inner side of the groove 11, the generation of burrs 16 at the mounting part can be suppressed. The other structures and effects are the same as those of the first embodiment.

[0039] Implementation 6

[0040] Fig.101 is a cross-sectional view showing a semiconductor package according to Embodiment 6. An inverted tapered anchor structure 17 inclined toward the center of the cooling plate 1 is provided on the side surface outside the groove 11. The molding resin 10 enters the gap of the anchor structure 17, thereby improving the adhesion between the cooling plate 1 and the molding resin 10. The other structures and effects are the same as those of Embodiment 1.

[0041] Implementation 7

[0042] Fig.11 1 is a cross-sectional view showing a semiconductor package according to Embodiment 7. The groove 11 extends to the outer end of the cooling plate 1. Therefore, on the upper surface of the cooling plate 1, only the insulating layer 2 and the mounting portion of the heat sink 3 protrude and have a step, forming a simple structure. By simplifying the structure of the cooling plate 1, the manufacturing process of the cooling plate 1 can be simplified. The other structures and effects are the same as those of Embodiment 1.

[0043] Implementation 8

[0044] Fig.12 2 is a cross-sectional view showing a semiconductor package according to Embodiment 8. The cooling plate 1 of Embodiments 1 to 7 is a pin fin type, but the cooling plate 1 of this embodiment is a base plate without heat dissipation fins. In this case, the same effects as those of Embodiment 1 can be obtained.

[0045] In addition, the semiconductor chip 4 is not limited to being formed of silicon, and can also be formed of a wide bandgap semiconductor having a larger bandgap than silicon. Examples of wide bandgap semiconductors are silicon carbide, gallium nitride-based materials, or diamond. The power semiconductor chip formed of such a wide bandgap semiconductor can be miniaturized due to its high voltage resistance and allowable current density. By using the miniaturized semiconductor chip, the semiconductor module assembled with the semiconductor chip can also be miniaturized. In addition, since the semiconductor chip has high heat resistance, the cooling plate of the radiator can be miniaturized, and the water cooling part can be air-cooled, so the semiconductor module can be further miniaturized. In addition, since the semiconductor chip has low power loss and high efficiency, the semiconductor module can be made more efficient.

[0046] Description of the label

[0047] 1 cooling plate, 2 insulating layer, 3 heat sink, 4 semiconductor chip, 10 molding resin, 11 groove, 12 cutout, 13 tapered portion, 14 recess, 15 tapered portion, 17 anchor structure

Claims

1. A semiconductor package, It is characterized in that have: Cooling plate; a heat sink disposed on the upper surface of the cooling plate via an insulating layer; a semiconductor chip disposed on the heat sink; and a molding resin that encapsulates the upper surface of the cooling plate, the heat sink, and the semiconductor chip, The insulating layer does not extend further than the heat sink to the sides. A groove is provided on the upper surface of the cooling plate below the outer periphery of the heat sink. The insulating layer is arranged to be suspended above the groove portion. The groove portion has an inner peripheral wall located on the inner peripheral side and an outer peripheral wall located on the outer peripheral side, and the molding resin is filled in the entire space between the inner peripheral wall and the outer peripheral wall of the groove portion.

2. The semiconductor package according to claim 1, It is characterized in that A cutout is arranged on the side of the heat sink.

3. The semiconductor package according to claim 1 or 2, It is characterized in that A tapered portion is provided on the outer side surface of the groove portion.

4. The semiconductor package according to claim 1 or 2, It is characterized in that The upper surface of the cooling plate is provided with a recess in a region other than a contact surface with the insulating layer.

5. The semiconductor package according to claim 1 or 2, It is characterized in that A tapered portion is provided on the inner side surface of the groove portion.

6. The semiconductor package according to claim 1 or 2, It is characterized in that An anchor structure is provided on the side surface outside the groove portion.

7. The semiconductor package according to claim 1 or 2, It is characterized in that The cooling plate is a susceptor plate.

8. The semiconductor package according to claim 1 or 2, It is characterized in that The semiconductor chip is formed of a wide bandgap semiconductor.

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