non-linear correction

Abstract

The nonlinear correction circuit (200) includes a nonlinear coefficient estimation circuit (204). The nonlinear coefficient estimation circuit (204) includes a data capture circuit (206), a nonlinear term generation circuit (208), a time-to-frequency conversion circuit (210), a bin identification circuit (212), a residual nonlinear conversion circuit (214), and a nonlinear coefficient generation circuit (216). The nonlinear term generation circuit (208) is coupled to the data capture circuit (206). The time-to-frequency conversion circuit (210) is coupled to the data capture circuit (206) and the nonlinear term generation circuit (208). The bin identification circuit (212) is coupled to the time-to-frequency conversion circuit (210). The residual nonlinear conversion circuit (214) is coupled to the bin identification circuit (212). The nonlinear coefficient generation circuit (216) is coupled to the bin identification circuit (212) and the residual nonlinear conversion circuit (214).

Description

Background Technology

[0001] An analog-to-digital converter (ADC) is a circuit that converts a continuous-time signal (e.g., voltage or current) into a discrete-time representation, which is proportional in amplitude to the continuous-time signal. ADCs are used for signal measurement in various electronic systems, such as mobile phones, audio and video devices, wired communication systems, measurement devices, and radar systems. Various error sources can affect ADC performance. For example, all types of ADCs can suffer from quantization errors, nonlinearities, and / or clock jitter. Summary of the Invention

[0002] The nonlinear correction circuit includes a nonlinear coefficient estimation circuit. The nonlinear coefficient estimation circuit includes a data acquisition circuit, a nonlinear term generation circuit, a time-frequency conversion circuit, a bin identification circuit, a residual nonlinear conversion circuit, and the nonlinear coefficient generation circuit. The nonlinear term generation circuit is coupled to the data acquisition circuit. The time-frequency conversion circuit is coupled to both the data acquisition circuit and the nonlinear term generation circuit. The bin identification circuit is coupled to the time-frequency conversion circuit. The residual nonlinear conversion circuit is coupled to the bin identification circuit. The nonlinear coefficient generation circuit is coupled to both the bin identification circuit and the residual nonlinear conversion circuit.

[0003] A nonlinear correction circuit includes a data path, a reference path, a nonlinear term generation circuit, a bin identification circuit, a residual nonlinear conversion circuit, and a nonlinear coefficient generation circuit. The data path includes a first digital step attenuator (DSA), a first analog-to-digital converter (ADC), a first data acquisition circuit coupled to the first ADC, and a first time-frequency conversion circuit coupled to the first data acquisition circuit. The reference path includes a second DSA, a second ADC, a second data acquisition circuit, a second time-frequency conversion circuit, a channel estimation circuit, a channel equalization circuit, and a source nonlinear subtraction circuit. The second DSA includes an input coupled to the input of the first DSA. The second ADC is coupled to the second DSA. The second data acquisition circuit is coupled to the second ADC. The second time-frequency conversion circuit is coupled to the second data acquisition circuit. The channel estimation circuit is coupled to both the first and second time-frequency conversion circuits. The channel equalization circuit is coupled to both the channel estimation circuit and the second time-frequency conversion circuit. The source nonlinear subtraction circuit is coupled to both the channel equalization circuit and the first time-frequency conversion circuit. The nonlinear term generation circuit is coupled to both the first data acquisition circuit and the first time-frequency conversion circuit. The bin identification circuit is coupled to both the source nonlinear subtraction circuit and the first time-frequency conversion circuit. The residual nonlinear conversion circuit is coupled to the bin identification circuit. The nonlinear coefficient generation circuit is coupled to both the bin identification circuit and the residual nonlinear conversion circuit.

[0004] A method for nonlinear correction includes receiving signals as inputs to a main data path and a reference data path. The signals are digitized by a first analog-to-digital converter (ADC) of the main data path and a second ADC of the reference data path. The output of the second ADC is subtracted from the output of the first ADC. Nonlinear correction coefficients are estimated based on the signal after subtraction. The nonlinear correction coefficients are applied to the signals to generate nonlinear correction data. Attached Figure Description

[0005] For a detailed description of the various examples, reference will now be made to the accompanying drawings, in which:

[0006] Figure 1 A block diagram of a system including nonlinear correction for an analog-to-digital converter is shown;

[0007] Figure 2 A block diagram of a nonlinear correction circuit according to the present disclosure is shown;

[0008] Figure 3 A block diagram of a warehouse identification circuit according to the present disclosure is shown;

[0009] Figure 4A , Figure 4B and Figure 4C An example warehouse identification for generating correction coefficients according to this disclosure is shown;

[0010] Figure 5 A block diagram of a digital nonlinear corrector circuit is shown.

[0011] Figure 6 Example results of nonlinear correction according to this disclosure are shown;

[0012] Figure 7 A block diagram of a nonlinear correction circuit according to the present disclosure is shown, which includes a reference data path that subtracts the input signal from the signal used to generate the nonlinear correction coefficients.

[0013] Figure 8 It shows that it is suitable for use in Figure 7 A block diagram of the channel estimation circuit used in the reference data path;

[0014] Figure 9 It shows that it is suitable for use in Figure 7 A block diagram of the channel equalization circuit used in the reference data path; and

[0015] Figure 10 and Figure 11 A flowchart of a method for nonlinear correction according to this disclosure is shown. Detailed Implementation

[0016] In this specification, the term "coupled" refers to an indirect or direct wired or wireless connection. Therefore, if a first device is coupled to a second device, the connection can be either a direct connection or an indirect connection via other devices and connections. Furthermore, in this specification, the term "based on" means "at least partially based on". Therefore, if X is based on Y, then X can be a function of Y and any number of other factors.

[0017] In some applications, analog-to-digital converters (ADCs) must meet stringent harmonic distortion and / or intermodulation distortion specifications. For example, ADCs used in wireless infrastructure must meet stringent third harmonic distortion and intermodulation distortion requirements to comply with cellular system standards. Harmonic distortion (e.g., third harmonic distortion) and intermodulation distortion of an ADC can be improved by applying factory-calibrated digital nonlinearity correction to the ADC's output. Because ADCs can operate over a wide range of sampling rates, and all sampling rates require good nonlinearity performance, some nonlinearity correction systems provide nonlinearity correction coefficients for each supported sampling rate, Nyquist zone, and digital step attenuator (DSA) range, and store them in memory. The time required to perform factory calibration and the memory required to store the coefficients increase equipment costs. Factory calibration does not account for other sources of nonlinearity, such as second-order nonlinearity caused by the circuit board on which the equipment is mounted, and variations due to temperature, voltage, and / or aging.

[0018] The nonlinear correction circuit disclosed herein determines the nonlinear correction coefficients during operation. Therefore, the cost of the equipment can be reduced by eliminating the need for in-plant calibration and non-volatile storage of correction coefficients. The nonlinear correction circuit includes a nonlinear coefficient estimation circuit that captures data at the input or output of the nonlinear corrector circuit, generates a nonlinear term based on the captured data, and transforms the captured data and the nonlinear term from the time domain to the frequency domain. A frequency bin with a low-level signal and a high-level nonlinear term is selected for nonlinear correction coefficient estimation. If the output of the nonlinear corrector circuit is captured, the response of the captured data is converted from residual nonlinearity to full nonlinearity. The nonlinear correction coefficients are estimated based on the nonlinear term of the selected frequency bin and the captured data.

[0019] In some systems, the ADC input signal is highly nonlinear. For example, digital predistortion can be applied to the ADC input signal. The implementation of the nonlinearity correction circuit disclosed herein ensures that the ADC nonlinearity is corrected and that the nonlinearity in the ADC input signal is unaffected by the nonlinearity correction. The nonlinearity correction circuit includes a main data path and a reference data path. The input signal is digitized in each data path and converted from the time domain to the frequency domain. A channel estimate for the reference data path is calculated relative to the main data path, and the channel estimate is applied to equalize the reference data path. The equalized reference data path data is subtracted from the main data path data, and the difference, along with the main data path ADC output, is provided to a nonlinearity coefficient estimation circuit to generate nonlinearity correction coefficients.

[0020] Figure 1 A block diagram of a system 100 including nonlinear correction for an analog-to-digital converter is shown. In some examples, system 100 implements part of an RF receiver. System 100 includes a digital step attenuator (DSA) circuit 102, an ADC 104, a nonlinear corrector circuit 106, a nonlinear correction coefficient estimator 108, and a digital signal processing circuit 118. Some implementations of system 100 include a second DSA circuit 120 and a second ADC 122. The digital signal processing circuit 118 is implemented in a digital signal processor (DSP) or other digital circuitry system and includes a digital down-converter 110. The DSA circuit 102 attenuates the input signal 112 by an attenuation value, which can be selected by a digital value provided to the DSA circuit 102. In some examples, the input signal 112 is an RF signal and is filtered by a filter circuit 124 (e.g., to limit the bandwidth of the input signal 112). The DSA circuit 102 is coupled to the ADC 104. Similarly, DSA circuit 120 attenuates input signal 112 by an attenuation value, which can be selected by a digital value provided to DSA circuit 120. DSA circuit 120 is coupled to ADC 122. In some embodiments of 100 as further described herein, ADC 122 digitizes 112 with better linearity than ADC 104, and the output of ADC 122 is applied to compensate for nonlinearities in input signal 112.

[0021] ADC 104 digitizes the output of DSA circuit 102. The output of ADC 104 includes nonlinearity introduced by ADC 104 and DSA circuit 102. Nonlinearity corrector circuit 106 receives the digital signal 114 output by ADC 104 and processes the digital signal 114 to compensate for the nonlinearity introduced by ADC 104 and DSA circuit 102. Nonlinearity correction coefficient estimator 108 determines the coefficient values ​​used by nonlinearity corrector circuit 106 to compensate for the nonlinearity of ADC 104 and DSA circuit 102. Nonlinearity correction coefficient estimator 108 estimates nonlinearity correction coefficients for a given sampling rate, Nyquist region, DSA setting, etc., for the operation of ADC 104.

[0022] The nonlinear corrector circuit 106 applies nonlinear correction coefficients to the digital signal 114 to compensate for the nonlinearity of the ADC 104 and DSA circuit 102, and provides the nonlinear correction data 116 to the digital signal processing circuit 118. In the digital signal processing circuit 118, the digital downconverter 110 downconverts the nonlinear correction data 116 and provides the in-phase and quadrature-phase data from the downconverter to downstream circuitry for further processing. For example, the digital downconverter 110 multiplies the nonlinear correction data 116 with the sine and cosine signals of the local oscillator.

[0023] The nonlinearity of the ADC 104 is modeled by applying a multi-tap Voltera model and a derivative-based model to the raw output samples of the ADC 104. For example, the nonlinearity of the ADC 104 can be modeled using second-order and third-order nonlinear terms, such as:

[0024] Second-order term: x 2 [n],x[n]x′[n],x′ 2 [n]

[0025] Third-order term: x 3 [n], x 2 [n]x'[n],x[n]x′ 2 [n],x′ 3 [n], x 2 [n]x[n+1]

[0026] Figure 2A block diagram of a nonlinear correction circuit 200 according to this disclosure is shown. The nonlinear correction circuit 200 eliminates the need for factory testing (and its cost) to generate the numerous sets of coefficients required for nonlinear compensation and the storage required to adapt to the various operating parameters of the DSA circuit 102 and ADC 104. Instead, the nonlinear correction circuit 200 generates nonlinear correction coefficients during operation. The nonlinear correction circuit 200 includes a nonlinear corrector circuit 202 and a nonlinear coefficient estimation circuit 204. The nonlinear corrector circuit 202 is one embodiment of the nonlinear corrector circuit 106 and is coupled to the nonlinear coefficient estimation circuit 204. The nonlinear coefficient estimation circuit 204 generates nonlinear correction coefficients during runtime during normal operation of the nonlinear corrector circuit 202 for use by the nonlinear corrector circuit 202.

[0027] The nonlinear coefficient estimation circuit 204 includes a data acquisition circuit 206, a nonlinear term generation circuit 208, a time-frequency conversion circuit 210, a memory identification circuit 212, a residual nonlinear conversion circuit 214, and a nonlinear coefficient generation circuit 216. The data acquisition circuit 206 is coupled to the input and output of the nonlinear corrector circuit 202 to selectively capture raw data samples of the digital signal 114 or samples of the nonlinear correction data 116 for generating nonlinear correction coefficients.

[0028] Data acquisition circuit 206 is coupled to nonlinear term generation circuit 208 and time-frequency conversion circuit 210. Nonlinear term generation circuit 208 receives acquired data from data acquisition circuit 206 and processes the data to generate nonlinear terms. For example, a set of 256+k samples is captured from x[n] (where x[n] is the output of ADC 104), and different NL terms, such as x, are generated from the captured samples. 3 [n], x 2 [n]x′[n],x 2 [n]x[n+1],(x′[n]) 3For each NL term, 256 samples are generated. Due to the memory effect when generating digital derivatives or other memory terms, an additional "k" samples are captured at the input, i.e., 256+k, to generate a valid 256 samples for each NL term. Digital derivatives are typically generated by antisymmetric FIR filters or other known devices. The nonlinear term generation circuit 208 is coupled to the time-frequency conversion circuit 210 and provides the nonlinear term generated based on the data captured by the data acquisition circuit 206 to the time-frequency conversion circuit 210. The time-frequency conversion circuit 210 converts the data captured by the data acquisition circuit 206 and the nonlinear term generated by the nonlinear term generation circuit 208 from the time domain to the frequency domain. For example, the time-frequency conversion circuit 210 applies a Fast Fourier Transform to the captured data received from the data acquisition circuit 206 and the nonlinear term generated by the nonlinear term generation circuit 208. In some embodiments, the time-frequency conversion circuit 210 applies a Fast Fourier Transform after multiplying the input data by a window function.

[0029] The time-frequency conversion circuit 210 is coupled to the bin identification circuit 212 and provides the frequency domain data and its nonlinear term derived from the data captured by the data acquisition circuit 206 to the bin identification circuit 212. The bin identification circuit 212 processes the frequency domain data to identify the frequency bin to be used to generate the nonlinear correction coefficients. More specifically, the bin identification circuit 212 identifies the frequency bin with a high-level nonlinear term and a low-level input signal to be used to generate the nonlinear correction coefficients. For example, let the nonlinear term be x... 3 [n], x 2 [n]x′[n],x 2 [n]x[n+1],(x′[n]) 3 So, a metric used to determine the nonlinear term created at the high level at the frequency bin is:

[0030] |F(x 3 (n))| 2 +|F(x 2 (n)x′(n))| 2 +|F(x 2 (n)x(n+1))| 2 +|F((x′[n]) 3 )| 2 >NLThresh(1)

[0031] And one metric used to determine the low level of the signal at the frequency compartment is:

[0032] |F(x(n))|<SigThresh (2)

[0033] Both of the above conditions must be met simultaneously before a frequency bin can be selected for estimation.

[0034] Figure 3 A block diagram of a bin identification circuit 300 according to the present disclosure is shown. The bin identification circuit 300 is one embodiment of the bin identification circuit 212. The bin identification circuit 300 includes a signal power circuit 302, a nonlinear term power circuit 304, a signal power comparator 306, a nonlinear term power comparator 308, and a decision circuit 310. The signal power circuit 302 calculates the signal power value for each frequency bin of the frequency domain signal received from the time-frequency conversion circuit 210. Similarly, the nonlinear term power circuit 304 calculates the nonlinear term power value for each frequency bin of the frequency domain nonlinear term received from the time-frequency conversion circuit 210. In some embodiments, for a given frequency bin, the nonlinear term power circuit 304 calculates the nonlinear term power as the sum of the squares or sums of the amplitudes of all nonlinear terms in the given frequency bin. In other embodiments, the amplitudes of nonlinear terms exceeding a threshold are used to calculate the nonlinear term power. In other embodiments, the amplitude of the frequency response of each nonlinear term at a given bin is compared to a threshold, and even if one exceeds the threshold, it is considered to have passed the nonlinear power threshold.

[0035] Signal power comparator 306 compares the frequency bin signal power value generated by signal power circuit 302 with a signal power threshold. Nonlinear term power comparator 308 compares the frequency bin nonlinear term power value generated by nonlinear term power circuit 304 with a nonlinear term power threshold. Decision circuit 310 identifies the frequency bins to be applied in nonlinear correction coefficient estimation based on the results of the comparisons performed by signal power comparator 306 and nonlinear term power comparator 308. Frequency bins with high nonlinear term power (e.g., power above the nonlinear term power threshold) and low signal power (e.g., power below the signal power threshold) are selected for nonlinear correction coefficient estimation. Therefore, decision circuit 310 identifies frequency bins with signal power less than the signal power threshold and nonlinear term power greater than the nonlinear term power threshold as suitable for nonlinear correction coefficient estimation.

[0036] In use for x 3 In the example of [n] or any third-order nonlinear binocular recognition circuit 300 operation, with a monotone input at f, x 3 The frequency response of [n] will be high at f and 3f. The signal level is high at the fundamental frequency f. The bin identification circuit 300 selects only the bins corresponding to 3f for nonlinear correction coefficient estimation.

[0037] In use for x 2 In the example of [n] or any second-order nonlinear binocular recognition circuit 300 operation, with a monotone input at f, x 2The frequency response of [n] will be high at 0 and 2f. The signal level is high at the fundamental frequency f. The bin identification circuit 300 selects only bins corresponding to 0 and 2f for nonlinear correction coefficient estimation.

[0038] In use for x 2 In the example of [n] or any second-order nonlinear binocular recognition circuit 300 operation, with two tone inputs at f1 and f2, x 2 The frequency response of [n] will be high at 0, f2-f1, 2f1, f1+f2, and 2f2. The bin identification circuit 300 selects only the bins corresponding to 0, f2-f1, 2f1, f1+f2, and 2f2 for nonlinear correction coefficient estimation.

[0039] In an example of the operation of the cannon identification circuit 300 for the combination of second- and third-order nonlinear terms, when there is a monotone input at f, the cannon identification circuit 300 selects only the cannons corresponding to 0, 2f, and 3f for the estimation of nonlinear correction coefficients.

[0040] In an example of the operation of the bin identification circuit 300 for the combination of second-order and third-order nonlinear terms, with two tone inputs at f1 and f2, the bin identification circuit 300 selects the second-order bins (0, f2-f1, 2f1, f1+f2 and 2f2) and the third-order bins (2f1-f2, 2f2-f1, 2f1+f2, 3f1, 3f2, 2f2+f1), excluding the basic bins f1 and f2.

[0041] Figure 4A and Figure 4B An example warehouse identification is shown in the warehouse identification circuit 300. Figure 4A The signal power with two-tone inputs having frequencies f1 and f2 is shown. For this input signal, the third-order nonlinear term (x) 3 Or any other third-order nonlinear term has eight components at 2f1-f2, f1, f2, 2f2-f1, 2f1+f2, 3f1, 3f2, and 2f2+f1. Based on a comparison of the signal and the nonlinear term with their respective power thresholds, frequency bins at 2f1-f2, 2f2-f1, 2f1+f2, 3f1, 3f2, and 2f2+f1 are selected by bin identification circuit 300 for nonlinear correction coefficient estimation.

[0042] Although this article has provided examples of monotone and ditone to describe the operation of the warehouse recognition circuit 300, in practice, the input signal is narrowband or wideband modulated data. Figure 4CExample bin identification for wideband data occupying the frequency band from f1 to f2 is shown. The regions selected for estimating the third-order nonlinear term are (2f1-f2 to f1), (f2 to 2f2-f1), and (3f1 to 3f2). The regions selected for estimating the second-order term are (0 to f2-f1) and (2f1 to 2f2). These regions can be aliased back to specific frequencies based on the sampling rate of the ADC104. In some cases, if the aliasing frequency falls back into the signal band, these frequency bins will not be used because they will not pass the signal power check.

[0043] Return now Figure 2 The residual nonlinear conversion circuit 214 is coupled to the bin identification circuit 212 and allows the nonlinear correction data 116 generated by the nonlinear corrector circuit 202 to be used as input to the nonlinear coefficient estimation circuit 204, which provides performance improvement for second-order effects caused by large original nonlinear levels. The residual nonlinear conversion circuit 214 modifies the frequency response of the nonlinear correction data 116 by adding multiple correction terms to the frequency response of the nonlinear correction data 116. Each correction term is the product of the frequency response of each nonlinear term and the corresponding correction coefficient value applied in the nonlinear corrector circuit 202. This modification of the frequency response of the nonlinear correction data 116 transforms the nonlinear measurement from a “residual nonlinear measurement” to a “fully nonlinear measurement.”

[0044] The frequency bins identified by bin identification circuit 212 and modified by residual nonlinear conversion circuit 214 are processed by nonlinear coefficient generation circuit 216 to estimate and track nonlinear correction coefficients for each DSA range for use by nonlinear corrector circuit 202. Nonlinear coefficient generation circuit 216 is coupled to bin identification circuit 212 and residual nonlinear conversion circuit 216 and generates nonlinear correction coefficients for the current usage configuration of DSA circuit 102 and ADC 104. In some embodiments, nonlinear coefficient generation circuit 216 includes a vector Kalman filter to generate nonlinear correction coefficients. At the frequency bins selected by bin identification circuit 212, the nonlinear term response is used as a weight for the coefficients to be estimated, and the “fully nonlinear measurement” provided by residual nonlinear conversion circuit 214 is used as the measurement, as shown by the matrix relationship in equation (7).

[0045] Figure 5 A block diagram of an example nonlinear corrector circuit 202 is shown. In the nonlinear corrector circuit 202, a nonlinear term generator 502 generates various nonlinear terms (e.g., the second-order and third-order nonlinear terms shown above for nonlinear correction). The estimated coefficient values ​​(C1… ... N This is then provided to the nonlinear corrector circuit 202 for nonlinear correction. The coefficient values ​​vary depending on the specific DSA circuit 102, ADC 104, and temperature.

[0046] Assume that digital nonlinearity correction applied to ADC 104 or analog circuits is modeled using the following four terms:

[0047] y[n]=x[n]+c1x 3 [n]+c2x 2 [n]x′[n]+c3x 2 [n]+c4x[n]x′[n]+noise (3)

[0049] in:

[0050] x[n] is the discrete output of the ADC 104 or analog circuit;

[0051] x′[n] is the effective derivative of x[n], which is the output of ADC 104;

[0052] c i These are the coefficients of each nonlinear term; and

[0053] y[n] is the output of the digital nonlinear corrector.

[0054] Equation (3) can be written in the frequency domain as:

[0055]

[0056] Equation (4) is valid for each frequency cell.

[0057] The left side of equation (4) represents the nonlinearity introduced by the ADC 104 or related analog circuitry. At frequencies where there is no ADC input signal, equation (4) can be written as:

[0058]

[0059] Equation (5) can be used to estimate the nonlinear coefficients C1, C2, C3, and C4. Furthermore, the original nonlinear level is below approximately -55 dBFS. In practice, all frequency bins with signal levels below a threshold (e.g., -55 dBFS) can be used to estimate the coefficients.

[0060] In the selected bin (selected by bin identification circuit 212), the linear equation simplifies to:

[0061]

[0062] The nonlinear correction circuit identifies multiple such linear equations and solves them to estimate the coefficients of all nonlinear terms.

[0063] For each selected cell, there exists a linear equation. For example, for x3 [n] Nonlinear or any other third-order nonlinear or combination of third-order nonlinear terms, providing six equations for each two-tone input. If there are 100 data acquisition blocks in a nonlinear estimation window, then 600 equations will be stored.

[0064]

[0065] in:

[0066] N is the number of equations, for example, in equation (7);

[0067] T is the number of nonlinear terms. Example 1: For x 3 [n], x 2 x′[n], T=2, Example 2: For x 3 [n], x 2 [n]x′[n],x 2 [n]x[n+1],(x′[n]) 3 T = 4;

[0068] h i，j It is the Fourier transform of the j-th nonlinear (NL) term of the i-th equation at the selected frequency bin of the selected capture set;

[0069] c is the Tx1 vector of the coefficients of the NL term to be estimated; and

[0070] m i It is the measurement value of the i-th equation, which is the Fourier transform of the ADC output x[n] in the selected frequency bin from the selected capture set.

[0071] Solve this system of linear equations (Hc = m) (e.g., using techniques based on least squares or Kalman filters) to estimate and track the nonlinear coefficients.

[0072] Some implementations of the nonlinear correction circuit allow nonlinear correction data to be used as input for nonlinear coefficient estimation. If the coefficient estimator input is taken from the input of the nonlinear corrector, the nonlinear estimator sees the entire nonlinearity of the ADC 104. However, if the coefficient estimator input is taken from the output of the nonlinear corrector, the nonlinear estimator only sees the residual nonlinearity left after nonlinear correction.

[0073] HΔc=m→H(cc corr )=m→Hc=Hc corr +m (8)

[0074] Therefore, in some implementations, Hc is used before coefficient estimation. corrAdding to m effectively generates a modified "m" that reflects the entire nonlinearity. This allows the estimator to always estimate the complete ADC nonlinearity. Using the nonlinear corrector output as input to the coefficient estimate results in improved performance due to reduced second-order effects. Other implementations also estimate residual coefficients from the residual nonlinearity and add them to the currently programmed coefficients.

[0075] Figure 6 Example results of nonlinear correction according to the nonlinear correction circuit 200 of this disclosure are shown. Figure 6 In the example, the operation of the nonlinear correction circuit 200 reduces the second and third harmonic distortion from -58 dBFS relative to full scale (dBFS) to -86 dBFS (full decibel scale).

[0076] In some systems, the input signal provided to the ADC 104 for digitization is highly nonlinear (e.g., an input signal with digital predistortion). In such systems, in addition to the nonlinearity of the ADC 104 and DSA circuit 102, the nonlinearity correction circuit 200 also attempts to compensate for the nonlinearity of the input signal. In such systems, some embodiments of the nonlinearity correction circuit of this disclosure include a highly linear, low signal-to-noise ratio reference path to aid in nonlinearity coefficient estimation. In such nonlinearity correction circuits, the reference path helps to subtract the digital step attenuator input (including the source nonlinear component) from the output of the ADC 104. In systems including a reference path, some embodiments of the nonlinearity correction circuit 200 omit checking for low signal power in the bin identification circuit 300 because the fundamental signal has already been removed from the signal processed by the nonlinearity correction circuit 200.

[0077] In practice, the circuit components of the main data path and the reference path are not well matched. For example, there may be gain, delay, and / or bandwidth mismatch between the main data path and the reference path. In some implementations, the mismatch varies with the setting of the digital step attenuator. To compensate for this mismatch, the output of the reference ADC (the ADC in the reference path) is fed to a channel equalizer before being used for signal subtraction. The channel equalizer matches the two data paths to accurately eliminate input signal and source nonlinearities. The following nonlinearity estimation equation is used for estimation at each identified bin:

[0078]

[0079] Once the reference path matches the main path, the output of the reference path effectively represents the inputs of the ADC and DSA circuits, and when subtracted from the output of the ADC 104, what remains are the components introduced by ADC nonlinearity and noise. This is what the right side of equation (9) represents. Note that the reference path may be noisy, and the effect of noise on the estimation can be minimized by averaging over time.

[0080] Ch models the frequency-related mismatch between paths. Subtract Ch*F(x) ref (n) cancels out all ADC inputs present at the selected compartment, so only the nonlinear components of ADC 104 and DSA circuit 102 are retained after cancellation.

[0081] Figure 7 A block diagram of a nonlinear correction circuit 700, including a reference data path, is shown. This reference data path prevents the nonlinear correction circuit 700 from compensating for input signal nonlinearity by subtracting the input signal from the signal used to generate the nonlinear correction coefficients. The nonlinear correction circuit 700 includes a reference path 704. The reference path 704 includes a DSA circuit 706, an ADC 708, a data acquisition circuit 705, a time-frequency conversion circuit 710, a channel estimation circuit 712, a channel equalization circuit 714, and a source nonlinearity subtraction circuit 716. The DSA circuit 706 is similar to the DSA circuit 120. The DSA circuit 706 includes an input coupled to the input of the DSA circuit 102 and an output coupled to the input of the ADC 708. The reference path 704 is more linear than the data path (main data path) formed by the DSA circuit 102 and the ADC 104 (e.g., the ADC 708 is more linear than the ADC 104 but may be noisier). The ADC 104 and ADC 708 digitize the input signal 112.

[0082] Data acquisition circuit 705 is coupled to the output of ADC 708 to capture data samples. Time-frequency conversion circuit 710 is coupled to data acquisition circuit 705. The samples captured by acquisition circuit 705 are provided to time-frequency conversion circuit 710. Time-frequency conversion circuit 710 converts the time-domain captured samples of ADC 708 into a frequency-domain signal 720. For example, time-frequency conversion circuit 710 applies FFT to the output signal received from ADC 708 to generate frequency-domain signal 720.

[0083] Time-frequency conversion circuit 710 is coupled to channel estimation circuit 712. Channel estimation circuit 712 receives frequency domain signal 720 generated by time-frequency conversion circuit 710 and frequency domain signal 718 generated by time-frequency conversion circuit 211, and estimates the channel of the data path formed by DSA circuit 102 and ADC 104 relative to the reference path of DSA circuit 706 and ADC 708. Channel estimation circuit 712 is coupled to channel equalization circuit 714. Channel equalization circuit is also coupled to time-frequency conversion circuit 710. Channel equalization circuit 714 receives channel estimation from channel estimation circuit 712 and applies channel estimation to equalize the frequency domain signal 720 received from time-frequency conversion circuit 710.

[0084] Channel equalization circuit 714 is coupled to source nonlinear subtraction circuit 716. Source nonlinear subtraction circuit 716 receives frequency domain signal 718 and equalized output signal 722 generated by channel equalization circuit 714. Source nonlinear subtraction circuit 716 subtracts equalized output signal 722 from frequency domain signal 718 to effectively remove input signal 112 from the signal provided to bin identification circuit 724. Therefore, the output of source nonlinear subtraction circuit effectively includes the nonlinearity introduced by ADC 104 and DSA circuit 102. Source nonlinear subtraction circuit 716 is coupled to bin identification circuit 724 and provides frequency domain signal 718 (with equalized output signal 722 subtracted) to bin identification circuit 724 for determining nonlinearity correction coefficients. Bin identification circuit 724 is one implementation of bin identification circuit 212 and is also coupled to time-frequency conversion circuit 210.

[0085] Barrier identification circuit 724 and residual nonlinear circuit 214 are coupled to nonlinear coefficient generation circuit 216. 216 estimates the nonlinear coefficients based on the frequency response of the nonlinear term generated by nonlinear term generation circuit 208 and the output of source nonlinear subtraction circuit 716 at the frequency barrier identified by barrier identification circuit 724. At the frequency barrier identified by barrier identification circuit 724, the frequency response of the nonlinear term is used as a weight for the nonlinear coefficients; the output of source nonlinear subtraction circuit 716 is used as a measurement in the nonlinear coefficient estimation.

[0086] Figure 8 A block diagram of a channel estimation circuit 800 for reference path 704 is shown. Channel estimation circuit 800 is one implementation of channel estimation circuit 712. Channel estimation circuit 800 includes a raw channel estimation circuit 802, a base channel removal circuit 804, a base channel memory 806, a slope and intercept estimation circuit 808, a base channel estimator 810, an intercept memory 812, and a slope memory 814. Raw channel estimation circuit 802 receives frequency domain signals 718 and 720 and provides a raw channel estimate for each frequency compartment by correlating the main path frequency domain response with the reference frequency domain response at each compartment. For example, the raw channel estimate is obtained as shown in equation (10). The raw inverse channel estimate is the ratio of the cumulative cross-correlation of the frequency responses of the main path and the reference path to the cumulative power of the main path response for a given frequency compartment.

[0087]

[0088] A base channel removal circuit 804 is coupled to an original channel estimation circuit 802 and a base channel memory 806. The base channel memory 806 provides base channel values ​​to the base channel removal circuit 804 for adjusting the original channel values. The base channel removal circuit 804 receives the original channel estimates generated by the original channel estimation circuit 802 and adjusts each original channel estimate to remove the base channel estimate values. Using the original channel estimates under a given DSA setting and for the estimated bin location, the base channel removal circuit 804 compensates for the base channel response contribution from the original channel estimates at the bin location.

[0089] Slope and intercept estimation circuit 808 is coupled to base channel memory 806 and base channel removal circuit 804. Slope and intercept estimation circuit 808 processes the adjusted channel values ​​received from base channel removal circuit 804 to estimate and track the slope and intercept values ​​set for each DSA. Slope and intercept estimation circuit 808 is coupled to intercept memory 812 and slope memory 814. Slope and intercept estimation circuit 808 stores the intercept value in intercept memory 812 and the slope value in slope memory 814 for use in DSA index values.

[0090] A base channel estimator 810 is coupled to a slope and intercept estimation circuit 808, an intercept memory 812, and a slope memory 814. The base channel estimator 810 uses slope and intercept values ​​stored in the slope memory 814 and intercept memory 812, respectively, to estimate the base channel values. The base channel values ​​model a common mismatch related to the frequency across different DSA settings, while the slope and intercept values ​​model a small residual mismatch for each DSA setting. The base channel estimator 810 is coupled to a base channel memory 806 and stores the base channel values ​​in the base channel memory 806. The base channel estimator 810 uses the corresponding intercept and slope values ​​to calculate the gain and delay mismatch for each DSA setting. If a common gain and / or delay component is identified across all DSA settings, the base channel estimator 810 applies the common portion of the mismatch to refine the base channel response. The refined base channel response is stored in the base channel memory 806. Given a refined base channel response, the previously estimated intercept and slope parameters are adjusted across all DSA settings to reflect only the residual mismatch. The adjusted slope and intercept values ​​are stored in slope memory 814 and intercept memory 812, respectively.

[0091] Once we know that a common gain or delay mismatch has been established across all DSA settings, the base channel is updated as follows:

[0092]

[0093] in:

[0094] bin is a specific frequency bin location, with a bin range of 0, 1, ..., N. FFT -1;

[0095] g mm It is a common gain mismatch across all DSA settings;

[0096] d mm It is a common delay mismatch across all DSA settings; and

[0097] N FFT It is the size of the FFT used for time-frequency conversion.

[0098] old_basec_ch was initially uniform in some implementations.

[0099] When the base channel has been updated, the intercept and slope settings for each DSA are updated as follows:

[0100] channel[bin][DSA]=old_base_ch[bin]*(old_Intercept[DSA]+bin*old_slope[DSA])=new_base_ch[bin]*(new_Intercept[DSA]+bin*new_slope[DSA]) (12)

[0101] Equation (12) is applied to the two bin positions for each DSA index. For example, at bin = 10 and 100. Then, the two linear equations are solved to obtain the new intercept and new slope values ​​for each DSA index.

[0102] Figure 9 A block diagram of a channel equalization circuit 900 applicable to reference path 704 is shown. Channel equalization circuit 900 is one implementation of channel equalization circuit 714. Channel equalization circuit 900 is coupled to time-frequency conversion circuit 710, base channel memory 806, intercept memory 812, and slope memory 814. Channel equalization circuit 900 includes calculation circuitry 902, which calculates a channel compensation value (channel equalization value) for each frequency block and applies the channel compensation value to the frequency domain reference data of each frequency block to equalize reference path 704. The calculation circuitry 902 of channel equalization circuit 900 calculates the channel compensation value as follows:

[0103] Channel[DSA][Bin]=BaseChannel[Bin]*(C Intercept [DSA]+C Slope [DSA]*Bin)(13)

[0104] in:

[0105] Channel is the channel compensation value;

[0106] DSA is the attenuation selection index (DSA index value) applied to the DSA circuit 102;

[0107] bin is the frequency bin index;

[0108] BaseChannel is the base channel value retrieved from the base channel memory 806.

[0109] C Intercept It is the truncated value retrieved from the truncated memory 812; and

[0110] C Slope It is the slope value retrieved from the slope memory 814.

[0111] The channel equalization circuit 900 calculates the equalized data value by multiplying the channel compensation value by the value of the frequency domain signal 720 (i.e., the frequency domain data value). The implementation of the channel equalization circuit 900 is compact in size (e.g., within 1 / 8 of the size of other equalization circuits).

[0112] Figure 10 A flowchart of a method 1000 for nonlinear correction according to this disclosure is shown. Although depicted sequentially for convenience, at least some of the actions shown may be performed in a different order and / or in parallel. Furthermore, some embodiments may perform only some of the actions shown. The operation of method 1000 is performed by an embodiment of nonlinear correction circuit 700.

[0113] In block 1002, nonlinear correction circuit 700 receives signals as inputs to the main data path (formed by DSA circuit 102 and ADC 104) and reference path 704. For example, the input signals are provided at the inputs of DSA circuit 102 and DSA circuit 706. In some examples, the input signals include nonlinearity.

[0114] In block 1004, ADC 104 digitizes the input signal in the main data path and ADC 708 digitizes the input signal in the reference path 704. Data acquisition circuitry 206 is coupled to ADC 104 and captures the output of ADC 104, and data acquisition circuitry 705 captures the output of ADC 708. In some embodiments of method 1000, data acquisition circuitry 206 may selectively capture the output of ADC 104 or the output of nonlinear corrector circuitry 202 for use as estimated input data. Time-frequency conversion circuitry 211 converts the captured digital output of ADC 104 from the time domain to the frequency domain, and time-frequency conversion circuitry 710 converts the captured digital output of ADC 708 from the time domain to the frequency domain.

[0115] In block 1006, channel estimation circuit 712 processes frequency domain data provided by time-frequency conversion circuits 710 and 211 to generate a channel estimate of reference path 704 relative to the main data path.

[0116] In block 1008, channel equalization circuit 714 applies channel estimation generated by channel estimation circuit 712 to equalize frequency domain signal 720.

[0117] In block 1010, source nonlinear subtraction circuit 716 subtracts equalization output signal 722 (equalization output of ADC 708 in the frequency domain) from frequency domain signal 718 (frequency domain output of ADC 104) to produce a signal minus reference.

[0118] In block 1012, nonlinear term generation circuit 208 processes the captured data and generates nonlinear terms for the data captured by data capture circuit 206. Time-frequency conversion circuit 210 converts the data captured by data capture circuit 206 and the nonlinear terms generated by nonlinear term generation circuit 208 from the time domain to the frequency domain.

[0119] In block 1014, the frequency bin identification circuit 212 identifies frequency bins for use in estimating the nonlinear correction coefficients. The identified frequency bins are those with signal power below a first threshold and nonlinear power above a second threshold.

[0120] In block 1016, the residual nonlinear conversion circuit 214 converts the residual nonlinear measurement into a fully nonlinear measurement by modifying the frequency response of the signal at the identified frequency bin. The frequency response is modified by adding multiple correction terms to the signal, where each correction term is the product of the frequency response of the nonlinear term and the corresponding nonlinear correction coefficient currently used in the nonlinear corrector circuit 202.

[0121] In block 1018, nonlinear coefficient generation circuit 216 generates and tracks nonlinear correction coefficients based on the signal (minus the reference signal) and the nonlinear term at the frequency bin identified by bin identification circuit 212.

[0122] In block 1020, nonlinear corrector circuit 202 applies nonlinear correction coefficients to compensate for nonlinear correction data 116 for nonlinearity introduced in digital signal 114 by ADC 104 and DSA circuit 102.

[0123] Figure 11 A flowchart of a method 1100 for nonlinear correction according to this disclosure is shown. Although depicted sequentially for convenience, at least some of the actions shown may be performed in a different order and / or in parallel. Furthermore, some embodiments may perform only some of the actions shown. The operation of method 1100 is performed by an embodiment of the nonlinear correction circuit 200.

[0124] In block 1102, nonlinear correction circuit 200 receives signals as inputs to DSA circuit 102 and ADC 104. For example, an input signal is provided at the input of DSA circuit 102.

[0125] In block 1104, ADC 104 digitizes the input signal. Data acquisition circuit 206 captures the output of ADC 104. In some embodiments of method 1100, data acquisition circuit 206 may selectively capture the output of ADC 104 or the output of nonlinear corrector circuit 202 for use as estimated input data. Time-frequency conversion circuit 211 converts the digital output of ADC 104 from the time domain to the frequency domain.

[0126] In block 1106, the nonlinear term generation circuit 208 processes the captured data and generates a nonlinear term for the captured data. The time-frequency conversion circuit 210 converts the data captured by the data capture circuit 206 and the nonlinear term generated by the nonlinear term generation circuit 208 from the time domain to the frequency domain.

[0127] In block 1108, the frequency bin identification circuit 212 identifies frequency bins for use in estimating the nonlinear correction coefficients. The identified frequency bins are those with signal power below a first threshold and nonlinear power above a second threshold.

[0128] In block 1110, the residual nonlinear conversion circuit 214 converts the residual nonlinear measurement into a fully nonlinear measurement by modifying the frequency response of the signal at the identified frequency bin. The frequency response is modified by adding multiple correction terms to the signal, where each correction term is the product of the frequency response of the nonlinear term and the corresponding nonlinear correction coefficient currently used in the nonlinear corrector circuit 202.

[0129] In block 1112, nonlinear coefficient generation circuit 216 generates and tracks nonlinear correction coefficients based on the signal and nonlinear term at the frequency bin identified by bin identification circuit 212.

[0130] In block 1114, nonlinear corrector circuit 202 applies nonlinear correction coefficients to compensate for nonlinear correction data 116 for nonlinearity introduced by ADC 104 in digital signal 114.

[0131] Modifications to the described embodiments are possible within the scope of the claims, and other embodiments are also possible.

Claims

1. A nonlinear correction circuit, comprising: The nonlinear coefficient estimation circuit includes: Data capture circuitry; A nonlinear term generation circuit coupled to the data acquisition circuit; A time-frequency conversion circuit coupled to the data acquisition circuit and the nonlinear term generation circuit; A bin identification circuit coupled to the time-frequency conversion circuit; The residual nonlinear conversion circuit coupled to the warehouse identification circuit; and A nonlinear coefficient generation circuit coupled to the bin identification circuit and the residual nonlinear conversion circuit.

2. The nonlinear correction circuit of claim 1 further includes a nonlinear corrector circuit coupled to the nonlinear coefficient estimation circuit and configured to generate nonlinear correction data based on the nonlinear correction coefficients generated by the nonlinear coefficient generation circuit.

3. The nonlinear correction circuit according to claim 2, wherein, The data capture circuit is configured to capture the nonlinear correction data.

4. The nonlinear correction circuit according to claim 2, wherein, The data capture circuit is configured to capture raw data samples as input to the nonlinear corrector circuit for nonlinear correction.

5. The nonlinear correction circuit according to claim 1, wherein, The nonlinear term generation circuit is configured to generate nonlinear terms from the data captured by the data capture circuit.

6. The nonlinear correction circuit according to claim 5, wherein, The time-frequency conversion circuit is configured to convert the nonlinear term and the data captured by the data capture circuit from the time domain to the frequency domain.

7. The nonlinear correction circuit according to claim 5, wherein: The nonlinear coefficient generation circuit is configured to estimate the nonlinear coefficient based on the frequency response of the nonlinear term at the frequency bin identified by the bin identification circuit and the frequency response of the output of the data acquisition circuit. and At each frequency cell identified by the cell identification circuit, the frequency response of the nonlinear term is used as a weight for the nonlinear coefficient; Furthermore, the frequency response of the output of the data acquisition circuit is used as a measurement when estimating the nonlinear coefficient.

8. The nonlinear correction circuit according to claim 5, wherein, The bin identification circuit is configured to identify frequency bins for use in estimating nonlinear correction coefficients, as frequency bins having signal power below a first threshold and nonlinear term power above a second threshold.

9. The nonlinear correction circuit according to claim 8, wherein, The residual nonlinear conversion circuit is configured to modify the frequency response of the signal by adding multiple correction terms to the signal at the frequency bin, wherein each correction term is the product of the frequency response of the nonlinear term and the corresponding nonlinear correction coefficient.

10. The nonlinear correction circuit according to claim 1, wherein: The data acquisition circuit is a first data acquisition circuit; The time-frequency conversion circuit is a first time-frequency conversion circuit; and The nonlinear correction circuit further includes: Data paths include: The first digital step attenuator is the first DSA; and The first analog-to-digital converter, i.e., the first ADC, is coupled to the first data acquisition circuit; and Reference paths include: The second DSA includes an input coupled to the input of the first DSA; A second ADC coupled to the second DSA; A second data acquisition circuit coupled to the second ADC; A second time-frequency conversion circuit coupled to the second data acquisition circuit; A channel estimation circuit coupled to the first time-frequency conversion circuit and the second time-frequency conversion circuit; A channel equalization circuit coupled to the channel estimation circuit and the second time-frequency conversion circuit; and A source nonlinear subtraction circuit coupled to the channel equalization circuit, the first time-frequency conversion circuit, and the bin identification circuit.

11. The nonlinear correction circuit according to claim 10, wherein, The channel equalization circuit is configured to equalize the reference path to the data path.

12. The nonlinear correction circuit according to claim 10, wherein, The channel estimation circuit includes: Base channel memory; Slope memory; Intercept memory; A raw channel estimation circuit is configured to generate a raw channel estimate based on the output of the first ADC and the output of the second ADC; A base channel removal circuit coupled to the original channel estimation circuit and the base channel memory; The slope and intercept estimation circuits are coupled to the base channel removal circuit, the slope memory, and the intercept memory; and A base channel estimator coupled to the slope and intercept estimation circuit and the base channel memory.

13. The nonlinear correction circuit according to claim 12, wherein, The channel equalization circuit includes a computation circuit, which is configured to: The channel equalization value is calculated as the following product: The base channel value retrieved from the base channel memory; and The sum of the intercept value retrieved from the intercept memory and the slope value retrieved from the slope memory is multiplied by the frequency bin index; and The equalization data value is calculated as the product of the channel equalization value and the frequency domain data value generated by the second time-frequency conversion circuit.

14. A nonlinear correction circuit, comprising: Data paths include: The first digital step attenuator is the first DSA; The first analog-to-digital converter is the first ADC; The first data acquisition circuit coupled to the first ADC; and A first time-frequency conversion circuit coupled to the first data acquisition circuit; Reference paths include: The second DSA includes an input coupled to the input of the first DSA; A second ADC coupled to the second DSA; A second data acquisition circuit coupled to the second ADC; A second time-frequency conversion circuit coupled to the second data acquisition circuit; A channel estimation circuit coupled to the first time-frequency conversion circuit and the second time-frequency conversion circuit; A channel equalization circuit coupled to the channel estimation circuit and the second time-frequency conversion circuit; and A source nonlinear subtraction circuit coupled to the channel equalization circuit and the first time-frequency conversion circuit; and A nonlinear term generation circuit coupled to the first data acquisition circuit and the first time-frequency conversion circuit; A bin identification circuit coupled to the source nonlinear subtraction circuit and the first time-frequency conversion circuit; The residual nonlinear conversion circuit coupled to the warehouse identification circuit; and A nonlinear coefficient generation circuit coupled to the bin identification circuit and the residual nonlinear conversion circuit.

15. The nonlinear correction circuit according to claim 14, wherein: The nonlinear coefficient generation circuit is configured to estimate the nonlinear coefficient based on the frequency response of the nonlinear term generated by the nonlinear term generation circuit and the output of the source nonlinear subtraction circuit at the frequency bin identified by the bin identification circuit. and At the frequency bin identified by the bin identification circuit, the frequency response of the nonlinear term is used as a weight for the nonlinear coefficient; Furthermore, the output of the source nonlinear subtraction circuit is used as a measurement value when estimating the nonlinear coefficient.

16. The nonlinear correction circuit according to claim 14, wherein, The channel estimation circuit is configured to equalize the reference path to the data path.

17. The nonlinear correction circuit according to claim 14, wherein, The channel estimation circuit includes: A slope memory, configured to store slope values ​​for DSA index values; An intercept memory configured to store intercept values ​​for the DSA index values; A base channel memory, configured to store base channel values ​​for a frequency bin; A raw channel estimation circuit is configured to generate a raw channel estimate based on the output of the first ADC and the output of the second ADC; A base channel removal circuit coupled to the original channel estimation circuit and the base channel memory; The slope and intercept estimation circuits are coupled to the base channel removal circuit, the slope memory, and the intercept memory; and A base channel estimator coupled to the slope and intercept estimation circuit and the base channel memory.

18. The nonlinear correction circuit according to claim 17, wherein, The channel equalization circuit includes: The calculation circuit is configured to calculate the channel compensation value for the frequency bin as the product of the base channel value and the intercept value for the frequency bin, and the product of the slope value and the frequency bin index for the DSA index value.

19. The nonlinear correction circuit of claim 14, further comprising a nonlinear corrector circuit coupled to the nonlinear coefficient generation circuit and configured to generate nonlinear correction data based on nonlinear correction coefficients generated by the nonlinear coefficient generation circuit.

20. The nonlinear correction circuit according to claim 19, wherein, The first data acquisition circuit is configured to selectively capture the nonlinear correction data or raw data samples provided by the first ADC to the nonlinear corrector circuit for nonlinear correction.

21. The nonlinear correction circuit according to claim 20, wherein, The nonlinear term generation circuit is configured to generate nonlinear terms from the data captured by the first data capture circuit.

22. The nonlinear correction circuit according to claim 21, wherein, The first time-frequency conversion circuit is configured to convert the nonlinear term and the data samples generated by the first ADC and captured by the first data acquisition circuit from the time domain to the frequency domain.

23. The nonlinear correction circuit according to claim 21, wherein, The bin identification circuit is configured to identify frequency bins for use in estimating nonlinear correction coefficients, as frequency bins of samples generated by the first ADC having signal power below a first threshold and nonlinear term power above a second threshold.

24. The nonlinear correction circuit according to claim 23, wherein, The residual nonlinear conversion circuit is configured to modify the frequency response of the signal by adding multiple correction terms to the signal at the frequency bin, wherein each correction term is the product of the frequency response of the nonlinear term and the corresponding nonlinear correction coefficient currently used in the nonlinear corrector circuit.

25. A method for nonlinear correction, comprising: Receive signals as inputs for the main data path and reference data path; The signal is digitized by the first analog-to-digital converter (ADC) of the main data path and the second ADC of the reference data path; The output of the second ADC is subtracted from the output of the first ADC to generate a signal minus the reference. The nonlinear correction coefficients are estimated based on the signal minus the reference. as well as The nonlinear correction coefficient is applied to the output of the first ADC to generate nonlinear correction data.

26. The method of claim 25, further comprising: Based on the output of the second ADC and the output of the first ADC, a channel estimate of the reference data path relative to the main data path is generated; as well as Before subtraction, the output of the second ADC is equalized based on the channel estimation.

27. The method of claim 26, further comprising: A nonlinear term is generated from the output of the first ADC; as well as The frequency bins are identified for use in estimating the nonlinear correction coefficients, as frequency bins having signal power below a first threshold and nonlinear power above a second threshold.

28. The method of claim 27, further comprising modifying the frequency response of the subtracted reference signal at the frequency bin by adding a plurality of correction terms to the signal at the frequency bin, wherein each correction term is the product of the frequency response of the nonlinear term and a corresponding nonlinear correction coefficient currently used to correct the output of the first ADC.

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