Voltage pre-regulator with positive and negative feedback

Abstract

This disclosure relates to a voltage pre-regulator with positive and negative feedback. The voltage pre-regulator can accept variable voltages in a medium voltage range (e.g., tens of volts) and provide a regulated voltage within the safe operating area of ​​low-voltage equipment. The use of a voltage pre-regulator allows circuits to perform additional regulation / conversion using low-voltage equipment without concern for damage. Because the disclosed circuits and methods use bias circuitry, the voltage pre-regulator disclosed herein can perform voltage reduction and pre-regulation functions using common transistor types. The bias circuitry uses positive feedback, eliminating the need for an additional startup circuitry system. The positive feedback is controlled by negative feedback, enabling the pre-regulator to provide a stable regulated voltage over a wide range of input voltage and temperature.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Patent Application 17 / 248,119, filed January 11, 2021. Technical Field

[0003] This disclosure relates to integrated circuits for voltage regulation, and more specifically to linear voltage regulators that can be started and controlled using positive and negative feedback. Background Technology

[0004] A voltage regulator is a circuit configured to convert a fluctuating input voltage at its input terminals into a substantially constant output voltage at its output. For example, a linear voltage regulator can use a controllable voltage drop between its input and output terminals to compensate for variations in the input voltage. For instance, as the input voltage increases, the controllable voltage drop increases, thus keeping the output voltage constant. Low-voltage devices can be used to provide accuracy for the regulated output voltage, but when the input voltage is high and the output voltage is low, it may be necessary to protect the low-voltage devices from the effects of high input voltages. Summary of the Invention

[0005] In at least one aspect, this disclosure generally describes a voltage pre-regulator. The voltage pre-regulator includes a bias circuit section and a regulator circuit section. The bias circuit section includes a feedback loop configured to amplify a leakage current generated by an input voltage, such that the leakage current increases according to positive feedback to become an amplified leakage current. The bias circuit section also includes a current source coupled to the feedback loop. The current source is configured to limit the increase of the amplified leakage current by applying negative feedback to the feedback loop, such that the bias circuit section outputs a bias current and a bias voltage. The regulator circuit section includes a laterally diffused metal-oxide-semiconductor (LDMOS) transistor configured to generate a voltage drop from the input to the output of the voltage pre-regulator based on the bias current and the bias voltage. The voltage pre-regulator is configured to output a regulated voltage based on the voltage drop.

[0006] In one possible implementation of the voltage pre-regulator, the current source is a depletion-mode native transistor (NVT).

[0007] In another possible implementation of the voltage pre-regulator, the feedback loop includes a first current mirror coupled at its output to the input of a second current mirror, and the second current mirror coupled at its output to the input of the first current mirror. A protection circuit may be coupled between the input and the first current mirror to clamp the voltage of the current source and protect it from damage.

[0008] In another possible implementation of the voltage pre-regulator, the regulator circuitry includes a voltage source. In one possible implementation, the voltage source includes a diode or a plurality of diodes connected in series. In another possible implementation, the voltage source includes a diode-connected transistor or a plurality of diode-connected transistors coupled in series.

[0009] In another possible implementation of the voltage pre-regulator, the bias circuit section is self-starting when the input voltage is applied.

[0010] In another possible implementation of the voltage pre-regulator, the positive and negative feedbacks are balanced under an equilibrium corresponding to the input voltage, and the bias current and bias voltage are based on this equilibrium.

[0011] In another aspect, this disclosure generally describes a method for voltage pre-regulation. The method includes receiving an input voltage in a bias circuit section of a voltage pre-regulator. The method also includes generating a bias current and a bias voltage using positive and negative feedback in the bias circuit section of the voltage pre-regulator, and applying the bias current and bias voltage to a regulator circuit section of the voltage pre-regulator. The method further includes outputting a regulated voltage based on a voltage drop from the input voltage, wherein the voltage drop is generated by the bias current and bias voltage.

[0012] In another aspect, this disclosure generally describes a system comprising a low-voltage device (e.g., a low-voltage regulator) and a voltage pre-regulator. The low-voltage device includes a transistor having a safe operating region (i.e., a low-voltage safe operating region) within a low-voltage range. The voltage pre-regulator is coupled to an input voltage outside the low-voltage safe operating region and is configured to provide a regulated voltage to the low-voltage device within the safe operating region. The voltage pre-regulator includes a bias circuit portion having a feedback loop configured to amplify a leakage current generated by the input voltage to produce an amplified leakage current that increases according to positive feedback. A current source is coupled to the feedback loop to limit the increase in the amplified leakage current by applying negative feedback to the feedback loop, such that an equilibrium is achieved between the positive and negative feedback, wherein, under said equilibrium, the bias circuit portion outputs a bias current and a bias voltage. The voltage pre-regulator also includes a regulator circuit section with a laterally diffused metal-oxide-semiconductor (LDMOS) transistor configured to generate a voltage drop from the input to the output of the voltage pre-regulator based on a bias current and a bias voltage, wherein the voltage pre-regulator is configured to output a regulated voltage based on the voltage drop.

[0013] In one possible implementation of the system, the low-voltage device and voltage pre-regulator are part of an overall integrated circuit.

[0014] In another possible implementation of the system, the low-voltage device is a low-voltage regulator.

[0015] The foregoing illustrative aspects and other exemplary objects and / or advantages of this disclosure, as well as the ways in which these objects and / or advantages are achieved, are further explained in the following detailed description and accompanying drawings. Attached Figure Description

[0016] Figure 1 This is a block diagram of a voltage regulator including a voltage pre-regulator according to a possible embodiment of the present disclosure.

[0017] Figure 2 This is a block diagram illustrating a voltage pre-regulator according to an embodiment of the present disclosure.

[0018] Figure 3 This is a schematic diagram of a voltage pre-regulator according to a first possible embodiment of the present disclosure.

[0019] Figure 4 This is a schematic diagram of a voltage pre-regulator according to a second possible embodiment of the present disclosure.

[0020] Figure 5 This is a schematic diagram of a voltage pre-regulator according to a third possible embodiment of the present disclosure.

[0021] Figure 6 This is a block diagram of a system including a voltage pre-regulator according to a possible embodiment of the present disclosure.

[0022] Figure 7 This is a flowchart of a voltage pre-regulation method according to a possible embodiment of the present disclosure.

[0023] The components in the accompanying drawings are not necessarily proportional to each other. In several views, the same reference numerals denote corresponding parts. Detailed Implementation

[0024] This disclosure describes a voltage pre-regulator (i.e., pre-regulator) configured to convert a voltage in a medium-voltage (i.e., MV) range to a voltage within the safe operating area (i.e., SOA) of a low-voltage (i.e., LV) device. The MV range can be from approximately 10 volts (V) to approximately 100 V, while the SOA of an LV device may be less than approximately 10 V. The disclosed pre-regulator can provide voltages suitable for conversion and / or regulation by various LV circuits. The pre-regulator can assist these LV circuits in conversion and / or regulation to achieve lower power consumption, better noise performance, and / or higher accuracy.

[0025] The disclosed pre-regulator does not require special (e.g., non-general-purpose, expensive, etc.) devices such as junction field-effect transistors (JFETs) or depletion-mode laterally diffused metal-oxide-semiconductor (DM-LDMOS) transistors to perform pre-regulation. Alternatively, the disclosed pre-regulator can use general-purpose MV transistors, such as (more general-purpose) enhancement-mode laterally diffused metal-oxide-semiconductor transistors (i.e., LDMOS), to perform pre-regulation because it includes a bias circuit system that balances positive and negative feedback to control the general-purpose MV transistor for pre-regulation. This balanced feedback in the bias circuit system ensures regulation within the startup time (e.g., less than about 1 millisecond (ms)) and provides a stable (e.g., variation of less than about 5%) output voltage over a wide range of input voltages (e.g., from about -40 degrees Celsius (°C) to about 150°C) over a temperature range (e.g., from about 5V to about 70V).

[0026] Figure 1 This is a block diagram of a voltage regulator including a voltage pre-regulator according to an embodiment of the present disclosure. The voltage regulator 100 can be configured to receive an input voltage (i.e., V) in the range of about 10 volts (V) to about 100 V (e.g., 40 V) in the mV range. IN And it generates an output voltage (i.e., V) in the range of approximately 1V to approximately 10V (e.g., 5V). OUT In other words, the voltage regulator 100 can be configured to reduce the voltage in the MV range to the voltage in the LV range.

[0027] Voltage regulator 100 is a linear regulator that adjusts the output voltage (V) by adjusting the voltage drop across transistor device 130. OUT Transistor device 130 may be an LDMOS transistor configured to handle voltages in the MV range at the drain terminal (e.g., shown in bold) and voltages in the LV range at the gate terminal 132. Transistor device 130 is thus coupled to an LV regulator 120 configured to output a gate voltage in the LV range to control the voltage drop across transistor device 130. For example, LV regulator 120 may use feedback 133 from the output to adjust the voltage drop so that the output remains stable within a desired accuracy (e.g., within 1%).

[0028] To provide the desired output accuracy, the LV regulator may include LV devices, each having an SOA (e.g., within the LV range). To prevent damage to the LV devices, the voltage regulator 100 also includes a voltage pre-regulator 200, which is configured to pre-regulate the input voltage (Vm) within the MV range. IN ) is converted into the regulated voltage (V) in the SOA of the LV device located in the LV regulator 120. REGAccordingly, adjust the voltage (V) REG This can be used to power the LV regulator 120. In other words, it regulates the voltage (V). REG The voltage pre-regulator 200 can be the supply voltage (i.e., the secondary power supply trunk) used for the LV regulator 120. The voltage pre-regulator 200 is configured to protect (i.e., shield) the LV devices in the LV regulator 120 from input voltages (V) outside the SOA of the LV devices. IN The effect of (i.e., the voltage within the MV range). In one possible implementation, the voltage pre-regulator 200 and the LV regulator 120 are included as integrated circuits (ICs) within the same IC package.

[0029] Figure 2 This is a block diagram illustrating a voltage pre-regulator according to an embodiment of the present disclosure. The voltage pre-regulator 200 includes an MV regulator 220 configured to provide a voltage drop (Vm) between its input and output terminals. DROP To provide a regulated voltage (V) at the output. REG The voltage drop can be compared with the output current (I). REG This is independent of load changes coupled to the pre-regulator, ensuring that load variations do not cause significant voltage changes (e.g., voltage drop) at the output. Furthermore, when using active devices (e.g., transistor devices), the voltage drop (V...) is... DROP ) can be compared with the input current (I) IN It is unrelated to the supply of regulating voltage (V). REG This is used for additional conversions and / or adjustments, so high precision is not required. For example, V REG The accuracy can be ten percent (%) or less. This accuracy may be due to a trade-off between voltage handling and precision. For example, a transistor device in MV regulator 220 may be able to handle voltages in the MV range without damage, but may produce a lower accuracy voltage drop (e.g., compared to an LV transistor device).

[0030] Using transistor devices to generate voltage drop (V) DROP Appropriate biasing may be required. Some less common transistor types (e.g., JFET, DM-LDMOS) can be biased for this purpose by simply grounding the gate terminal or by pulling the gate terminal slightly up from ground. However, these less common transistor devices may not be widely available and / or may be more difficult to manufacture (e.g., using other devices). As mentioned above, the voltage pre-regulator 200 and LV regulator 120 can be included as ICs within the same IC package (e.g., as part of an overall integrated circuit). In this case, it may be desirable to use transistor devices manufactured using process technologies compatible with common transistor types.

[0031] LDMOS transistor 221 (i.e., LDMOS) is a transistor device that can be fabricated using common transistor types (i.e., using common process flows). While this simplifies fabrication, biasing LDMOS transistor 221 can be more difficult than biasing less common (i.e., more difficult to fabricate) transistor types. Accordingly, voltage pre-regulator 200 also includes bias circuit 210. Bias circuit 210 is configured to receive input voltage (V... IN And generate a bias voltage (V) BIAS ) and bias current (I BIAS This circuit controls the operating point of the LDMOS transistor 221 in the MV regulator 220. The bias circuit 210 can use positive feedback 211 and negative feedback 212 to help generate a bias voltage (V). BIAS ) and bias current (I BIAS ).

[0032] The positive feedback 211 and negative feedback 212 of the bias circuit 210 can operate in concert to generate a bias voltage (V). BIAS For example, during startup, due to positive feedback 211, the bias voltage (V) BIAS The bias voltage rises rapidly. The negative feedback 212 limits the rise of the bias voltage to a predetermined value so that after the start-up period, the bias voltage is stabilized at the predetermined value achieved by the opposing effects of the positive feedback 211 and the negative feedback 212.

[0033] Figure 3 This is a schematic diagram of a voltage pre-regulator according to a possible embodiment of the present disclosure. The voltage pre-regulator 300 includes a bias circuit portion 310 (i.e., a bias circuit) and an MV regulator portion 320 (i.e., an MV regulator). The bias circuit portion 310 is configured to couple to the input voltage (V... IN The gate output bias voltage (V) of the LDMOS transistor (i.e., MLD4) between the current mirrors (i.e., MLD5, MLD6) in the MV regulator section 320 and the current mirrors (i.e., MLD5, MLD6) in the MV regulator section 320. BIAS Bias voltage (V) BIAS ) and output voltage source 335 (V O Control the operating point of MLD4 so that the output current (I) O The current flows through MLD4. This current is mirrored by current mirrors (i.e., MLD5, MLD6) and generates a voltage drop (V) across the LDMOS output transistor (MLD6). DROP ), so that the regulating voltage (V) REG The voltage regulation (V) appears at the output of the voltage pre-regulator 300. REG It can be approximately equal to the voltage of the output voltage source 335 (V). O Additionally, the output current (I) OThis can be approximated by the bias current (I) flowing through the second LDMOS transistor (MLD2). BIAS This is because the dimensions of the fourth LDMOS transistor (MLD4) and the second LDMOS transistor (MLD2) can be approximately equal, and because they have the same gate voltage and source voltage.

[0034] The bias circuit section 310 of the voltage pre-regulator 300 operates using both positive and negative feedback. At startup, the first node (A) and the second node (B) are coupled to the input voltage (V). IN (i.e., supply voltage). At startup, the first LDMOS transistor (MLD1) is in a non-conducting state (i.e., OFF state), allowing only a (small) leakage current (I) to conduct. LEAK Leakage current (I) LEAK The leakage current (I) is coupled to the first current mirror (M4, M5). The first current mirror (M4, M5) amplifies the leakage current (I). LEAK To generate an amplified leakage current (I) AMP_LEAK The amplification occurs because the M5 transistor of the first current mirror is x times larger than the M4 transistor of the first current mirror (e.g., 5 times).

[0035] The first LDMOS transistor (MLD1) is part of the second current mirror (MLD1, MLD2). The second current mirror (MLD1, MLD2) further amplifies the amplified leakage current (I). AMP_LEAK This is because the first LDMOS transistor (MLD1) of the second current mirror is n times (e.g., 5 times) larger than the second LDMOS transistor (MLD2) of the second current mirror.

[0036] After being amplified by the second current mirrors (MLD1, MLD2), the amplified leakage current (I) AMP_LEAK The leakage current is fed back to the first current mirror (M4, M5), and this process is repeated. In other words, a feedback loop is formed between the first current mirror (M4, M5) and the second current mirror (MLD1, MLD2). The output of the first current mirror is coupled to the input of the second current mirror, and the output of the second current mirror is coupled to the input of the first current mirror. Positive feedback exists because the first current mirror is configured to amplify the amplified leakage current by a first amplification factor based on a first size difference between the transistors (M4, M5), and the second current mirror is configured to amplify the amplified leakage current by a second amplification factor based on a second size difference between the transistors (MLD1, MLD2). Positive feedback can amplify very small leakage currents (I0, M1, M2). LEAK This is rapidly converted into a much larger amplified leakage current (I). AMP_LEAK The voltage pre-regulator 300 is self-starting because of leakage current (I). LEAKThis occurs naturally during startup due to the device physical characteristics (e.g., thermal response) of the transistor (MLD1).

[0037] The bias circuit section 310 also includes an LDMOS transistor (MLD3) configured to provide a voltage drop across the SOA of the LV transistor (M5) in the first current mirror (M4 M5) from the range of MV. In other words, the LDMOS transistor (MLD3) shields the LV transistor (M5) from damage that could occur if a voltage in the range of MV is applied to its drain. The bias transistor (M3) configures the LDMOS transistor (MLD3) to conduct the same current as the LV transistor (M5) and reduces the voltage required to protect the LV transistor (M5).

[0038] When the second node (B) is at the input voltage, the positive feedback can reduce the voltage at the first node (A), thereby increasing the amplified leakage current (IA). AMP_LEAK To limit the increase caused by positive feedback, the bias circuit section includes a current source 330 coupled between the input of the voltage pre-regulator and the input of the first current mirror. With the amplified leakage current (I... AMP_LEAK The voltage (V) increases due to positive feedback, generating a voltage across the current source. CS Voltage (V) CS With the amplified leakage current (I) AMP_LEAK The current source 330 increases with the increase of the leakage current (I). In other words, above the current level, the current source 330 has an amplified leakage current (I). AMP_LEAK The voltage (V) corresponding to ) CS This voltage can reduce the first magnification factor of the first current mirror as the amplified leakage current increases, so that the amplified leakage current eventually stops increasing.

[0039] At startup, the second node (B) (i.e., the source of MLD1) is at the input voltage (V). IN (that is, V) CS =0). When the amplified leakage current reaches a certain value, the current provided by the current source 330 becomes limited, and a voltage (V) is formed across the current source 330. CS Accordingly, the voltage at the second node is based on V. CS From V IN The voltage drop decreases because the current demand on current source 330 increases due to positive feedback. The voltage drop at the second node (B) affects the amplified leakage current (I). AMP_LEAK The increase in current source voltage has a negative impact. For example, the gate-source voltage on the transistor (MLD1) of the second current mirror can be reduced based on the voltage of the current source, so that MLD1 conducts less as the amplified leakage current increases. Ultimately, the current source-induced impact on I... AMP_LEAK The negative impact of the increase offset the effect of the current mirror on I.AMP_LEAK Positive impacts of growth.

[0040] When a balance is achieved between positive and negative feedback, the voltage at the first node (A) is such that the output V of the MV regulator section 320 is reached. REG The value of the fourth LDMOS transistor (MLD4) in the MV regulator section 320 can have the same size as the second LDMOS transistor (MLD2), so that the output current (I) O This is equal to the current flowing through the second LDMOS transistor (MLD2). Equalization is a state in the bias circuit where the effects of positive and negative feedback are balanced, keeping the amplified leakage current at a fixed level (i.e., not increasing due to positive feedback). Equalization corresponds to the input voltage; therefore, as the input voltage changes, the bias current and bias voltage based on equalization will also change.

[0041] V IN Subsequent changes can cause a responsive change in the voltage at the first node A and the second node. For example, V IN An increase in bias voltage can lead to an increase in voltage at the first node (A) and the second node (B). Therefore, the bias voltage (V) BIAS ) Response to V IN The output current (I) increases with the increase of [something]. O ) remains unchanged because V IN and V BIAS The increase maintained the gate-source voltage of MLD4. Furthermore, the output voltage (V... O (V) remains unchanged. (This is followed by an incomplete sentence or a question mark.) IN While maintaining I O and V O This leads to an increase in the channel resistance (i.e., resistance) of MLD6, which corresponds to V DROP Therefore, as VIN increases, VDROP can increase, causing V... REG Maintain the regulated voltage.

[0042] Figure 4 This is a schematic diagram of a voltage pre-regulator according to another possible embodiment of the present disclosure. The voltage pre-regulator 400 includes a bias circuit portion 410 and an MV regulator portion 420 as previously described; however, in the illustrated embodiment, the bias circuit portion 410 includes a protection circuit 415. The protection circuit may include one or more circuit elements (e.g., Zener diodes, diodes, diode-connected transistors, etc.) to clamp the voltage. Figure 4 The protection circuit 415 shown includes one or more diode-connected transistors configured to transmit the input voltage (V) IN The voltage difference between the first node (A) and the first node (A) is clamped to a few volts (e.g., 5V).

[0043] Protection circuit 415 is configured to prevent the voltage across current source 430 from exceeding a level that could damage the current source. For example, the current source could be implemented as an LV transistor that could be damaged by voltages above the clamping level. Protection circuit 415 is also configured to prevent the gate-source voltage of the second LDMOS transistor (MLD2) from exceeding a level that could damage the LDMOS transistor. Although the LDMOS transistor is configured to handle the MV between its drain and source, it may be configured to handle only the LV between its gate and source.

[0044] The protection circuit can operate under certain conditions. For example, during startup, V IN It may become high voltage before the transistors (e.g., MLD1, MLD2) can respond. In this case, the protection circuit can clamp (i.e., hold) the voltage at a safe value until the circuit is configured to a steady state.

[0045] Figure 4 The illustrated MV regulator section 420 embodiment includes an output voltage source 435 comprising one or more diodes. These one or more diodes (e.g., three diodes connected in series) are connected in series such that the output voltage (V... O The sum of the voltage drops across each diode is the voltage across the diode. The regulation voltage (V) of the voltage pre-regulator 400 is... REG It is approximately equal to the output voltage of the output voltage source 435.

[0046] Figure 5 This is a schematic diagram of a voltage pre-regulator according to another possible embodiment of this disclosure. The voltage pre-regulator 500 includes a bias circuit portion 510 and an MV regulator portion 520. The current source of the bias circuit portion 510 is implemented as a depletion-mode native transistor (i.e., NVT 530). NVT 530 may be an LV device. Accordingly, the illustrated embodiment includes a protection circuit 515 to prevent damage to the NVT (and MLD2), as previously described. The gate terminal of the NVT is connected to the source terminal of the NVT. In operation, the voltage drop across NVT 530 is virtually zero until the current through the NVT reaches a value based on the NVT's dimensions (e.g., a limit). When the current demand increases above this value, a voltage will be generated across NVT 530. The dimensions (e.g., length) of the NVT can be selected (e.g., made long) such that the NVT has high resistance.

[0047] like Figure 5As shown, the output voltage source 535 of the MV regulator section 520 can be implemented as one or more diode-connected transistors (M6, M7, M8). These one or more (e.g., three) diode-connected transistors (M6, M7, M8) are connected in series, such that the output voltage (V... O The voltage drop across each diode-connected transistor is the sum of the voltage drops across the transistor. The regulation voltage (V) of the voltage pre-regulator 500 is... REG The voltage is approximately equal to the output voltage of the output voltage source 535. The voltage pre-regulator 500 can output approximately equal to I. O The current is approximately equal to the current flowing through the second LDMOS transistor (MLD2). This current is determined by the operating point (i.e., the equilibrium point) of MLD2, which is based on the balance between the positive and negative feedback of the bias circuit section 510. In other embodiments, the output voltage source 535 can be implemented as a Zener diode.

[0048] Figure 6 This is a block diagram of a system including a voltage pre-regulator according to possible embodiments of the present disclosure. The system may include multiple subsystems configured for various functions. For example, system 600 may be a mobile device including a microcontroller 620, an LED controller 630, and an LV input / output (I / O) controller 640. The system may include a battery (not shown) configured to generate a supply voltage (i.e., a first mains voltage). The supply voltage (i.e., V... IN The voltage can be within the MV range. Accordingly, the system may include a voltage pre-regulator configured to receive a first mains voltage (i.e., V). IN It outputs a second mainline voltage (i.e., V) that is lower than the first mainline voltage. REG For example, the second mainline voltage can be within the LV range. Accordingly, the microcontroller 620, LED controller 630, and LV I / O controller 640, operating within the LV range, can be coupled to the second mainline voltage (V) without damage. REG The subsystem can also convert and / or regulate the second mains voltage. For example, the LV I / O controller may include a linear regulator (not shown) to generate a voltage lower than the second supply mains voltage (V). REG The voltage pre-regulator 610 uses the regulated voltage as the supply voltage for its circuit. It can use standard LV devices to facilitate any boost / buck DC / DC or regulation.

[0049] Figure 7 This is a flowchart of a voltage pre-regulation method according to a possible embodiment of the present disclosure. Method 700 includes receiving a supply voltage (V) 710 at the bias circuit portion (i.e., the bias circuit) of the voltage pre-regulator. INThe supply voltage is in the MV range. The method also includes generating a 720Ω bias current (I0.05) using positive and negative feedback in the bias circuit. BIAS ) and bias voltage (V BIAS For example, positive feedback may include using current mirrors with transistors of different scales to amplify the leakage current. The current mirrors may include two current mirrors configured in a feedback loop for amplifying the leakage current. Negative feedback may include adjusting the voltage of one of the current mirrors based on the level of the amplified leakage current. For example, adjustment may include using a current source coupled between the input voltage and the transistor to reduce the voltage on one of the transistors in the current mirrors, the current source having a voltage dependent on the current flowing through the transistor. The method also includes applying a bias current and a bias voltage (i.e., output, coupled, transmitted) to the MV regulator portion of the voltage pre-regulator (i.e., the MV regulator). The MV regulator portion may include a voltage source (e.g., a series-connected diode, a series-connected diode-connected transistor) and the regulating voltage may be approximately equal to (e.g., within one volt) the voltage level (V) of the voltage source. O The method also includes an output 740 with a regulated voltage (V) in the LV range. REG For example, the MV regulator may include a voltage source and can be controlled by (i.e., based on) the bias current (I) received from the bias circuit. BIAS ) and bias voltage (V BIAS ) control voltage drop (V DROP Make the regulated voltage approximately equal to the output voltage of the voltage source (V). O ).

[0050] While certain features of the described embodiments have been shown as described herein, many modifications, substitutions, alterations, and equivalents will now occur to those skilled in the art. For example, a pre-regulator may be made to convert voltages in the high-voltage (i.e., HV) range (e.g., >100V) to voltages within the safe operating area of ​​an LV device. This may be partly due to the use of LDMOS devices. In some possible embodiments, these devices may be configured to handle HV at their drain terminals (or gate terminals). Various other devices may be used to generate / clamp voltages between terminals. While diodes and diode-connected transistors are described in the illustrated embodiments, Zener diodes may also be suitable. Therefore, it should be understood that the appended claims are intended to cover all such modifications and variations falling within the scope of the embodiments. It should be understood that they are presented by way of example only and not limitation, and various changes in form and detail may be made. Any part of the apparatus and / or method described herein may be combined in any combination, except for mutually exclusive combinations. The embodiments described herein may include various combinations and / or sub-combinations of the functions, components, and / or features of the different embodiments described.

[0051] Typical embodiments have been disclosed in the specification and / or the figures. This disclosure is not limited to such exemplary embodiments. The use of the term "and / or" includes any and all combinations of one or more of the associated listed items. The figures are schematic and therefore not necessarily drawn to scale. Unless otherwise stated, particular terms are used in a general and descriptive sense and not for limiting purposes.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. Similar or equivalent methods and materials to those described herein may be used in practice or testing of this disclosure. As used in the specification and appended claims, the singular forms “a,” “an,” and “the” include the plural forms unless the context clearly specifies otherwise. As used herein, the term “comprising” and variations thereof are used synonymously with the term “including” and variations thereof and are open-ended, non-limiting terms. The terms “optional” or “optionally” as used herein mean that a feature, event, or condition subsequently described may or may not occur, and the description includes instances where said feature, event, or condition occurs and instances where it does not occur. A range may be expressed herein as from “about” one particular value and / or to “about” another particular value. When such a range is expressed, one aspect includes from one particular value and / or to another particular value. Similarly, when values ​​are expressed as approximate values, the use of the antecedent “about” will help to understand that the particular value forms another aspect. It will be further understood that each endpoint of a range is significant relative to and independent of the other endpoint.

[0053] Some implementations can be achieved using various semiconductor processing and / or packaging technologies. Some implementations can be achieved using various types of semiconductor processing technologies associated with a semiconductor substrate, including but not limited to, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), and so on.

[0054] It should be understood that in the foregoing description, when an element is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, it may be directly on, connected to, or coupled to another element, or one or more intermediate elements may be present. In contrast, when an element is referred to as being directly on, directly connected to, or directly coupled to another element, no intermediate elements are present. Although the terms "directly on," "directly connected to," or "directly coupled to" may not be used throughout the detailed description, elements shown as being directly on, directly connected to, or directly coupled may be referred to in this way. If present, the claims of this application may be modified to refer to the exemplary relationships described in the specification or shown in the figures.

[0055] As used herein, the singular form may include the plural form unless the context clearly indicates otherwise. Spatial relative terms (e.g., above, above, upper, below, under, lower, etc.) are intended to cover different orientations of the device in use or operation other than those depicted in the figures. In some embodiments, the relative terms above and below may include vertical above and vertical below, respectively. In some embodiments, the term proximity may include lateral proximity or horizontal proximity.

Claims

1. A voltage pre-regulator, comprising: The bias circuit section includes: A first current mirror and a second current mirror are connected to form a feedback loop, the feedback loop being configured to amplify the leakage current generated by the input voltage of the voltage pre-regulator, such that the leakage current increases according to positive feedback to become an amplified leakage current, and A transistor coupled between the input voltage and the feedback loop, the transistor being configured as a current source, the current source being configured to limit the increase of the amplified leakage current by applying negative feedback to the feedback loop, such that the bias circuit portion outputs a bias current and a bias voltage after the startup period; and The regulator circuitry includes a laterally diffused metal-oxide-semiconductor (LDMOS) transistor configured to generate a voltage drop from the input to the output of a voltage pre-regulator based on the bias current and the bias voltage, the voltage pre-regulator being configured to output a regulated voltage based on the voltage drop.

2. The voltage pre-regulator according to claim 1, wherein the input voltage is in the medium voltage (MV) range and the regulated voltage is in the low voltage (LV) range.

3. The voltage pre-regulator according to claim 1, wherein the output terminal of the first current mirror is coupled to the input terminal of the second current mirror, and the output terminal of the second current mirror is coupled to the input terminal of the first current mirror.

4. The voltage pre-regulator according to claim 3, wherein The first current mirror is configured to amplify the leakage current by a first amplification factor based on a first size difference between the transistors of the first current mirror; and The second current mirror is configured to amplify the leakage current by a second amplification factor based on a second size difference between the transistors of the second current mirror.

5. The voltage pre-regulator of claim 4, wherein the transistor generates a voltage corresponding to the amplified leakage current, and during the startup period, the voltage decreases the first amplification factor of the first current mirror as the amplified leakage current increases.

6. The voltage pre-regulator of claim 5, wherein the transistor is a depletion-mode native transistor (NVT).

7. The voltage pre-regulator of claim 5 further includes a protection circuit coupled between the input terminal and the first current mirror, the protection circuit being configured to clamp the voltage of the current source to protect the current source from damage.

8. The voltage pre-regulator according to claim 1, wherein the regulator circuit portion includes a voltage source, and the regulated voltage is equal to the voltage source.

9. The voltage pre-regulator according to claim 8, wherein the voltage source comprises a diode or a plurality of diodes connected in series.

10. The voltage pre-regulator of claim 8, wherein the voltage source comprises a diode-connected transistor or a plurality of diode-connected transistors coupled in series.

11. The voltage pre-regulator of claim 1, wherein the bias circuit portion is self-starting when the input voltage is applied.

12. The voltage pre-regulator of claim 1, wherein after the start-up period, the positive feedback and the negative feedback are balanced under equilibrium to generate the bias current and the bias voltage.

13. A voltage pre-regulation method, the method comprising: The input voltage is received in the bias circuit section of the voltage pre-regulator; According to the positive feedback amplification of leakage current, the positive feedback is generated by a first current mirror and a second current mirror connected to form a feedback loop; The amplification factor of the leakage current is limited by negative feedback, which is applied to the feedback loop by a transistor coupled between the input voltage and the feedback loop; When the positive feedback and the negative feedback are balanced, a bias current and a bias voltage are generated. Apply bias current and bias voltage to the regulator circuit section of the voltage pre-regulator; as well as The output regulated voltage is based on the voltage drop from the input voltage, which is generated by the bias current and the bias voltage.

14. The voltage pre-regulation method according to claim 13, wherein the input voltage is in the medium voltage (MV) range and the regulated voltage is in the low voltage (LV) range.

15. The voltage pre-regulation method according to claim 13, wherein... Each current mirror includes transistors of different sizes to produce their respective amplification factors.

16. The voltage pre-regulation method of claim 13, wherein the negative feedback is a voltage generated by the transistor.

17. The voltage pre-regulation method of claim 16, wherein the voltage is a gate-source voltage corresponding to the level of the amplified leakage current.

18. A system including a voltage pre-regulator, the system comprising: Low-voltage devices, including transistors that have a safe operating zone in a low-voltage range; as well as A voltage pre-regulator, coupled to an input voltage located outside the safe operating area, and configured to provide a regulated voltage to the low-voltage equipment within the safe operating area, the voltage pre-regulator comprising: The bias circuit section includes: A first current mirror and a second current mirror are connected to form a feedback loop, the feedback loop being configured to amplify the leakage current generated by the input voltage to produce an amplified leakage current that increases according to positive feedback, and A transistor coupled between the input voltage and the feedback loop is configured as a current source to limit the increase of the amplified leakage current by applying negative feedback to the feedback loop, such that the positive and negative feedbacks are balanced after the startup period, wherein, under this balance, the bias circuit portion outputs a bias current and a bias voltage. The regulator circuitry includes a laterally diffused metal-oxide-semiconductor (LDMOS) transistor configured to generate a voltage drop from the input of a voltage pre-regulator to its output based on the bias current and the bias voltage, the voltage pre-regulator being configured to output the regulated voltage based on the voltage drop.

19. The system of claim 18, wherein the low-voltage device is a low-voltage regulator.

20. The system of claim 18, wherein the low-voltage device and the voltage pre-regulator are part of an integrated circuit.

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