Non-volatile memory devices, controllers, and methods of operating the same

Abstract

Non-volatile memory devices, controllers, and methods of operating the same are provided. The controller includes a non-volatile memory interface circuit connected to at least one non-volatile memory device and configured to control the at least one non-volatile memory device, and an error correction circuit configured to perform an error correction operation on a codeword received from the non-volatile memory interface circuit according to an error correction decoding level selected from among a plurality of error correction decoding levels, wherein the non-volatile memory interface circuit is further configured to receive side information from the at least one non-volatile memory device, predict a distribution of memory cells based on the side information, and select the error correction decoding level from among the plurality of error correction decoding levels according to the predicted distribution.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2021-0005211, filed on January 14, 2021, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a non-volatile memory device, a controller for controlling a non-volatile memory device, a storage device having a non-volatile memory device, and a method for reading the non-volatile memory device. Background Technology

[0003] Typically, memory devices can use error correction code (ECC) circuitry to generate error correction codes during write operations, and then correct errors in the data by referring to these codes during read operations. However, when memory cells are severely degraded, ECC circuitry may not be able to perform corrections. In this case, a read retry operation can be performed using a sensing technique different from that used in normal read operations. Summary of the Invention

[0004] A non-volatile memory device that can reduce the latency of defense codes is provided, a controller for controlling the non-volatile memory device, a storage device having a non-volatile memory device, and a method for reading the non-volatile memory device are provided.

[0005] Additional aspects will be set forth in part in the description which follows, and will be apparent in part from the description, or may be learned by practice of the presented embodiments.

[0006] According to one aspect of the disclosure, a controller includes: a non-volatile memory interface circuit connected to at least one non-volatile memory device and configured to control the at least one non-volatile memory device; and an error correction circuit configured to perform an error correction operation on codewords received from the non-volatile memory interface circuit according to an error correction decoding level among a plurality of error correction decoding levels, wherein the non-volatile memory interface circuit is further configured to: receive auxiliary information from the at least one non-volatile memory device, predict the distribution of memory cells based on the auxiliary information, and select an error correction decoding level from the plurality of error correction decoding levels according to the predicted distribution.

[0007] According to one aspect of the disclosure, a method of operating a controller includes: receiving auxiliary information from at least one non-volatile memory device via at least one pin; determining an error correction decoding level from a plurality of error correction decoding levels based on the auxiliary information; and performing an error correction operation according to the determined error correction decoding level.

[0008] According to one aspect of the disclosure, a non-volatile memory device includes: a plurality of memory blocks comprising at least two strings between respective bit lines and a common source line, wherein each of the at least two strings includes at least one string select transistor, a plurality of memory cells, and at least one ground transistor connected in series between one of the bit lines and the common source line, wherein the gate of the at least one string select transistor is connected to a string select line, wherein each of the plurality of memory cells is configured to receive a word line voltage from a respective word line, and wherein the gate of the at least one ground transistor is connected to a ground select line; and control logic configured to: perform at least one on-chip valley search (OVS) read operation for memory cells connected to a word line of a memory block selected from the plurality of memory blocks based on a first read command, and output detection information of the at least one OVS read operation to an external device based on a specific command, wherein the detection information includes: information about whether the search for an optimal valley was successful, or information about the height value of the optimal valley.

[0009] According to one aspect of the disclosure, a storage device includes at least one non-volatile memory device and a controller, the controller being configured to control the at least one non-volatile memory device, and comprising: a control pin configured to provide a control signal to the at least one non-volatile memory device; a buffer memory configured to store a table for executing a plurality of defense codes; an error correction circuit configured to correct errors in first read data of a first page read from the at least one non-volatile memory device based on a first read command; and at least one processor configured to drive a defense code management unit based on the uncorrectable errors in the first read data, wherein the defense code management unit is configured to: receive auxiliary information from the at least one non-volatile memory device via at least one of the control pins, and select a defense code among a plurality of defense codes, or a defense code stream among a plurality of defense code streams, based on the auxiliary information.

[0010] According to one aspect of the disclosure, a method for reading a storage device includes: performing a normal read operation based on a default read level; determining whether the data read in the normal read operation is error-correctable; performing an on-chip valley search (OVS) read operation based on the determination that the read data is not error-correctable; and executing adaptive defense code based on detection information of the OVS read operation if the result of the OVS read operation is a read failure, wherein the adaptive defense code corresponds to one of a hard decision read operation, a soft decision read operation, and a valley search read operation based on the detection information.

[0011] According to one aspect of the disclosure, a non-volatile memory device includes: a memory cell region having a first metal pad; a peripheral circuit region having a second metal pad and being vertically connected via the first and second metal pads; a memory cell array including a plurality of memory blocks having a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines in the memory cell region; a line decoder configured to select one of the plurality of word lines in the peripheral circuit region; a page buffer circuit having a plurality of page buffers connected to the plurality of bit lines in the peripheral circuit region; and control logic configured to... The device is configured to receive a Command Latch Enable (CLE) signal, an Address Latch Enable (ALE) signal, a Chip Enable signal, a Write Enable (WE) signal, a Read Enable signal, and a Data Strobe signal via control pins, and to perform an On-Chip Valley Search (OVS) read operation by latching a command or address on the edge of the WE signal in response to the CLE and ALE signals. The control logic is configured to output detection information of the OVS read operation to an external device based on a specific command, and the detection information includes information about whether the search for the optimal valley was successful or about the valley height value of the optimal valley. According to one aspect of the disclosure, a method for controlling a storage device includes: performing a read operation to obtain read data; detecting errors in the read data; determining whether the errors in the read data are correctable; performing an On-Chip Valley Search (OVS) read operation based on the determination that the errors in the read data are uncorrectable; obtaining detection information corresponding to the OVS read operation; selecting a data recovery process from a plurality of data recovery processes based on the detection information; and executing the selected data recovery process. Attached Figure Description

[0012] The above and other aspects, features, and advantages of specific embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 This is a diagram illustrating the storage device 10 according to an embodiment;

[0014] Figure 2 This illustrates an embodiment. Figure 1 A diagram of a non-volatile memory device 100 shown in the figure;

[0015] Figure 3 This is an illustration based on an embodiment. Figure 1 A circuit diagram of one of the memory blocks, BLKi, shown in the diagram;

[0016] Figure 4 This is a diagram illustrating a controller 200 according to an embodiment;

[0017] Figure 5A , Figure 5B and Figure 5C This is a diagram showing the error correction circuit 230 of the controller 200 according to an embodiment;

[0018] Figure 6 This is a diagram illustrating the defense code flow of a general-purpose storage device according to an embodiment;

[0019] Figure 7 This is a diagram illustrating the adaptive defense code operation of a storage device according to an embodiment;

[0020] Figure 8 This is a flowchart illustrating adaptive defense code of a storage device according to an embodiment;

[0021] Figure 9 This illustrates an embodiment. Figure 8 The flowchart of operation S130 is shown in the figure;

[0022] Figure 10A and Figure 10B This is a diagram illustrating an OVS read operation according to an embodiment;

[0023] Figures 11A to 11E This is a diagram illustrating adaptive defense code that depends on the valley height of the storage device 10 according to an embodiment;

[0024] Figure 12 This is a diagram illustrating an example of an ECC decoding mode that selects adaptive defense codes based on distribution according to an embodiment;

[0025] Figure 13 This is a diagram illustrating the storage device 20 according to an embodiment;

[0026] Figure 14 This is a diagram illustrating a controller 400 with an adaptive ECC scheduler 462 according to an embodiment;

[0027] Figure 15 This is a diagram illustrating a controller according to another embodiment;

[0028] Figure 16 This is a flowchart illustrating a reading method of the storage device 10 according to an embodiment;

[0029] Figure 17 This is a diagram illustrating a method for reading from a storage device according to another embodiment;

[0030] Figure 18 This is a ladder diagram illustrating adaptive defense code processing of a storage device according to another embodiment;

[0031] Figure 19 This is a ladder diagram illustrating adaptive defense code processing of a storage device 10 according to another embodiment;

[0032] Figure 20 This is a ladder diagram illustrating adaptive defense code processing of a storage device 10 according to another embodiment;

[0033] Figure 21 This is a ladder diagram illustrating a read operation of a storage device 10 according to another embodiment;

[0034] Figure 22 This is a diagram illustrating a storage device 30 according to another embodiment; and

[0035] Figure 23 This is a diagram illustrating a non-volatile memory device 1000 implemented in a C2C structure according to another embodiment. Detailed Implementation

[0036] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0037] As is conventional in the art, embodiments can be described and illustrated in terms of blocks that perform one or more functions. These blocks (which may be referred to herein as units or modules, or named such as drivers, controllers, devices, etc.) can be physically implemented by analog or digital circuitry (such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuitry, etc.) and can be driven by firmware and software. For example, the circuitry can be implemented in one or more semiconductor chips or on a substrate support (such as a printed circuit board, etc.). The circuitry included in the block can be implemented by dedicated hardware, or by a processor (e.g., one or more programmed microprocessors and associated circuitry), or by a combination of dedicated hardware for performing some functions of the block and a processor for performing other functions of the block. Each block of an embodiment can be physically divided into two or more interactive and discrete blocks. Similarly, the blocks of an embodiment can be physically combined into more complex blocks.

[0038] Typically, products based on NAND flash memory solutions (such as solid-state drives (SSDs) or universal flash storage (UFS)) may include various technologies that extend the product's lifespan by delaying NAND flash memory degradation caused by user use; these technologies are collectively referred to as defense codes. NAND flash memory degradation can be caused by process fragmentation and various external environmental factors. NAND flash memory degradation can increase the number of errors in read data, which can make data recovery via error correction codes (ECC) difficult, potentially reducing product reliability. Defense codes can aid in ECC data recovery by suppressing the increase in errors caused by NAND flash memory degradation.

[0039] The term "defense code" can also refer to a software recovery algorithm in a narrow sense. Defense codes can be implemented through firmware within a solution. Furthermore, the term "defense code" can also refer to algorithms used to improve characteristics within a single NAND flash memory cell, as well as ECC hardware IP within the controller. In the following description, the term "defense code" may be used to refer to a software recovery algorithm as defined in the narrower sense, but the disclosure is not limited thereto.

[0040] Generally, defense code algorithms used to prevent NAND flash memory degradation can be mainly divided into prevention techniques and recovery techniques. Prevention techniques can preemptively protect NAND flash memory from degradation and can include garbage collection (e.g., block management), wear leveling (e.g., pursuing uniform degradation), and read reclaim (e.g., predicting the degree of degradation in advance and preventing defects by transing that degree). Techniques that use variable parameters based on the program-erase (PE) cycle to extend the service life can also be classified into a broader range of prevention defense codes.

[0041] Recovery defense codes can represent any techniques that reduce errors to correct errors when the ECC circuit cannot correct them (e.g., when there are too many errors). A typical recovery defense code might be a technique that reduces the number of errors by moving the read level to an optimal position when the number of errors increases due to incorrect read levels.

[0042] Furthermore, various methods exist for finding read levels with the minimum number of distributed errors. Typically, there are methods that quickly find the optimal read level by sacrificing accuracy, and methods that require considerable effort to find the most accurate read level. A Predefined Table (PDT) is a typical example of the former. Defense codes using a PDT can continue to attempt until the error is corrected by the ECC circuit using a predetermined set of read levels. Although the read level accuracy is not 100%, the attempts can be made rapidly and multiple times, allowing defense codes to be deployed at an early stage.

[0043] Furthermore, unlike table approach methods, there can be algorithms that use mathematical algorithms to find the optimal valley by estimating the shape near the valley of the distribution. For example, less read estimation (LRE) defenses can fall into this category. Because many resources can be used to find the valley, the algorithm can be strategically deployed in the later stages of the defense code.

[0044] Furthermore, advanced ECC circuits can maximize error correction capabilities by using information about whether the read data is "0" or "1" and information about the reliability of that information. Advanced ECC circuits can, for example, use low-density parity check (LDPC) codes. Typically, a hard-decision read can be a method of extracting information about whether the data is "0" or "1" by reading only the region near the valley once. Conversely, a soft-decision read can be a method of extracting information about the reliability of the 0 / 1 information by reading the region near the valley multiple times using different read levels.

[0045] Generally, performing ECC decoding or correction using only hard decision read results is referred to as HD decoding, while ECC decoding using soft decision read results is referred to as SD decoding. Soft decision decoding offers significantly better correction capabilities than hard decision decoding. However, because soft decision reads involve a larger number of reads, they can burden product performance. Therefore, generally speaking, hard decision decoding can be performed first by executing hard decision reads, and if hard decision decoding fails, soft decision reads with stronger correction capabilities can be performed, making soft decision decoding efficient.

[0046] Hard-decision decoding may fail because the read level is incorrectly sought. When hard-decision decoding fails even when the read level is correctly sought, performing soft-decision read / decode may be efficient. When errors increase due to incorrect read level seeking, performing hard-decision decoding after quickly seeking the read level again may be more efficient.

[0047] Regarding the non-volatile memory device, controller for controlling the non-volatile memory device, storage device having the non-volatile memory device, and its reading method in the example embodiments, when errors are not correctable in the default read, an operation to search for the optimal valley of the non-volatile memory device can be performed. Read data and optimal valley detection information (e.g., an indication of whether the optimal valley search was successful or the optimal valley height) can be transmitted to the controller, and the optimal defense code can be selected using the optimal valley detection information, or the optimal defense code stream can be selected using the optimal valley detection information. In other words, the controller can use the read data and the received detection information to determine the error level or distribution shape of the read data and can select the optimal defense code or the optimal defense code stream. For example, when it is determined that the read data is normal, the controller can select the basic defense code stream, and when it is determined that the number of errors is high, the controller can select a defense code stream that can directly enter soft decision read / decode instead of hard decision. Furthermore, when it is determined that the read level is incorrect, the controller can select a defense code stream that can send a re-read request to the NAND flash memory without performing ECC decoding.

[0048] Regarding the non-volatile memory device, controller for controlling the non-volatile memory device, storage device having the non-volatile memory device, and reading method thereof in the example embodiments, the reliability of the reading operation can be quickly ensured by performing a defense code operation based on the detection information of the optimal valley search operation according to the optimal defense code or the optimal defense code stream.

[0049] Figure 1 This is a diagram illustrating a storage device 10 according to an example embodiment. (Refer to...) Figure 1 The storage device 10 may include at least one non-volatile memory device 100 (NVM) and a controller 200 (CNTL).

[0050] At least one non-volatile memory device 100 may be implemented to store data. The non-volatile memory device 100 may be implemented as NAND flash memory, vertical NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin-transfer torque random access memory (STT-RAM), etc. Furthermore, the non-volatile memory device 100 may be implemented in a three-dimensional array structure. Example embodiments are applicable to flash memory devices in which the charge storage layer is formed by conductive floating gates, and also to charge-trapped flash memory (CTF) in which the charge storage layer is formed by an insulating layer. In the following description, for ease of description, the non-volatile memory device 100 may be implemented as a vertical NAND flash memory device (VNAND).

[0051] Furthermore, the non-volatile memory device 100 may be implemented as including a plurality of memory blocks BLK1 to BLKz (where z is an integer equal to or greater than 2) and control logic 150. Each of the plurality of memory blocks BLK1 to BLKz may include a plurality of pages Page 1 to Page m (where m is an integer equal to or greater than 2). Each of the plurality of pages Page 1 to Page m may include a plurality of memory cells. Each of the plurality of memory cells may store at least one bit.

[0052] Control logic 150 can receive commands and addresses from controller 200, and can perform operations corresponding to the received commands (e.g., programming operations, reading operations, erasing operations, etc.) on the memory cells corresponding to the addresses.

[0053] Furthermore, control logic 150 may include on-chip valley search (OVS) circuitry 155. OVS circuitry 155 may be implemented to perform on-chip valley search (OVS) operations. Typically, OVS operations may include operations to acquire cell counts based on various develop times, operations to determine the OVS detection status based on the acquired cell counts, and a main sensing operation to perform sensing by changing the actual develop time based on the determined OVS detection status. In one embodiment, the develop time is the period during which the voltage change of the sensing node occurs. OVS circuitry 155 may be implemented to store detection information (OVSDI) corresponding to the result of the OVS operation. Detection information (OVSDI) may be, for example, detection status information or cell count information. Detection information OVSDI may include information indicating the optimal distribution valley corresponding to the state (e.g., develop time information).

[0054] The controller 200 can be connected to at least one non-volatile memory device 100 via multiple control pins for sending control signals (e.g., command latch enable (CLE) signal, address latch enable (ALE) signal, one or more chip enable (CE) signals, write enable (WE) signal, read enable (RE) signal, one or more data strobe (DQS) signals, data signal (DQ), etc.), and can also be implemented to control the non-volatile memory device 100 using control signals. For example, the non-volatile memory device 100 can perform programming / reading / erasing operations by latching a command (CMD) or address (ADD) at the edge of the write enable (WE) signal according to the command latch enable (CLE) signal and the address latch enable (ALE) signal.

[0055] In addition, the controller 200 may include at least one processor (e.g., a central processing unit (CPU)) 210, a buffer memory 220, and an error correction circuit 230, which may be, for example, an ECC circuit.

[0056] CPU 210 can be implemented to control the overall operation of storage device 10. CPU 210 can perform various management operations (such as cache / buffer management, firmware management, garbage collection management, wear leveling management, deduplication management, read refresh / reclaim management, bad block management, multi-stream management, host data and non-volatile memory mapping management, quality of service (QoS) management, system resource allocation management, non-volatile memory queue management, read level management, erase / programming management, hot / cold data management, power failure protection management, dynamic thermal management, initialization management and redundant array of low-cost disks (RAID) management).

[0057] Furthermore, CPU 210 can be implemented to drive adaptive defense code unit (e.g., adaptive recovery code unit) 211. Using OVS-based detection information OVSDI, adaptive defense code unit 211 can select the best defense code or the best set of defense codes. In one example embodiment, adaptive defense code unit 211 can be implemented as firmware or software, or any combination thereof.

[0058] In one example embodiment, the adaptive defense code unit 211 can use detection information OVSDI to select one of a performance reliability defense code, a lifetime reliability defense code, and a machine learning defense code. The reliability defense code may include temperature compensation defense code, address compensation defense code, history defense code, on-chip valley search (OVS) defense code, RPF, predefined table (PDT) defense code, etc. Furthermore, the lifetime defense code may include minimum read estimation (LRE), DRR, SWING, and soft decision offset tracking (SDOT).

[0059] In another example embodiment, the adaptive defense code unit 211 may use detection information OVSDI to select a series of defense codes. The series of defense codes may represent the consecutive operation of at least two different defense codes.

[0060] Figure 1 The adaptive defense code unit 211 shown can be executed in the controller 200. However, its example embodiments are not limited thereto. The adaptive defense code unit can also be executed in the non-volatile memory device 100.

[0061] The buffer memory 220 can be implemented as volatile memory (e.g., static random access memory (SRAM), dynamic RAM (DRAM), synchronous RAM (SDRAM), etc.) or non-volatile memory (e.g., flash memory, PRAM, MRAM, resistive RAM (ReRAM), FRAM, etc.). The buffer memory 220 may include at least one predefined table (PDT), an OVS table (OVST), and a history read level table (HRT).

[0062] The PDT may include first read level offset information. In one example embodiment, the PDT may include first read level offset information corresponding to the elapsed time since programming. In one example embodiment, in addition to the elapsed time since programming, the PDT may also include first read level offset information corresponding to various degradation information (e.g., temperature, programming / erase cycle, read cycle, word line disconnection, word line position information, etc.).

[0063] OVST may include second read level offset information corresponding to the detection information OVSDI. Here, the detection information OVSDI may be configured as development time information corresponding to the optimal distribution valley. In other words, the second read level offset information may include read level offset information corresponding to the development time information of the OVS operation being performed. Therefore, OVST may be a table obtained by converting the detection information OVSDI into read level offset information.

[0064] The HRT may include third read level offset information in relation to historical read operations. In one example embodiment, the third read level offset information may include information obtained by accumulating second read level offset information. In another example embodiment, the third read level offset information may be determined using first and second read level offset information. The third read level offset information may include the optimal read level for performing the historical read operation. Examples of historical read operations are described in U.S. Patent Nos. 10,120,589 and 10,373,693, the disclosures of which are incorporated herein by reference in their entirety.

[0065] Error correction circuit 230 can be implemented to generate error correction codes during programming operations and to recover data using the error correction codes during read operations. In other words, error correction circuit 230 can generate error correction codes to correct faulty or erroneous bits in data received from non-volatile memory device 100. Error correction circuit 230 can form data with parity bits added by performing error correction encoding on the data provided to non-volatile memory device 100. The parity bits can be stored in non-volatile memory device 100.

[0066] Furthermore, the error correction circuit 230 can perform error correction decoding on data output from the non-volatile memory device 100. The error correction circuit 230 can use parity checking to correct errors. The error correction circuit 230 can use one or more of the following to correct errors: LDPC code, BCH code, turbo code, Reed-Solomon code, convolutional code, recursive systematic code (RSC), and coded modulation (such as trellis-coded modulation (TCM) and block-coded modulation (BCM)).

[0067] When error correction is not feasible in the error correction circuit 230, a read retry operation may be performed. In one example embodiment, the read retry operation may include an OVS operation.

[0068] The storage device 10 in the example embodiment may include an adaptive defense code unit 211, which can select / execute the best defense code or the best set of defense codes using detection information OVSDI based on OVS operation after the uncorrectable error correction code (UECC) is generated, so that performance improvements (such as reduced latency of the ECC decoder and defense code) can be expected.

[0069] Figure 2 It is shown Figure 1 A diagram showing a non-volatile memory device 100. (Refer to...) Figure 2 The non-volatile memory device 100 may include a memory cell array 110, a row decoder 120 (row DEC), a page buffer (e.g., a page buffer circuit) 130, an input / output buffer (e.g., an input / output buffer circuit) 140, control logic 150, a voltage generator 160, and a cell counter 170.

[0070] Memory cell array 110 can be connected to row decoder 120 via word line WL or select lines SSL and GSL (not shown). Memory cell array 110 can be connected to page buffer circuitry 130 via bit line BL. Memory cell array 110 may include multiple cell strings. Each channel of a cell string may be formed in a vertical or horizontal direction. Each cell string may include multiple memory cells. Multiple memory cells can be programmed, erased, or read by voltage supplied to bit line BL or word line WL. Typically, programming operations can be performed on a page-by-page basis, and erasing operations can be performed on a block-by-block basis. Examples of such memory cells are described in detail in U.S. Patents 7,679,133, 8,553,466, 8,654,587, 8,559,235, and 9,536,970, the disclosures of which are incorporated herein by reference in their entirety. In one example embodiment, the memory cell array 110 may include a two-dimensional memory cell array, and the two-dimensional memory cell array may include a plurality of NAND strings arranged along the row and column directions.

[0071] The row decoder 120 can be implemented to select one of the memory blocks BLK1 to BLKz of the memory cell array 110 in response to address ADD. The row decoder 120 can select one of the word lines of the selected memory block in response to address ADD. The row decoder 120 can transfer a word line voltage VWL corresponding to the operating mode to the word line of the selected memory block. During programming operations, the row decoder 120 can apply programming and verification voltages to the selected word line and can apply a pass voltage to the unselected word line. During read operations, the row decoder 120 can apply a read voltage to the selected word line and can apply a read pass voltage to the unselected word line.

[0072] Page buffer circuit 130 can be implemented as a write driver or a sense amplifier. During a programming operation, page buffer circuit 130 can apply a bit line voltage corresponding to the data to be programmed to the bit line of memory cell array 110. During a read operation or a verified read operation, page buffer circuit 130 can detect the data stored in the selected memory cell via bit line BL. Each of the plurality of page buffers PB1 to PBn (n is an integer equal to or greater than 2) included in page buffer circuit 130 can be connected to at least one bit line.

[0073] Each of the multiple page buffers PB1 to PBn can be implemented to perform sensing and latching for performing OVS operations. In other words, each of the multiple page buffers PB1 to PBn can perform multiple sensing operations under the control of control logic 150 to identify one of the states stored in a selected memory cell. Furthermore, each of the multiple page buffers PB1 to PBn can store each piece of data sensed through the multiple sensing operations, and can select one of the data under the control of control logic 150. In other words, each of the multiple page buffers PB1 to PBn can perform sensing multiple times to identify one of the states. Furthermore, each of the multiple page buffers PB1 to PBn can select or output the best data among the multiple pieces of data sensed under the control of control logic 150.

[0074] Input / output buffer circuit 140 can provide data from an external entity to page buffer circuit 130. Input / output buffer circuit 140 can provide commands (CMD) from an external entity to control logic 150. Input / output buffer circuit 140 can provide addresses (ADD) from an external entity to control logic 150 or line decoder 120. Furthermore, input / output buffer circuit 140 can output data sensed and latched by page buffer circuit 130 to an external entity.

[0075] Control logic 150 may be implemented to control line decoder 120 and page buffer circuitry 130 in response to a command CMD sent from an external entity. Furthermore, control logic 150 may include OVS circuitry 155 for performing OVS operations.

[0076] OVS circuit 155 controls page buffer circuit 130 and voltage generator 160 for OVS operation. OVS circuit 155 controls page buffer circuit 130 to perform multiple sensing operations to identify the specific state of selected memory cells. Furthermore, OVS circuit 155 controls multiple page buffers PB1 to PBn to store sensing data corresponding to each of the multiple sensing results in multiple latch groups, each of the multiple page buffers PB1 to PBn. Additionally, OVS circuit 155 performs processing for selecting the best data among the multiple sensing data. To select the best data, OVS circuit 155 can refer to a counting result nC provided from cell counter 170. In other words, OVS circuit 155 controls page buffer circuit 130 to select and output the read result closest to the distribution valley among the multiple sensing results.

[0077] Furthermore, the OVS circuit 155 can store development time information corresponding to OVS operation. The OVS circuit 155 can output the stored development time information as detection information OVSDI to the controller 200. In one example embodiment, the detection information OVSDI can be output using the Universal Internal Bus (UIB), or it can be output in response to a specific command (e.g., a get feature command, a status read command, etc.).

[0078] Voltage generator 160 can be implemented, under the control of control logic 150, to generate various types of word line voltages to be applied to each word line and well voltages to be supplied to the bulk (e.g., well region) formed by the memory cells. The word line voltages applied to each word line may include programming voltage, pass voltage, read voltage, and read pass voltage, etc.

[0079] Cell counter 170 can be implemented to count memory cells corresponding to a specific threshold voltage range based on data sensed by page buffer circuit 130. For example, cell counter 170 can count the number of memory cells having a threshold voltage within a specific threshold voltage range by processing data sensed in each of a plurality of page buffers PB1 to PBn.

[0080] Figure 3 This is a diagram showing a circuit diagram of a memory block BLKi (where i is an integer equal to or greater than 2). Multiple memory NAND strings included in the memory block BLKi may be formed along a direction perpendicular to the substrate (e.g., the Z direction).

[0081] Reference Figure 3 The memory block BLKi may include multiple memory NAND strings NS11 to NS33 connected between bit lines BL1, BL2, and BL3 and the common-source line CSL. Each of the multiple memory NAND strings NS11 to NS33 may include a string select transistor SST, multiple memory cells MC1, MC2, ..., MC8, and a ground select transistor GST. Figure 3 In this context, each of the multiple memory NAND strings NS11 to NS33 may include eight memory cells MC1, MC2, ..., MC8, but the example embodiments are not limited thereto.

[0082] The serial select transistor SST can be connected to the corresponding serial select lines SSL1, SSL2, and SSL3. Multiple memory cells MC1, MC2, ..., MC8 can be connected to the corresponding gate lines GTL1, GTL2, ..., GTL8, respectively. Gate lines GTL1, GTL2, ..., GTL8 can be word lines, and a portion of gate lines GTL1, GTL2, ..., GTL8 can be dummy word lines. The ground select transistor GST can be connected to the corresponding ground select lines GSL1, GSL2, and GSL3. The serial select transistor SST can be connected to the corresponding bit lines BL1, BL2, and BL3, and the ground select transistor GST can be connected to the common-source line CSL.

[0083] Word lines of the same height (e.g., WL1) can be connected together, and ground select lines GSL1, GSL2, and GSL3 can be separated from string select lines SSL1, SSL2, and SSL3, respectively. Figure 3 In this embodiment, the memory block BLKi can be connected to eight gate lines GTL1, GTL2, ..., GTL8, but the embodiments are not limited to this.

[0084] Figure 4 This is a diagram illustrating a controller 200 according to an example embodiment. (Refer to...) Figure 4 The controller 200 may include a host interface 201 (host I / F), a memory interface 202 (NVM I / F), at least one CPU 210, a buffer memory 220, an error correction circuit 230, a flash translation layer 240 (FTL) (which may be, for example, a flash translation layer manager), a packet manager 250, and an encryption device 260 (AES).

[0085] Host interface 201 may be implemented to send packets to and receive packets from a host. Packets sent from the host to host interface 201 may include data or commands to be written to non-volatile memory device 100. Packets sent from host interface 201 to the host may include responses to data or commands read from non-volatile memory device 100. Memory interface 202 may send data to be written to non-volatile memory device 100 or receive data read from non-volatile memory device 100. Memory interface 202 may be implemented in compliance with standards such as the Joint Electronic Equipment Commission (JEDEC) Toggle or Open NAND Flash Interface (ONFI) standards.

[0086] The flash translation layer manager 240 can perform various functions, such as address mapping, wear leveling, and garbage collection. Address mapping can be an operation that translates a logical address received from the host into a physical address used to actually store data in the non-volatile memory device 100. Wear leveling can be a technique that prevents excessive degradation of specific blocks by allowing for uniform use of blocks in the non-volatile memory device 100. For example, wear leveling can be implemented using firmware techniques that balance the erase counts of physical blocks. Garbage collection can be a technique that ensures available capacity in the non-volatile memory device 100 by copying valid data from blocks to new blocks and erasing existing blocks.

[0087] Packet manager 250 can generate packets according to the protocol of the interface negotiated with the host, or can parse various information from packets received from the host. Furthermore, buffer memory 220 can temporarily store data to be written to or read from non-volatile memory device 100. In one example embodiment, buffer memory 220 may be included in controller 200. In another example embodiment, buffer memory 220 may be located outside controller 200.

[0088] Encryption device 260 may use a symmetric key algorithm to perform at least one of encryption and decryption operations on data input to CPU 210. Encryption device 260 may use the Advanced Encryption Standard (AES) algorithm to encrypt and decrypt data. Encryption device 260 may include an encryption module and a decryption module.

[0089] Figure 5A , Figure 5B and Figure 5C This is a diagram illustrating the error correction circuit 230 of the controller 200 according to an example embodiment.

[0090] Reference Figure 5A The error correction circuit 230 may include an ECC encoding circuit 231 and an ECC decoding circuit 232. The ECC encoding circuit 231 may, in response to the ECC control signal ECC_CON, generate parity bits ECCP[0:7] for the data WData[0:63] to be written into the memory cells of the memory cell array 111. The parity bits ECCP[0:7] may be stored in the ECC cell array 112. In one example embodiment, the ECC encoding circuit 231, in response to the ECC control signal ECC_CON, generates parity bits ECCP[0:7] for the data WData[0:63] to be written into the memory cells including the defective cells.

[0091] ECC decoding circuit 232 can respond to ECC control signal ECC_CON by using data RData[0:63] read from memory cells of memory cell array 111 and parity bits ECCP[0:7] read from ECC cell array 112 to correct erroneous bit data, and can output the error-corrected data Data[0:63](DQ). In one example embodiment, ECC decoding circuit 232 can respond to ECC control signal ECC_CON by using data RData[0:63] read from memory cells including defective cells and parity bits ECCP[0:7] read from ECC cell array 112 to correct erroneous bit data, and can output the error-corrected data Data[0:63](DQ).

[0092] Reference Figure 5B The ECC encoding circuit 231 may include a syndrome generator 231-1, which is configured to receive 64-bit write data WData[0:63] and base bits B[0:7] in response to the ECC control signal ECC_CON, and to generate parity bits ECCP[0:7] (i.e., the syndrome) using an XOR array. For example, the base bits B[0:7] may be bits used to generate the parity bits ECCP[0:7] of the 64-bit write data WData[0:63], and may include the b'00000000 bit. The base bits B[0:7] may use other bits instead of the b'00000000 bit.

[0093] Reference Figure 5CThe ECC decoding circuit 232 may include a corrector generator 232-1, a coefficient calculator 232-2, a 1-bit error position detector 232-3, and an error corrector 232-4. The corrector generator 232-1 can receive 64-bit read data RData[0:63] and 8-bit parity bits ECCP[0:7] in response to the ECC control signal ECC_CON, and can use an XOR array to calculate and generate corrector data S[0:7]. The coefficient calculator 232-2 can use the corrector data S[0:7] to calculate the coefficients of the error position equation. In the error position equation, the reciprocal of the error bit can be the root. The 1-bit error position detector 232-3 can use the calculated error position equation to calculate the position of a 1-bit error. The error corrector 232-4 can determine the 1-bit error position based on the detection result of the 1-bit error position detector 232-3. Error corrector 232-4 can correct errors by inverting the logical values ​​of the erroneous bits in the 64-bit read data RData[0:63] (i.e., the data sent to the global input / output line (GIO[0:63])) according to the determined 1-bit error location information, and can output the corrected 64-bit read data Data[0:63] (DQ).

[0094] Figure 6 This is a diagram illustrating the processing corresponding to the defense code stream of a general-purpose storage device.

[0095] General-purpose storage devices can recover from NVM errors through a combination of ECC operations and read-level search algorithms. (See reference...) Figure 6 According to the general defense code flow, HD reading / decoding can be performed in operation S610, and if the operation fails in operation S620, HD decoding can be re-performed in operation S630 using a predefined table (PDT) with a new read level. The PDT defense code can store read level values ​​and can attempt to recover quickly in the event of an error by using these values. Errors can be recovered by reading level values ​​through pre-profiling for each possible error scenario.

[0096] When HD decoding fails during operation S640, an accurate valley-finding algorithm (such as Minimum Read Estimate (LRE)) can be used during operation S650, and if HD decoding fails during operation S660, SD read / decode can be performed during operation S670. The LRE defense code searches for the optimal read level by modeling the cell distribution in two or three dimensions using cell count information.

[0097] When SD decoding fails during operation S680, during operation S690, correction can be attempted by changing the soft decision offset (SDOT, Soft Decision Offset Tracking) compared to the default value of the less read estimate. Additionally, error recovery can be attempted by shifting the read level searched in the less read estimate to the left / right (swing defense code).

[0098] A generic defense code flow can be executed according to a predetermined process (e.g., a fixed procedure), regardless of the NVM's state. When the NVM deteriorates significantly, the frequency of executing the defense code flow can increase. This can lead to severe performance degradation, making the user aware of the degradation caused by increased latency in the defense code.

[0099] The storage device and its reading method in the example embodiment can accurately monitor the state of the NVM and can modify the defense code stream based on the monitoring results. Therefore, the storage device and reading method in the example embodiment can solve the latency problem of the defense code stream.

[0100] Figure 7 This is a diagram illustrating the adaptive defense code operation of a storage device according to an example embodiment. (Refer to...) Figure 7 The adaptive defense code unit (e.g., adaptive recovery code unit) 211 can use detection information OVSDI to select one of a plurality of defense code streams or a series of defense codes, and defense code operations can be performed according to the selected defense code stream. Figure 7 For ease of description, only three defense code streams are shown; however, the embodiments are not limited to these.

[0101] The storage device 10 in the example embodiment can be used in a non-volatile memory device 100 (such as, for example...). Figure 1 Side information generated during a read operation (as shown in the diagram) is used to predict the distribution of the non-volatile memory device 100, allowing for the selection of an optimal defensive code stream based on the predicted distribution, and enabling the execution of defensive code. In one example embodiment, the side information may include information about the success of a valley search (or search for the optimal valley) based on the OVS operation, or information about the height of the optimal valley.

[0102] When the non-volatile memory device 100 transmits OVS information OVSDI to the controller 200 (e.g., for example) Figure 1 When (as shown in the diagram), in addition to reading data, the controller 200 can use the OVS information OVSDI to select one of the three defense code streams and execute the defense code.

[0103] First, when it is determined that the data read is normal, defense code operations can be performed according to the basic defense code stream. In an example embodiment, the first defense code stream can perform the following operations in sequence: hard decision read operation through the first predefined table PDT1, hard decision read operation through the second predefined table PDT2, 2-bit soft decision read operation after valley search performed through minimum read estimation (LRE), 3-bit soft decision read operation after valley search performed through LRE, and 3-bit soft decision read operation and SDOT read operation after valley search performed through LRE.

[0104] Second, when it is determined that there are many errors in the read data, defense code operations can be performed based on a defense code stream that directly enters SD decoding instead of HD decoding. In an example embodiment, the second defense code stream may perform the following operations in sequence: a 3-bit soft decision read operation after valley search via LRE, a 3-bit soft decision read operation and a first SDOT read operation after valley search via LRE, a 3-bit soft decision read operation and a second SDOT read operation after valley search via LRE, and a smart soft decision read operation after valley search via LRE.

[0105] Third, when it is determined that a change in the read level is needed, a defense code operation can be performed by rereading the NVM without decoding, as requested. In an example embodiment, the third defense code stream may include a hard decision read operation using a first predefined table PDT1, a hard decision read operation using a second predefined table PDT2, a hard decision read operation using a third predefined table PDT3, a 2-bit soft decision read operation after valley search via minimum read estimation (LRE), a 3-bit soft decision read operation after valley search via LRE, and a 3-bit soft decision read operation after valley search via LRE and an SDOT (scanning method) read operation. A 2-bit soft decision read operation may require 2 bits of data for the read decision, and a 3-bit soft decision read operation may require 3 bits of data for the read decision.

[0106] It should be understood that Figure 7 The number of defense code streams and each defense code stream shown are merely examples.

[0107] Figure 8 This is a flowchart illustrating adaptive defense code for a storage device according to an example embodiment. (Refer to...) Figures 1 to 8 The adaptive defense code operation of storage device 10 can be executed as follows.

[0108] During operation S110, storage device 10 may perform a default read operation in response to a request from an external host. The default read operation may be a normal read operation or a historical read operation. The default read may mean performing HD decoding by reading at a default read level. When decoding fails (e.g., when UECC is generated or ECC decoding fails), defense code may be executed (meaning valley search via OVS sensing).

[0109] In operation S120, when it is determined that the error correction circuit 230 cannot be passed (e.g., for example...), Figure 1 When correcting errors in the read data of the default read operation (as shown in the diagram), the storage device 10 may enter an adaptive defense code operation. When the storage device enters the defense code, the controller 200 of the storage device 10 (e.g., ...) Figure 1 (As shown) can simultaneously send OVS read commands to non-volatile memory device 100 (e.g., as shown) Figure 1 (As shown in the diagram). The non-volatile memory device 100 can perform an OVS read operation in response to an OVS read command. In operation S130, the non-volatile memory device 100 can output the data read in the OVD read operation and the OVS detection information OVSDI to the controller 200.

[0110] During operation S140, the controller 200 can perform adaptive ECC decoding using the OVS detection information OVSDI. In this case, the read data and OVS sensing data can be sent to the controller. With this information, since it is clear that ECC cannot correct errors, the controller can determine whether to perform ECC decoding on the corresponding data through internal calculation or request a reread to the NAND. In other words, when it is determined that a more powerful valley search algorithm (LRE) is needed, a valley search using the LRE can be requested from the NAND, and as a determining factor, a method that cleverly uses OVS data or a method that uses ECC corrector weights can be considered. The ECC corrector can be a metric used to estimate how many errors occur in the read data using the characteristics of the ECC code, and can be calculated within the ECC engine. Regarding the weights, the corrector can be a vector including 0s and 1s as elements, and the weights can be the number of 1s, and it can be estimated that the larger the number, the more errors are likely to occur.

[0111] The adaptive ECC decoding operation can be performed as follows. After operation S130, in operation S141, the controller 200 can determine whether it is necessary to search for the optimal valley through Less Read Estimate (LRE). When error correction is not possible and the number of errors is greater than a predetermined value, it can be determined that LRE is needed, and LRE can be performed in operation S142.

[0112] When LRE is not required, operation S143 can determine whether the valley height extracted from the OVS detection information OVSDI is less than the first reference value PDV1. When the valley height is less than the first reference value PDV1, operation S144 can use the modified read level to perform hard decision decoding. In operation S145, if no further hard decision decoding passes, 3-bit soft decision decoding can be performed.

[0113] When the valley height is not less than the first reference value PDV1, it can be determined in operation S146 whether the valley height is less than the second reference value PDV2. The second reference value PDV2 can be higher than the first reference value PDV1. When the valley height is less than the second reference value PDV2, 2-bit soft decision decoding can be performed in operation S147. When 2-bit soft decision decoding fails in operation S146 or the valley height is not less than the second reference value PDV2, 3-bit soft decision decoding can be performed in operation S145.

[0114] like Figure 8 As shown, simple operation can be performed without a feedback loop between the controller and the NAND. Once the NAND transmits OVS information and reads data, the controller can simply select the ECC decoding mode without requesting additional operations from the NAND, which can represent a narrower range of operations than typical operations.

[0115] As another example, the optimal valley information provided by NAND can be more or less specific than the X and Y counts. More specific information might be provided when the cell counts near the valley (e.g., X1, X2, Y1, and Y2) are sent more specifically than the X and Y counts. In this case, there might be an overhead in data transmission, but the error level can be measured more accurately.

[0116] In this embodiment, by simply reading and sending the X+Y count, the burden of data transmission can be reduced, and information about the error level can be predicted even if there is no information about the valley location. When the valley is not changed, the defense code stream can be modified by simply knowing the error level (e.g., by simply selecting the decoding mode).

[0117] Figure 9 It is shown Figure 8 The flowchart shows an example of operation S130. (Refer to...) Figures 1 to 9 The following steps can be performed to process the output of OVS read data and OVS detection information OVSDI.

[0118] In operation S131, the non-volatile memory device 100, which receives an OVS read command from the controller 200, can perform OVS sensing. On-chip valley search (OVS) can be an algorithm used to quickly read distribution data near valleys and determine the direction in which the optimal read level is likely to be found. Valley search methods using the PDT method can be randomly selected, making them potentially inaccurate, while OVS can perform the search by predicting the distribution shape, making it more likely to find the optimal read level. When a valley search is successfully performed using this method, data can be read with reduced errors, and the data can be sent to the controller.

[0119] In operation S132, during the OVS sensing operation, it can be determined whether the valley search was successful. When the valley search is successful, in operation S133, a data reading operation can be performed using the read level corresponding to the searched valley, and the OVS detection information OVSDI can be output accordingly.

[0120] If the valley search fails, operation S134 can determine whether the number of repeated valley searches is the maximum value. If the number of repetitions is not the maximum value, operation S135 can use the OVS sensing result to change the read level, and operation S131 can be executed. If the number of repetitions is the maximum value, operation S133 can be executed.

[0121] OVS operation provides information about whether the read level is well matched, and also the error level when a well match occurs. This information can be used to determine whether to perform a read level search (LRE).

[0122] Figure 10A and Figure 10B This is a diagram illustrating an OVS read operation according to an example embodiment. For example... Figure 10A As shown, the OVS operation for searching the distribution valleys of states S1 and S2 can be performed through multiple sensing operations. Multiple sensing operations can be performed simultaneously in multiple page buffer groups.

[0123] Reference Figure 10B On-chip valley search can be performed by storing sensing results by sequentially latching sensing nodes into the first page buffer PGB1 and the second page buffer PGB2 at the same time point during different development periods.

[0124] A pre-charge operation can be performed from time point T0 to time point T1. For pre-charge, the first bit line and the first sensing node connected to each of the first page buffers PBG1 can be charged. When the bit line establishment signal is activated, the sensing node and the first bit line can be pre-charged to a predetermined level. When the first bit line establishment signal is deactivated to a high level at time point T1, the pre-charge circuit of each of the first page buffers PBG1 can be turned off. Furthermore, when the second bit line establishment signal is deactivated to a high level at time point T2, which follows time point T1, the pre-charge circuit of each of the second page buffers PBG2 can be turned off. In this case, the level of the sensing node of each of the first page buffers PBG1 and the level of the sensing node of each of the second page buffers PBG2 (in...) Figure 10B The value (indicated by "VSO") can be changed based on the magnitude of the current flowing to the corresponding bit line, depending on whether the memory cell is on or off.

[0125] like Figure 10B As shown, each of the first page buffers PBG1 can precharge the sensing node from time point T0 to time point T1, and can develop the first bit line from time point T1 to time point T4. Each of the second page buffers PBG2 can precharge the sensing node from time point T0 to time point T1, and can develop the second bit line from time point T2 (which may be later than time point T1) to time point T4. For example, a re-precharge can be performed from time point T6 to time point T7. The first sensing operation may include a latch reset nS sensing operation performed at time point T3 and a latch set S sensing operation performed at time point T5. The first cell count information can be calculated using the on-cell count values ​​of the latch reset nS sensing operation and the latch set S sensing operation in the first page buffer PGB1. In addition, the second cell count information can be calculated using the on-cell count values ​​of the latch reset nS sensing operation and the latch set S sensing operation in the second page buffer PGB2. Based on the first unit count information and the second unit count information of the first sensing operation, the detection condition corresponding to the distribution valley (e.g., one of C1 to C5 corresponding to the optimal read level) can be determined, and the development time tSODev1 to tSODev5 of the second sensing operation corresponding to the determined detection condition can be determined.

[0126] Figures 11A to 11E This is a diagram illustrating adaptive defense code that depends on the valley height of storage device 10 according to an example embodiment.

[0127] Figure 11AThis indicates when a valley-finding algorithm (such as LRE) can be used. Typically, OVS information can be cell count information corresponding to normal X and Y. X can be the cell count value read when the reference target level is below a predetermined level, and Y can be the cell count value read when the reference target level is above a predetermined level.

[0128] In one example embodiment, the read levels may mismatch when the X and Y values ​​are significantly different from each other. Therefore, a new valley search operation may be required. When the valleys match well, the X and Y values ​​can be very similar. In this case, performing ECC decoding may be worthwhile.

[0129] Reference Figure 11B Although valleys can be well searched, the ECC decoding method can be optimally chosen based on the valley height compared to reference values ​​α and β. For example, when valleys are well searched, the number of errors can be predicted by counting X and Y. When it is assumed that there are many errors in this prediction, it may be better to go directly to SD decoding instead of HD decoding. When the error may not be correctable with HD decoding, time can be saved.

[0130] like Figure 11C As shown, when the valley height is equal to or greater than the second reference value β corresponding to PDV2, 3-bit SD decoding can be performed immediately. Figure 11D As shown, when the valley height is equal to or greater than the first reference value α corresponding to PDV1 and less than the second reference value β corresponding to PDV2, 2-bit SD decoding can be performed immediately. Figure 11E As shown, HD decoding can be performed when the valley height is less than the first reference value α that corresponds to PDV1.

[0131] As described above, the adaptive ECC decoding method can reduce defense code latency by eliminating inefficient operations in the defense code. Since space can be generated to add another strong defense code that utilizes the reduced latency, a defense code stream with stronger corrective capabilities can be provided.

[0132] In particular, because the time spent on ECC decoding in the defense code stream is very long, eliminating meaningless ECC decoding can be efficient in terms of latency reduction.

[0133] Figure 12 This is a diagram illustrating an example of an ECC decoding mode based on distributed selection of adaptive defense codes according to an example embodiment. (Refer to...) Figure 12 Strong error region A, weak error region B, weak correction region C, and strong correction region D can exist in the upper state.

[0134] In one example embodiment, the controller 200 can use OVS detection information OVSDI to determine whether to perform HD decoding or SD decoding. An HD read operation can be an operation that reads data based on the on or off state of a memory cell by providing a predetermined hard-decision read voltage to the memory cell. An SD read operation can be an operation that reads data by providing multiple soft-decision read voltages with predetermined offsets based on the hard-decision read voltage.

[0135] Furthermore, the log likelihood ratio (LLR) can be a specific value provided to the data used in the decoding process, and can be a value that adds reliability to the data. In other words, the LLR value can add reliability to the determination of whether the data is 0 or 1. In an example embodiment, OVS detection information OVSDI can be used to determine reliability and repetition count. In one example embodiment, controller 200 can determine the LLR value of an ECC decoding operation or the repetition count of an SD read operation based on the OVS detection information OVSDI.

[0136] Figures 1 to 1 Figure 1 illustrates adaptive defense code selection using OVS detection information (OVSDI). It should be understood that the embodiments are not limited to OVS detection information. Example embodiments may be described by selectively operating ECC decoding using various auxiliary information other than OVS detection information.

[0137] Figure 13 This is a diagram illustrating a storage device 20 according to an example embodiment. (Refer to...) Figure 13 The storage device 20 may include at least one non-volatile memory device 300 (NVM) and a controller 400 (CNTL) for controlling the non-volatile memory device 300.

[0138] The non-volatile memory device 300 may include an auxiliary information generator 301 for generating auxiliary information. In one example embodiment, the auxiliary information generator 301 may generate relevant auxiliary information by performing an OVS operation. In one example embodiment, the auxiliary information generator 301 may generate relevant auxiliary information by performing a cell counting operation. In one example embodiment, the auxiliary information generator 301 may generate relevant auxiliary information by performing a read operation on the spare area of ​​a page. Furthermore, the non-volatile memory device 300 may output auxiliary information according to periodic / aperiodic requests from the controller 400. In one example embodiment, the auxiliary information may be transmitted via at least one line between the non-volatile memory device 300 and the controller 400. In another example embodiment, the auxiliary information may be transmitted via at least one data line between the non-volatile memory device 300 and the controller 400.

[0139] The controller 400 may include error correction circuitry 430 (which may be, for example, ECC circuitry) and non-volatile memory interface circuitry 460 (NVM I / F).

[0140] Error correction circuitry 430 may include decoding mode register 431. Decoding mode register 431 may store optimal decoding mode information corresponding to auxiliary information sent from non-volatile memory device 300. Decoding modes may include HD decoding mode, 1-bit SD decoding mode, 2-bit SD decoding mode, and 3-bit SD decoding mode.

[0141] The non-volatile memory interface circuit 460 can generate commands for controlling the non-volatile memory device 300. The non-volatile memory interface circuit 460 may include an error evaluator 461 and an ECC scheduler 462.

[0142] Error evaluator 461 can use auxiliary information received from non-volatile memory device 300 to generate decoding mode information for determining the level of ECC decoding.

[0143] ECC scheduler 462 can control the decoding of error correction circuit 430 based on auxiliary information received from non-volatile memory device 300. For example, ECC scheduler 462 can select the ECC level for ECC decoding based on the auxiliary information.

[0144] Figure 14 This is a diagram illustrating a controller 400 with an adaptive ECC scheduler 462 according to an example embodiment.

[0145] Reference Figure 14 Multiple non-volatile memory devices NVM1, NVM2, ..., NVMp (where p is an integer equal to or greater than 2) can be connected to the ECC scheduler 462 and can send and receive data.

[0146] The ECC scheduler 462 can receive auxiliary information from each of a plurality of non-volatile memory devices NVM1, NVM2, ..., NVMp, select the optimal ECC decoding level corresponding to the auxiliary information, and control the error correction circuit 430 to perform ECC decoding operations according to the selected ECC decoding level. Furthermore, the ECC scheduler 462 can send pseudo-codewords to the error correction circuit 430 and receive feedback signals from the error correction circuit 430.

[0147] The error correction circuit 430 can be implemented to perform decoding operations based on multiple decoding levels. Figure 14 For ease of description, three decoding levels are shown, but the example embodiments are not limited to these. The error correction circuit 430 can operate at the optimal decoding level based on the decoding mode information stored in the decoding mode register 431. The error-corrected data in the error correction circuit 430 can be sent to the host.

[0148] exist Figure 14 In this system, the level of ECC decoding can be determined based on the results of error assessment of the non-volatile memory device. However, exemplary embodiments thereof are not limited to this. The level of ECC decoding can be determined based on error assessment of other memory devices in the controller.

[0149] Figure 15 This is a diagram illustrating a controller according to another example embodiment. In one example embodiment, controller 400a may include NVM control circuitry 460a, error correction circuitry 430a, host IP 450, DRAM 421, and SRAM 422. (See also...) Figure 15 The error correction circuit 430a can determine the optimal ECC decoding level using error evaluation of each of the internal memories DRAM 421 and SRAM 422 or error evaluation of each of the external non-volatile memory devices NVM1 to NVMp. Therefore, the error correction circuit 430a can perform error correction operations that can be fast and highly reliable.

[0150] In one example embodiment, the error estimator connected to each of the non-volatile memory devices NVM1 to NVMp can be coupled with... Figure 13 The error estimator 461 shown is implemented in the same manner. In one example embodiment, the error estimator connected to each of the memory devices DRAM 421 and SRAM 422 can be implemented in the same manner as... Figure 13 The error estimator 461 shown is implemented in the same manner. In another example embodiment, the error estimator connected to each of the memory devices DRAM 421 and SRAM 422 can be... Figure 13 The error evaluator 461 shown in the figure is implemented differently.

[0151] Figure 16 This is a flowchart illustrating a reading method of the storage device 10 according to an example embodiment. (Refer to...) Figures 1 to 16 The reading operation of storage device 10 can be performed as follows.

[0152] During operation S210, storage device 10 (e.g., for example) Figure 1 (As shown) can perform a normal read operation using the default read level in response to a read request from an external host. The non-volatile memory device 100 of storage device 10 (e.g., Figure 1 (As shown) can output read data to controller 200 according to normal read operations (e.g., Figure 1 (As shown in the diagram). In operation S220, the controller 200 may use the error correction circuit 230 to determine whether error correction of the read data is not feasible (e.g., determine whether UECC is generated).

[0153] When error correction is not feasible, in operation S230, controller 200 may send an OVS read command to non-volatile memory device 100, and non-volatile memory device 100 may perform an OVS read operation in response to the OVS read command. The read data from the OVS read operation and OVS detection information OVSDI may be output to controller 200. In operation S240, when error correction based on the read data from the OVS read operation is not feasible, controller 200 may use the OVS detection information OVSDI to execute adaptive defense code.

[0154] Figure 17 This is a diagram illustrating a method for reading from a storage device according to another example embodiment. (Refer to...) Figures 1 to 17 The storage device 20 can be executed as follows (e.g., for example) Figure 13 The read operation is shown in the figure.

[0155] In operation S310, controller 400 (e.g., for example) Figure 13 (as shown) can be obtained from a non-volatile memory device 300 (such as, for example) Figure 13 (As shown in the diagram) Receives auxiliary information. This auxiliary information may be related to the cell distribution characteristics of the non-volatile memory device 300. For example, the auxiliary information may include cell count information, valley search detection information, etc.

[0156] In operation S320, the controller 400 can use auxiliary information to select the ECC decoding level. In operation S330, the controller 400 can perform ECC decoding operation according to the selected ECC decoding level.

[0157] Figure 18 This is a ladder diagram illustrating adaptive defense code processing of a storage device according to another example embodiment. (Refer to...) Figures 1 to 18 The following can be used to execute the defense code processing of the storage device.

[0158] In operation S10, the controller CNTL (which may correspond, for example, to controller 200 or controller 400) may send a first read command to the non-volatile memory device NVM (which may correspond, for example, to non-volatile memory device 100). In operation S11, the non-volatile memory device NVM may perform a first OVS read operation in response to the first read command. When the valley search is successful, the read data of the first OVS read operation may be output to the controller CNTL in operation S12-1. When the valley search is unsuccessful, the non-volatile memory device NVM may change the read level in operation S12-2, and may perform a second OVS read operation using the changed read level in operation S13. In operation S14, the read data of the second OVS read operation may be output to the controller CNTL.

[0159] Subsequently, in operation S15, the controller CNTL determines whether error correction for the read data is not feasible. If error correction is not feasible, in operation S16, the controller CNTL can send a specific command to the non-volatile memory device NVM. In operation S17, the non-volatile memory device NVM, in response to the specific command, sends OVS detection information OVSDI to the controller CNTL. The controller CNTL can then use the OVS detection information OVSDI to execute adaptive defense code. The controller CNTL can use the OVS detection information OVSDI to select and execute the optimal defense code. In operation S18, the controller CNTL can send a second read command corresponding to the optimal defense code to the non-volatile memory device NVM. The second read command may include a read command corresponding to one of a hard decision read operation, a soft decision read operation, and an LRE (valley search) read operation. In operation S19, the non-volatile memory device NVM, in response to the second read command, performs a hard decision read / soft decision read / LRE read operation. The read data from the read operation can be output to the controller CNTL.

[0160] In one example embodiment, at least one OVS read operation may include a first OVS read operation, and when no optimal valley is found in the first OVS read operation, the control logic may change the read level and execute a second OVS read operation. In one example embodiment, at least one OVS read operation may include a first OVS read operation, and when the detection condition of the first OVS read operation is an edge case, the control logic may change the read level and execute a second OVS read operation. In one example embodiment, the control logic may receive a second read command corresponding to the detection information, and may execute at least one of a hard decision read operation, a soft decision read operation, and a valley search read operation in response to the second read command. In one example embodiment, the size of the first sector data (e.g., HD read data) output in response to the first read command and the size of the second sector data (e.g., HD+SD read data) output in response to the second read command may be different from each other.

[0161] Figure 19 This is a ladder diagram illustrating adaptive defense code processing for a storage device (which may correspond to storage device 10) according to another example embodiment. (Refer to...) Figures 1 to 19 The defense code processing of storage device 10 can be executed as follows.

[0162] In operation S20, the controller CNTL can send a first read command to the non-volatile memory device NVM. In operation S21, the non-volatile memory device NVM can perform an OVS read operation in response to the first read command. In operation S22, the read data from the OVS read operation can be output to the controller CNTL. In operation S23, the controller CNTL can send a specific command to the non-volatile memory device NVM. In operation S24, the non-volatile memory device NVM can send OVS detection information OVSDI to the controller CNTL in response to the specific command.

[0163] In operation S25, the controller CNTL can determine whether errors in the read data of the OVS read operation cannot be corrected. If error correction is not possible, the controller CNTL can use the OVS detection information OVSDI to change the read level in operation S26.

[0164] Subsequently, in operation S27, the controller CNTL can send a second read command along with a modified read level to the non-volatile memory device NVM. The second read command may include a read command corresponding to one of a hard-decision read operation, a soft-decision read operation, and a valley-search read operation (such as an LRE (valley-search) read operation). In operation S28, the non-volatile memory device NVM can perform a hard-decision read / soft-decision read / LRE read operation in response to the second read command. In operation S29, the read data from the read operation can be output to the controller CNTL.

[0165] Figure 20 This is a ladder diagram illustrating adaptive defense code processing for a storage device (which may correspond to storage device 10) according to another example embodiment. (Refer to...) Figures 1 to 20 The following can be used to execute the defense code processing of the storage device.

[0166] In operation S30, the controller CNTL can send a read command to the non-volatile memory device NVM. In operation S31, the non-volatile memory device NVM can perform a first read operation using OVS sensing in response to the read command.

[0167] In operation S32, it can be determined whether the detection condition of the first read operation is an edge. If the detection condition is not an edge, in operation S33, the read data of the second read operation can be output to the controller CNTL. If the detection condition is an edge, in operation S34, the non-volatile memory device NVM can change the read level. In operation S35, the non-volatile memory device NVM can perform the second read operation based on the internally changed read level using OVS sensing.

[0168] Subsequently, in operation S36, it can be determined whether the detection status of the second read operation is an edge. If the detection status of the second read operation is not an edge, in operation S37, the read data of the second read operation can be output to the controller CNTL. If the detection status of the second read operation is an edge, operation S34 can be executed.

[0169] Subsequently, in operation S38, the controller CNTL can send a specific command to the non-volatile memory device NVM. In operation S39, the non-volatile memory device NVM can send OVS detection information OVSDI to the controller CNTL in response to the specific command.

[0170] Figure 21 This is a ladder diagram illustrating a read operation of a storage device (which may correspond to storage device 10) according to another example embodiment. (Refer to...) Figures 1 to 21 The following read operations can be performed on the storage device.

[0171] During operation S40, the host can send a read request along with the address ADD to the storage device 10 (e.g., for example...). Figure 1 (As shown in the diagram). In operation S41, the controller CNTL (which may correspond to the controller 200 of the storage device 10) can receive a read request, search the history buffer, determine whether to perform a history read operation or a normal read operation, and can send a normal / history read command corresponding to the determined operation to the non-volatile memory device NVM (e.g., as shown in the diagram). Figure 1 The non-volatile memory device 100 shown is described. In operation S42, the non-volatile memory device NVM can perform a read operation in response to a normal / historical read command, and can send the read data accordingly to the controller 200.

[0172] Subsequently, in operation S43, the controller CNTL can perform error correction on the data read by the error correction circuit 230. When there is no error or the error is correctable, the read data or the corrected data can be sent to the host in operation S44-1.

[0173] When error correction is not feasible, the controller CNTL can send a read retry command to the non-volatile memory device NVM in operation S44-2. In operation S45, the non-volatile memory device NVM can perform a read operation using OVS sensing in response to such a read retry command, and can send the read data to the controller 200.

[0174] Subsequently, in operation S46, the controller CNTL can perform error correction again on the data read from the error correction circuit 230. When no error exists or error correction is feasible, the read data or corrected data can be sent to the host in operation S47. Subsequently, in operation S48, the controller CNTL can send a specific command to the non-volatile memory device NVM to obtain read retry information with read level information. In operation S49, the non-volatile memory device NVM can output read retry information in response to the specific command. Subsequently, in operation S50, the controller CNTL can finally update the historical read level table HRT using the read retry information.

[0175] Subsequently, in operation S51, when a read request for the same address ADD is received from the host, in operation S52, the storage device 10 can use the OVS detection information OVSDI to send the best read command (e.g., SD / HD / LRE read command) to the non-volatile memory device NVM.

[0176] The storage device in the example embodiment may include an artificial intelligence processor dedicated to defense code.

[0177] Figure 22 This is a diagram illustrating a storage device 30 according to another example embodiment. (Refer to...) Figure 22 ,and Figure 1 Compared to the example shown, the controller 200a of the storage device 30 may include an artificial intelligence processor 212 (e.g., a processing unit for artificial intelligence) for executing adaptive defense code units. The artificial intelligence processor 212 may perform machine learning to manage the reliability of the non-volatile memory device 100.

[0178] The non-volatile memory device in the example embodiment can be implemented in a chip-to-chip (C2C) architecture.

[0179] Figure 23 This diagram illustrates a non-volatile memory device 1000 implemented with a C2C structure according to another embodiment. In the C2C structure, an upper chip including cell regions (CELL) can be fabricated on a first wafer, and a lower chip including peripheral circuit regions (PERI) can be fabricated on a second wafer different from the first wafer. The upper and lower chips are connected to each other by a bonding method. For example, the bonding method may be a method of electrically connecting a bonding metal formed on the lowest metal layer of the upper chip to a bonding metal formed on the highest metal layer of the lower chip. In one example embodiment, when the bonding metal is formed of copper (Cu), the bonding method may be a Cu-to-Cu bonding method. In another example embodiment, the bonding metal may be formed of aluminum (Al) or tungsten (W).

[0180] Each of the peripheral circuit region PERI and cell region CELL of the non-volatile memory device 1000 may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0181] The Peripheral Circuit Region (PERI) may include a first substrate 1210, an interlayer insulating layer 1215, a plurality of circuit devices 1220a, 1220b, and 1220c formed on the first substrate 1210, first metal layers 1230a, 1230b, and 1230c connected to each of the plurality of circuit devices 1220a, 1220b, and 1220c, and second metal layers 1240a, 1240b, and 1240c formed on the first metal layers 1230a, 1230b, and 1230c. In one example embodiment, the first metal layers 1230a, 1230b, and 1230c may be formed of tungsten, which has a relatively high resistivity. In one example embodiment, the second metal layers 1240a, 1240b, and 1240c may be formed of copper, which has a relatively low resistivity.

[0182] Figure 23 The diagram shows first metal layers 1230a, 1230b, and 1230c and second metal layers 1240a, 1240b, and 1240c, but exemplary embodiments thereof are not limited thereto. At least one metal layer may be further formed on the second metal layers 1240a, 1240b, and 1240c. At least a portion of one or more metal layers formed on the second metal layers 1240a, 1240b, and 1240c may be formed of aluminum having a resistivity different from that of the copper forming the second metal layers 1240a, 1240b, and 1240c.

[0183] In one example embodiment, an interlayer insulating layer 1215 may be disposed on a first substrate 1210 to cover a plurality of circuit devices 1220a, 1220b and 1220c, first metal layers 1230a, 1230b and 1230c, and second metal layers 1240a, 1240b and 1240c. In one example embodiment, the interlayer insulating layer 1215 may include an insulating material (such as silicon oxide or silicon nitride).

[0184] Lower bonding metals 1271b and 1272b may be formed on a second metal layer 1240b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 1271b and 1272b in the peripheral circuit region PERI are electrically connected to the upper bonding metals 1371b and 1372b of the cell region CELL via a bonding method. In one example embodiment, the lower bonding metals 1271b and 1272b and the upper bonding metals 1371b and 1372b may be formed of aluminum, copper, or tungsten. Furthermore, the upper bonding metals 1371b and 1372b of the cell region CELL may be referred to as a first metal pad, and the lower bonding metals 1271b and 1272b may be referred to as a second metal pad.

[0185] A cell region (CELL) may include at least one memory block. In one example embodiment, the cell region (CELL) may include a second substrate 1310 and a common-source line 1320. Multiple word lines 1330 (which may include word lines 1331 to 1338) may be stacked on the second substrate 1310 in a direction perpendicular to the upper surface of the second substrate 1310 (e.g., the Z-axis direction). In one example embodiment, a serial select line and a ground select line may be arranged above and below the multiple word lines 1330. In one example embodiment, the multiple word lines 1330 may be positioned between the serial select line and the ground select line.

[0186] In the bit line bonding region BLBA, the channel structure CH may extend in a direction perpendicular to the upper surface of the second substrate 1310 (e.g., the Z-axis direction) and may pass through multiple word lines 1330, as well as serial select lines and ground select lines. The channel structure CH may include a data storage layer, a channel layer, and a buried insulating layer, the channel layer being electrically connected to a first metal layer 1350c and a second metal layer 1360c. For example, the first metal layer 1350c may be a bit line contact, and the second metal layer 1360c may be a bit line. In one example embodiment, the second metal layer 1360c may extend in a first direction parallel to the upper surface of the second substrate 1310 (e.g., the Y-axis direction).

[0187] like Figure 23As shown, the region where the channel structure CH and the second metal layer 1360c are provided can be referred to as the bit line bonding region BLBA. In an example embodiment, in the bit line bonding region BLBA, the second metal layer 1360c may be electrically connected to the circuit arrangement 1220c in which the page buffer 1393 is provided in the peripheral circuit region PERI. For example, the second metal layer 1360c may be connected to the upper bonding metals 1371c and 1372c in the cell region CELL. The upper bonding metals 1371c and 1372c may be connected to the lower bonding metals 1271c and 1272c, which are connected to the circuit arrangement 1220c of the page buffer 1393. In the word line bonding region WLBA, multiple word lines 1330 may extend in a second direction (e.g., the X-axis direction) that is parallel to the upper surface of the second substrate 1310 and perpendicular to the first direction. In one example embodiment, the word line bonding region (WLBA) may be connected to a plurality of cell contact plugs 1340 (including, for example, cell contact plugs 1341 to 1347). For example, a plurality of word lines 1330 and a plurality of cell contact plugs 1340 may be connected to each other via pads provided by at least a portion of the plurality of word lines 1330 extending in a second direction at different lengths. In one example embodiment, a first metal layer 1350b and a second metal layer 1360b may be sequentially connected to the cell contact plugs 1340 connected to the plurality of word lines 1330. In one example embodiment, the plurality of cell contact plugs 1340 may be connected in the word line bonding region (WLBA) to the peripheral circuitry region (PERI) via upper bonding metals 1371b and 1372b of the cell region (CELL) and lower bonding metals 1271b and 1272b of the peripheral circuitry region (PERI).

[0188] In one example embodiment, a plurality of cell contact plugs 1340 may be electrically connected to a circuit arrangement 1220b that houses the line decoder 1394 in the peripheral circuitry region PERI. In one example embodiment, the operating voltage of the circuit arrangement 1220b that houses the line decoder 1394 may differ from the operating voltage of the circuit arrangement 1220c that houses the page buffer 1393. For example, the operating voltage of the circuit arrangement 1220c that houses the page buffer 1393 may be greater than the operating voltage of the circuit arrangement 1220b that houses the line decoder 1394.

[0189] A common-source contact plug 1380 may be disposed in the external pad bonding region PA. In one example embodiment, the common-source contact plug 1380 may be formed of a conductive material (such as a metal, metal compound, or polysilicon). The common-source contact plug 1380 may be electrically connected to a common-source wire 1320. A first metal layer 1350a and a second metal layer 1360a may be sequentially stacked above the common-source contact plug 1380. For example, the region where the common-source contact plug 1380, the first metal layer 1350a, and the second metal layer 1360a are disposed may be referred to as the external pad bonding region PA. The second metal layer 1360a may be electrically connected to an upper metal via 1371a. The upper metal via 1371a may be electrically connected to an upper metal pattern 1372a.

[0190] The first input / output pad 1205 and the second input / output pad 1305 can be disposed in the external pad bonding area PA. (Refer to...) Figure 23 A lower insulating layer 1201 covering the lower surface of the first substrate 1210 may be formed below the first substrate 1210. Furthermore, a first input / output pad 1205 may be formed on the lower insulating layer 1201. In one example embodiment, the first input / output pad 1205 can be connected via a first input / output contact plug 1203 to at least one of a plurality of circuit devices 1220a, 1220b, and 1220c disposed in the peripheral circuit region PERI. In one example embodiment, the first input / output pad 1205 can be separated from the first substrate 1210 via the lower insulating layer 1201. Furthermore, because a side insulating layer is disposed between the first input / output contact plug 1203 and the first substrate 1210, the first input / output contact plug 1203 and the first substrate 1210 can be electrically separated from each other.

[0191] Reference Figure 23 An upper insulating layer 1301 covering the upper surface of the second substrate 1310 may be formed on the second substrate 1310. Furthermore, a second input / output pad 1305 may be disposed on the upper insulating layer 1301. In one example embodiment, the second input / output pad 1305 may be connected to at least one of a plurality of circuit devices 1220a, 1220b, and 1220c disposed in the peripheral circuit region PERI via a second input / output contact plug 1303, a lower metal pattern 1272a, and a lower metal via 1271a.

[0192] In one example embodiment, the second substrate 1310 and the common source line 1320 may not be located in the region where the second input / output contact plug 1303 is provided. Furthermore, the second input / output pad 1305 may not overlap with the multiple word lines 1330 in a third direction (e.g., the Z-axis direction). See also... Figure 23The second input / output contact plug 1303 may be separated from the second substrate 1310 in a direction parallel to the upper surface of the second substrate 1310. Furthermore, the second input / output contact plug 1303 may pass through the interlayer insulation layer 1315 of the cell region and may be connected to the second input / output pad 1305. In one example embodiment, the second input / output pad 1305 may be electrically connected to the circuit device 1220a.

[0193] In one example embodiment, the first input / output pad 1205 and the second input / output pad 1305 may be selectively formed. For example, the non-volatile memory device 1000 may include only the first input / output pad 1205 disposed on the first substrate 1210 or the second input / output pad 1305 disposed on the second substrate 1310. In another example embodiment, the non-volatile memory device 1000 may include both the first input / output pad 1205 and the second input / output pad 1305.

[0194] In each of the outer pad bonding region PA and bit line bonding region BLBA, which are respectively included in the cell region CELL and the peripheral circuit region PERI, the metal pattern of the uppermost metal layer may exist as a dummy pattern, or the uppermost metal layer may be empty.

[0195] In the external pad bonding region PA, the non-volatile memory device 1000 in the example embodiment may form a lower metal pattern 1273a on the uppermost metal layer of the peripheral circuit region PERI, having the same shape as the upper metal pattern 1372a of the cell region CELL, to correspond to the upper metal pattern 1372a formed on the uppermost metal layer of the cell region CELL. In the peripheral circuit region PERI, the lower metal pattern 1273a formed on the uppermost metal layer of the peripheral circuit region PERI may not be connected to a contact. Similarly, in the external pad bonding region PA, an upper metal pattern having the same shape as the lower metal pattern of the peripheral circuit region PERI may be formed on the upper metal layer of the cell region CELL, to correspond to the lower metal pattern formed on the uppermost metal layer of the peripheral circuit region PERI.

[0196] The storage device and its reading method in the example embodiment can reduce the latency of the controller's ECC decoder and defense code.

[0197] The storage device and operating method in the example embodiments can store auxiliary information for the internal valley search algorithm and can send the information to the controller when a read is performed in the NAND. In one example embodiment, the controller can determine the ECC and defense code mode based on the corresponding auxiliary information and can feed the corresponding information back to the NAND.

[0198] In one example embodiment, as NAND errors increase, after an ECC failure, operations can be performed using optimal recovery defense codes, allowing unnecessary recovery defense code patterns to be omitted and overall recovery latency to be reduced.

[0199] General-purpose defense code techniques can only predict the level of error and can determine the ECC operating mode based on the prediction. The defense code technique in the example embodiment can use auxiliary information about the internal operation of the NAND to estimate the accuracy of the current read level and the error level, such that the estimated accuracy can be used for both ECC operation and defense code operation. General-purpose defense code techniques can simply determine which ECC operation will be performed, but the defense code technique in the example embodiment can determine the overall recovery defense code mode.

[0200] According to the above example embodiments, the non-volatile memory device, the controller for controlling the non-volatile memory device, the storage device having the non-volatile memory device, and the reading method thereof can reduce the defense code latency by using auxiliary information to select the best defense code, select the best defense code stream, or select the best error correction decoding level.

[0201] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and alterations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A controller, comprising: A non-volatile memory interface circuit is connected to at least one non-volatile memory device and is configured to control the at least one non-volatile memory device. as well as The error correction circuit is configured to perform error correction operations on codewords received from the non-volatile memory interface circuit according to an error correction decoding level selected from a plurality of error correction decoding levels. The non-volatile memory interface circuit is also configured as follows: Receive auxiliary information from the at least one non-volatile memory device. Based on auxiliary information, predict the distribution of memory cells, and An error correction decoding level is selected from the plurality of error correction decoding levels based on the predicted distribution. The auxiliary information includes detection information for the Katagaya search operation.

2. The controller according to claim 1, wherein, The multiple error correction decoding levels include a first level associated with hard decision decoding, a second level associated with 2-bit soft decision decoding, and a third level associated with 3-bit soft decision decoding.

3. The controller according to claim 1, wherein, The error correction circuitry includes a decoding mode register, which is configured to store the selected error correction decoding level.

4. The controller according to claim 1, wherein, Auxiliary information is transmitted from the at least one non-volatile memory device via at least one dedicated pin.

5. The controller according to claim 1, wherein, The auxiliary information includes valley height values ​​based on the on-chip valley search operation.

6. The controller according to claim 5, wherein, Based on the valley height value being less than the first reference value, the non-volatile memory interface circuit is also configured to select a hard decision decoding level from the plurality of error correction decoding levels.

7. The controller according to claim 5, wherein, Based on the valley height value being equal to or greater than a first reference value and less than a second reference value, the non-volatile memory interface circuit is further configured to select a 2-bit soft-decision decoding level from the plurality of error correction decoding levels, and The second reference value is greater than the first reference value.

8. The controller according to claim 7, wherein, Based on the valley height value being equal to or greater than the second reference value, the non-volatile memory interface circuit is also configured to select a 3-bit soft decision decoding level from the plurality of error correction decoding levels.

9. The controller according to any one of claims 1 to 8, wherein, The non-volatile memory interface circuit is also configured to send an automatic reread command to the at least one non-volatile memory device based on the predicted distribution.

10. A method of operating a controller, the method comprising: Receive auxiliary information from at least one non-volatile memory device via at least one pin; Based on auxiliary information, the error correction decoding level is determined from multiple error correction decoding levels; as well as Error correction operations are performed based on the determined error correction decoding level. The auxiliary information includes detection information for the Katagaya search operation.

11. The operating method according to claim 10, further comprising: Send the on-chip valley search read command to the at least one non-volatile memory device; as well as Receive detection information of on-chip valley search operation corresponding to the on-chip valley search read command from the at least one non-volatile memory device. The detection information includes: information on whether the search for the optimal valley was successful, or information on the valley height value of the optimal valley.

12. The operating method according to claim 10, further comprising: A specific command is used to request the at least one non-volatile memory device to output auxiliary information to the at least one non-volatile memory device.

13. The operating method according to claim 10, further comprising: Based on auxiliary information, a defense code stream is selected from multiple defense code streams.

14. The operating method according to claim 10, further comprising: Based on auxiliary information, change the read level associated with at least one defense code.

15. A non-volatile memory device, comprising: A plurality of memory blocks comprising at least two strings between a plurality of bit lines and a common source line, wherein each of the at least two strings comprises at least one string select transistor, a plurality of memory cells, and at least one ground transistor connected in series between one of the plurality of bit lines and the common source line, wherein the gate of the at least one string select transistor is connected to a string select line, wherein each of the plurality of memory cells is configured to receive a word line voltage from a corresponding word line, and wherein the gate of the at least one ground transistor is connected to a ground select line; and The control logic is configured to: perform at least one on-chip valley search read operation on a memory cell connected to a word line of a memory block selected from the plurality of memory blocks, based on a first read command, and output detection information of the at least one on-chip valley search read operation to an external device based on a specific command. The detection information includes: information on whether the search for the optimal valley was successful, or information on the height value of the optimal valley.

16. The non-volatile memory device according to claim 15, wherein, The at least one on-chip valley search read operation includes a first on-chip valley search read operation, and In addition, since the optimal valley was not detected in the first valley search and read operation, the control logic is also configured to change the read level and perform the second valley search and read operation according to the changed read level.

17. The non-volatile memory device according to claim 15, wherein, The at least one on-chip valley search read operation includes a first on-chip valley search read operation, and Among them, based on the detection status of the first Shanggu search and read operation, which is an edge case, the control logic is also configured to: change the read level and perform the second Shanggu search and read operation according to the changed read level.

18. The non-volatile memory device according to any one of claims 15 to 17, wherein, The control logic is also configured to: receive a second read command corresponding to the detection information, and perform at least one of a hard decision read operation, a soft decision read operation, and a valley search read operation based on the second read command.

19. The non-volatile memory device according to claim 18, wherein, The size of the first sector data is different from the size of the second sector data output in response to the second read command.

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