Patterning method

Abstract

According to one aspect, a patterning method is provided that includes: on a lower pattern memory layer, forming a first upper blocking pattern, then forming an upper pattern memory layer, then forming a second upper blocking pattern; subsequently, patterning upper trenches in the upper pattern memory layer using lithography and etching, and forming a spacer line along sidewalls of the upper trenches to define spaced-apart upper trenches, at least a subset of which is interrupted by a corresponding first upper block; forming first lower trenches in the lower pattern memory layer by etching the spaced-apart upper trenches into the lower pattern memory layer, at least a subset of the first lower trenches being interrupted by portions of the lower pattern memory layer at locations defined by a corresponding block in the first upper block; subsequently, forming an auxiliary trench mask stack and patterning auxiliary trenches therein using lithography and etching; and thereafter, patterning second lower trenches in the lower pattern memory layer, the patterning including using the patterned auxiliary trench mask stack, the spacer line, and the second upper block as etch masks, at least a subset of the second lower trenches being interrupted by portions of the lower pattern memory layer at locations defined by a corresponding block in the second upper block.

Description

Technical Field

[0001] The present invention relates to a patterning method. Background Technology

[0002] Photolithography and etching processes (“photolithography-etching”) are commonly used in semiconductor device fabrication, such as forming trenches, openings, or other patterns in hard mask layers, dielectric layers, metal layers, or semiconductor layers. Patterns, such as trench patterns, can be defined photolithographically in a resist layer (i.e., exposed and developed) and transferred to the underlying layer by etching. The minimum critical size (CD) of a pattern based on photolithography-etching depends on the wavelength of light used to expose the resist. Therefore, extreme ultraviolet lithography (EUVL) enables patterns with reduced CD compared to current techniques based on, for example, 193i.

[0003] In spacer-assisted multiple patterning techniques (also known as self-aligned multiple patterning techniques) such as SADP or SAQP, raster-patterned layers of the mandrel and spacer lines can be used to form a sub-photolithographic closely spaced line pattern in the underlying layer. Multiple patterning can be combined with blocking techniques to enable the formation of interrupted or discontinuous lines.

[0004] EP 3618103 discloses a patterning method based on a combination of two photolithography etching processes supplemented with spacing-assisted (SA) technology. Therefore, this method is called the "SALELE" patterning process. The two LE processes allow the formation of two sets of alternating trenches in the target layer. Using two LE processes, a relatively tight spacing pattern can be formed by combining two relaxed pitch patterns. Simultaneously, the addition of the spacing-assisted technology ensures at least a minimum separation distance between adjacent trenches in the target layer. By using a block pattern, interrupted trenches with small tip-to-tip separation distances can be formed.

[0005] While existing patterning methods offer a path to more invasive target CDs, more invasive target CDs mean increasing sensitivity to process variability, particularly to edge placement errors (EPE). Summary of the Invention

[0006] In view of the above, one objective of this invention is to provide a patterning method capable of forming trench patterns, including interrupted trenches, which are less sensitive to process variations, particularly with improved EPE margin. Other and additional objectives may be understood from the following description.

[0007] According to a first aspect of the present invention, a patterning method is provided, the method comprising:

[0008] On the lower pattern memory layer used to memorize the first and second lower groove patterns, a first upper barrier pattern is formed, then an upper pattern memory layer is formed, and then a second upper barrier pattern is formed.

[0009] Subsequently, upper trenches are patterned in the upper pattern memory layer using photolithography and etching, and spacing lines are formed along the sidewalls of the upper trenches to define the upper trenches that provide spacing, with at least one subset interrupted by a corresponding first upper block.

[0010] By etching the spaced upper trench into the lower pattern memory layer, a first lower trench is patterned in the lower pattern memory layer, and at least a subset of the first lower trench is interrupted at a corresponding (first) lower pattern memory layer portion at a location defined by a corresponding block in the first upper block.

[0011] Subsequently, an auxiliary trench mask stack is formed, and the auxiliary trenches therein are patterned using photolithography and etching; and

[0012] Subsequently, the second lower trench in the lower pattern memory layer is patterned, the patterning including: using a patterned auxiliary trench mask stack, a spacer line, and a second upper barrier as an etching mask, at least a subset of the second lower trench is preserved at the corresponding (second) lower pattern memory layer portion interrupted at the location defined by a corresponding barrier in the second upper barrier.

[0013] The method of this invention allows the patterns of first and second trenches to be "memorized" in an underlying pattern memory layer. The memorized patterns can then be used to pattern an underlying layer, which may, for example, form a "target layer." The method of this invention is based on an advantageous combination of two photolithography etching (LE) patterning processes supplemented with spacing-assisted (SA) technology. Therefore, the method of this invention can also be referred to as a "SALELE" patterning process and has advantages corresponding to the SALELE process described above. Specifically, compared to conventional SADP and SAQP techniques, the method of this invention improves the flexibility of trench pattern shape. Furthermore, compared to conventional pure photolithography patterning techniques, this method can form trench patterns with a smaller CD (cutoff diameter).

[0014] Furthermore, patterning the upper groove and the second lower groove using the LE process can create a relatively tight pitch pattern by combining two relaxed pitch patterns (e.g., a first sub-pattern including the first lower groove and a subsequent second sub-pattern including the second lower groove). This can be particularly advantageous when combined with EUVL, another technique that is prone to random failures if used to directly form invasive scale patterns. Relaxed printing also offers the corresponding advantages described in application 193i.

[0015] A first upper barrier defines the interruption location of at least one subset of the first lower trench to be formed in the lower pattern memory layer. A second upper barrier defines the interruption location of at least one subset of the second lower trench to be formed in the lower pattern memory layer.

[0016] Using blocks to define trench breaks enables the formation of break trenches with smaller inter-tip spacing, rather than directly “printing” photolithographically defined break trenches into the pattern memory layer.

[0017] As further explained below, the formation of the first and second upper barriers can include a tone-inversion approach, i.e., including filling the openings in the (first / second) auxiliary barrier mask layers with material. The tone-inversion approach can define a smaller tip-to-tip separation than the "positive" printing of the barrier in the layer. It also allows for the use of trimming techniques to achieve even smaller tip-to-tip separations, as described below.

[0018] According to the method, the first and second lower trenches may each include one or more interrupted trenches, defined by a pattern of a first upper barrier (hereinafter referred to as the first upper barrier pattern) and a pattern of a second upper barrier (hereinafter referred to as the second upper barrier pattern). The trench being “interrupted” means that the trench includes a pair of aligned trench segments separated by trench interruptions (e.g., barriers), or a portion of a layer forming a trench segment.

[0019] Patterning the first lower trench includes etching a spaced upper trench into a lower pattern memory layer. Therefore, the spaced upper trench can be transferred to the lower pattern memory layer by etching to form a first lower trench consistent with the spaced upper trench. Since the spaced upper trench includes one or more trenches interrupted by a first upper barrier, the corresponding trench interruption can be formed in the first lower trench located below the first upper barrier and thus defined by the first upper barrier. Therefore, the method can include using the first upper barrier as an etching mask while etching the spaced upper trench into the lower pattern memory layer.

[0020] Patterning the second lower trench includes using a second upper barrier as an etch mask. Therefore, the second upper barrier can be transferred (similar to the first upper barrier) into the lower pattern memory layer as a portion of the second lower pattern memory layer that interrupts the trench formation of the second lower trench. The transfer of the second upper barrier to the lower pattern memory layer can be a sequential process, wherein the second upper barrier pattern is sequentially transferred (by etching) to one or more layers between the second upper barrier and the lower pattern memory layer, and finally transferred to the lower pattern memory layer.

[0021] Forming a second upper barrier before patterning the upper trench in the upper pattern memory layer allows the end of the second upper barrier to self-align relative to the upper trench, and thus self-align relative to the first lower trench. As will be further described below, if a portion of the second upper barrier protrudes into the area covering the region where the upper trench will be formed, said portion can be removed before etching the upper trench.

[0022] It should be noted that the second upper barrier may or may not exist as an etching mask before the second lower trench patterning is completed. That is, the second upper barrier may be used as an etching mask during at least the initial portion of the second lower trench patterning.

[0023] For example, during the initial pattern transfer step, a second upper barrier can be used as an etching mask, wherein the pattern of the second upper barrier can first be transferred to an upper pattern memory layer and / or into a supplementary pattern memory layer, which can be formed between the upper pattern memory layer and the second barrier pattern. The second upper barrier can then optionally be removed, and alternatively, during the final transfer to the lower pattern memory layer, the second upper barrier pattern, stored in the upper and / or supplementary pattern memory layers, can be used as an etching mask. In either case, a trench interruption can be formed in a second lower trench located below the second upper barrier and thus defined by the second upper barrier.

[0024] The first and second lower pattern memory layer portions may be referred to as the first and second lower barriers or barrier portions, respectively, although they may form continuous portions of the patterned lower pattern memory layer rather than forming discrete material barriers as the first and second upper barriers do.

[0025] The method of the present invention can provide the above-mentioned advantages, combined with the margin for improvement of EPE that allows for reduced sensitivity to process variability, especially during the patterning of the second lower trench.

[0026] According to some embodiments, improved margins can be facilitated at least in part by forming a first upper barrier and also memorizing the first upper barrier as a corresponding lower pattern memory layer portion / first lower barrier portion. Therefore, during the second lower trench patterning, the first lower pattern memory layer portion can be masked by the first upper barrier. The first upper barrier (which, according to some embodiments, may be a monochromatic or duochromatic barrier) can thus provide masking for the first lower barrier portion during the second lower trench patterning. Therefore, even if the auxiliary trenches in the auxiliary trench mask stack extend above / overlap with the first lower barrier portion, the first upper barrier can offset the etching of the first lower barrier. Therefore, after the second lower trench is formed, trench interruptions of the first lower trench, which are memorized as the first lower barrier portion, can also be retained.

[0027] Furthermore, according to this method, interval lines may exist during the patterning of the first and second lower trenches.

[0028] The presence of the spacer line ensures a minimum separation distance between the first and second lower trenches. Therefore, if an auxiliary trench in the auxiliary trench mask stack (by design or due to EPE) extends above or overlaps the first lower trench, the spacer line portion extending along the exposed first lower trench can mask the lower memory layer portion below the spacer line portion (and thus counteract the etching of that lower memory layer portion). Thus, the second lower trench can be etched in the lower patterned memory layer via the overlapping auxiliary trenches, while the spacer line portion ensures that the first and second lower trenches are separated by the masked lower memory layer portion, for example, having a width determined by the linewidth of the spacer line.

[0029] The method may include removing the auxiliary trench mask stack, the upper memory layer, and the remaining portion of the spacers after the second lower trench patterning. It may also remove the first and second upper barriers (if they still exist) and supplement the upper barrier (if it exists).

[0030] As can be understood from the above discussion, the lower and upper pattern memory layers form separate layers, each formed of a corresponding material. Therefore, the material of the lower pattern memory layer (“lower layer material”) and the material of the upper pattern memory layer (“upper layer material”) may differ. For example, the lower layer material may be a dielectric material, such as an oxide, nitride, or carbide. The upper layer material may be amorphous silicon (aSi).

[0031] The first and second upper barriers can form corresponding patterns / groups of blocky material bodies (barrier materials) that are different from the layers in the lower and upper pattern memory layers. The first and second upper barriers can be formed of the same or different materials. The barrier material can be a metallic material, such as a metal nitride, metal carbide, or metal oxide.

[0032] The spacer lines can advantageously be formed of a material different from each of the upper, lower, and barrier materials (“spacer materials”). Spacer lines can be formed of typical spacer materials, such as oxides or nitrides deposited by atomic layer deposition (ALD).

[0033] Spacer lines can be formed using a sidewall spacer formation process. Forming spacer lines may include etching back a conformally deposited spacer layer. For example, the spacer layer may be conformally deposited (e.g., by ALD) on a patterned upper memory layer and cover the sidewalls and bottom surface of the upper trench. The spacer layer may then undergo etching back (i.e., by, for example, vertical bias dry etching, from top to bottom) such that the corresponding bottom surface of the upper trench is exposed (again) and the spacer layer portion remains on the upper trench sidewall to form the spacer line. The spacer formation process allows for reliable formation of spacer lines with uniform linewidth / thickness, thereby helping to reduce process variability.

[0034] As described above, the first and second upper barriers can be formed using a hue inversion method:

[0035] The pattern forming the (first / second upper) barrier may include forming a (first / second) auxiliary barrier mask layer and a block opening therein, and depositing a barrier material in the block opening, wherein the barrier material deposited in the block opening forms the (first / second upper) barrier.

[0036] The barrier material can be deposited on the auxiliary barrier mask layer and in the barrier opening, and then etched back to expose the auxiliary barrier mask layer, wherein the remaining barrier material in the barrier opening forms a (first / second upper) barrier.

[0037] The barrier material can be conformally deposited, causing the barrier material deposited on the sidewalls of the barrier opening to merge with the barrier opening (thus closing / compressing the barrier opening). The barrier material can be etched back (from top to bottom), causing the barrier material deposited outside the barrier opening to be removed and the barrier material remaining in the barrier opening to form a first / second upper barrier. Conformal deposition may help fill small CD barrier openings.

[0038] In either case, the first / second barrier can be formed from a single deposited barrier material, thus being a "single-toned" barrier.

[0039] Before forming the upper pattern memory layer, a first auxiliary barrier mask layer may be formed on the lower pattern memory layer. Before forming the upper pattern memory layer, the first auxiliary barrier mask layer may be selectively removed relative to the barrier material in the barrier opening. Alternatively, according to an alternative method, the upper pattern memory layer may be formed on both the barrier material in the barrier opening and the first auxiliary barrier mask layer.

[0040] A second auxiliary barrier mask layer can be formed on the upper pattern memory layer. Before patterning the upper trench in the upper pattern memory layer, the second auxiliary barrier mask layer can be selectively removed relative to the barrier material in the barrier opening. Alternatively, according to an alternative method, the upper trench can be patterned using the remaining second auxiliary barrier mask layer on the upper pattern memory layer. Therefore, the upper trench can be patterned to extend through the second auxiliary barrier mask layer and further into the upper pattern memory layer.

[0041] According to one variant, tone inversion can be combined with patterning of blocking features:

[0042] The patterning of the first upper barrier may include: forming a (first / second) barrier material layer and a (first / second) auxiliary barrier mask layer, forming a barrier opening in the (first / second) auxiliary barrier mask layer, depositing auxiliary barrier material in the barrier opening; selectively removing the auxiliary barrier mask layer relative to the auxiliary barrier material; and subsequently, using the remaining auxiliary barrier material as an etching mask, patterning the barrier material layer.

[0043] The remaining auxiliary barrier material can form an auxiliary barrier. The first / second upper barrier can be defined as a "two-tone" barrier formed by the auxiliary barrier and a portion of the remaining barrier material layer retained below the auxiliary barrier. This can give the upper barrier an increased etching budget. However, the auxiliary barrier can be removed during subsequent process steps or directly after the barrier material layer is patterned, wherein the upper barrier can be formed solely by the portion of the remaining barrier material layer.

[0044] An auxiliary barrier material can be selectively deposited on the bottom surface of the auxiliary barrier opening to form an auxiliary barrier. A portion of the barrier material layer surface in the auxiliary barrier opening can serve as a seeding surface during selective deposition. The auxiliary barrier material can be a metal. A metal nitride barrier material layer can facilitate seeding. Another exemplary auxiliary barrier material is a metal oxide.

[0045] Before forming the upper pattern memory layer, a first barrier material layer and an auxiliary barrier mask layer can be formed on the lower pattern memory layer. A second barrier material layer and an auxiliary barrier mask layer can be formed on the upper pattern memory layer.

[0046] In any of the above methods, forming the blocking opening in the (first / second) auxiliary blocking mask layer may include photolithography and etching.

[0047] Optionally, the photolithography and etching steps may be supplemented by a “shrink” step to form a CD-reduced barrier opening, wherein the initial barrier opening may first be formed in the (first / second) auxiliary barrier mask layer using photolithography and etching, and then the (final) barrier opening may be formed by depositing an inner liner layer in accordance with the sidewalls of the initial barrier opening.

[0048] The liner can be conformally deposited. The (conformal) liner can be etched back (e.g., anisotropically etched in a top-down direction) to remove the bottom surface of the liner portion (horizontally oriented) that blocks the opening, thereby leaving the liner portion on the (vertically oriented) sidewall of the initial blocking opening unchanged.

[0049] Upper trench patterning may include forming an upper auxiliary trench mask stack on an upper pattern memory layer, wherein patterning the auxiliary upper trench includes using photolithography and etching to etch the auxiliary upper trench into the upper pattern memory layer. Therefore, an upper trench consistent with the auxiliary upper trench can be formed in the upper pattern memory layer.

[0050] According to some embodiments, at least one subset of the second upper barrier can be formed such that corresponding portions protrude into the region where the auxiliary upper trench will be formed. In other words, each corresponding portion can protrude into a (corresponding) region of the lower pattern memory layer in which a portion of the first lower trench will be formed. The corresponding portion of the second barrier can be exposed to the auxiliary upper trench. The method may further include etching away (i.e., removing by etching) the (protruding / exposed) corresponding portion from the auxiliary upper trench. As discussed above, this allows the ends of the second upper barrier to self-align relative to the upper trench, and thus self-align relative to the first lower trench. The “etch-away” step can advantageously be performed before etching the auxiliary trench into the upper pattern memory layer.

[0051] According to some embodiments, a supplementary pattern memory layer can be formed between the upper pattern memory layer and the second upper barrier. The method may further include using the supplementary pattern memory layer as an etch stop layer when the corresponding portion is etched away from the auxiliary upper trench. Therefore, when the exposed portion of the second upper barrier is etched away, the patterning of the upper trench can be facilitated by avoiding the introduction of thickness variations within the layer. Furthermore, the etch budget of the lower layer can thus be preserved. The supplementary pattern memory layer can be formed on the upper surface of the upper pattern memory layer, where the lower layer can be formed accordingly.

[0052] According to some embodiments, at least a subset of the second lower trenches may be formed alternately with at least a subset of the first lower trenches. That is, in these subsets of trenches, a second lower trench may be formed between a pair of first lower trenches, and vice versa. Thus, alternating first and second lower trenches can form a trench pattern with decreasing spacing.

[0053] According to some embodiments, at least one of the auxiliary trenches in the auxiliary trench mask stack can extend over the patterned lower pattern memory layer in which a second lower trench will be formed, and over an adjacent first lower trench, wherein the second lower trench is spaced apart from the adjacent first lower trench by a portion of the lower pattern memory layer retained on a spacer line. Therefore, the auxiliary trench can extend into / cover the region above the region where the second lower trench will be formed, and additionally extend into / cover the region above / cover the region of the already formed adjacent first lower trench. Thus, the second lower trench can be etched into the (patterned) lower pattern memory layer via a widened auxiliary trench opening in the auxiliary trench mask stack. The presence of the spacer line ensures a minimum separation distance between adjacent first and second lower trenches.

[0054] The at least one auxiliary trench may further extend (enter the region) above / cover the following components: a first upper barrier and a lower pattern memory layer portion / first lower barrier portion along the first lower trench below the first upper barrier. However, since the first upper barrier is present above the first lower barrier portion, the lower memory layer can still be etched via the auxiliary trench opening without etching the earlier memory trench interruption of the first lower trench (i.e., the first lower barrier portion therein).

[0055] According to an embodiment in which a supplementary pattern memory layer is formed between an upper pattern memory layer and a second barrier, the method may further include: patterning the supplementary auxiliary pattern memory layer to form a supplementary upper barrier pattern consistent with the pattern of the second upper barrier before forming the auxiliary trench mask stack, said patterning including using the second upper barrier as an etch mask. The advantages associated with the supplementary pattern memory layer have been discussed above. The supplementary pattern memory layer further ensures that even if the second upper barrier is removed / consumed during the method process, the pattern of the second upper barrier remains memorized (i.e., as a consistent pattern with the supplementary upper barrier).

[0056] The lower pattern memory layer and the supplementary pattern memory layer can be formed as layers with similar etching properties, such that the pattern of the second upper barrier can be transferred to the supplementary pattern memory layer while the upper trenches providing the spacing are etched into the lower pattern memory layer. This makes it possible to pattern the supplementary pattern memory layer without any additional etching steps.

[0057] According to an embodiment, the method may further include: patterning the (patterned) upper memory layer before forming the auxiliary trench mask stack to form a pattern of the upper patterned memory layer portion that conforms to the pattern of the second upper barrier. Patterning may include using the second upper barrier as an etch mask.

[0058] Therefore, the upper memory layer can be removed from the "non-blocking" area, thereby reducing the amount of upper memory layer material that needs to be removed after the first and second lower trenches are patterned.

[0059] The second lower pattern memory layer can be formed below the upper pattern memory layer.

[0060] The upper pattern memory layer portion (which may be referred to as the "third upper blocking portion") may be used together with the second upper blocking and / or supplementary upper blocking as a combined blocking etch mask for the lower pattern memory layer during the second lower trench patterning.

[0061] The first upper barrier can be formed with a greater thickness than the second upper barrier. After patterning the upper pattern memory layer portion and before forming the auxiliary trench mask stack, the method may further include: removing the second upper barrier such that at least a thickness portion of the first upper barrier remains unchanged after removal of the second upper barrier. The remaining (thickness portion) of the first upper barrier can subsequently mask the first lower pattern memory layer portion during the second lower trench patterning, more specifically during the etching of the second lower trench in the lower pattern memory layer. This is feasible even if the first and second upper barriers contain the same material or materials with similar etching properties. Therefore, as discussed above, even if the auxiliary trench in the auxiliary trench mask stack extends over / overlaps with the first lower barrier portion, the first upper barrier can still counteract the etching of the first lower barrier portion. Removing the second upper barrier allows for the prevention of the remaining portion of the second upper barrier from falling into the lower layer during subsequent process steps involving the removal of the underlying material.

[0062] Alternatively, the step of patterning the third upper blocking portion in the patterned upper memory layer can be omitted before forming the auxiliary trench mask stack. According to an alternative embodiment, the auxiliary trench mask stack can instead be formed on the upper patterned memory layer, wherein spaced upper trench patterning is provided. Then, patterning the second lower trench in the lower patterned memory layer may include: etching back the upper surface portion of the patterned upper patterned memory layer exposed in the auxiliary trench, followed by etching back the upper surface portion of the lower patterned memory layer exposed in the auxiliary trench.

[0063] During the etch-back of the patterned upper pattern memory layer, a second upper barrier and / or a supplementary upper barrier can be used as an etch mask. Therefore, the pattern of the upper pattern memory layer portion can be retained at the location defined by the second / supplementary upper barrier. A second lower pattern memory layer portion can be formed beneath the upper pattern memory layer portion.

[0064] According to some implementations, a lower pattern memory layer may be formed on a target layer, and the method may further include: patterning the target layer using a patterned lower pattern memory layer, wherein the target pattern layer is one of a hard mask layer, a dielectric layer, or a metal layer.

[0065] The "first target trench" and the "second target trench" can therefore be formed below the first lower trench and the second lower trench, respectively.

[0066] The first and second target trenches can be patterned simultaneously in the underlying layer. Alternatively, the first and second target trenches can be patterned sequentially. That is, in the target layer, the first target trench can be patterned before the second target trench. This method also allows for a reduction in the number of times the layer beneath the target layer (such as an insulating layer) is exposed to the etchant.

[0067] The above method can be advantageously combined with methods for forming interconnect structures. Therefore, in one aspect, the method for forming an interconnect structure may include:

[0068] According to the above method or any implementation or variation thereof, a lower pattern memory layer is formed on the insulating layer, and first and second lower trenches are formed therein;

[0069] After forming the first and second lower trenches in the lower pattern memory layer, the target trenches are patterned in the insulating layer using the lower pattern memory layer (e.g., as an etch mask); and

[0070] Conductive material is deposited in trenches within the insulating layer.

[0071] The first and second target trenches, which correspond to the first and second lower trenches respectively, can therefore be formed in the insulating layer.

[0072] The method may further include: after patterning a first lower trench in the lower pattern memory layer and before forming an auxiliary trench mask stack, using photolithography and etching to form a (first) via etch (mask) stack, and forming a (first) via opening through the via etch stack that exposes the bottom surface of the selected first lower trench in the lower pattern memory layer. The method may further include: etching the exposed bottom surface to form an opening in the target memory layer. The method may further include: etching an insulating layer through the (first) via opening to form a (first) via in the insulating layer.

[0073] Thus, a (first) via can be formed in the insulating layer. The via can be self-aligned with a selected first lower trench in the lower pattern memory layer due to this patterning method, and therefore also with a selected first target trench in the insulating layer below the selected first lower trench.

[0074] Via openings can be formed above or overlapping the selected first lower trench. The via openings can expose spacer layer portions on the opposite side of the selected first lower trench. The opening width in the via-hole etch stack can exceed the width of the selected first lower trench (i.e., a relaxed CD relative to the width of the selected first lower trench). This allows for loose printing of the openings within the via-hole etch stack.

[0075] The via etching (mask) stack may include filling an upper trench and a first lower trench that provide spacing, wherein forming the via opening may include selectively etching the mask material onto the spacer lines (i.e., etching at a rate greater than the "spacer material"). This allows the via opening to self-align relative to the spacer lines. Furthermore, the retained spacer line portions may increase etch margin as the via opening further transitions into the lower layer.

[0076] The method may further include: after patterning a first lower trench in the lower pattern memory layer and before forming an auxiliary trench mask stack, using photolithography and etching to form a (second) via-hole etch (mask) stack, and forming a (second) via opening through the via-hole etch stack, the upper memory layer, and the lower pattern memory layer. The method may further include: etching an insulating layer through the (second) via opening to form a (second) via in the insulating layer.

[0077] Thus, a (second) via can be formed in the insulating layer. The via opening can be self-aligned with the selected second lower trench in the target memory layer due to this patterning method, and therefore also with the selected second target trench in the insulating layer below the selected second lower trench.

[0078] (Second) The via openings in the via etch (mask) stack can be formed at a location between a pair of upper trenches. The width of the opening in the via etch stack can exceed the spacing between the pair of upper trenches. This allows for loose printing of the openings in the via etch stack.

[0079] The upper memory layer can be selectively etched to the spacers (i.e., the "upper material" is etched at a rate greater than the "spacer material"). This allows the via openings to self-align relative to the spacers. Furthermore, the retained spacer portions increase etch margin as the via openings are further transferred into the lower layer.

[0080] The method may include depositing a conductive material to fill first and second target trenches in an insulating layer and first and second vias in the insulating layer. Attached Figure Description

[0081] The above and other objects, features, and advantages of the invention will be better understood from the following illustrative and non-limiting detailed description with reference to the accompanying drawings. In the drawings, similar reference numerals will be used for similar elements unless otherwise stated.

[0082] Figure 1-19 The process flow of the patterning method is explained.

[0083] Figure 20-23 The method for forming the first barrier is explained.

[0084] Figure 24-27 The second method of barrier formation was explained. Detailed Implementation

[0085] Now refer to Figure 1-19 A method for patterning trenches is described. The method includes forming a trench pattern in a lower pattern memory layer 14. The trench pattern can be transferred to a lower hard mask layer 12, as described below, which can then be used to pattern trenches in an insulating layer 10. In the illustrated method, the hard mask layer 12 is therefore the bottommost or target pattern memory layer 12, which can be used to pattern the (final) target trenches in the insulating layer 10 (thus representing the final target layer). The trenches in the insulating layer 10 can be filled with a conductive material, such as a metal, to form conductive lines of an interconnect level of an interconnect structure, for example, in a back-end-of-line (BEOL) process. However, it will be noted that this method has a more general applicability to patterning trenches in any layer. For example, the layer 12 to be patterned can be a semiconductor layer or a metal layer. This method is also compatible with tone inversion methods, where trenches in the lower pattern memory layer 14 can be etched into a target pattern memory layer (e.g., a hard mask layer similar to the hard mask layer 12). The trenches in the target pattern memory layer can be filled with a gap-filling material to form line features of the gap-filling material (e.g., oxide, a-Si, or SoC). The target pattern memory layer can then be selectively removed relative to the line features. The line features can, in turn, be used as an etch mask during the etching of another underlying target layer (e.g., a metal layer, semiconductor layer, or dielectric layer) to form line features in said underlying layer.

[0086] refer to Figure 1 The diagram shows a portion of a structure that will undergo the processing steps of this patterning method, in perspective. This structure may extend laterally or horizontally beyond the shown portion. Unless otherwise specified, the extension of this portion through the shown plane of the structure is common throughout all the figures. Note that the relative dimensions of the elements shown, especially the relative thicknesses of the layers, are merely schematic and may differ from the physical structure for purposes of clarity. Figure 1In this context, directions X and Y indicate the first and second horizontal directions, respectively, parallel to the in-plane directions (i.e., the main extension planes and main surfaces of each layer). Direction Z indicates the vertical direction, or equivalent to the bottom-up direction or the layer stacking direction, thus perpendicular to the main extension planes and main surfaces of each layer. As can be understood, terms such as “above,” “above,” “below,” “upper,” “under,” “below,” etc., should be understood as relative positions viewed along the vertical direction. The “width” of a trench or the “line width” of a feature should be understood as a dimension along the second horizontal direction Y. For example, the “longitudinal” or “length” dimension of a trench should be understood as a dimension along the first horizontal direction X.

[0087] Figure 1 A layer stack is depicted, comprising a hard mask layer 12 and a lower pattern memory layer 14 in the top direction. The lower pattern memory layer 14 may be shown as being formed on the hard mask layer 12. However, it is contemplated that an interface layer, such as an adhesive layer, is provided between layers 12 and 14. If an interface layer is present, it may be patterned in the same steps as layer 14 or in the same steps as layer 12.

[0088] The hard mask layer 12 is formed of a hard mask material, such as a metallic material, such as a metal nitride, metal carbide, or metal oxide, for example, TiN, W. x C y Al X O y Or Al x N y The lower pattern memory layer 14 can be a dielectric material layer, such as an oxide, nitride, or carbide, for example, SiO2, SiCO, SiC, SiN, or SiCN. For example, layers 12 and 14 can be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD).

[0089] As used herein, the term "pattern memory layer" refers to a layer (e.g., a hard mask layer) that can be patterned to "memorize" or "store" one or more portions of a "target" pattern that can be further transferred to lower layers. For the sake of brevity, the term "memory layer" may be used below.

[0090] like Figure 1 As further shown, the layer stack can be formed on the insulating layer 10. The insulating layer 10 can be an oxide material, such as SiO2, or another conventional low-k dielectric. One or more interface layers 11 (e.g., interface layers and / or oxide capping layers) may optionally be present between the target memory layer 12 and the insulating layer 10.

[0091] The insulating layer 10 may be formed on the substrate 1, such as a semiconductor substrate. An active device layer including a semiconductor device (such as a transistor) may be fabricated on the main surface of the substrate 1. The active device layer may also be referred to as the front-end process portion (FEOL portion). The insulating layer 10 may be formed on (not shown) a conductive structure (such as conductive lines of a lower interconnect layer) or on a contact structure for a device (such as source / drain or gate contacts of a semiconductor device), as known in the art.

[0092] Figure 2-3 The diagram illustrates how a pattern for a first upper barrier 16 is formed on a lower pattern memory layer 14, followed by the formation of an upper pattern memory layer 18, and subsequently, the formation of a pattern for a second upper barrier 22. The upper pattern memory layer 18 is used to memorize a set of upper trenches, as described below.

[0093] A first upper barrier 16 is formed on the lower memory layer 14. An upper memory layer 18 is formed on the lower memory layer 14 and the first upper barrier 16. The upper memory layer 18 thus covers the lower memory layer 14 and the first upper barrier 16. A second upper barrier 22 is formed on the upper memory layer 18.

[0094] The upper memory layer 18 can be, for example, an a-Si layer, such as an a-Si layer deposited by CVD, ALD, or PVD. Figure 3 In this context, the upper memory layer 18 is depicted with a planar upper surface. However, it should be noted that due to the presence of the first upper barrier 16, the upper surface of the upper memory layer 20 may exhibit a (slightly) varied morphology. If such a morphological variation is not required, the upper surface can be planarized, for example, by CMP, before subsequent processing steps.

[0095] As shown in the figure, a supplementary pattern memory layer 20 may also be formed between the upper pattern memory layer 18 and the second upper barrier 22. The supplementary memory layer 20 may be formed on the upper memory layer 18, wherein the second upper barrier 22 may be formed on the supplementary memory layer 20. In the following, it will be assumed that layers 14 and 20 are formed as layers with similar etching properties, for example, by being formed from the same material (e.g., SiN). However, layer 20 may also be a different material, for example, any material selected in conjunction with the lower memory layer 14. The function of the supplementary memory layer 20 will become clear from the further description below. However, it should be noted that the supplementary pattern memory layer 20 is optional, and if it is not present, the second barrier 22 may be formed on the upper memory layer 18 (i.e., directly on the upper memory layer 18).

[0096] The respective patterns of the first and second upper barriers 16, 22 allow for the formation of interrupted first and second lower trenches. Thus, each of the first / second upper barriers 16 / 22 is formed at a position overlapping with a corresponding portion of the lower memory layer 16, which will define a trench interruption between two aligned trench segments of the first / second lower trench to be formed (i.e., define the "tip-to-tip" position of the trench segment).

[0097] The critical dimension (CD) of the barrier 16 / 22 can refer to the dimension of the barrier (or the corresponding barrier opening 104 / 204, see below) along the X direction. Therefore, the CD of the barrier defines the dimension of the corresponding groove interruption or the separation between the tips.

[0098] The first and second upper barriers 16 and 22 can be formed using a color inversion method. (Refer to...) Figure 20-23 Describe the first scheme for forming a barrier. (Refer to...) Figure 24-27 A second scheme for forming a barrier is described. Although the first and second schemes will be disclosed with reference to the first upper barrier 16 and the second upper barrier 22 respectively, it should be understood that both schemes are applicable to forming the first or second upper barriers 16, 22.

[0099] exist Figure 20 In this structure, an auxiliary blocking mask layer 102 is formed on the lower memory layer 14. The pattern of the blocking opening 104 is formed in the auxiliary blocking mask layer 102. Figure 21 In this process, barrier material 106 is deposited on the auxiliary barrier mask layer 102 and in the barrier opening 104. Figure 22 In the process, the barrier material 106 is etched back to expose the auxiliary barrier mask layer 102, so that a portion of the barrier material remains in the barrier opening to form the first upper barrier 16.

[0100] The blocking opening 104 can be formed using photolithography and etching. For example, a mask stack including a photoresist layer as the uppermost layer is formed on an auxiliary blocking mask layer 102. The pattern of the opening can be defined photolithographically in the photoresist layer, and the opening can be etched into the mask stack and then into the auxiliary blocking mask layer 102. The opening thus transferred in the auxiliary blocking mask layer 102 can define the pattern of the blocking opening 104. A suitable wet etching process or dry etching process, such as RIE, can be used.

[0101] Optionally, the transferred opening can be “shrink” to define the (final) pattern of the barrier opening 104 by conformally depositing the auxiliary barrier mask layer 102 and following the liner layer of the (initial) opening sidewalls. Subsequently, an anisotropic etching-back step can be applied to the liner layer exposed to the underlying memory layer 14 in the (CD-shrink) barrier opening 104 (in a top-down direction). The etching-back can include a dry etching process, such as RIE.

[0102] For example, the auxiliary barrier mask layer 102 can be an oxide, such as SiO2; a metallic material, such as a metal nitride or metal oxide, such as TiN, AlxNy, AlXOy-TiOx, or ZrOx; or a nitride or carbide (e.g., SiCO or SiN). Suitable conventional deposition processes, such as CVD, ALD, or PVD, can be used. An (optional) liner layer can be formed of the same material as layer 102 and deposited via ALD. The barrier material can be deposited conformally (e.g., via ALD) or non-conformally (e.g., via CVD or PVD). For example, the barrier material can be a metal nitride or metal oxide, such as TiN, AlxNy, AlXOy-TiOx, or ZrOx; or a nitride or carbide, such as SiCO or SiN, but in any case, it must differ from the material of the auxiliary barrier mask layer 102 and the material of the underlying memory layer 14 to achieve etch selectivity.

[0103] The auxiliary blocking mask layer 102 can be removed after the formation of the first upper blocking layer 16, as shown in the figure. However, the auxiliary blocking mask layer 102 can also remain on top of the lower memory layer 14, wherein the upper memory layer 18 can be formed on both the auxiliary blocking mask layer 102 and the first upper blocking layer 16. As will be understood, the auxiliary blocking mask layers 102 each need to be opened subsequently, for example, before etching the lower memory layer 14, but this method can be performed in another manner as described herein.

[0104] According to the second barrier formation method, a barrier material layer 201 and an auxiliary barrier mask layer 202 are formed on the upper memory layer 18. The auxiliary barrier mask layer 202 can be formed on top of the barrier material layer 201, as shown in the figure. In the illustrated embodiment, the barrier material layer 201 is formed on the supplementary memory layer 20. However, if layer 20 is not formed, the barrier material layer 201 can also be formed on the upper memory layer 18.

[0105] The pattern of the auxiliary blocking opening 204 is formed in the auxiliary blocking mask layer 202. Figure 25 In this process, auxiliary barrier material 208 is selectively deposited in the barrier opening 204. Figure 26 In this process, the auxiliary barrier mask layer 202 is selectively removed relative to the auxiliary barrier material 208, while the auxiliary barrier material 208 is retained to form the auxiliary barrier 208. Figure 27 In this process, an auxiliary barrier 208 is used as an etching mask to pattern the barrier material layer 201, such that a portion 201a of the barrier material layer 201 remains below the auxiliary barrier 208. A dry etching process, such as RIE, can be used.

[0106] The auxiliary barrier mask layer 202 and the barrier opening 204 can each be formed using a technique similar to that described above for layers / openings 102 / 104. Optionally, a shrinkage step as described above can be performed to form a CD-reduced barrier opening 204. The material examples listed for layer 102 and the inner liner layer are also applicable to the second scheme.

[0107] The auxiliary barrier material 208 can be selectively deposited on the bottom surface of the barrier opening 204 formed by the barrier material layer 201, wherein the bottom surface of the barrier material can serve as a seeding surface for the material 208. A metal nitride (e.g., TiN) barrier material layer 201 enables region-selective deposition of the metal auxiliary barrier material 208 (e.g., Ru). However, TiN and Ru represent only one example; other material combinations are possible.

[0108] The deposition of the auxiliary barrier material 208 can continue until an auxiliary barrier 208 of the desired thickness is formed in the barrier opening 204. For example... Figure 25 As shown, deposition can stop before the auxiliary barrier 208 fills the full depth of the barrier opening 204.

[0109] The "two-tone" upper barrier 22 can be formed accordingly by an auxiliary barrier 208 and a retained portion of the remaining barrier material layer 201a, which has an increased etch budget for the upper barrier. However, the auxiliary barrier can be removed during subsequent process steps or directly after the barrier material layer is patterned, wherein the upper barrier can be formed solely by the portion of the remaining barrier material layer 201a.

[0110] After forming the first and second barriers 16, 22, the method continues to pattern the upper trench 28 of the upper memory layer 18 in photolithography and etching processes. Figure 4 In this process, a (first) upper auxiliary trench mask stack 24 is formed on the upper memory layer 18 (e.g., on the supplementary memory layer 20, or on the layer 18 in the absence of layer 20). Figure 4-5 The patterning of the auxiliary upper trench 26 in the mask stack 24 by photolithography and etching is depicted. Figure 6 Shown in such Figure 7 The optional step shown is to remove the protruding portion of the second barrier 22 from the auxiliary upper trench 26 before etching the auxiliary upper trench 26 into the upper pattern memory layer 18. Therefore, an upper trench 28 following the auxiliary upper trench 26 can be formed in the upper pattern memory layer. In other words, an upper trench 28 can be formed below each auxiliary upper trench 26.

[0111] As shown in the figure, the upper groove 28 can extend along the X direction and be formed with various widths (along the Y direction). The upper groove 28 can be formed with various longitudinal dimensions (along the X direction).

[0112] As shown, at least a subset of the upper trench 28 may extend across and expose one or more first upper barriers 16. In turn, each first upper barrier 16 may be formed along the upper trench 22. Thus, the first upper barriers 16 may define a trench interruption along the upper trench 22.

[0113] Refer again Figure 4 The auxiliary trench mask stack 24 may include one or more mask material layers 24a-24d and a resist layer 24e as the top layer. For example, the mask material layer may include a patterned layer 24a, one or more anti-reflective coatings (e.g., SiOC layers and / or spin-coated glass layers 24b, 24d) and an organic spin-coated material (e.g., SOC layer 24c).

[0114] The auxiliary trench 26 can first be formed in the resist layer 24e by photolithography, and then transferred downwards into the stack 24 by etching. One or more layers of the stack 24 can be consumed during the transfer process, depending on its composition and the etching chemicals used, such as... Figure 6 As shown, only a subset of the original layers (e.g., layers 24a-c) are retained. However, in any case, the auxiliary trench mask stack 24 should be maintained to a certain extent so that it can be used as an etching mask for patterning the upper trench 28.

[0115] Subsequently, the upper trench 28 can be formed by etching the upper memory layer 18 through the auxiliary trench 26 using the auxiliary trench mask stack 24 as an etching mask. The upper trench 28 can be etched using a suitable etching process, such as dry etching or reactive ion etching (RIE). For example, etching chemicals containing bromine (e.g., HBr), chlorine (e.g., Cl2), or fluorine (e.g., SF6, CF4) can be used to achieve selective "a-Si etching," that is, selective etching of a-Si relative to the auxiliary trench mask stack 24 (e.g., an auxiliary trench mask stack containing organic spin-coating materials, such as SOC layer 24c).

[0116] Before etching the upper memory layer 18, the supplementary memory layer 20 can be opened from the auxiliary trench 26, and then the auxiliary trench 26 can be etched into the upper memory layer 18.

[0117] like Figure 5As shown, corresponding portions of at least a subset of the second upper barrier 22 protrude into the region where the auxiliary upper trench 26 is subsequently formed. Therefore, the method may include etching away the corresponding barrier portions exposed in the auxiliary upper trench 26. This can provide enhanced robustness for the EPE during the formation of the second upper barrier 22. The second upper barrier 22 may be formed such that its lateral dimension (i.e., its length dimension, along the Y direction) exceeds the intended width (i.e., along the Y direction) of the second lower trench 50, defining a trench interruption. Forming such an elongated second upper barrier 22 can facilitate alignment of the second upper barrier 22 with the second lower trench 50 to be formed, for example, preventing the second upper barrier 22 from causing partial interruptions in the second lower trench 50. Simultaneously, the ends of the thus "trimmed" second upper barrier 50 can be self-aligned relative to the auxiliary upper trench 26.

[0118] During this etching step, the supplementary memory layer 20 can be used as an etch stop layer, such as Figure 5 As shown. For example, Cl2-based chemicals can be used to selectively etch the TiN blocking portion relative to the SiN layer. However, if there is sufficient etch contrast between the materials of the upper memory layer 18 and the second upper block 22 to allow removal of the protruding second upper block portion without introducing excessive morphological changes to the upper memory layer 18 within the auxiliary upper trench 26, the second upper block 22 can also be trimmed without the auxiliary memory layer 20.

[0119] Figure 7 The diagram shows the upper memory layer 18, patterned therein with upper trenches 28, after the (remaining portion) of the auxiliary trench mask stack 24 has been removed. For example, removing the auxiliary trench mask stack 24 can include "SOC etching," such as a RIE using oxygen-containing etch chemicals diluted with Ar or He, or N2 / H2-based etch chemicals. As shown, the upper trenches 28 expose a portion of the upper surface of the lower memory layer 14. Each upper trench 28 is formed over the area / part of the hard mask layer 12 (and insulating layer 10) where the first target trench 52 will be formed (see, for example...). Figure 18 The second upper block 22 (which can be modified as described above) is retained on the patterned upper memory layer 18, for example, on the patterned supplementary memory layer 20.

[0120] exist Figure 8 In the middle, the spacing line 30 runs along the sidewall of the upper trench 28, thereby defining a set of upper trenches 28' that provide spacing in the upper memory layer 18, at least a subset of which is interrupted by the corresponding first upper block 16.

[0121] The spacer line 24 can be formed during the sidewall spacer deposition process by anisotropically etching back (from top to bottom) the ALD deposition material layer, which is, for example, an oxide, such as SiO2; or a metal oxide layer, such as AlO2. x or TiO x Or carbides or nitrides, such as SiCO, SiN, AlN, AlON, SiCN. Figure 10 As shown, the spacer line 30 may follow the sidewall of each upper groove 28. In other words, the spacer line 30 may cover the sidewall of the upper groove 28 and extend along the sidewall of the upper groove 28.

[0122] exist Figure 9 In the lower memory layer 14, a pattern has been created to form a first lower trench 32 therein. The patterning may include etching an upper trench 28' that provides spacing into the lower memory layer 14. In other words, the lower memory layer 14 may be etched, while the spacer line 24, the first upper barrier 19, and the patterned upper memory layer 20 act as an etching mask.

[0123] Therefore, at least one subset of the first lower trench 32 can be interrupted along its length by the lower memory layer portion 14a (“first lower blocking portion”) below the corresponding first upper blocking portion 16.

[0124] After the lower memory layer 14 is patterned, the first upper barrier 16 and the upper groove 28' providing the spacing lines are thus "memorized" in the patterned lower memory layer 14.

[0125] Patterning of the lower memory layer 14 may include an etching process (e.g., a dry etching process) that allows selective etching of the lower memory layer 14 relative to the upper memory layer 20, the spacer 30, and the first upper barrier 16. For example, the RIE contains, for instance, fluorine-based chemicals (e.g., CHF3, CH3F, C4F8, CF4, CH2F2), optionally using continuous wave plasma, plasma pulse, or cyclic processes (e.g., quasi-atomic layer etching), which can be used to achieve selective “SiN etching” relative to TiN, a-Si, and oxides (e.g., silicon oxide) or metal oxides (e.g., SiO2 or TiO2). x Each selective etching of SiN in ))

[0126] like Figure 9As shown, while etching the first lower trench 32 into the lower memory layer 14, the supplementary pattern memory layer 20 is etched using the second upper barrier 22 as an etching mask. Thus, a supplementary upper barrier 20a pattern is formed that conforms to the pattern of the second upper barrier 22. Each supplementary upper barrier 20a is formed from a portion of the supplementary pattern memory layer 20 retained beneath the corresponding second upper barrier 22. Simultaneous etching of layers 14 and 20 is achieved through their similar etching properties. If layers 14 and 20 are instead formed of different materials, layers 14 and 20 can be etched sequentially, for example, first the supplementary pattern memory layer 20, then the lower memory layer 14.

[0127] In the method shown, after the supplementary upper barrier 20a is formed, the second upper barrier 22 remains on the supplementary upper barrier 20a. However, this is merely an example, and other options are possible, such as after the formation of the supplementary upper barrier 20a, or after the formation of the third upper barrier portion 18a (see [link to example]). Figure 14 After the second lower trench 50 is formed or after the second target trench 54 is formed, the second upper barrier 22 is removed.

[0128] Figure 10 and 10A The process of forming a (first) via for patterning a (first) via opening is shown, the via opening being aligned with a first set of lower grooves 32 and correspondingly aligned with a first target groove 52. Figure 11 and 11A The process of forming a (second) via for patterning a (second) via is shown, which is aligned with a second set of lower trenches 50 and correspondingly aligned with a second target trench 54. Figure 10 and Figure 11 The formation of a single via and two vias are shown respectively; however, as will be understood, any number of vias can be formed accordingly. If the formation of the first and / or second via is not required, the relevant steps can be omitted. The method can then proceed to... Figure 12 The stage shown.

[0129] Figure 10A show Figure 10A cross-section along line A-A' of the structure. A (first) via-hole etch stack 34 has been formed on this structure. The via-hole etch stack 34 may include one or more layers of mask material, such as a planarization layer 34a covering the patterned upper memory layer 20 and supplementing and / or second upper barriers 20a, 22. The planarization layer mask material may include SOC or some other conventional organic spin-coated layer. The via-hole etch stack 34 may further include a resist layer 34b as the top layer. Although not shown, the via-hole etch stack 34 may include additional mask materials, such as one or more anti-reflective coatings (e.g., SiOC layers) and / or spin-coated glass layers.

[0130] An opening 36 can be formed in the via etch stack 34 by photolithography and etching. This opening can be formed above a "selected" first lower trench 36 at a location overlapping the area of ​​the insulating layer 10 where the via is required. The opening 36 can be etched through the via etch stack 34 to expose, for example, the bottom surface of the selected first lower trench 26 formed by the hard mask layer 12.

[0131] like Figure 10A As shown, the bottom surface can then be etched back (from top to bottom) to extend the opening 36 into the hard mask layer 12. A via 37 can then be formed in the insulating layer 10 (and any interface layer 11, if present) by etching layers 10 / 11 through the opening 36. After forming the via 37, the via etch stack 34 can be removed.

[0132] like Figure 10A As shown, the opening 36 can be defined with a relaxed CD relative to the selected first lower trench 32, and the resist layer 34b is used as an etching mask to transfer it into the stack 34 while the mask material 34a is selectively etched to the spacer line 30. As shown, the CD of the opening 36 in the resist layer 34b can be further relaxed by selectively etching the mask material 34a to the upper memory layer 18, also partially overlapping with the upper memory layer 18. For example, as discussed above, organic spin-coating materials (such as SOC) can be etched at a higher rate than oxide spacers and a-Si etched using SOC. Similarly, the hard mask layer 12 can be opened by selectively etching the hard mask material to the spacer line 30 and optionally the upper memory layer 14. For example, the TiN hard mask layer 12 can be opened using Cl2 / CH4 / Ar chemicals or Cl2 / HBr chemicals. Figure 10A The amount of back etching of the spacer layer portion 30 exposed in the visible opening 36 is merely an example and may vary depending on the selectivity of the etching process used.

[0133] Figure 11A Showing Figure 11A cross-section along line B-B' of the middle structure. A (second) via-hole etch stack 38 has been formed on this structure. The via-hole etch stack 38 can typically have the same composition as the (first) via-hole stack 34, and thus includes a planarization layer of masking material 38a (e.g., SOC) and a topmost resist layer 38b. Via openings 40 can be formed in the via-hole etch stack 38 similarly using photolithography and etching. However, the second via formation process differs from the first via formation process in that the via opening 40 is defined at a location between a pair of spaced upper trenches 28', thus overlapping with a portion of the lower memory layer 14 where the second lower trench 50 will be formed. Therefore, the via opening 40 also needs to be transferred through the upper memory layer 18 (e.g., using selective "a-Si etching") and the lower memory layer 14 (e.g., using selective "SiN etching") before etching the vias 39 in the insulating layer 10. After the via 39 is formed, the via etch stack 38 can be removed.

[0134] Figure 12 The structure is shown after the first and second via formation processes are completed. The depth of vias 37 and / or 39 may be only the initial depth at this stage and may be deepened at later stages, such as during the etching of trenches in the insulating layer 10.

[0135] The method continues by patterning the second lower trench 50 in the lower memory layer 14. Patterning includes multiple processing steps, as referenced... Figure 13-17 As shown.

[0136] exist Figure 13 In this process, the upper memory layer 18 is further patterned to form an upper memory layer portion 18a (“third upper blocking portion”) pattern conforming to the pattern of the second upper blocking 22. Patterning may include etching the upper memory layer 18 using the second upper blocking 22 as an etch mask (e.g., using selective “a-Si etching”). Therefore, the upper memory layer 18 can be removed from the “non-blocking” area while leaving the third upper blocking portion 18a below the second upper blocking 22.

[0137] exist Figure 14 In this process, the second upper barrier 22 is removed by etching. This optional step allows for the prevention of any remaining portion of the second upper barrier 22 from falling into the lower layer during subsequent process steps involving the removal of the underlying material (e.g., the removal of the third upper barrier 18a, as described below).

[0138] As can be understood, however, removing the second upper barrier 22 can result in the simultaneous etching of the first upper barrier 16. If the first and second upper barriers 16, 22 are formed of materials with similar etching properties (e.g., the same material), this could reduce the mask budget for the first upper barrier 16. However, forming the first upper barrier 16 with a thickness greater than the second upper barrier 22 allows the removal of the second upper barrier 22, such that at least a thick portion of the first upper barrier 16 can be retained, thereby providing masking for the first lower barrier portion 14a during subsequent patterning of the lower memory layer 14.

[0139] exist Figure 15 In this configuration, a (second) auxiliary trench mask stack 46 is formed on the lower memory layer 14, the spacer line 30, and the third upper blocking portion 18a. The auxiliary trench mask stack 46 may include one or more layers of mask material covering the lower memory layer 14 and the third upper blocking portion 18a. As shown, the stack 46 may include a planarization layer 46a of the mask material, such as an organic spin-coating material like SOC. The stack 46 may include a topmost photoresist layer 46c. The stack 46 may include one or more additional layers 46b, such as one or more anti-reflective coatings, for example, a SiOC layer, and / or a spin-coated glass layer.

[0140] The trenches 48 in the photoresist layer 48c can be defined using photolithography, and then as follows: Figure 16 As shown, for example, the trench 48 is further etched into the lower layer of the stack 46 by a planarization layer 46a, thereby patterning the auxiliary trench 48 in the auxiliary trench mask stack 46.

[0141] As shown in the figure, the auxiliary groove 48 can extend along the X direction and be formed with various widths (along the Y direction). The auxiliary groove 48 can be formed with various longitudinal dimensions (along the X direction).

[0142] As shown, at least a subset of the auxiliary trench 48 may extend across and expose one or more third upper blocking portions 18a and (if present) supplementary blocking portions 20a on top. In turn, each third upper blocking portion 18a may be formed along the auxiliary trench 48.

[0143] As further shown, at least a subset of the auxiliary trench 48 may be formed with an increased CD (i.e., width) to extend over the portion of the patterned lower pattern memory layer 14 that will form the second lower trench, and to extend over the adjacent first lower trench 32 or over a pair of first lower trenches on either side thereof (e.g., portion 14c). The presence of the spacing line 30 ensures a minimum separation distance between adjacent first and second lower trenches 32, 50.

[0144] The auxiliary trench 48 added to the CD can extend further above the first lower blocking portion 14a along the first lower trench 32. The presence of the first upper blocking portion 16 on top of the lower blocking portion 14a ensures that the first lower blocking portion 14a is preserved when the lower memory layer 14 is etched via the auxiliary trench 48, thereby preserving the trench interruption of earlier memory for the first lower trench. Figure 17 This can be seen more easily in the illustration, which shows a cross-section along the first lower groove 32 adjacent to the second lower groove 50.

[0145] exist Figure 17 In this process, the second lower trench 50 is patterned by etching a second lower trench 50 in the lower memory layer 14. During etching, the patterned auxiliary trench mask stack 46, the spacer lines 30, together with the third upper barrier portion 18a and the supplementary barrier 20a, serve as an etching mask. Therefore, the second lower trench 50 can be etched in the region of the lower memory layer 50 exposed within the auxiliary trench 48. Thus, at least a subset of the second lower trench 50 can be interrupted by the lower patterned memory layer portion 14b (“second lower barrier portion”) located below the corresponding portion in the third upper barrier portion 18a. As described above, the second lower trench 50 can be etched, for example, using selective “SiN etching”.

[0146] As shown in the figure, the second lower trench 50 etched via the CD-widened auxiliary trench 48 can start from the adjacent first lower trench 32 through a corresponding (linear) lower pattern memory layer portion retained below the spacer line 30. As shown in the figure, at least the second lower trench 50 etched via the CD-widened auxiliary trench 48 can be formed alternately with the first lower trench 32.

[0147] like Figure 17 As shown, etching of the lower memory layer 14 can also consume the supplementary barrier 20a. This is a result of the similar etching properties of the barrier 20a and layer 14. Alternatively, if layers 14 and 20 are formed of different materials that provide sufficient etching contrast, the supplementary barrier 20a can be retained after etching of the second lower trench 50 is completed.

[0148] Although the second upper barrier 22 is removed before etching the second lower trench 50 in the illustrated process flow, the second upper barrier is used as an etching mask to pattern the supplementary barrier 20a and / or the third upper barrier portion 18a, and is accordingly used as an etching mask to define trench interruptions in the second lower trench 50 during the initial step of patterning the second lower trench 50. However, variations exist in the method where, for example, the second upper barrier 22 may be retained to mask the third upper barrier portion 18a and / or the supplementary barrier 20a during etching of the second lower trench 50.

[0149] exist Figure 18 In this process, the auxiliary trench mask stack 46 has been removed from the patterned lower memory layer 14 (e.g., using SOC etching) to expose the patterned lower memory layer 14 having first and second lower trenches 32, 50 formed therein.

[0150] The hard mask layer 12 is further patterned using a patterned lower pattern memory layer 14 as an etch mask. Therefore, target trenches 52 and 54 can be formed by etching the lower trenches 32 and 50 into the hard mask layer 12, so as to form a first target trench 52 below each first lower trench 32 and a second target trench 54 below each second lower trench 50.

[0151] Below each of the first lower blocking portions 14a, a first hard mask blocking portion 12a has been formed, thereby interrupting the corresponding first target trench 52. Below each of the second lower blocking portions 14b, a second hard mask blocking portion 12b has been formed, thereby interrupting the corresponding second target trench 54.

[0152] exist Figure 19 In this process, while the patterned hard mask layer 12 masks the layers 10 / 11, trenches are further etched in the insulating layer 10 and the interface layer 11, thereby forming a first trench 56 below each first target trench 52 and a second trench 58 below each second target trench 54. Thus, the trench pattern defined in the lower memory layer 14 has been transferred to the hard mask layer 12 and subsequently to the insulating layer 10, including any interrupted trenches.

[0153] Etching the trenches in the insulating layer 10 can simultaneously create the final deepened vias 37' and 39', similar to a conventional dual damascene process.

[0154] The trenches 56, 58 and vias 37', 39' in insulating layer 10 can subsequently be filled with a conductive material to form conductive lines and conductive vias in the interconnect structure. However, as will be understood, the conductive material may be deposited first after the removal of masking features (e.g., hard mask layer 12 and underlying memory layer 14). The conductive material may be one or more metals conventionally used to form metal lines and vias in BEOL processes, such as, for example, W, Cu, Al, Ru.

[0155] In the foregoing, the inventive concept has been described primarily with reference to a limited number of examples. However, as will be readily understood by those skilled in the art, other examples besides those disclosed above are equally possible within the scope of the inventive concept as defined by the appended claims.

[0156] For example, the method can continue by depositing another insulating layer over insulating layer 10 and the metal wires and vias therein. The above method steps can then be repeated to form higher interconnect layers. This can be repeated until the desired number of interconnect layers are formed.

[0157] exist Figure 18 In this process, the hard mask layer 12 is also masked by the third upper block 18a and the spacing line 30. This can provide an increased mask budget during the patterning of the hard mask layer 12. However, one or more of these features can also be removed before patterning. Moreover, the lower memory layer 14 can be removed before the trenches 56, 58 are formed in the insulating layer 10.

[0158] Furthermore, in the illustrated process flow, target trenches 52 and 54 are etched simultaneously. However, a sequential approach is also possible, wherein the first target trench 52 is etched in the hard mask layer 12 before the second target trench 54. The first target trench 52 may be formed, for example, after the formation of the first lower trench 32 and before the formation of the third upper blocking portion 18a (e.g., before the first via formation process). The second target trench 54 may be formed after the formation of the second lower trench 50.

[0159] According to another variant, the following can be omitted: Figure 13 The step shown is a separate step of patterning the third upper blocking portion 18a. Alternatively, an auxiliary trench mask stack 46 can be formed on the upper pattern memory layer 18, such as... Figure 12 As shown, the upper groove 28' that provides the spacing is still retained. Then, the patterning of the second lower groove 50 can be performed according to the combination. Figure 15-17 The process is performed in the manner outlined above, but additionally includes etching back the upper surface portion of the patterned upper memory layer 18 exposed in the auxiliary trench 48, and subsequently etching back the upper surface portion of the lower patterned memory layer 14 exposed in the auxiliary trench 48. During the etching back of the patterned upper patterned memory layer, the second upper barrier 22 and / or supplementary upper barrier 20a may be used as etching masks to define an interruption in the second lower trench 50. The auxiliary trench mask stack 18a and the portion of the upper memory layer 18 masked by the auxiliary trench mask stack 18 may then be removed.

Claims

1. A patterning method, the method comprising: On the lower pattern memory layer (14) used to memorize the patterns of the first and second lower grooves (32, 50), a pattern of the first upper barrier (16) is formed, then an upper pattern memory layer (18) is formed, and then a pattern of the second upper barrier (22) is formed. Subsequently, the upper trenches (28) are patterned in the upper pattern memory layer (18) using photolithography and etching, and spacing lines (30) are formed along the sidewalls of the upper trenches (28) to define the upper trenches (28') that provide spacing, at least one subset of which is interrupted by a corresponding first upper block (16). By etching the spaced upper trench (28') into the lower pattern memory layer (14), the first lower trench (32) is patterned in the lower pattern memory layer (14), and at least a subset of the first lower trench (32) is retained at the location defined by the corresponding lower pattern memory layer portion (14a) interrupted by the corresponding barrier in the first upper barrier (16). Subsequently, an auxiliary trench mask stack (46) is formed and the auxiliary trenches (48) therein are patterned using photolithography and etching; and Subsequently, the second lower trench (50) in the lower pattern memory layer (14) is patterned, the patterning including: using a patterned auxiliary trench mask stack (46), spacers (30) and a second upper barrier (22) as an etching mask, at least a subset of the second lower trench (50) is preserved at the corresponding lower pattern memory layer portion (14b) interrupted at the position defined by the corresponding barrier in the second upper barrier (22). The patterns forming the first upper barrier (16) and / or the second upper barrier (22) include: Forming auxiliary barrier mask layers (102, 202) and barrier openings (104, 204) therein; and Deposit barrier material in the barrier opening (16, 208).

2. The method as described in claim 1, wherein, The pattern forming the first upper barrier (16) and / or the pattern forming the second upper barrier (22) include: A barrier material layer (201) is formed, and then an auxiliary barrier mask layer (202) is formed. An auxiliary blocking opening (204) is formed in the auxiliary blocking mask layer; Deposit auxiliary barrier material (208) in the auxiliary barrier opening (204); The auxiliary barrier mask layer (202) is selectively removed to the auxiliary barrier material (208); and Subsequently, the remaining auxiliary barrier material (208) was used as an etching mask to pattern the barrier material layer (201).

3. The method as described in claim 1 or 2, wherein, The blocking material or auxiliary blocking material (16, 208) is deposited on the auxiliary blocking mask layer (102, 202) and in the blocking opening (104, 204), and then etched back to expose the auxiliary blocking mask layer, such that the blocking material or auxiliary blocking material remains in the blocking opening; or the auxiliary blocking material (208) is selectively deposited on the bottom surface of the auxiliary blocking opening (204).

4. The method as described in claim 1 or 2, wherein, Patterning the upper trench (28) includes forming an upper auxiliary trench mask stack (24) on the upper pattern memory layer (18), wherein patterning the auxiliary upper trench (26) therein includes using photolithography and etching to etch the auxiliary upper trench (26) into the upper pattern memory layer (18). The method further includes forming at least one subset of the second upper barrier (22) such that a corresponding portion of it protrudes into the region where the auxiliary upper trench (26) will be formed, wherein the method further includes etching away the corresponding portion from the auxiliary upper trench.

5. The method of claim 4, wherein, A supplementary pattern memory layer (20) is formed between the upper pattern memory layer (18) and the second upper barrier (22), and the method further includes using the supplementary pattern memory layer (20) as an etch stop layer when the corresponding portion is etched away from the auxiliary upper trench.

6. The method as described in claim 1 or 2, wherein, At least one subset of the second lower trench (50) is alternately formed with at least one subset of the first lower trench (32).

7. The method as described in claim 1 or 2, wherein, At least one of the auxiliary trenches in the auxiliary trench mask stack extends over the partially patterned lower pattern memory layer (14) in which the second lower trench will be formed and over the adjacent first lower trench (32), wherein the second lower trench is spaced apart from the adjacent first lower trench (32) by the lower pattern memory layer portion (14) retained below the spacing line (30).

8. The method of claim 7, wherein, The auxiliary trench extends above the first upper barrier (16) positioned along the adjacent first lower trench.

9. The method as claimed in claim 1 or 2, wherein, A supplementary pattern memory layer (20) is formed between the upper pattern memory layer (18) and the second barrier (22), and the method further includes: patterning the supplementary pattern memory layer (20) to form a pattern of the auxiliary upper barrier (20a) conforming to the pattern of the second upper barrier before forming the auxiliary trench mask stack, the patterning including using the second upper barrier (22) as an etching mask.

10. The method of claim 9, wherein, The lower pattern memory layer (14) and the supplementary pattern memory layer (20) are formed as layers with similar etching properties, such that the pattern of the second upper barrier (22) is transferred to the supplementary pattern memory layer (20) while the upper trench (28') providing the spacing is etched into the lower pattern memory layer (14).

11. The method of claim 1 or 2, further comprising: Before forming the auxiliary trench mask stack (46), the upper memory layer (18) is patterned to form a pattern of the upper pattern memory layer portion (18a) conforming to the pattern of the second upper barrier (22), the patterning including using the second upper barrier (22) as an etching mask.

12. The method of claim 11, wherein, The first upper barrier (16) is formed to be thicker than the second upper barrier (22), and the method further includes removing the second upper barrier (22) after the patterning of the upper pattern memory layer portion (18a) and before the formation of the auxiliary trench mask stack (46), such that during the patterning of the second lower trench (50), at least a thick portion of the first upper barrier (16) remains to mask the first lower pattern memory layer portion.

13. The method as claimed in claim 1 or 2, wherein, An auxiliary trench mask stack (46) is formed on the upper pattern memory layer (18), in which spaced upper trenches (28') are patterned. Patterning the second lower trench (50) in the lower pattern memory layer (14) includes: etching back the upper surface portion of the patterned upper pattern memory layer (18) exposed in the auxiliary trench (48), and then etching back the upper surface portion of the lower pattern memory layer (14) exposed in the auxiliary trench (48).

14. The method as claimed in claim 1 or 2, wherein, The lower pattern memory layer (14) is formed on the target layer (12), and the method further includes: patterning the target layer (12) using the patterned lower pattern memory layer (14), wherein the target pattern layer is one of a hard mask layer, a dielectric layer or a metal layer.

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