Package structure and method of manufacturing the same

Abstract

A package structure and a method of manufacturing the same are provided. A package structure includes a circuit substrate, a semiconductor device, and a ring structure. The circuit substrate has a first region and a second region connected to the first region. The circuit substrate includes at least one wiring layer including a dielectric portion and a conductive portion disposed on the dielectric portion. A first ratio of a total volume of the conductive portion of the wiring layer in the first region to a total volume of the dielectric portion and the conductive portion of the wiring layer in the first region is less than a second ratio of a total volume of the conductive portion of the wiring layer in the second region to a total volume of the dielectric portion and the conductive portion of the wiring layer in the second region. The semiconductor device is disposed over the circuit substrate in the first region and electrically coupled to the circuit substrate. The ring structure is disposed over the circuit substrate in the second region.

Description

Technical Field

[0001] This invention provides a packaging structure and its manufacturing method. Background Technology

[0002] The development of miniaturization of semiconductor devices and electronic components has made it possible to integrate more devices and components into a given volume, resulting in high integration density of various semiconductor devices and / or electronic components. Summary of the Invention

[0003] This invention provides a packaging structure including a circuit substrate, a semiconductor device, and a ring structure. The circuit substrate has a first region and a second region connected to the first region, wherein the circuit substrate includes at least one wiring layer. The at least one wiring layer includes a dielectric portion and a conductive portion disposed above the dielectric portion, wherein a first ratio of the total volume of the conductive portion of the at least one wiring layer in the first region to the total volume of the dielectric and conductive portions of the at least one wiring layer in the first region is less than a second ratio of the total volume of the conductive portion of the at least one wiring layer in the second region to the total volume of the dielectric and conductive portions of the at least one wiring layer in the second region. The semiconductor device is disposed above the circuit substrate in the first region, wherein the semiconductor device is electrically coupled to the circuit substrate. The ring structure is disposed above the circuit substrate in the second region.

[0004] This invention provides a packaging structure including a substrate, a semiconductor device, a metal support structure, and a ring structure. The substrate has a first region and a second region surrounding the first region. The semiconductor device is disposed above the substrate in the first region and electrically coupled to the substrate. The metal support structure is located in the substrate in the second region and is electrically isolated from the semiconductor device. The ring structure is disposed above the substrate in the second region, wherein the ring structure overlaps with the metal support structure in its vertical projection onto the substrate along the stacking direction of the ring structure and the substrate.

[0005] This invention provides a method for manufacturing a package structure, comprising the following steps: providing a circuit substrate having a first region and a second region connected to the first region, the circuit substrate including at least one wiring layer, the at least one wiring layer including a dielectric portion and a conductive portion disposed above the dielectric portion, and a first ratio of the total volume of the conductive portion in the at least one wiring layer included in the first region to the total volume of the dielectric portion and the conductive portion in the at least one wiring layer included in the first region being less than a second ratio of the total volume of the conductive portion in the at least one wiring layer included in the second region to the total volume of the dielectric portion and the conductive portion in the at least one wiring layer included in the second region; providing a semiconductor device above the circuit substrate; mounting the semiconductor device onto the circuit substrate in the first region, the semiconductor device being electrically coupled to the circuit substrate; and providing a ring structure above the circuit substrate in the second region. Attached Figure Description

[0006] The following detailed description, taken in conjunction with the accompanying drawings, will best convey aspects of this disclosure. Note that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12A , Figure 13A and Figure 14A This is a schematic cross-sectional view illustrating a method of manufacturing a packaging structure according to some embodiments of the present disclosure.

[0008] Figure 12B , Figure 13B and Figure 14B They are shown separately in Figure 12A , Figure 13A and Figure 14A The diagram shows a schematic plan view of the packaging structure.

[0009] Figure 15 This is a flowchart illustrating a method for manufacturing a packaging structure according to some embodiments of the present disclosure.

[0010] Figures 16A to 16D This is an enlarged schematic cross-sectional view according to some embodiments of the present disclosure, showing... Figure 12AVarious embodiments of the support structure in the dashed area U shown in the figure.

[0011] Figure 17 This is a schematic cross-sectional view illustrating the packaging structure according to an alternative embodiment of the present disclosure.

[0012] Figure 18 This is a schematic cross-sectional view illustrating a packaging structure according to some embodiments of the present disclosure.

[0013] Figures 19A to 19D This is an enlarged schematic cross-sectional view according to some embodiments of the present disclosure, shown in Figure 18 Various embodiments of the support structure in the dashed area V shown in the figure.

[0014] Figure 20 This is a schematic cross-sectional view illustrating the packaging structure according to an alternative embodiment of the present disclosure.

[0015] Figure 21 This is a schematic cross-sectional view illustrating a packaging structure according to some embodiments of the present disclosure.

[0016] Figures 22A to 22D This is an enlarged schematic cross-sectional view according to some embodiments of the present disclosure, shown in Figure 21 Various embodiments of the support structure in the dashed area W shown in the figure.

[0017] Figure 23 This is a schematic cross-sectional view illustrating the packaging structure according to an alternative embodiment of the present disclosure.

[0018] Figure 24A This is a schematic cross-sectional view illustrating a packaging structure according to some embodiments of the present disclosure.

[0019] Figure 24B It is shown Figure 24A A schematic plan view of the packaging structure shown.

[0020] Figure 25 This is a schematic cross-sectional view illustrating the packaging structure according to an alternative embodiment of the present disclosure.

[0021] Figure 26A This is a schematic cross-sectional view illustrating a packaging structure according to some embodiments of the present disclosure.

[0022] Figure 26B It is shown Figure 26A A schematic plan view of the packaging structure shown.

[0023] Figure 27 This is a schematic cross-sectional view illustrating the packaging structure according to an alternative embodiment of the present disclosure.

[0024] Figure 28This is a schematic cross-sectional view illustrating a packaging structure according to some embodiments of the present disclosure.

[0025] Figure 29 This is a schematic cross-sectional view illustrating a packaging structure according to some embodiments of the present disclosure.

[0026] Figure 30 This is a schematic cross-sectional view illustrating a packaging structure according to some embodiments of the present disclosure.

[0027] Figure 31 This is a schematic cross-sectional view illustrating a packaging structure according to some embodiments of the present disclosure.

[0028] Figure 32 This is a schematic cross-sectional view illustrating a packaging structure according to some embodiments of the present disclosure.

[0029] Figure 33 This is a schematic cross-sectional view illustrating a packaging structure according to some embodiments of the present disclosure.

[0030] Figure 34 This is a schematic cross-sectional view illustrating a packaging structure according to some embodiments of the present disclosure.

[0031] Figure 35 This is a schematic cross-sectional view illustrating a packaging structure according to some embodiments of the present disclosure.

[0032] Figure 36 This is a schematic cross-sectional view illustrating a packaging structure according to some embodiments of the present disclosure.

[0033] Figure 37 This is a schematic cross-sectional view illustrating a packaging structure according to some embodiments of the present disclosure.

[0034] [Explanation of Symbols]

[0035] 10, 10a, 10b, 10c, 20, 20a, 20b, 20c, 30, 30a, 30b, 30c, 40, 50: Supporting structure

[0036] 11: Part One

[0037] 12: Part Two

[0038] 13: Part Three

[0039] 102, 106: Carrier

[0040] 104, 108: Peel-off layers

[0041] 110: Re-layout of the wiring structure

[0042] 112, 112a, 112b, 112c, 118, 322A, 322a, 322B, 322b, 322c: Dielectric layers

[0043] 114, 114a, 114b, 114c: Seed layers

[0044] 114m: Seed layer material

[0045] 116, 116a, 116b, 116c: Patterned conductive layers

[0046] 122, 124, 126: Metal pattern under the bump

[0047] 140A, 140B, 230c, 240c: Passivation layer

[0048] 150A, 150B, 190: Conductive terminals

[0049] 160, 400: Bottom filling material

[0050] 170, 170m, 860: Insulating Encapsulation

[0051] 180: Conductive post

[0052] 160t, 170t, 180t, S7, S8, S110b, S112a, S114a, S116a, S116b, S116c: Surface

[0053] 230, 240, 820a, 820b: Semiconductor dies

[0054] 230a, 240a: Active surfaces

[0055] 230b, 240b: Seam Pads

[0056] 230d, 240d, 234: Through holes

[0057] 240e, 230e: Protective layer

[0058] 230f, 240f: Backside surface

[0059] 230s: Die stacking

[0060] 230sw, 240sw: Sidewall

[0061] 240s: Semiconductor substrate

[0062] 231: Carrier Core

[0063] 232: Dielectric film

[0064] 233: Core

[0065] 235: Encapsulation

[0066] 300A, 300B, 300C, 300D, 300E, 810: Substrate

[0067] 302: Zone 1

[0068] 304: Second District

[0069] 310: Core Section

[0070] 312: Core Dielectric Layer

[0071] 314: Through-hole / Perforation

[0072] 316A, 316B: Core conductive layer

[0073] 318A, 318B: Conductive caps

[0074] 320A, 320A', 320B, 320B': Wiring section

[0075] 324A, 324a, 324B, 324b, 324c: Conductive layers

[0076] 330A, 330B: Solder mask layer

[0077] 510, 530: Adhesives

[0078] 520, 520A, 520B: Ring structure

[0079] 520b, 540b: Bottom surface

[0080] 520t: Top surface

[0081] 540: Cover

[0082] 550: Thermal interface material

[0083] 600: Conductive terminal

[0084] 800: Package

[0085] 830a, 830b: Joint lines

[0086] 840, 850: Conductive pads

[0087] 1000A, 1000B, 2000A, 2000B, 3000A, 3000B, 4000A, 4000B, 5000A, 5000B, 6000, 7000, 8000A, 8000B, 9000A, 9000B, 10000A, 10000B, 11000A, 11000B: Package Structure

[0088] AA: Line

[0089] D1: Distance

[0090] DA1, DA2: Connecting membranes

[0091] ML1, ML2, ML3: Metallization layers

[0092] O1, O2, O3, O4, O5, O6, O7, O8: Open

[0093] P1, P2, P3: Semiconductor devices

[0094] S10, S20, S30, S40: Steps

[0095] S110t: Outermost surface

[0096] T1, T2, T2', T2", T3, T3', T3": Thickness

[0097] U, V, W: Dashed line area

[0098] W1, W1', W1”, W2: Width

[0099] X, Y, Z: Direction Detailed Implementation

[0100] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, or the like are illustrated below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. Other components, values, operations, materials, arrangements, or the like are expected. For example, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be reused in various instances of this disclosure. Such reuse is for the purpose of brevity and clarity and does not in itself imply a relationship between the various embodiments and / or configurations discussed.

[0101] Furthermore, for ease of explanation, spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper,” and similar expressions may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. In addition to the orientations illustrated in the figures, these spatially relative terms are intended to cover different orientations of the device during use or operation. The device may be otherwise oriented (rotated 90 degrees or otherwise), and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0102] In addition, for ease of explanation, terms such as "first", "second", "third", "fourth", "fifth", "sixth" and similar terms may be used in this document to describe similar or different elements or features shown in the figure, and may be used interchangeably depending on the order of their existence or the context of the description.

[0103] Other features and processes may also be included. For example, test structures may be included to aid in the verification testing of three-dimensional (3D) packages or three-dimensional integrated circuit (3DIC) devices. These test structures may, for example, include test pads formed in redistribution layers or on a substrate, enabling testing of the 3D package or 3DIC, the use of probes and / or probe cards, and similar operations. Verification testing can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be used in conjunction with testing methods including intermediate verification of known good dies to improve yield and reduce costs.

[0104] It should be understood that the following embodiments of this disclosure provide applicable concepts that can be implemented in a wide variety of specific environments. The specific embodiments discussed herein are illustrative only and are not intended to limit the scope of this disclosure. (Semiconductor) package structures and methods of manufacturing thereof are provided according to various exemplary embodiments. Before detailing the illustrated embodiments, certain advantageous features and aspects of the embodiments of this disclosure will be summarized. Package structures can be employed to improve stress concentration and / or warpage problems during manufacturing and / or operation. The following describes a package structure having a semiconductor device disposed on a substrate with a supporting structure and a ring structure, wherein the positioning of the ring structure overlaps with the positioning of the supporting structure in the stacking direction of the semiconductor device and the substrate. Because the support structure is made of a metallic material (e.g., copper or the like) embedded in the substrate, its location is considered to be a region with high-density metallic material (e.g., a high Cu-density region), which suppresses the coefficient of thermal expansion (CET) between the annular structure and the substrate, thereby avoiding or reducing stress concentration and / or warpage problems (e.g., between the annular structure and the substrate). Furthermore, a lid is used in the package structure to position it above the semiconductor device and the annular structure, wherein the lid is thermally coupled to the semiconductor device and the annular structure, thereby enhancing heat dissipation. Additionally, the lid, the annular structure, and the adhesive used to fix the lid and the annular structure to the substrate together constitute an electromagnetic interference shielding structure for the semiconductor device. Intermediate stages of forming the package structure are shown according to some embodiments. Some variations of some embodiments are discussed. Throughout the various views and illustrative embodiments, the same reference numerals are used to indicate the same elements.

[0105] The embodiments described are intended to provide further explanation but are not intended to limit the scope of this disclosure. For example, some actions may occur in a different order and / or simultaneously with other actions or events besides those shown and / or described herein. Furthermore, not all actions shown may be necessary to implement one or more aspects or embodiments illustrated herein, and one or more actions illustrated herein may be performed in one or more separate actions and / or phases.

[0106] Figures 1 to 14B This is a schematic cross-sectional view or plan view illustrating a method of manufacturing a package structure 1000A according to some embodiments of the present disclosure, wherein the cross-sectional view is taken along line AA drawn in the plan view. Figure 15 This is a flowchart illustrating a method for manufacturing a packaging structure according to some embodiments of the present disclosure. Figures 16A to 16D This is an enlarged schematic cross-sectional view according to some embodiments of the present disclosure, showing... Figure 12A Various embodiments of the support structure in the dashed area U are illustrated. In these embodiments, the manufacturing method is part of a wafer-level packaging process. It should be noted that the process steps described herein cover a portion of the manufacturing process used to fabricate (semiconductor) package structures, which include semiconductor components such as semiconductor devices (or dies / chips). The embodiments are intended to provide further explanation but are not intended to limit the scope of this disclosure.

[0107] Reference Figure 1 In some embodiments, a carrier 102 is provided. In some embodiments, the carrier 102 is a glass carrier or any suitable carrier for carrying a semiconductor wafer or reconstructed wafer in a method of manufacturing a semiconductor device (or component / die / chip, etc.) P1. In some embodiments, the carrier 102 is coated with a release layer 104 (e.g., Figure 1 (As shown). The material of the release layer 104 can be any material suitable for bonding and peeling the carrier 102 to the layer above or any wafer disposed thereon.

[0108] In some embodiments, the release layer 104 comprises a dielectric material layer made of a dielectric material, including any suitable polymer-based dielectric material (e.g., benzocyclobutene (BCB) or polybenzoxazole (PBO)). In alternative embodiments, the release layer 104 comprises a dielectric material layer made of an epoxy-based heat-release material that loses its adhesive properties upon heating, such as a light-to-heat-conversion (LTHC) release coating. In yet another alternative embodiment, the release layer 104 comprises a dielectric material layer made of an ultraviolet (UV) adhesive that loses its adhesive properties upon exposure to UV light. The release layer 104 may be dispensed and cured as a liquid, may be a laminated film stacked on the carrier 102, or may be the like. For example, such as Figure 1 As shown, the top surface of the release layer 104, which is opposite the bottom surface of the release layer 104 that contacts the carrier 102, is flush with it and has a high degree of coplanarity. In some embodiments, the release layer 104 is an LTHC layer with good chemical resistance, and such a layer can be peeled off from the carrier 102 at room temperature by applying laser irradiation; however, this disclosure is not limited thereto.

[0109] In an alternative embodiment, a buffer layer (not shown) is applied onto the release layer 104, wherein the release layer 104 is sandwiched between the buffer layer and the carrier 102, and the top surface of the buffer layer may further provide high coplanarity. In some embodiments, the buffer layer may be a dielectric material layer. In some embodiments, the buffer layer may be a polymer layer made of polyimide (PI), PBO, BCB, or any other suitable polymer-based dielectric material. In some embodiments, the buffer layer may be an Ajinomoto Buildup Film (ABF), a Solder Resist Film (SR), or the like. In other words, the buffer layer is an optional dielectric layer and may be omitted based on requirements and design layout; this disclosure is not limited thereto.

[0110] continue Figure 1 In some embodiments, a dielectric layer 112a is formed on the release layer 104 and over the carrier 102. In some embodiments, the dielectric layer 112a is formed by (but not limited to) forming a dielectric material blanket over the top surface of the release layer 104 to completely cover the release layer 104, and patterning the dielectric material blanket to form a dielectric layer 112a having a plurality of openings O1 that expose portions of the release layer 104 located beneath it.

[0111] The dielectric layer 112a may be made of PI, PBO, BCB, nitrides such as silicon nitride, oxides such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), combinations thereof, or the like. This material may be patterned using photolithography and / or etching processes. In some embodiments, the dielectric material blanket layer is formed using suitable fabrication techniques such as spin coating, chemical vapor deposition (CVD) (e.g., plasma-enhanced chemical vapor deposition (PECVD)), or similar processes.

[0112] Subsequently, in some embodiments, a seed layer material 114m is formed above the dielectric layer 112a, such as... Figure 1As shown. In some embodiments, a seed layer material 114m is formed on a dielectric layer 112a and extends into an opening O1 formed in the dielectric layer 112a. In other words, the seed layer material 114m penetrates the dielectric layer 112a, and the sidewalls of the opening O1 are completely covered by the seed layer material 114m.

[0113] In some embodiments, the seed layer material 114m is formed on the release layer 104 and over the carrier 102 as a blanket layer made of a metal or metal alloy material, but this disclosure is not limited thereto. In some embodiments, the seed layer material 114m is referred to as a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, the seed layer material 114m comprises titanium, copper, molybdenum, tungsten, titanium nitride, titanium tungsten, combinations thereof, or the like. For example, the seed layer material 114m may comprise a titanium layer and a copper layer above the titanium layer. The seed layer material 114m may be formed using, for example, sputtering, physical vapor deposition (PVD), or similar processes. In some embodiments, the seed layer material 114m is conformally formed on the dielectric layer 112a by sputtering and is in contact with the dielectric layer 112a and the release layer 104 exposed by the opening O1. Throughout this document, the term "copper" is used to include substantially pure elemental copper, copper containing unavoidable impurities, and copper alloys containing small amounts of elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum, or zirconium.

[0114] like Figure 1 As shown, in some embodiments, after forming the seed layer material 114m, a patterned conductive layer 116a is formed on the seed layer material 114m and above the dielectric layer 112a. In some embodiments, the patterned conductive layer 116a can be formed (but is not limited to) by forming a conductive material blanket layer over the dielectric layer 112a to completely cover the seed layer material 114m, and patterning the conductive material blanket layer to form the patterned conductive layer 116a. The patterned conductive layer 116a can be made of a conductive material (e.g., copper, copper alloys, aluminum, aluminum alloys, or combinations thereof) formed by electroplating or deposition, said conductive material being patterned using photolithography and etching processes to form multiple conductive patterns / fragments. In some embodiments, each of the conductive patterns / fragments includes a line portion extending horizontally (e.g., direction X or direction Y) above the seed layer material 114m and / or, in addition to the line portion extending horizontally (e.g., direction X or direction Y) above the seed layer material 114m, a via portion connected to the line portion and extending vertically (e.g., direction Z) into a corresponding opening O1. Directions X, Y, and Z may be different from each other. For example, such as... Figure 1As shown, directions X, Y, and Z are perpendicular to each other. In some embodiments, the patterned conductive layer 116a is a patterned copper layer or other suitable patterned metal layer. For example, some portions of the patterned conductive layer 116a further extend into the opening O1.

[0115] Reference Figure 2 In some embodiments, the seed layer material 114m is patterned to form the seed layer 114a. In some embodiments, a patterned conductive layer 116a is used as an etching mask to pattern the seed layer material 114m to form the seed layer 114a. For example, the etching process may be a dry etching process, a wet etching process, or a combination thereof; this disclosure is not limited thereto. In other words, for example, in a vertical projection along direction Z onto dielectric layer 112a, the patterned conductive layer 116a completely overlaps with the seed layer 114a. That is, the sidewalls of the patterned conductive layer 116a are substantially aligned with the sidewalls of the seed layer 114a. In some embodiments, such as Figure 2 As shown, the patterned conductive layer 116a is electrically connected to the seed layer 114a located below it. In some embodiments, the patterned conductive layer 116a and the seed layer 114a together are referred to as the metallization layer ML1 (or redistribution layer).

[0116] continue Figure 2 In some embodiments, a dielectric layer 112b is formed over a patterned conductive layer 116a. In some embodiments, the dielectric layer 112b has a plurality of openings O2, each of which exposes a portion of the patterned conductive layer 116a. Figure 2 As shown, for example, through opening O2, the surface S116a of the patterned conductive layer 116a is partially exposed for electrical connection to a connector formed later. The formation and material of the dielectric layer 112b can be related to... Figure 1 The process and materials used to form dielectric layer 112a described herein are the same or similar, and therefore will not be repeated here for the sake of brevity. In one embodiment, the material of dielectric layer 112b is the same as that of dielectric layer 112a. In an alternative embodiment, the material of dielectric layer 112b is different from that of dielectric layer 112a; however, this disclosure is not limited thereto.

[0117] Reference Figure 3 In some embodiments, in Figure 2The illustrated structure sequentially comprises a seed layer 114b, a patterned conductive layer 116b, a dielectric layer 112c, a seed layer 114c, a patterned conductive layer 116c, and a dielectric layer 118 to form a redistributed circuit structure 110 on the release layer 104 and over the carrier 102. In some embodiments, the seed layer 114b is formed on the dielectric layer 112b and extends into an opening O2 formed in the dielectric layer 112b to physically contact the patterned conductive layer 116a exposed by the opening O2. In other words, the seed layer 114b penetrates the dielectric layer 112b, and the sidewalls of the opening O2 are completely covered by the seed layer 114b. In some embodiments, a patterned conductive layer 116b is formed on (e.g., in solid contact with) a seed layer 114b, wherein the patterned conductive layer 116b overlaps with the seed layer 114b in a vertical projection along direction Z onto the dielectric layer 112a. That is, the sidewalls of the seed layer 114b are substantially aligned with the sidewalls of the patterned conductive layer 116b. For example, such as... Figure 3 As shown, the patterned conductive layer 116b is electrically coupled to the patterned conductive layer 116a through the seed layer 114b. In some embodiments, the patterned conductive layer 116b and the seed layer 114b together are referred to as the metallization layer ML2 (or redistribution layer).

[0118] In some embodiments, a dielectric layer 112c having a plurality of openings O3 is formed on a patterned conductive layer 116b, each of the plurality of openings O3 exposing a portion of the patterned conductive layer 116b. Figure 3 As shown, the surface S116b of the patterned conductive layer 116b is partially exposed through the opening O3 for electrical connection to the connector formed later.

[0119] In some embodiments, a seed layer 114c is formed on a dielectric layer 112c and extends into an opening O3 formed in the dielectric layer 112c to physically contact the patterned conductive layer 116b exposed by the opening O3. In other words, the seed layer 114c extends through the dielectric layer 112c, and the sidewalls of the opening O3 are completely covered by the seed layer 114c. In some embodiments, a patterned conductive layer 116c is formed on the seed layer 114c (e.g., in physical contact with the seed layer 114c), wherein the patterned conductive layer 116c overlaps with the seed layer 114c in a vertical projection along the direction Z onto the dielectric layer 112a. That is, the sidewalls of the seed layer 114c are substantially aligned with the sidewalls of the patterned conductive layer 116c. For example, such as Figure 3As shown, the patterned conductive layer 116c is electrically coupled to the patterned conductive layer 116b through the seed layer 114c. In some embodiments, the patterned conductive layer 116c and the seed layer 114c together are referred to as the metallization layer ML3 (or redistribution layer).

[0120] In some embodiments, a dielectric layer 118 having a plurality of openings O4 is formed on a patterned conductive layer 116c, each of the plurality of openings O4 exposing a portion of the patterned conductive layer 116c. Figure 3 As shown, the surface S116c of the patterned conductive layer 116c is partially exposed through the opening O4 for electrical connection to a connector formed later. Based on this, a redistributed circuit structure 110 is fabricated.

[0121] The formation and materials of seed layers 114b and 114c can be independently related to... Figures 1 to 2 The process and materials used to form the seed layer 114a described herein are the same as or similar to those used elsewhere. The formation and materials of the patterned conductive layers 116b and 116c can be independently compared with those used elsewhere. Figure 1 The process and materials used to form the patterned conductive layer 116a described herein are the same as or similar, and the formation and materials of the dielectric layers 112b, 112c, and 118 can be independently compared with those described herein. Figure 1 The process and materials used to form dielectric layer 112a described herein are the same or similar, and therefore will not be repeated herein. In one embodiment, the seed layers 114a, 114b, and 114c are made of the same material. Alternatively, the seed layers 114a, 114b, and 114c may be partially or completely different from each other. In one embodiment, the patterned conductive layers 116a, 116b, and 116c are made of the same material. Alternatively, the patterned conductive layers 116a, 116b, and 116c may be partially or completely different from each other independently. In one embodiment, the dielectric layers 112a, 112b, 112c, and 118 are made of the same material. Alternatively, the materials of dielectric layers 112a, 112b, 112c, and 118 may be partially or entirely different from each other.

[0122] In some embodiments, such as Figure 3As shown, the redistribution circuit structure 110 is formed on the release layer 104 and includes a dielectric layer 112 (e.g., dielectric layers 112a to 112c), a seed layer 114 (e.g., seed layers 114a to 114c), a patterned conductive layer 116 (e.g., patterned conductive layers 116a to 116c), and a dielectric layer 118. However, in this disclosure, the number of dielectric layers 112, seed layers 114, and patterned conductive layers 116 is not limited to... Figure 3 The accompanying drawings show that each of the dielectric layer 112, the seed layer 114, and the patterned conductive layer 116 may be one or more layers. In some embodiments, the dielectric layer 112, the seed layer 114, and the patterned conductive layer 116 are sandwiched between the release layer 104 and the dielectric layer 118, and are stacked sequentially.

[0123] In this disclosure, a set of multilayers (e.g., dielectric layer 112a, seed layer 114a, and patterned conductive layer 116a), a set of multilayers (e.g., dielectric layer 112b, seed layer 114b, and patterned conductive layer 116b), and a set of multilayers (e.g., dielectric layer 112c, seed layer 114c, and patterned conductive layer 116c) may be individually referred to as the build-up layer of the redistribution circuit structure 110, and the dielectric layer 118 may be referred to as the passivation layer of the redistribution circuit structure 110, for providing protection to the underlying build-up layers. For illustrative purposes, Figure 3 The redistribution structure 110 includes three stacked layers; however, this disclosure is not limited thereto. The number of stacked layers included in the redistribution structure 110 is not limited in this disclosure and can be selected based on requirements and design layout. That is, the number of stacked layers included in the redistribution structure 110 can be one or more, as long as the redistribution structure 110 can provide power to a semiconductor die (e.g., as will be discussed later). Figure 5 The 230 and / or 240 (in the configuration) provide sufficient wiring functionality.

[0124] continue Figure 3In some embodiments, after the redistribution wiring structure 110 is formed, a plurality of under-bump metallurgy (UBM) patterns 122 are formed on the dielectric layer 118, and the plurality of UBM patterns 122 extend into openings O4 formed in the dielectric layer 118 to physically contact the patterned conductive layer 116c exposed by the openings O4 for electrical connection of the redistribution wiring structure 110. In this disclosure, the UBM patterns 122 facilitate electrical connection between the redistribution wiring structure 110 and subsequently formed conductive elements (e.g., connectors, such as conductive balls or conductive bumps; semiconductor components, such as passive semiconductor elements; or the like). However, this disclosure is not limited thereto; alternatively, the UBM patterns 122 may be omitted based on design layout and requirements.

[0125] The material of the under-bump metal pattern 122 may include copper, nickel, titanium, tungsten, or alloys thereof or the like, and may be formed in a single-layer or multi-layer manner by electroplating and etching processes (e.g., any two or more stacked layers in an under-bump metal pattern 122 may contain different materials). The number of under-bump metal patterns 122 is not limited in this disclosure and corresponds to the number of conductive elements formed later.

[0126] Reference Figure 4 In some embodiments, a passivation layer 140A is formed over the redistribution wiring structure 110. In some embodiments, the passivation layer 140A is formed on an under-bump metal pattern 122, wherein the under-bump metal pattern 122 is constrained by the redistribution wiring structure 110 (e.g., dielectric layer 118) and the passivation layer 140A. In some embodiments, the passivation layer 140A exposes each of the under-bump metal patterns 122 in an accessible manner through a plurality of openings O5 formed in the passivation layer 140A for electrical connection to a subsequently formed connector. For example, each of the under-bump metal patterns 122 is fully exposed by an opening O5 formed in the passivation layer 140A, such as Figure 4 As shown. However, this disclosure is not limited thereto; as an alternative, the passivation layer 140A may expose a portion of each of the metal patterns 122 under the bumps in an accessible manner through the opening O5 formed in the passivation layer 140A.

[0127] In some embodiments, the passivation layer 140A is formed by (but not limited to) forming a dielectric material blanket over the outermost surface S110t of the redistributed circuit structure 110 to completely cover the under-bump metal pattern 122, and patterning the dielectric material blanket to form a passivation layer 140A with an opening O5 that exposes the portion of the under-bump metal pattern 122 located beneath it. The material of the passivation layer 140A may be PI, PBO, BCB, nitrides such as silicon nitride, oxides such as silicon oxide, PSG, BSG, BPSG, combinations thereof, or the like, and may be patterned using photolithography and / or etching processes. In some embodiments, the dielectric material blanket is formed by suitable fabrication techniques such as spin coating, CVD (e.g., PECVD), or similar processes.

[0128] In some embodiments, passivation layer 140A is referred to as a protective layer for the redistributed wiring structure 110 and the under-bump metal pattern 122, providing protection to the redistributed wiring structure 110 and the under-bump metal pattern 122. In one embodiment, the material of passivation layer 140A is the same as the material of dielectric layer 112 (e.g., dielectric layer 112a, dielectric layer 112b, or dielectric layer 112c) or dielectric layer 118. In an alternative embodiment, the material of passivation layer 140A is different from the material of dielectric layer 112 (e.g., dielectric layer 112a, dielectric layer 112b, or dielectric layer 112c) or dielectric layer 118. However, this disclosure is not limited thereto; alternatively, passivation layer 140A may be omitted.

[0129] Reference Figure 4 In some embodiments, a plurality of conductive terminals 150A are formed on the under-bump metal pattern 122 and above the redistribution wiring structure 110. In some embodiments, the conductive terminals 150A are electrically coupled to the redistribution wiring structure 110 through the under-bump metal pattern 122. Due to the presence of the under-bump metal pattern 122, the adhesive strength between the conductive terminals 150A and the redistribution wiring structure 110 is enhanced.

[0130] In some embodiments, conductive terminals 150A are bonded to the under-bump metal pattern 122 using flux. In some embodiments, conductive terminals 150A are disposed on the under-bump metal pattern 122 using a ball-mounting process or a reflow process. Conductive terminals 150A are, for example, microbumps, chip connectors (e.g., controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, solder balls, or other connectors). The number of conductive terminals 150A is not limited to this disclosure and may be specified and selected based on the number of openings O5 (or the number of under-bump metal patterns 122 exposed by the openings O5). When solder is used, the solder may include eutectic solder or non-eutectic solder. The solder may contain lead or be lead-free and may contain Sn-Ag, Sn-Cu, Sn-Ag-Cu, or the like.

[0131] In one embodiment, conductive terminal 150A is referred to as a conductive connector for connection to another package or circuit substrate (e.g., an organic substrate, such as a printed circuit board, PCB). In an alternative embodiment, conductive terminal 150A is referred to as a conductive terminal for inputting / outputting electrical signals and / or power signals. In yet another alternative embodiment, conductive terminal 150A is referred to as a conductive terminal for connection to one or more semiconductor dies, said one or more semiconductor dies independently comprising active devices (e.g., transistors, diodes, etc.) and / or passive devices (e.g., capacitors, resistors, inductors, etc.), other components (e.g., one or more integrated passive devices (IPDs)) or combinations thereof. This disclosure is not limited thereto.

[0132] Reference Figure 5 In some embodiments, at least one semiconductor die is provided. For example, semiconductor dies 230 and 240 are arranged side-by-side with each other in the XY plane (see also...). Figure 13B In some embodiments, such as Figure 5 As shown, semiconductor dies 230 and 240 are picked up and placed on the redistribution wiring structure 110 (e.g., the outermost surface S110t of the redistribution wiring structure 110). In some embodiments, semiconductor dies 230 and 240 are bonded to the redistribution wiring structure 110 via conductive terminals 150A and under-bump metal patterns 122. It should be understood in this disclosure that the illustrations of semiconductor dies 230, 240, and other components in all figures are schematic and not to scale.

[0133] like Figure 5As shown, in some embodiments, the semiconductor die 230 includes a die stack 230s having an active surface 230a and a back surface 230f opposite to the active surface 230a, a plurality of pads 230b distributed on the active surface 230a, a passivation layer 230c covering a portion of the active surface 230a and the pads 230b, a plurality of conductive vias 230d connected to the pads 230b exposed by the passivation layer 230c, and a protection layer 230e disposed on the conductive vias 240d. The pads 230b, the passivation layer 230c, the conductive vias 230d, and the protection layer 230e are formed on the die stack 230s. The pad 230b is partially exposed by the passivation layer 230c, and the vias 230d are respectively disposed on the pad 230b and electrically connected to the pad 230b. The protective layer 230e covers the passivation layer 230c and the vias 230d exposed by the vias 230d.

[0134] However, this disclosure is not limited thereto. For example, the via 230d and the protective layer 230e may be omitted. In an alternative embodiment, the semiconductor die 230 may include a die stack 230s having an active surface 230a and a back surface 230f opposite to the active surface 230a, the plurality of pads 230b distributed on the active surface 230a, and a passivation layer 230c covering a portion of the active surface 230a and the pads 230b.

[0135] For example, pad 230b is an aluminum pad or other suitable metal pad. In some embodiments, passivation layer 230c and protective layer 230e may be a PBO layer, a PI layer, or other suitable polymer. In some alternative embodiments, passivation layer 230c and protective layer 230e may be made of inorganic materials such as silicon oxide, silicon nitride, silicon oxynitride, or any suitable dielectric material. For example, the material of passivation layer 230c may be the same as or different from the material of protective layer 230e. For example, via 230d is a copper pillar, a copper alloy pillar, or other suitable metal pillar containing copper.

[0136] Die stacks 230s may include a base tier and at least one inner tier stacked thereon. For example... Figure 5As shown, for example, a die stack 230s includes a carrier die 231, a plurality of dielectric films 232, a plurality of dies 233, a plurality of vias 234, and an encapsulation body 235, wherein the dies 233 are sequentially disposed on the carrier die 231 along direction Z, and the vias 234 are grouped into multiple different groups to electrically connect the carrier die 231 and two adjacent and overlapping dies 233. In some embodiments, different groups of vias 234 are independently covered by a corresponding one of the dielectric films 232, and the surface of the carrier die 231 exposed by the dielectric films 232 and the dies 233, the sidewalls of the dielectric films 232, and the sidewalls of the dies 233 are covered by the encapsulation body 235. Figure 5 As shown, in some embodiments, the via 234 is separated from the encapsulation 235 by a dielectric film 232. For example, the carrier die 231 is referred to as the base level of the die stack 230s, while each of the dies 233 is referred to as a stacking tier or inner level of the die stack 230s. Figure 5 As shown, for example, the carrier die 231 of the die stack 230s (e.g., the base layer) is electrically connected to a via 230d via a pad 230b, wherein the via 230d is referred to as a conductive terminal of the semiconductor die 230 for electrical connection to an external component. The number of carrier dies 231 included in the base layer and the number of dies 233 included in each inner layer are independently not limited to this disclosure and may be one or more based on requirements and design layout.

[0137] It should be noted that each of the carrier die 231 and die 233 may further include interconnect structures (not shown), multiple conductive pads (not shown), a passivation layer (not shown), and a post-passivation layer (not shown). The carrier die 231 described herein may be referred to as a semiconductor chip or integrated circuit (IC). In some embodiments, the carrier die 231 includes one or more digital chips, analog chips, or mixed-signal chips, such as application-specific integrated circuit (ASIC) chips, sensor chips, wireless and radio frequency (RF) chips, logic chips, or voltage regulator chips. Logic chips may be central processing units (CPUs), graphics processing units (GPUs), system-on-a-chip (SoCs), microcontrollers, or the like. In some embodiments, each of the dies 233 includes a memory die (e.g., a dynamic random-access memory (DRAM) die, a static random-access memory (SRAM) die, a synchronous dynamic random-access memory (SDRAM), NAND flash memory, etc.). That is, in some embodiments, the semiconductor die 230 includes a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module, or the like. For example, the die 233 included in the die stack 230s of the semiconductor die 230 is a high bandwidth memory (HBM) die, and the carrier die 231 is a logic die that provides control functions for these memory dies, such as... Figure 5 As shown.

[0138] In some embodiments, the dielectric film 232 independently comprises a PBO layer, a PI layer, or other suitable polymer. In some alternative embodiments, the material of the dielectric film 232 comprises inorganic materials such as silicon oxide, silicon nitride, silicon oxynitride, or any suitable dielectric material. The dielectric film 232 can be formed by suitable fabrication techniques such as spin coating, CVD (e.g., PECVD), or similar processes. Alternatively, each of the dielectric films 232 is, for example, a non-conductive film (NCF) that can be formed by lamination. For example, the via 234 is a copper pillar, a copper alloy pillar, or other suitable metal pillar containing copper.

[0139] In some embodiments, the material of the encapsulation 235 includes molding compounds, molding underfills, resins (e.g., epoxy resins), or the like. In some alternative embodiments, the material of the encapsulation 235 includes, for example, nitrides such as silicon nitride, oxides such as silicon oxide, PSG, BSG, BPSG, combinations thereof, or the like. In yet another alternative embodiment, the material of each encapsulation 235 includes an organic material (e.g., epoxy resin, PI, PBO, or the like), or a mixture of inorganic and organic materials (e.g., a mixture of silicon oxide and epoxy resin, or the like). In some embodiments, the encapsulation 235 can be formed by a molding process, such as compression molding. In some alternative embodiments, the encapsulation 235 can be formed by a suitable fabrication technique, such as CVD (e.g., high-density plasma chemical vapor deposition (HDPCVD) or PECVD). Figure 5 As shown, for example, the back surface 230f of the semiconductor die 230 includes the surface of the encapsulation 235 and the surface of the die 233 included in the outermost layer of the inner layers in the die stack 230s, wherein the surface of the die 233 included in the outermost layer is substantially flush with and coplanar with the surface of the encapsulation 235.

[0140] like Figure 5As shown, in some embodiments, the semiconductor die 240 includes a semiconductor substrate 240s having an active surface 240a and a back surface 240f opposite to the active surface 240a, a plurality of pads 240b distributed on the active surface 240a, a passivation layer 240c covering a portion of the active surface 240a and the pads 240b, a plurality of vias 240d connected to the pads 240b exposed by the passivation layer 240c, and a protective layer 240e disposed on the vias 240d. The pads 240b, the passivation layer 240c, the vias 240d, and the protective layer 240e are formed on the semiconductor substrate 240s. The pad 240b is partially exposed by the passivation layer 240c, and the vias 240d are respectively disposed on the pad 240b and electrically connected to the pad 240b. The protective layer 240e covers the passivation layer 240c and the vias 240d exposed by the vias 240d.

[0141] The semiconductor substrate 240s may be made of a silicon substrate, which includes active components (e.g., transistors and / or memories, such as N-type metal-oxide-semiconductor (NMOS) and / or P-type metal-oxide-semiconductor (PMOS) devices or the like) and / or passive components (e.g., resistors, capacitors, inductors, or the like) formed therein. In some embodiments, such active and passive components may be formed in a front-end-of-line (FEOL) process. In alternative embodiments, the semiconductor substrate 240s may be a bulk silicon substrate (e.g., a bulk single-crystal silicon substrate), a doped silicon substrate, an undoped silicon substrate, or a silicon-on-insulator (SOI) substrate, wherein the dopant of the doped silicon substrate may be an N-type dopant, a P-type dopant, or a combination thereof. This disclosure is not limited thereto.

[0142] Additionally, the semiconductor substrate 240s may also include interconnect structures (not shown) disposed on the active surface 240a. In some embodiments, the interconnect structure may include one or more interlayer dielectric layers and one or more patterned conductive layers stacked alternately to provide wiring functionality for active and passive components embedded in the semiconductor substrate 240s, wherein the pad 240b may be referred to as the outermost layer of the patterned conductive layers. In one embodiment, the interconnect structure may be formed in a back-end-of-line (BEOL) process. For example, the interlayer dielectric layer may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a dielectric layer formed of other suitable dielectric materials, and may be formed by deposition or similar processes. For example, the patterned conductive layer may be a patterned copper layer or other suitable patterned metal layer, and may be formed by electroplating or deposition. However, this disclosure is not limited thereto.

[0143] The materials of pad 240b, passivation layer 240c, via 240d, and protective layer 240e may be similar to or substantially the same as the materials of pad 230b, passivation layer 230c, via 230d, and protective layer 230e, respectively; therefore, for the sake of brevity, they will not be repeated herein. For example, the material of passivation layer 240c may be substantially the same as or different from the material of protective layer 240e.

[0144] However, this disclosure may not be limited thereto; alternatively, the via 240d and the protective layer 240e may be omitted. In an alternative embodiment, the semiconductor die 240 may include a semiconductor substrate 240s having an active surface 240a and a back surface 240f opposite to the active surface 240a, a plurality of pads 240b distributed on the active surface 240a, and a passivation layer 240c covering a portion of the active surface 240a and the pads 240b.

[0145] Semiconductor die 240 may be referred to as a semiconductor die or chip that independently includes digital chips, analog chips, or mixed-signal chips. In some embodiments, the semiconductor die 240 is: a logic die, such as a CPU, GPU, neural network processing unit (NPU), deep learning processing unit (DPU), tensor processing unit (TPU), SoC, application processor (AP), and microcontroller; a power management die, such as a power management integrated circuit (PMIC) die; a wireless and radio frequency (RF) die; a baseband (BB) die; a sensor die, such as an optical / image sensor chip; a micro-electro-mechanical system (MEMS) die; a signal processing die, such as a digital signal processing (DSP) die; a front-end die, such as an analog front-end (AFE) die; an application-specific die, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), etc.; combinations thereof; or the like. In alternative embodiments, the semiconductor die 240 is independently: an artificial intelligence (AI) engine, such as an AI accelerator; a computing system, such as an AI server, a high-performance computing (HPC) system, a high-power computing device, a cloud computing system, an edge computing system, etc.; a combination thereof; or the like. The type of semiconductor die 240 may be selected and specified based on requirements and design requirements, and is therefore not specifically limited in this disclosure.

[0146] like Figure 5As shown, for illustrative purposes, only one semiconductor die 230 and one semiconductor die 240 are illustrated. However, it should be noted that the number of semiconductor dies 230 and the number of semiconductor dies 240 can be independently selected and specified based on requirements and design layout; this disclosure is not limited thereto. In some embodiments, the number of semiconductor dies 230 is one or more, and the number of semiconductor dies 240 is zero, one, or more than one. In embodiments where the number of semiconductor dies 230 is more than one, the semiconductor dies 230 may be of the same type. Alternatively, the semiconductor dies 230 may be partially or entirely of different types. In embodiments where the number of semiconductor dies 240 is more than one, the semiconductor dies 240 may be of the same type. Alternatively, the semiconductor dies 240 may be partially or entirely of different types.

[0147] like Figure 5 As shown, for example, semiconductor dies 230 and 240 are mounted to the redistribution structure 110 via flip-chip bonding. However, this disclosure is not limited thereto; alternatively, semiconductor dies 230 and 240 are mounted to the redistribution structure 110 via hybrid bonding (see [link to documentation]). Figure 28 The semiconductor device P2 is illustrated in the package structure 6000. In some embodiments, one or more additional semiconductor dies other than semiconductor dies 230 and 240 are provided, wherein the additional semiconductor dies may be of the same or different type independently compared to semiconductor dies 230 and / or semiconductor dies 240. This disclosure is not limited thereto. In this disclosure, direction Z may be referred to as the stacking direction of the redistribution circuit structure 110 and semiconductor dies 230, 240.

[0148] Reference Figure 6 In some embodiments, an underfill material 160 is formed between semiconductor dies 230, 240 and the redistributed wiring structure 110, and the underfill material 160 is distributed around the conductive terminals 150A. In some embodiments, the underfill material 160 at least fills the gaps between the conductive terminals 150A and between the redistributed wiring structure 110, the conductive terminals 150A, the semiconductor dies 230, and the semiconductor dies 240. Figure 6 As shown, for example, an underfill material 160 is disposed on the redistribution wiring structure 110 and wraps around the sidewalls of the conductive terminal 150A to provide structural support and protection to the conductive terminal 150A. In some embodiments, the underfill material 160 completely covers the sidewalls of the semiconductor dies 230, 240 (e.g., sidewalls 230sw, sidewalls 240sw) and exposes the back surfaces of the semiconductor dies 230, 240 in an accessible manner (e.g., back surface 230f, back surface 240f), such as... Figure 6 As shown.

[0149] However, this disclosure is not limited thereto. In an alternative embodiment (not shown), the underfill material 160 covers a portion of the sidewall 230sw of the semiconductor die 230 and a portion of the sidewall 240sw of the semiconductor die 240, and further fully exposes the back surface 230f of the semiconductor die 230 and the back surface 240f of the semiconductor die 240. In yet another alternative embodiment (not shown), the underfill material 160 fully covers the sidewalls (e.g., sidewalls 230sw, sidewall 240sw) and back surfaces (e.g., back surface 230f, back surface 240f) of the semiconductor dies 230 and 240. In yet another alternative embodiment (not shown), the underfill material 160 fully and accessiblely exposes the sidewalls (e.g., sidewalls 230sw, sidewall 240sw) and back surfaces (e.g., back surface 230f, back surface 240f) of the semiconductor dies 230 and 240. Due to the presence of the bottom filler material 160, the bonding strength between the vias 230d and 240d and the conductive terminal 150A is enhanced, thereby ensuring the electrical coupling of the semiconductor dies 230 and 240 and the redistributed circuit structure 110.

[0150] In one embodiment, the underfill material 160 may be formed by underfill dispensing or any other suitable method. In some embodiments, the underfill material 160 may be a molding compound comprising a polymeric material (e.g., epoxy resin, resin, and the like) with or without a hardener, fillers (e.g., silica fillers, glass fillers, alumina, silica, and the like), adhesion promoters, combinations thereof, and the like. Alternatively, the underfill material 160 may be omitted.

[0151] Reference Figure 7 In some embodiments, semiconductor dies 230 and 240 are encapsulated within an insulating enclosure 170m. In some embodiments, the insulating enclosure 170m is formed on the underfill material 160 and over the redistribution wiring structure 110. The insulating enclosure 170m may at least fill the gaps between semiconductor dies 230 and 240 and between the underfill material 160 and semiconductor dies 230 and 240. In some embodiments, the insulating enclosure 170m covers semiconductor dies 230 and 240, the underfill material 160, and the redistribution wiring structure 110 exposed by the semiconductor dies 230 and 240 and the underfill material 160. In other words, for example, semiconductor dies 230 and 240 are not exposed in an accessible manner by the insulating enclosure 170m and are embedded within the insulating enclosure 170m.

[0152] In some embodiments, the insulating encapsulation 170m is a molding compound formed by a molding process. The molding process may include compression molding or transfer molding. The insulating encapsulation 170m may include a polymer (e.g., epoxy resin, phenolic resin, silicone resin, or other suitable resin), a dielectric material, or other suitable material. Alternatively, the insulating encapsulation 170m may comprise an acceptable insulating encapsulation material. In some embodiments, the insulating encapsulation 170m may also comprise an inorganic filler or inorganic compound (e.g., silica, clay, etc.) that may be added to the insulating encapsulation 170m to optimize its coefficient of thermal expansion (CTE). This disclosure is not limited thereto.

[0153] In one embodiment, the material of the insulating encapsulation 170m may be different from the material of the underfill material 160, wherein there is a clear interface (not shown) between the insulating encapsulation 170m and the underfill material 160, such as... Figure 7 As shown. However, this disclosure is not limited thereto; the material of the insulating encapsulation 170m may be the same as the material of the underfill material 160, wherein there is no clear interface between the insulating encapsulation 170m and the underfill material 160.

[0154] Reference Figure 8 In some embodiments, the insulating encapsulation 170m is planarized to form an insulating encapsulation 170 that exposes the semiconductor die 230 and the semiconductor die 240. In some embodiments, such as Figure 8 As shown, after planarization, the back surface 230f of semiconductor die 230, the back surface 240f of semiconductor die 240, and the surface 160t of the underfill material 160 are exposed by the surface 170t of the insulating encapsulation 170. That is, for example, the back surface 230f of semiconductor die 230, the back surface 240f of semiconductor die 240, and the surface 160t of the underfill material 160 become substantially flush with the surface 170t of the insulating encapsulation 170. In other words, the back surface 230f of semiconductor die 230, the back surface 240f of semiconductor die 240, the surface 160t of the underfill material 160, and the surface 170t of the insulating encapsulation 170 are substantially coplanar.

[0155] For example, the insulating encapsulation 170m can be planarized by mechanical grinding or chemical mechanical polishing (CMP). After the planarization step, a cleaning step may be performed as appropriate, for example, to clean and remove residues generated by the planarization step. However, this disclosure is not limited thereto, and the planarization step can be performed by any other suitable method. In some embodiments, during the planarization of the insulating encapsulation 170m, the semiconductor die 230, the semiconductor die 240, and / or the underfill material 160 may also be planarized. In some embodiments, the planarization step may be performed, for example, on an over-molded insulating encapsulation 170m to make the surface 170t of the insulating encapsulation 170, the back surface 230f of the semiconductor die 230, the back surface 240f of the semiconductor die 240, and / or the surface 160t of the underfill material 160 flush.

[0156] For example, semiconductor dies 230 and 240 are exposed laterally by an insulating encapsulation 170. In some embodiments, such as Figure 8 As shown, semiconductor dies 230 and 240 are exposed in an accessible manner by an insulating enclosure 170. This configuration ensures better heat dissipation for semiconductor dies 230 and 240.

[0157] In an alternative embodiment, the surface 160t of the bottom filler 160 is lower than the surface 170t of the insulating encapsulation 170. In such an alternative embodiment, the bottom filler 160 is embedded within the insulating encapsulation 170 and is not exposed in an accessible manner by the surface 170t of the insulating encapsulation 170.

[0158] Reference Figure 9 In some embodiments, Figure 8 The entire structure illustrated is flipped (upside down) and placed on a carrier 106 coated with a release layer 108, and the carrier 102 is peeled off from the redistributed circuit structure 110. In some embodiments, the redistributed circuit structure 110 (e.g., dielectric layer 112a and seed layer 114a) is easily separated from the carrier 102 due to the presence of the release layer 104, wherein the redistributed circuit structure 110 (e.g., the surface S112a of dielectric layer 112a and the surface S114a of seed layer 114a) is exposed. In some embodiments, the carrier 102 is separated from the redistributed circuit structure 110 by a peeling process, and the carrier 102 and the release layer 104 are removed. In one embodiment, the peeling process is a laser peeling process.

[0159] In some embodiments, the material of carrier 106 may be the same as the material of carrier 102; however, this disclosure is not limited thereto. In alternative embodiments, the material of carrier 106 may be different from the material of carrier 102. In some embodiments, the material and formation of release layer 108 may be the same as or different from the material and formation of release layer 104; this disclosure is not limited thereto.

[0160] Reference Figure 10 A passivation layer 140B is formed on the redistributed wiring structure 110 (e.g., in the Z direction, surface S110b is opposite to the outermost surface S110t). For example, the passivation layer 140B exposes at least a portion of the exposed portion of the seed layer 114a in an accessible manner through a plurality of openings O6 formed in the passivation layer 140B for electrical connection to a subsequently formed connector. In one embodiment, the exposed portion of the seed layer 114a is partially and accessiblely exposed by the openings O6 formed in the passivation layer 140B. However, this disclosure is not limited thereto; alternatively, each exposed portion of the seed layer 114a may be fully and accessiblely exposed by the openings O6 formed in the passivation layer 140B, such as... Figure 10 As shown.

[0161] The formation, material, and structure of passivation layer 140B are similar to those previously used in... Figure 4 The process, materials, and construction of forming the passivation layer 140A described herein are similar or identical, and therefore will not be repeated here for the sake of brevity. In some embodiments, the passivation layer 140B is referred to as a protective layer of the redistribution structure 110, used to provide protection to the redistribution structure 110. Similar to the passivation layer 140A, the passivation layer 140B may be omitted as an alternative.

[0162] continue Figure 10 In some embodiments, a plurality of under-bump metal patterns 124 are formed on the passivation layer 140B, and the plurality of under-bump metal patterns 124 extend into openings O6 formed in the passivation layer 140B to physically contact the seed layer 114a exposed by the openings O6 for electrical connection of the redistribution circuit structure 110. In this disclosure, the under-bump metal patterns 124 facilitate electrical connection between the redistribution circuit structure 110 and conductive elements (e.g., connectors, such as conductive balls or conductive bumps; semiconductor components, such as semiconductor passive elements; or the like) formed subsequently.

[0163] However, this disclosure is not limited thereto; as an alternative, the under-bump metal pattern 124 may be omitted based on design layout and requirements. The formation, material, and construction of the under-bump metal pattern 124 are similar to those previously described in... Figure 3The process, materials and structure for forming the metal pattern 122 under the bump described herein are similar or identical, and therefore, for the sake of brevity, they will not be repeated here.

[0164] After that, continue Figure 10 In some embodiments, a plurality of conductive terminals 150B are formed on the under-bump metal pattern 124 and above the redistributed wiring structure 110. In some embodiments, the conductive terminals 150B are electrically coupled to the redistributed wiring structure 110 via the under-bump metal pattern 124. Due to the presence of the under-bump metal pattern 124, the adhesion strength between the conductive terminals 150B and the redistributed wiring structure 110 is enhanced. In some embodiments, the conductive terminals 150B are referred to as conductive connectors for connection to another package or circuit substrate (e.g., an organic substrate, such as a PCB).

[0165] This disclosure is not limited thereto. In an alternative embodiment, conductive terminal 150B is referred to as a conductive terminal for inputting / outputting electrical signals and / or power signals. In yet another alternative embodiment, conductive terminal 150B is referred to as a conductive terminal for connection to one or more semiconductor dies, said one or more semiconductor dies independently including active devices (e.g., transistors, diodes, etc.) and / or passive devices (e.g., capacitors, resistors, inductors, etc.), other components (e.g., one or more integrated passive devices (IPDs)) or combinations thereof. The formation, materials, and construction of conductive terminal 150B are consistent with those previously described in... Figure 5 The process, materials and structure for forming the conductive terminal 150A described in the previous article are similar or identical, and therefore will not be repeated here for the sake of brevity.

[0166] Additionally, semiconductor dies 230 and 240 are arranged in an array, and conductive terminals 150B can be divided into multiple groups corresponding to the number of semiconductor dies 230 and 240. In some embodiments, some conductive terminals 150B are electrically connected to semiconductor die 230 via some under-bump metal patterns 124, redistribution wiring structure 110, some under-bump metal patterns 122, and some conductive terminals 150A. In some embodiments, some conductive terminals 150B are electrically connected to semiconductor die 240 via some under-bump metal patterns 124, redistribution wiring structure 110, some under-bump metal patterns 122, and some conductive terminals 150A. In some embodiments, some conductive terminals 150B may be electrically floated or grounded, but this disclosure is not limited thereto. However, this disclosure is not limited thereto; alternatively, the conductive terminal 150B may be omitted, wherein the exposed metallization layer ML1 may function as the conductive terminal 150B as described above.

[0167] Reference Figure 11 In some embodiments, Figure 10 The entire structure illustrated is flipped (upside down), and then the carrier 106 is peeled off from the structure to form the semiconductor device P1. In some embodiments, the carrier 106 is separated from the semiconductor dies 230, 240, underfill material 160, and insulating encapsulation 170 by a peeling process, wherein the carrier 106 and the release layer 108 are removed, and the semiconductor dies 230, 240, underfill material 160, and insulating encapsulation 170 are exposed. In one embodiment, the peeling process is a laser peeling process. During the peeling step, a holding device (not shown) is used to hold the conductive terminals 150B to secure the semiconductor device P1 before the carrier 106 is peeled off. The holding device may be tape, adhesive carrier, or suction cup.

[0168] In some embodiments, conductive terminals 150B are released from the holding device to form semiconductor device P1. In some embodiments, prior to releasing conductive terminals 150B from the holding device, a dicing process is performed to cut the interconnected semiconductor devices P1 (e.g., in wafer form) into individual and separate semiconductor devices P1 (e.g., in monomer form). In one embodiment, the dicing process is a wafer dicing process including mechanical sawing or laser cutting. At this point, the fabrication of semiconductor device P1 is complete. In some embodiments, semiconductor device P1 is referred to as an integrated fan-out (InFO) package. Semiconductor device P1 may be further mounted with an interposer, additional package, chip / die, and / or other electronic components to form a stacked semiconductor device, such as an InFO package-on-package (PoP) structure, see [link to documentation]. Figure 29 The semiconductor device P3 with package structure 7000 is shown in the figure (it will be discussed in more detail later).

[0169] Reference Figure 12A and Figure 12B In some embodiments, according to Figure 15 Step S10 involves providing a substrate 300A in which the support structure 10 is embedded. In some embodiments, the substrate 300A includes a core portion 310, a plurality of routing portions 320A and 320B, and a plurality of solder resist layers 330A and 330B. The routing portions 320A and 320B are located on opposite sides of the core portion 310 along the Z direction. The solder resist layer 330A is disposed on the routing portion 320A, and the solder resist layer 330B is disposed on the routing portion 320B. In some embodiments, the routing portion 320A is sandwiched between the solder resist layer 330A and the core portion 310, and the routing portion 320B is sandwiched between the solder resist layer 330B and the core portion 310.

[0170] In some embodiments, the core portion 310 includes a core dielectric layer 312, a plurality of through holes 314, a plurality of core conductive layers 316A and 316B, and a plurality of conductive caps 318A and 318B. In some embodiments, the core dielectric layer 312 includes a prepreg (containing epoxy resin, resin, silica filler, and / or glass fiber), ABF, resin-coated copper foil (RCC), polyimide, photo image dielectric (PID), ceramic core, glass core, molding compound, combinations thereof, or the like. However, this disclosure is not limited thereto, and other dielectric materials may also be used. The core dielectric layer 312 may be formed by a lamination process, a coating process, or a similar process. In some embodiments, core conductive layers 316A and 316B are formed on opposite sides of the core dielectric layer 312. In some embodiments, core conductive layers 316A and 316B comprise copper, tungsten, aluminum, silver, gold, combinations thereof, or the like. Conductive caps 318A and 318B are respectively located above core conductive layers 316A and 316B. In some embodiments, for example, conductive caps 318A and 318B comprise copper or other suitable conductive materials. In some embodiments, core dielectric layer 312 is referred to as a base substrate or core substrate.

[0171] In some embodiments, a through-hole 314 is disposed in and penetrates the core dielectric layer 312, providing an electrical connection between core conductive layers 316A and 316B. In other words, the through-hole 314 provides multiple electrical paths between circuits located on two opposite sides of the core dielectric layer 312. In some embodiments, the through-hole 314 is lined with an insulating material, wherein a liner (not shown) separates the through-hole 314 from the core dielectric layer 312. The liner may be referred to as a barrier layer. In some embodiments, the method of forming the through-hole 314 includes the following steps: First, a plurality of openings (not shown) are formed at predetermined locations (of the through-hole 314) by means of, for example, mechanical or laser drilling, etching, or other suitable removal techniques. A desmear treatment may be performed to remove residue remaining in the openings formed in the core dielectric layer 312. Subsequently, the openings may be filled to a predetermined thickness with one or more conductive materials to provide the through-hole 314. For example, the opening can be filled with copper through electroplating or electroless coating, deposition, or similar processes. In some embodiments, the through hole 314 is referred to as a conductive via or a through via.

[0172] This disclosure is not limited thereto; alternatively, the through-via may include a plated throughvia (not shown), wherein the opening may be lined with a conductive material and filled with an insulating material. In some alternative embodiments, the method of forming the through-via includes the following steps: First, a plurality of openings (not shown) are formed at predetermined locations by means of, for example, mechanical or laser drilling, etching, or other suitable removal techniques. A decontamination process may be performed to remove any residue remaining in the openings. Subsequently, the openings may be plated to a predetermined thickness with one or more conductive materials, thereby providing a plurality of plated through-vias. For example, the openings may be plated with copper by electroplating or electroless plating.

[0173] In some embodiments, the core conductive layer 316A, core conductive layer 316B, conductive cap 318A, conductive cap 318B, and through-hole 314 can be formed by the following steps. First, a first conductive material (not shown) is formed on two opposing surfaces of the core dielectric layer 312. Then, as described above, a through-hole 314 is formed to pass through the core dielectric layer 312 and provide an electrical connection between the first conductive materials formed on the two surfaces of the core dielectric layer 312. Subsequently, a second conductive material is formed over the first conductive materials on the opposing surfaces of the core dielectric layer 312, wherein the second conductive material may be different from the first conductive material. In some embodiments, the first and second conductive materials can be formed by any suitable method (e.g., chemical vapor deposition (CVD), sputtering, printing, plating, or similar processes). The first and second conductive materials can then be patterned together to form the core conductive layers 316A, 316B and the conductive caps 318A, 318B, respectively. In some embodiments, photolithography and etching processes or other suitable removal techniques may be used to partially remove the first conductive material and the second conductive material. That is, for example, through-hole 314 further penetrates the core conductive layers 316A and 316B, such as... Figure 12A and Figure 16A As shown.

[0174] However, this disclosure is not limited thereto; as an alternative, the core conductive layer 316A, core conductive layer 316B, conductive cap 318A, conductive cap 318B, and through-hole 314 can be formed by the following steps: forming through-hole 314 to pass through the core dielectric layer 312 as described above; sequentially forming a first conductive material and a second conductive material above opposite surfaces of the core dielectric layer 312; and patterning the first conductive material and the second conductive material to form the core conductive layers 316A, 316B and the conductive caps 318A, 318B; thereby, the through-hole 314 provides electrical connection between the first conductive material and the second conductive material respectively formed on the two surfaces of the core dielectric layer 312. For such alternative embodiments, the through-hole 314 does not penetrate the core conductive layer 316A and the core conductive layer 316B (see [link to alternative embodiment]). Figure 16B ).

[0175] like Figure 12AAs shown, in some embodiments, wiring portions 320A and 320B are respectively disposed on opposite sides of the core portion 310 in the Z direction. For example, wiring portion 320A is formed above the conductive cover 318A of the core portion 310, while wiring portion 320B is formed above the conductive cover 318B of the core portion 310. In some embodiments, the formation of wiring portion 320A may include sequentially forming a plurality of dielectric layers 322A (including dielectric layers 322a, 322b, and 322c) and a plurality of conductive layers 324A (including conductive layers 324a, 324b, and 324c). For example, dielectric layers 322A and conductive layers 324A are alternately stacked above the shown top surface (not labeled) of the core portion 310. Similarly, the formation of the wiring portion 320B may include the sequential formation of a plurality of dielectric layers 322B (including dielectric layers 322a, 322b, and 322c) and a plurality of conductive layers 324B (including conductive layers 324a, 324b, and 324c). For example, dielectric layers 322B and conductive layers 324B are alternately stacked above the shown bottom surface (not marked) of the core portion 310.

[0176] In some embodiments, wiring portions 320A and 320B are individually referred to as a redistribution structure or rewiring structure, wherein dielectric layer 322a and conductive layer 324a are considered together as a wiring layer, dielectric layer 322b and conductive layer 324b are considered together as a wiring layer, and dielectric layer 322c and conductive layer 324c are considered together as a wiring layer. In some embodiments, the material of dielectric layers 322A and 322B (e.g., each of dielectric layers 322a, 322b, and 322c) may be ABF, prepreg, RCC, polyimide, PID, molding compound, combinations thereof, or the like. In some alternative embodiments, core dielectric layer 312 and dielectric layers 322A and 322B may be made of the same material. For example, the material of core dielectric layer 312 and dielectric layers 322A and 322B may be a molding compound such as an epoxy molding compound (EMC). Dielectric layer 322A and dielectric layer 322B can be formed by lamination process, coating process or similar process.

[0177] In some embodiments, the materials of conductive layers 324A and 324B (e.g., each of conductive layers 324a, 324b, and 324c) include aluminum, titanium, copper, nickel, tungsten, and / or alloys thereof. Conductive layers 324A and 324B can be formed by forming conductive material layers via a lamination process, a deposition process, or a similar process, followed by a patterning process. The patterning process may include dry etching, wet etching, or a combination thereof. In some embodiments, the formation and material of each of conductive layers 324A and 324B are related to… Figures 1 to 3 The processes and materials used to form the metallization layers ML1 to ML3 described herein are the same or similar.

[0178] Despite Figure 12A The diagram shows three conductive layers and three dielectric layers for each of wiring portions 320A and 320B, but this disclosure is not limited thereto. In some alternative embodiments, the number of dielectric layers 322A and 322B and the number of conductive layers 324A and 324B may be adjusted according to design requirements. In some embodiments, the total number of conductive and dielectric layers included in each of wiring portions 320A and 320B may be one to eight layers in total. In some embodiments, the number of conductive and dielectric layers in wiring portion 320A is equal to the number of conductive and dielectric layers in wiring portion 320B. Alternatively, the total number of conductive and dielectric layers in wiring portion 320A may differ from the total number of conductive and dielectric layers in wiring portion 320B.

[0179] In some embodiments, the thickness of the core portion 310 is approximately in the range of 30 μm to 2000 μm. In some embodiments, in the Z direction, the thickness of each of the dielectric layers 322A and 322B is approximately in the range of 5 μm to 50 μm, and the thickness of each of the conductive layers 324A and 324B is approximately in the range of 2 μm to 50 μm. In some embodiments, the thickness of the outermost conductive layer (e.g., conductive layer 324c) may be greater than the thickness of the inner conductive layers (e.g., conductive layers 324a and 324b).

[0180] continue Figure 12AIn some embodiments, a solder resist layer 330A is formed on the outermost surface of the wiring portion 320A away from the core portion 310, and a solder resist layer 330B is formed on the outermost surface of the wiring portion 320B away from the core portion 310. For example, the outermost conductive layers (e.g., conductive layer 324c) of the wiring portions 320A and 320B are exposed in an accessible manner through the outermost surfaces of the solder resist layers 330A and 330B, respectively. For example, the outermost conductive layer 324c of the wiring portion 320A is substantially coplanar with and substantially flush with the outermost surface of the solder resist layer 330A, and the outermost conductive layer 324c of the wiring portion 320B is substantially coplanar with and substantially flush with the outermost surface of the solder resist layer 330B.

[0181] In some embodiments, substrate 300A has a first region 302 and a second region 304 surrounding the first region 302. See also Figure 12A and Figure 12B For example, the first region 302 is connected to (e.g., in contact with) the second region 304. In some embodiments, the first region is referred to as a device region, which is provided with a semiconductor component, such as a semiconductor device P1, formed or disposed later. In some embodiments, the second region is referred to as a peripheral region surrounding the device region, which is provided with a non-semiconductor component, such as a connection structure (e.g., a socket or the like), a support structure (e.g., a reinforcement or the like), a heat sink, a combination thereof, or the like. In some embodiments, the substrate 300A is considered as a circuit structure (e.g., an organic substrate in which a circuit system structure is embedded, such as a PCB).

[0182] like Figure 12A and Figure 12B As shown, in some embodiments, the support structure 10 is located inside the substrate 300A. For example, a portion of each layer of the conductive layer 324A (e.g., conductive layers 324a to 324c) of the wiring portion 320A located in the second region 304 of the substrate 300, a portion of the through-hole 314 of the core portion 310, and a portion of each layer of the conductive layer 324B (e.g., conductive layers 324a to 324c) of the wiring portion 320B together constitute the support structure 10. In some embodiments, the support structure 10 penetrates the wiring portion 320A, the core portion 310, and the wiring portion 320B. In other words, the support structure 10 can penetrate the substrate 300A. Figure 12A As shown, for example, the thickness T2 of the support structure 10 is substantially equal to the thickness T1 of the substrate 300A. This disclosure is not limited thereto; alternatively, the support structure in this disclosure may not penetrate the substrate. In this disclosure, the support portion 10 may be referred to as a metallic or conductive support structure.

[0183] In some embodiments, the support structure 10 is electrically isolated from portions of wiring portions 320A, 320B included in the substrate 300A and portions of core portion 310, which are used to provide wiring functionality to a later-formed or later-placed semiconductor component disposed within the first region 302. That is, there is no electrical impact (e.g., negative impacts such as noise or the like) on the later-formed or later-placed semiconductor component caused by the support structure 10. Alternatively, the support structure 10 may be electrically coupled to other portions of wiring portions 320A, 320B included in the substrate 300A and other portions of core portion 310, which are not used to provide wiring functionality to a later-formed or later-placed semiconductor component disposed within the first region 302. That is, the support structure 10 may be electrically floated or electrically grounded through the substrate 300A. However, this disclosure is not limited thereto; alternatively, the support structure 10 may be electrically isolated from the substrate 300A. That is, the support structure 10 may be electrically floated or electrically grounded by itself.

[0184] For example, such as Figure 12A and Figure 16A As shown, the support structure 10 includes a first portion 11, a second portion 12, and a third portion 13 located between and electrically connected to the first portion 11 and the second portion 12. In some embodiments, the first portion 11 includes portions of a wiring portion 320A located in a second region of the substrate 300A, such as a portion of conductive layer 324a, a portion of conductive layer 324b, and a portion of conductive layer 324c included in the wiring portion 320A. In some embodiments, the second portion 12 includes portions of a wiring portion 320B located in a second region of the substrate 300A, such as a portion of conductive layer 324a, a portion of conductive layer 324b, and a portion of conductive layer 324c included in the wiring portion 320B. In some embodiments, the third portion 13 includes portions of a core portion 310 located in the second region of the substrate 300A, such as a through-hole 324 included in the core portion 310. For example, as... Figure 12B As shown, the support structure 10 is in the form of a complete (continuous) frame ring. In some embodiments, at least one or all of the portions of conductive layers 324a to 324c in the first portion 11 are in the form of a complete (continuous) frame ring. In some embodiments, at least one or all of the portions of conductive layers 324a to 324c in the second portion 12 are in the form of a complete (continuous) frame ring. In some embodiments, the third portion 13 includes one or more through holes 314, wherein such through holes 314 are in the form of a complete (continuous) frame ring.

[0185] For example, such as Figure 12A and Figure 16A As shown, the sidewalls of the support structure 10 are wavy. In some embodiments, the cross-sectional shape of the conductive layers 324a to 324c included in the support structure 10 includes a T-shape.

[0186] However, this disclosure is not specifically limited thereto. In some alternative embodiments, the sidewalls of the support structure are non-wavy. For example, support structure 10a includes continuous and vertical sidewalls, see [link to relevant documentation]. Figure 16B In some embodiments, Figure 16B The cross-sectional shape of the conductive layers 324a to 324c included in the support structure 10a includes a rectangular shape.

[0187] In an alternative embodiment, support structure 10b includes discontinuous and flat sidewalls. For example, support structures 10b and 10c each include sidewalls comprising a continuous and inclined sidewall of a first portion 11, a continuous and inclined sidewall of a second portion 12, and a continuous and vertical sidewall of a third portion 13, see [link to relevant documentation]. Figure 16C and Figure 16D In some embodiments, Figure 16C The cross-sectional shape of the conductive layers 324a to 324c in the first portion 11 of the support structure 10b includes a trapezoidal shape, the trapezoidal shape having dimensions that gradually decrease from the core portion 310 toward the solder resist layer 330A, and Figure 16C The cross-sectional shape of the conductive layers 324a to 324c in the second portion 12 of the support structure 10b includes a trapezoidal shape, the trapezoidal shape having dimensions that gradually decrease from the core portion 310 toward the solder resist layer 330B. In some embodiments, Figure 16D The cross-sectional shape of the conductive layer 324a to conductive layer 324c in the first part 11 of the support structure 10c includes a trapezoidal shape, the trapezoidal shape having dimensions that gradually increase from the core part 310 toward the solder resist layer 330A, and Figure 16D The cross-sectional shape of the conductive layer 324a to conductive layer 324c in the second part 12 of the support structure 10c includes a trapezoidal shape, the trapezoidal shape having a size that gradually increases from the core part 310 toward the solder resist layer 330B.

[0188] Return to reference Figure 12A and Figure 16AIn some embodiments, for each wiring layer in the wiring portion 320A of the substrate 300A, a first ratio A is given to the total volume of the conductive portion (e.g., one of conductive layers 324a to 324c) within the first region 302 and the total volume of the conductive portion (e.g., one of conductive layers 324a to 324c) and a corresponding dielectric portion (e.g., a corresponding portion of dielectric layers 322a to 322c) of the wiring layer within the first region 302, and a second ratio B is given to the total volume of the conductive portion (e.g., one of conductive layers 324a to 324c) within the second region 304 and the corresponding dielectric portion (e.g., a corresponding portion of dielectric layers 322a to 322c) of the wiring layer within the second region 304, wherein the first ratio A is less than the second ratio B. In some embodiments, the first ratio A is less than 80%. For example, the first ratio A is approximately greater than or substantially equal to 60% and approximately less than 80%. In some embodiments, the second ratio B is greater than or substantially equal to 80%. For example, the second ratio B is approximately greater than or substantially equal to 80% and approximately less than or substantially equal to 100%.

[0189] In some embodiments, for each wiring layer in the wiring portion 320B of the substrate 300A, a third ratio of the total volume of the conductive portion (e.g., one of conductive layers 324a to 324c) in the first region 302 to the total volume of the conductive portion (e.g., one of conductive layers 324a to 324c) and a corresponding dielectric portion (e.g., a corresponding portion of dielectric layers 322a to 322c) of the wiring layer in the first region 302 is C, and a fourth ratio of the total volume of the conductive portion (e.g., one of conductive layers 324a to 324c) in the second region 304 to the total volume of the conductive portion (e.g., one of conductive layers 324a to 324c) and a corresponding dielectric portion (e.g., a corresponding portion of dielectric layers 322a to 322c) of the wiring layer in the second region 304 is D, wherein the third ratio C is less than the fourth ratio D. In some embodiments, the third ratio C is less than 80%. For example, the third ratio C is approximately greater than or substantially equal to 60% and approximately less than 80%. In some embodiments, the fourth ratio D is greater than or substantially equal to 80%. For example, the fourth ratio D is approximately greater than or substantially equal to 80% and approximately less than or substantially equal to 100%.

[0190] In some embodiments, for the core portion 310 of substrate 300A, a fifth ratio of the total volume of conductive portions (e.g., vias 314) within the first region 302 to the total volume of the conductive portions (e.g., vias 314) and a corresponding dielectric portion (e.g., core dielectric layer 312) within the first region 302 is E, and a sixth ratio of the total volume of conductive portions (e.g., vias 314) within the second region 304 to the total volume of the conductive portions (e.g., vias 314) and a corresponding dielectric portion (e.g., core dielectric layer 312) within the second region 304 is F, wherein the fifth ratio E is less than the sixth ratio F. In some embodiments, the fifth ratio E is less than 80%. For example, the fifth ratio E is approximately greater than or substantially equal to 60%, and approximately less than 80%. In some embodiments, the sixth ratio F is greater than or substantially equal to 80%. For example, the sixth ratio F is approximately greater than or substantially equal to 80%, and approximately less than or substantially equal to 100%. In the embodiment where the sixth ratio F is substantially equal to 100%, there is no dielectric in the second region 304.

[0191] In one embodiment, the first ratio A, the third ratio C, and the fifth ratio E are substantially equal to each other. In an alternative embodiment, the first ratio A, the third ratio C, and the fifth ratio E are partially or entirely different from each other. In one embodiment, the wiring layers included in wiring portion 310A have the same first ratio A. Alternatively, the wiring layers included in wiring portion 310A may have partially or entirely different first ratios A. In one embodiment, the wiring layers included in wiring portion 310B have the same third ratio C. Alternatively, the wiring layers included in wiring portion 310B may have partially or entirely different third ratios C.

[0192] Similarly, in one embodiment, the second ratio B, the fourth ratio D, and the sixth ratio F are substantially equal to each other. In an alternative embodiment, the second ratio B, the fourth ratio D, and the sixth ratio F are partially or entirely different from each other. In one embodiment, the wiring layers included in wiring portion 310A have the same second ratio B. Alternatively, the wiring layers included in wiring portion 310A may have partially or entirely different second ratios B. In one embodiment, the wiring layers included in wiring portion 310B have the same fourth ratio D. Alternatively, the wiring layers included in wiring portion 310B may have partially or entirely different fourth ratios D.

[0193] In one embodiment, substrate 300A includes active and / or passive devices (not shown) that can be used to generate a functional design of package structure 1000A, such as transistors, capacitors, resistors, combinations thereof, or the like. The active and / or passive devices can be formed using any suitable method. However, this disclosure is not limited thereto; in alternative embodiments, substrate 300A does not substantially have active and / or passive devices.

[0194] Reference Figure 13A and Figure 13B In some embodiments, according to Figure 15 In step S20, the semiconductor device P1 is placed above and mounted on the substrate 300A within the first region 302. For example, the semiconductor device P1 is picked up and placed on the substrate 300A, and then bonded to the substrate 300A by flip-chip bonding. In some embodiments, the semiconductor device P1 is electrically coupled to the substrate 300A by connecting a conductive terminal 150B to a wiring portion 320A (e.g., the outermost conductive layer exposed by the solder mask layer 330A (e.g., conductive layer 324c)). For example, the semiconductor device P1 is mechanically and electrically connected to the substrate 300A via the conductive terminal 150B. In some embodiments, the semiconductor device P1 is electrically isolated from the support structure 10. Although for illustrative purposes, Figure 13A and Figure 13B Only one semiconductor device P1 is shown, but the number of semiconductor devices P1 may be one or more depending on the requirements and design layout.

[0195] In an alternative embodiment, before mounting the semiconductor device P1 onto the substrate 300A, a plurality of solder regions (not shown) may be formed on the outermost conductive layer (e.g., conductive layer 324c) of the wiring portion 320A exposed by the solder resist layer 330A. The solder regions may be pre-solder paste formed by printing or similar techniques. In some embodiments, the material of the solder regions may include lead-free solder materials (e.g., Sn-Ag-based or Sn-Ag-Cu-based materials) with or without additional impurities (e.g., Ni, Bi, Sb, Au, or the like).

[0196] In some embodiments, such as Figure 13A As shown, an underfill material 400 is formed on the substrate 300A to fill the gap between the semiconductor device P1 and the substrate 300A, and to wrap the sidewalls of the conductive terminal 150B. Due to the presence of the underfill material 400, the bonding strength between the semiconductor device P1 and the substrate 300A is enhanced, thereby ensuring the electrical coupling between the semiconductor device P1 and the substrate 300A. The formation of the underfill material 400 and the material can be compatible with... Figure 6The process and materials used to form the bottom filler 160 described herein are the same or similar, and therefore will not be repeated here for the sake of brevity. In an alternative embodiment, the bottom filler 400 may be omitted.

[0197] In embodiments where the passivation layer 140B, the under-bump metal pattern 124, and the conductive terminal 150B are omitted, the semiconductor device P1 can be mounted to the substrate 300A via hybrid bonding (including metal-to-metal bonding and dielectric-to-dielectric bonding). This disclosure is not limited thereto.

[0198] In other alternative embodiments, before mounting the semiconductor device P1 onto the substrate 300A, the semiconductor device P1 may be mounted to an interposer (not shown), wherein the interposer is further mounted to the substrate 300A via a plurality of additional conductive connections. For example, such an interposer is sandwiched between the semiconductor device P1 and the substrate 300A. The interposer may provide further wiring functionality to the semiconductor device P1, which may be or may include a substrate type having substrate vias with or without additional wiring layers, or may be or may include a type with a redistributed wiring structure, but this disclosure is not limited thereto. In embodiments including an interposer, the manufactured package structure is referred to as a chip-on-wafer-on-substrate (CoWoS) package. Additional conductive connectors may be microbumps, metal pillars, bumps formed by electroless nickel-electroless palladium-immersion gold (ENEPIG), controlled-collapse chip interconnect (C4) bumps (e.g., which may have a size of about 80 μm, but are not limited to), ball grid array (BGA) bumps or balls (e.g., which may have a size of about 400 μm, but are not limited to), solder balls, or the like. This disclosure is not limited thereto.

[0199] Reference Figure 14A and Figure 14B In some embodiments, according to Figure 15In step S30, an annular structure 520 is provided and then bonded to a substrate 300A within a second region 304. For example, the bottom surface 520b of the annular structure 520 is adhered to the shown top surface of the substrate 300A using an adhesive 510, wherein the annular structure 520 surrounds the semiconductor device P1. In some embodiments, in a plan view (e.g., an XY plane), the annular structure 520 is in the form of a complete (continuous) frame ring having an inner sidewall (not labeled) facing the semiconductor device P1 and an outer sidewall (not labeled) opposite the inner sidewall. For example, in a plan view, the annular structure 520 is close to and separated from the semiconductor device P1 by a gap. At this point, the package structure 1000A has been manufactured. The package structure 1000A may be referred to as a flip-chip package (having an InFO package). Due to the presence of the annular structure 520, the loading effect of the substrate 300A (e.g., between the first region 302 and the second region 304) is suppressed, thereby achieving warpage control of the package structure 1000A.

[0200] In some embodiments, the material of the ring structure 520 includes a conductive material, a thermally conductive material, or a combination of conductive and thermally conductive materials. In some embodiments, the material of the ring structure 520 includes a metal or metal alloy, such as copper, aluminum, alloys thereof, combinations thereof, or the like. In some embodiments, the adhesive 510 includes a conductive adhesive, a thermally conductive adhesive, or a combination of conductive and thermally conductive adhesive. The adhesive 510 may also contain fillers. For example, fillers include metal fillers or metal alloy fillers. The ring structure 520 is electrically and thermally connected to the substrate 300A via the adhesive 510. Figure 14A As shown, in some embodiments, after the annular structure 520 is mounted onto the substrate 300A, the top surface (e.g., 170t / 160t) of the semiconductor device P1 is lower than the top surface 520t of the annular structure 520 at a distance D1, wherein the top surface 520t is opposite to the bottom surface 520b in the Z direction. In this way, the annular structure 520 further protects the semiconductor device P1 from physical damage during transport, transfer, and / or operation. In some embodiments, the annular structure 520 is electrically isolated from the semiconductor device P1. That is, the annular structure 520 will not cause any electrical effects on the semiconductor device P1 (e.g., negative effects such as noise or the like).

[0201] In such Figure 14A and Figure 14BIn some embodiments of the package structure 1000A shown, the positioning position of the annular structure 520 overlaps with the positioning position of the support structure 10 in a vertical projection along direction Z onto the substrate 300A. In some embodiments, the width (e.g., lateral or horizontal dimension) W1 of the annular structure 520 is substantially equal to the width (e.g., lateral or horizontal dimension) W2 of the support structure 10. Based on the configuration of the annular structure 520 and the support structure 10, CTE mismatch between the annular structure 520 and the substrate 300A is further suppressed, thus ensuring better warpage control of the package structure 1000A. This disclosure is not limited thereto; the support structure 10 may adopt other possible profiles or lateral dimensions (in the cross-sectional view), as long as the positioning position of the annular structure 520 overlaps with the positioning position of the support structure 10. For example, as another alternative, the width of the support structure may be greater than or less than the width of the annular structure.

[0202] Figure 17 This is a schematic cross-sectional view illustrating a package structure 1000B according to an alternative embodiment of the present disclosure. Elements similar to or substantially the same as those described above will use the same reference numerals, and certain details or descriptions of the same elements (e.g., formation and materials) and their relationships (e.g., relative positioning configuration and electrical connections) will not be repeated here. Reference Figure 17 In some embodiments, the packaging structure 1000B is constructed according to... Figure 15 Step S40 follows as follows Figure 14A The process described herein is used to manufacture a cover 540 and to mount the cover 540 onto an annular structure 520.

[0203] For example, the bottom surface 540b of the cover 540 is adhered to the top surface 520t of the annular structure 520 by an adhesive 530, wherein the cover 540, adhesive 530, annular structure 520, adhesive 510, and substrate 300A together define a receiving space (not labeled) surrounding the semiconductor device P1. In some embodiments, in a plan view (not shown), the cover 540 is in the form of a solid block having sidewalls substantially aligned in the Z direction with the outer sidewalls of the substrate 300A. The cover 540 may be referred to as a heat dissipation element of the package structure 1000B. Alternatively, the cover 540, annular structure 520, and the adhesive 530 therebetween may be referred to together as a heat dissipation element of the package structure 1000B. Due to the presence of such a heat dissipation element, the heat dissipation of the semiconductor device P1 in the package structure 1000B is improved.

[0204] Furthermore, thermal interface material can be coated onto the semiconductor device P1 to facilitate heat dissipation in the package structure 1000B. For example... Figure 17As shown in the packaging structure 1000B, a thermal interface material 550 is located between the indicated top surface (e.g., surface 170t / surface 160t) of the semiconductor device P1 and the bottom surface 540b of the cover 540 to thermally couple the semiconductor device P1 to the cover 540, which further helps to dissipate heat from the semiconductor device P1 to the cover 540.

[0205] The thermal interface material 550 may comprise any suitable thermally conductive material, such as a polymer having a good thermal conductivity (which may be between about 3 W / (m·K) and about 10 W / (m·K) or higher), and may be formed on the indicated top surface (e.g., surface 170t / surface 160t) of the semiconductor device P1 by liquid dispensing. In some embodiments, the thermal interface material 550 is a thin-film type thermal interface material, such as a graphene sheet, carbon nanotube sheet, or the like, and is formed on the indicated top surface (e.g., surface 170t / surface 160t) of the semiconductor device P1 by lamination or similar means. This disclosure does not specifically limit the thickness of the thermal interface material 550, as long as the thermal interface material 550 is thick enough to adequately dissipate heat from the semiconductor device P1 to the cover 540.

[0206] However, this disclosure is not limited thereto; alternatively, the thermal interface material 550 may be omitted, wherein the cover 540 is separated from the semiconductor device P1 (e.g., its indicated top surface (e.g., surface 170t / surface 160t)) by a gap (e.g., an air gap). In some embodiments, the material of the cover 540 includes a conductive material, a thermally conductive material, or a combination of conductive and thermally conductive materials. In some embodiments, the material of the cover 540 includes a metal or metal alloy, such as copper, aluminum, alloys thereof, combinations thereof, or the like. In some embodiments, the adhesive 530 includes a conductive adhesive, a thermally conductive adhesive, or a combination of conductive and thermally conductive adhesive. The adhesive 530 may also contain fillers. For example, the fillers include metal fillers or metal alloy fillers. The material of the adhesive 510 may be the same as the material of the adhesive 530. Alternatively, the material of the adhesive 510 may be different from the material of the adhesive 530. Furthermore, the material of the annular structure 520 may be the same as the material of the cover 540. Alternatively, the material of the annular structure 520 may be different from the material of the cover 540.

[0207] The cover 540 is electrically and thermally connected to the annular structure 520 via adhesive 530, and further electrically and thermally connected to the substrate 300A via the annular structure 520 and adhesive 510. In some embodiments, the cover 540, adhesive 530, annular structure 520, and adhesive 510 together constitute an electromagnetic interference (EMI) shielding structure for the semiconductor device P1 (which is electrically connected to the substrate 300A). Based on this EMI shielding structure, the effects caused by electromagnetic waves generated by other electronic components located outside the package structure 1000B can be suppressed, thereby enhancing the reliability and performance of the package structure 1000B.

[0208] In some embodiments, the thickness of the annular structure 520 is greater than the thickness of the cover 540 when measured along the Z direction. However, this disclosure is not limited thereto; alternatively, the thickness of the annular structure 520 may be less than or substantially equal to the thickness of the cover 540 when measured along the Z direction.

[0209] In some embodiments, the package structure 1000B further includes a plurality of conductive terminals 600 disposed on the bottom surface of the substrate 300A, such as... Figure 17 As shown. In some embodiments, some of the conductive terminals 600 are electrically connected to the semiconductor device P1 via the substrate 300A. In some embodiments, some of the conductive terminals 600 are electrically connected to the support structure 10. The conductive terminals 600 can be used to physically and electrically connect the substrate 300A and / or the support structure 10 to other devices, packages, connection components, and the like. In some embodiments, the conductive terminals 600 are referred to as conductive connectors of the package structure 1000B (acting as conductive input / output terminals of the semiconductor device P1) for providing physical and / or electrical connections to external components. In alternative embodiments, multiple conductive terminals 600 may also be used in the package structure 1000A.

[0210] The number of conductive terminals 600 is not limited to the embodiments described and can be selected based on requirements and design layout. Conductive terminals 600 may be microbumps, metal pillars, bumps formed by electroless nickel-palladium immersion gold (ENEPIG), controlled-collapse chip connection (C4) bumps (e.g., which may have a size of, but is not limited to, about 80 μm), ball grid array (BGA) bumps or balls (e.g., which may have a size of, but is not limited to, about 400 μm), solder balls, or the like. This disclosure is not limited thereto. When solder is used, the solder may comprise eutectic solder or non-eutectic solder. The solder may contain lead or be lead-free, and may contain Sn-Ag, Sn-Cu, Sn-Ag-Cu, or the like. In alternative embodiments, conductive terminals 600 may be omitted from package structure 1000B.

[0211] In other embodiments, multiple additional semiconductor devices (not shown) are employed to form on at least one of the shown top or bottom surfaces of substrate 300A in package structures 1000A and 1000B. The additional semiconductor devices can be used as surface devices to provide additional functionality or programming to semiconductor device P1. For example, the additional semiconductor devices include surface mount devices (SMDs) or integrated passive devices (IPDs), which include passive devices intended to be connected to and engaged with semiconductor device P1, such as resistors, inductors, capacitors, jumpers, combinations thereof, or the like. For example, the additional semiconductor devices are electrically connected to semiconductor device P1 via substrate 300A. The number of additional semiconductor devices is not limited and can be selected based on requirements and design layout.

[0212] Figure 18 This is a schematic cross-sectional view illustrating a package structure 2000A according to some embodiments of the present disclosure. Figures 19A to 19D This is an enlarged schematic cross-sectional view according to some embodiments of the present disclosure, shown in Figure 18 Various embodiments of the support structure in the dashed area V shown in the figure. Figure 20 This is a schematic cross-sectional view illustrating a package structure 2000B according to an alternative embodiment of the present disclosure. Components similar to or substantially the same as those described above will use the same reference numerals, and certain details or descriptions of the same components (e.g., formation and materials) and their relationships (e.g., relative positioning configuration and electrical connections) will not be repeated here.

[0213] In some embodiments, Figure 18 The 2000A's packaging structure is similar to Figure 14A and Figure 14B The package structure 1000A differs from the package structure 2000A in that, in the package structure 2000A, the support structure 10 is replaced by a support structure 20, wherein the support structure 20 includes a first portion 11 and a third portion 13 connected to the first portion 11. In other words, the support structure 20 does not include the second portion 12 of the support structure 10. For example, the support structure 20 does not penetrate the substrate 300A. For example, as... Figure 18 As shown, the thickness T2' of the support structure 20 is less than the thickness T1 of the substrate 300A. In some embodiments, the support structure 20 penetrates the wiring portion 320A and the core portion 310, wherein the wiring portion 320B does not have the support structure 20. The details of the first portion 11 and the third portion 13 of the support structure 20 are the same as previously described. Figure 12A , Figure 12B and Figure 16AThe first part 11 and the third part 13 of the support structure 10 described herein are the same, and the configuration of the support structure 20 and the ring structure 520 is the same as previously described. Figure 14A and Figure 14B The configurations of the support structure 10 and the annular structure 520 described herein are the same or similar; therefore, for the sake of brevity, they will not be repeated herein. In some embodiments, the width of the support structure 20 is substantially equal to the width of the annular structure 520. Alternatively, as another alternative, the width of the support structure 20 may be greater than or less than the width of the annular structure 520.

[0214] Similar to support structure 10, the sidewalls of support structure 20 are as follows: Figure 18 and Figure 19A The wavy form shown refers to the T-shaped cross-sectional shape of the conductive layers 324a to 324c included in the support structure 20. It should be understood that the support structure 20 can also be a modification of the support structure 10; see [link to relevant documentation]. Figure 19B Support structure 20a Figure 19C Support structure 20b and Figure 19D The supporting structure is 20c. For example, Figure 19B The support structure 20a includes continuous and vertical sidewalls, wherein the cross-sectional shape of the conductive layers 324a to 324c included in the support structure 20a includes a rectangular shape. For other examples, Figure 19C Support structure 20b and Figure 19D Each of the supporting structures 20c includes discontinuous and flat sidewalls, including in Figure 19C The cross-sectional shape of the conductive layers 324a to 324c in the first portion 11 of the support structure 20b includes a trapezoidal shape, the trapezoidal shape having dimensions that gradually decrease from the core portion 310 toward the solder resist layer 330A, and includes Figure 19D The cross-sectional shape of the conductive layer 324a to conductive layer 324c in the first part 11 of the support structure 20c includes a trapezoidal shape, the trapezoidal shape having dimensions that gradually increase from the core part 310 toward the solder resist layer 330A.

[0215] This disclosure is not limited thereto; the support structure 20 may adopt other possible contours or lateral widths (in the sectional view), as long as the positioning position of the annular structure 520 overlaps with the positioning position of the support structure 20.

[0216] In addition, a cover can be used for better heat dissipation. For example, Figure 20 The packaging structure of 2000B and Figure 18 The encapsulation structure 2000B is similar to that of 2000A; the difference is that encapsulation structure 2000B also includes adhesive 530, cover 540, thermal interface material 550, and multiple conductive terminals 600. For example... Figure 20 As shown in the encapsulation structure 2000B, in some embodiments, the cover 540 is adhered to the annular structure 520 by adhesive 530 and to the semiconductor device P1 by thermal interface material 550, and the conductive terminal 600 is connected to the substrate 300A opposite to the semiconductor device P1.

[0217] For example, a cover 540, adhesive 530, annular structure 520, adhesive 510, and substrate 300A together define an enclosure space (not labeled) surrounding the semiconductor device P1. The cover 540 (or bonded together with the annular structure 520 and the adhesive 530 therebetween) can be referred to as a heat dissipation element of the package structure 2000B. Based on this heat dissipation element, the heat dissipation of the semiconductor device P1 in the package structure 2000B is improved. In some embodiments, the cover 540, adhesive 530, annular structure 520, and adhesive 510 together constitute an EMI shielding structure for the semiconductor device P1 (electrically connected to the substrate 300A). Based on this EMI shielding structure, the effects of electromagnetic waves generated by other electronic components located outside the package structure 2000B can be suppressed, thereby enhancing the reliability and performance of the package structure 2000B.

[0218] Heat dissipation is further improved because the thermal interface material 550 thermally couples the cover 540 to the semiconductor device P1. However, the thermal interface material 550 may be omitted. In some embodiments, the conductive terminal 600 physically and electrically connects to the substrate 300A and / or the support structure 20 for further electrical connection to other devices, packages, connection components, and the like. However, the thermal interface material 550 and / or the conductive terminal 600 may be omitted. Details, formation, and materials of the adhesive 530, cover 540, thermal interface material 550, and conductive terminal 600 have been described. Figure 17 The details have been described in the previous section and will therefore not be repeated here for the sake of simplicity. In an alternative embodiment, multiple conductive terminals 600 may also be used in the package structure 2000A for further electrical connection to external components.

[0219] Figure 21 This is a schematic cross-sectional view illustrating a package structure 3000A according to some embodiments of the present disclosure. Figures 22A to 22D This is an enlarged schematic cross-sectional view according to some embodiments of the present disclosure, shown in Figure 21 Various embodiments of the support structure in the dashed area W shown in the figure. Figure 23 This is a schematic cross-sectional view illustrating a package structure 3000B according to an alternative embodiment of the present disclosure. Components similar to or substantially the same as those described above will use the same reference numerals, and certain details or descriptions of the same components (e.g., formation and materials) and their relationships (e.g., relative positioning configuration and electrical connections) will not be repeated herein.

[0220] In some embodiments, Figure 21 The 3000A's packaging structure is similar to Figure 14A and Figure 14B The package structure 1000A differs from the package structure 3000A in that, in the package structure 3000A, the support structure 10 is replaced by a support structure 30, wherein the support structure 30 includes a second portion 12 and a third portion 13 connected to the second portion 12. In other words, the support structure 30 does not include the first portion 11 of the support structure 10. For example, the support structure 30 does not penetrate the substrate 300A. For example, as... Figure 21 As shown, the thickness T2” of the support structure 30 is less than the thickness T1 of the substrate 300A. In some embodiments, the support structure 30 penetrates the wiring portion 320B and the core portion 310, wherein the wiring portion 320A does not have the support structure 30. The details of the second portion 12 and the third portion 13 of the support structure 30 are the same as previously described. Figure 12A , Figure 12B and Figure 16A The second part 12 and the third part 13 of the support structure 10 described herein are the same, and the configuration of the support structure 30 and the ring structure 520 is the same as previously described. Figure 14A and Figure 14B The configurations of the support structure 10 and the annular structure 520 described herein are the same or similar; therefore, for the sake of brevity, they will not be repeated herein. In some embodiments, the width of the support structure 30 is substantially equal to the width of the annular structure 520. Alternatively, as another alternative, the width of the support structure 30 may be greater than or less than the width of the annular structure 520.

[0221] Similar to support structure 10, the sidewalls of support structure 30 are as follows: Figure 21 and Figure 22A The wavy form shown refers to the T-shaped cross-sectional shape of the conductive layers 324a to 324c included in the support structure 30. It should be understood that the support structure 30 can also be a modification of the support structure 10; see [link to relevant documentation]. Figure 22B Support structure 30a Figure 22C Support structure 30b and Figure 22D The supporting structure is 30c. For example, Figure 22B The support structure 30a includes continuous and vertical sidewalls, wherein the cross-sectional shape of the conductive layers 324a to 324c included in the support structure 30a includes a rectangular shape. For other examples, Figure 22C Support structure 30b and Figure 22D Each of the supporting structures 30c includes discontinuous and flat sidewalls, including in Figure 22CThe cross-sectional shape of the conductive layers 324a to 324c in the second part 12 of the support structure 30b includes a trapezoidal shape, the trapezoidal shape having dimensions that gradually decrease from the core portion 310 toward the solder resist layer 330B, and includes Figure 22D The cross-sectional shape of the conductive layer 324a to conductive layer 324c in the second part 12 of the support structure 30c includes a trapezoidal shape, said trapezoidal shape having dimensions that gradually increase from the core portion 310 toward the solder resist layer 330B. This disclosure is not limited thereto; the support structure 30 may adopt other possible contours or lateral widths (in the cross-sectional view), as long as the positioning position of the annular structure 520 overlaps with the positioning position of the support structure 30.

[0222] In addition, a cover can be used for better heat dissipation. For example, Figure 23 The 3000B packaging structure and Figure 21 The package structure 3000B is similar to that of the 3000A; the difference is that the package structure 3000B also includes an adhesive 530, a cover 540, a thermal interface material 550, and multiple conductive terminals 600. For example... Figure 23 As shown in the encapsulation structure 3000B, in some embodiments, a cover 540 is adhered to an annular structure 520 by an adhesive 530 and to a semiconductor device P1 by a thermal interface material 550, and a conductive terminal 600 is connected to a substrate 300A opposite to the semiconductor device P1 for further electrical connection to external components. In some alternative embodiments, the thermal interface material 550 and / or the conductive terminal 600 may be omitted. Details, formation, and materials of the adhesive 530, cover 540, thermal interface material 550, and conductive terminal 600 are described in [the original text]. Figure 17 The details have been described in the previous section and will not be repeated here for the sake of simplicity. In other alternative embodiments, multiple conductive terminals 600 may also be used in the package structure 3000A.

[0223] In alternative embodiments, the width of the support structure in this disclosure may be greater than or less than the width of the annular structure. In various embodiments, Figure 24A and Figure 24B These are schematic cross-sectional views and schematic plan views of the 4000A package structure. Figure 25 This is a schematic cross-sectional view of the 4000B package structure. In various embodiments, Figure 26A and Figure 26B These are schematic cross-sectional views and schematic plan views of the 5000A package structure. Figure 27 This is a schematic cross-sectional view of the 5000B package structure. Components similar to or substantially the same as those described above will use the same reference numerals, and certain details or descriptions of the same components (e.g., formation and materials) and their relationships (e.g., relative positioning configuration and electrical connections) will not be repeated here.

[0224] In some embodiments, Figure 24A and Figure 24B The 4000A's packaging structure is similar to Figure 14A and Figure 14B The package structure 4000A differs from the package structure 4000A in that the annular structure 520 is replaced by an annular structure 520A, wherein the width W1' of the annular structure 520A is smaller than the width W2 of the support structure 10. In some embodiments, in a vertical projection along the direction Z onto the substrate 300A, the positioning position of the annular structure 520A completely overlaps (e.g., falls completely within) the positioning position of the support structure 10. Furthermore, a cover (e.g., cover 540) may be used for better heat dissipation, and multiple conductive terminals (e.g., conductive terminals 600) may be used for further electrical connection to external components, see [link to relevant documentation]. Figure 25 The package structure 4000B is used. In other alternative embodiments, multiple conductive terminals (e.g., conductive terminals 600) may also be used in the package structure 4000A.

[0225] In some embodiments, Figure 26A and Figure 26B The 5000A's packaging structure is similar to Figure 14A and Figure 14B The package structure 5000A differs from the previous one in that, in the package structure 5000A, the annular structure 520 is replaced by an annular structure 520B, wherein the width W1” of the annular structure 520B is greater than the width W2 of the support structure 10. In some embodiments, in the vertical projection along the direction Z onto the substrate 300A, the positioning position of the support structure 10 completely overlaps (e.g., falls completely within) the positioning position of the annular structure 520A. Furthermore, a cover (e.g., cover 540) may be used for better heat dissipation, and multiple conductive terminals (e.g., conductive terminals 600) may be used for further electrical connection to external components, see [link to relevant documentation]. Figure 27 The package structure 5000B is an example. In other alternative embodiments, multiple conductive terminals (e.g., conductive terminals 600) may also be used in the package structure 5000A.

[0226] Alternatively, the width of the annular structure 520 may remain constant, while the width of the support structure 10 may be modified (e.g., reduced or increased compared to the width W2), as long as the positioning of the annular structure 520 overlaps with the positioning of the support structure 10. This disclosure is not limited thereto.

[0227] Figure 29This is a schematic cross-sectional view illustrating a package structure 7000 according to some embodiments of the present disclosure. Elements similar to or substantially the same as those described above will use the same reference numerals, and certain details or descriptions of the same elements (e.g., formation and materials) and their relationships (e.g., relative positioning configuration and electrical connections) will not be repeated herein. In some embodiments, Figure 29 The packaging structure of 7000 is similar to Figure 14A and Figure 14B The package structure 1000A differs from the package structure 7000 in that semiconductor device P1 is replaced by semiconductor device P3. Semiconductor device P3 is similar to semiconductor device P1; however, semiconductor device P3 also includes multiple conductive pillars 180, multiple conductive terminals 190, and a package body 800. The conductive pillars 180 and conductive terminals 190, encapsulated in an insulating package body 170, are used to electrically connect semiconductor dies 230 and 240 to the package body 800.

[0228] Reference Figure 29 In some embodiments, conductive posts 180 are formed on the redistribution wiring structure 110 (e.g., on the side where the outermost surface S110t is located). In some embodiments, conductive posts 180 may be integrated fan-out (InFO) vias. Figure 29 As shown, the conductive pillar 180 is physically connected to the metallization layer ML3 of the redistributed wiring structure 110 via a bump under-bump metal pattern 126 formed on the dielectric layer 118 and extending into a plurality of openings O7 formed in the dielectric layer 118, such that the conductive pillar 180 is electrically connected to the redistributed wiring structure 110. In some embodiments, the bump under-bump metal pattern 126 is exposed by the passivation layer 140A through a plurality of openings O8 formed in the passivation layer 140A. The formation and material of the bump under-bump metal pattern 126 are related to... Figure 3 The metal pattern 122 under the bump described herein is formed and made of a similar or identical material, and the formation of openings O7 and O8 is respectively similar to... Figures 1 to 4 The formation of openings O4 and O5 described herein is similar or identical, and therefore will not be repeated herein. In some embodiments, conductive posts 180 are arranged beside semiconductor dies 230 and 240 and positioned along the periphery of semiconductor device P3. The number of conductive posts 180 is not limited to... Figure 29 The attached diagram shows the figures, and the number of openings O7 and O8 can be adjusted based on requirements and design specifications.

[0229] In some embodiments, the conductive pillar 180 is formed by photolithography, plating, photoresist stripping, or any other suitable method. For example, plating processes may include electroplating, electroless plating, or similar processes. For example, the conductive pillar 180 may be formed by: forming a mask pattern (not shown) covering the redistributed circuit structure 110, the mask pattern having a plurality of openings exposing a metal pattern 126 under bumps formed in the passivation layer 140A; forming a metal material filling the openings and openings O8 formed in the mask pattern by electroplating or deposition to form the conductive pillar 180; and then removing the mask pattern. In one embodiment, the mask pattern may be removed, for example, using oxygen plasma or the like, by an acceptable ashing process and / or photoresist stripping process. In some embodiments, the material of the conductive pillar 180 may include a metallic material, such as copper or a copper alloy or the like.

[0230] However, this disclosure is not limited thereto. In an alternative embodiment, the conductive post 180 may be a pre-fabricated conductive post that can be picked up and placed on the redistribution wiring structure 110. Alternatively, the under-bump metal pattern 126 may be omitted.

[0231] Subsequently, in some embodiments, a plurality of conductive terminals 190 are formed on the surface 180t of the conductive post 180. For example, the conductive terminals 190 are bonded to the conductive post 180 by a soldering process. The material of the conductive terminals 190 may include solder balls or BGA balls. In some embodiments, such as Figure 29 As shown, conductive terminals 190 are electrically connected to the redistribution structure 110 via conductive posts 180 and under-bump metal patterns 126. That is, for example, some conductive terminals 190 are electrically connected to the semiconductor die 230 via the redistribution structure 110, corresponding conductive posts 180, and corresponding under-bump metal patterns 126, and some conductive terminals 190 are electrically connected to the semiconductor die 240 via the redistribution structure 110, corresponding conductive posts 180, and corresponding under-bump metal patterns 126.

[0232] In some embodiments, conductive pillars 180 are formed on the redistribution structure 110 before the semiconductor dies 230 and 240 are disposed above the redistribution structure 110. In an alternative embodiment, conductive pillars 180 are formed on the redistribution structure 110 after the semiconductor dies 230 and 240 are disposed above the redistribution structure 110. In some embodiments, the insulating encapsulation 170 is formed by a transfer molding process or a compression molding process followed by a CMP process, such that the surface 180t of the conductive pillars 180 is substantially coplanar with the surface 170t of the insulating encapsulation 170, such that... Figure 29 As shown.

[0233] like Figure 29 As shown, for example, a conductive post 180 is embedded inside an insulating enclosure 170, wherein a conductive terminal 190 is disposed on the surface 180t of the conductive post 180 exposed by the insulating enclosure 170. In some embodiments, the underfill material 160, the conductive post 180, and the semiconductor dies 230 and 240 are encapsulated in the insulating enclosure 170, wherein the surface 160t of the underfill material 160, the surface 180t of the conductive post 180, the back surface 230f of the semiconductor die 230, and the back surface 240f of the semiconductor die 240 are substantially flush with and coplanar with the surface 170t of the insulating enclosure 170 (e.g., exposed in an accessible manner through the surface 170t of the insulating enclosure 170).

[0234] In some embodiments, a package 800 is provided and bonded to a conductive post 180 via conductive terminals 190 exposed by an insulating encapsulation 170 for forming a semiconductor device P3.

[0235] In some embodiments, the package 800 includes a substrate 810, semiconductor dies 820a and 820b, bonding wires 830a and 830b, conductive pads 840 and 850, an insulating encapsulation 860, and bonding solder balls (not shown). Figure 29 As shown, for example, a semiconductor die 820a having a connecting film DA1 disposed thereon and a semiconductor die 820b having a connecting film DA2 disposed thereon are provided and disposed on a substrate 810. In some embodiments, the connecting film DA1 is located between the semiconductor die 820a and the substrate 810, and the connecting film DA2 is located between the semiconductor die 820a and the semiconductor die 820b. In some embodiments, due to the presence of the connecting films DA1 and DA2 respectively disposed between the semiconductor die 820a and the substrate 810 and between the semiconductor die 820a and the semiconductor die 820b, the semiconductor dies 820a and 820b are stably bonded to the substrate 810. In some embodiments, the connecting films DA1 and DA2 may be, for example, die bonding films, layers made of adhesive or epoxy resin, or the like.

[0236] For example, semiconductor dies 820a and 820b are mounted on one side of substrate 810 (e.g., surface S7). In some embodiments, semiconductor dies 820a and 820b may be logic chips (e.g., central processing units, microcontrollers, etc.), memory chips (e.g., dynamic random access memory (DRAM) chips, static random access memory (SRAM) chips, etc.), power management chips (e.g., power management integrated circuit (PMIC) chips), radio frequency (RF) chips, sensor chips, signal processing chips (e.g., digital signal processing (DSP) chips), front-end chips (e.g., analog front-end (AFE) chips, the like, or combinations thereof). For example, semiconductor dies 820a and 820b are DRAM chips, such as... Figure 29 As shown. In one embodiment, semiconductor die 820a and semiconductor die 820b may be the same. However, this disclosure is not limited thereto; in alternative embodiments, semiconductor die 820a and semiconductor die 820b may be different from each other. The number of each of semiconductor die 820a and semiconductor die 820b may be one or more, and this disclosure is not particularly limited thereto.

[0237] In some embodiments, bonding wires 830a and 830b are used to provide electrical connections between semiconductor dies 820a and 820b and a number of conductive pads 840 (e.g., bonding pads) located on the surface S7 of substrate 810. Due to the presence of bonding wires 830a and 830b, semiconductor dies 820a and 820b are electrically connected to substrate 810.

[0238] In some embodiments, an insulating encapsulation 860 is formed on the surface S7 of the substrate 810 to encapsulate semiconductor dies 820a, 820b, bonding wires 830a, 830b, and conductive pads 840, thereby protecting these components. In some embodiments, the material of the insulating encapsulation 860 is the same as that of the insulating encapsulation 170m / insulating encapsulation 170 or encapsulation 235, and therefore will not be described further herein. In one embodiment, the material of the insulating encapsulation 860 is different from that of the insulating encapsulation 170m / insulating encapsulation 170 or encapsulation 235, and this disclosure is not limited thereto.

[0239] In some embodiments, interconnects (not shown) or through insulator vias (not shown) embedded in the substrate 810 may be used to provide an electrical connection between conductive pads 840 and conductive pads 850 (e.g., bonding pads) located on another surface of the substrate 810 (e.g., surface S8 opposite surface S7 along direction Z). In some embodiments, in addition to some conductive pads 840 and bonding wires 830a, 830b, some conductive pads 850 are also electrically connected to semiconductor dies 820a and 820b via these through insulator vias or interconnects (not shown).

[0240] In some embodiments, the conductive pads 850 of the package 800 are electrically connected to the conductive posts 180 via conductive terminals 190 sandwiched between the conductive pads 850 and the conductive posts 180. In some embodiments, the redistribution wiring structure 110 is electrically connected to the substrate 810 of the package 800 via the conductive posts 180, conductive terminals 190, and conductive pads 850. In some embodiments, some of the conductive terminals 150A are electrically connected to the substrate 810 of the package 800 via the redistribution wiring structure 110, conductive posts 180, conductive terminals 190, and conductive pads 850. In some embodiments, semiconductor dies 230 and 240 are independently electrically connected to semiconductor dies 820a and 820b of the package 800 via the redistribution wiring structure 110, conductive posts 180, conductive terminals 190, conductive pads 850 and 840, and bonding wires 830a and 830b. In other words, for example, semiconductor dies 820a and 820b are electrically connected to semiconductor dies 230 and 240. In some embodiments, semiconductor device P3 is referred to as an InFO package with a PoP structure. Package structure 7000 may be referred to as a flip-chip package with a PoP InFO package.

[0241] Figure 30 This is a schematic cross-sectional view illustrating a package structure 8000A according to some embodiments of the present disclosure. Figure 31 This is a schematic cross-sectional view illustrating a package structure 8000B according to some embodiments of the present disclosure. Elements similar to or substantially the same as those described above will use the same reference numerals, and certain details or descriptions of the same elements (e.g., formation and materials) and their relationships (e.g., relative positioning configuration and electrical connections) will not be repeated herein. In some embodiments, Figure 30 The 8000A's packaging structure is similar to Figure 14A and Figure 14BThe package structure 1000A differs from the 8000A in that, in the package structure 8000A, substrate 300A is replaced by substrate 300B, wherein substrate 300B includes a core portion 310, wiring portions 320A', wiring portions 320B', solder mask layer 330A, and solder mask layer 330B. Details of the core portion 310, solder mask layer 330A, and solder mask layer 330B have been previously described. Figure 12A , Figure 12B and Figure 16A The above has been described in the text; therefore, for the sake of brevity, it will not be repeated in this article.

[0242] In some embodiments, wiring portions 320A' and 320B' are disposed on two opposite sides of the core portion 310, solder mask layer 330A is disposed on wiring portion 320A', and solder mask layer 330B is disposed on wiring portion 320B'. Wiring portions 320A' and 320B' are electrically coupled to each other through the core portion 310. Figure 30 As shown, for example, wiring portion 320A' and wiring portion 320B' each include only one wiring layer, such as a dielectric layer 322a and a conductive layer 324a disposed thereon. The formation, materials, and configuration of wiring portion 320A' and wiring portion 320B' are the same as previously described. Figure 12A , Figure 12B and Figure 16A The processes, materials, and configurations for forming wiring portions 320A and 320B described herein are similar or identical, and therefore, for the sake of brevity, will not be repeated herein. Furthermore, a cover (e.g., cover 540) may be used for better heat dissipation, and multiple conductive terminals (e.g., conductive terminal 600) may be used for further electrical connection to external components, see [link to relevant documentation]. Figure 31 The package structure 8000B is an example. In other alternative embodiments, multiple conductive terminals (e.g., conductive terminals 600) may also be used in the package structure 8000A.

[0243] In the above embodiments, substrates 300A and 300B are cored substrates or cored circuit substrates. However, this disclosure is not limited thereto; as another option, the substrates of this disclosure (e.g., substrates 300C, 300D, and 300E) may be coreless substrates or coreless circuit substrates.

[0244] Figure 32 This is a schematic cross-sectional view illustrating a package structure 9000A according to some embodiments of the present disclosure. Figure 33This is a schematic cross-sectional view illustrating a package structure 9000B according to some embodiments of the present disclosure. Elements similar to or substantially the same as those described above will use the same reference numerals, and certain details or descriptions of the same elements (e.g., formation and materials) and their relationships (e.g., relative positioning configuration and electrical connections) will not be repeated herein. In some embodiments, Figure 32 The 9000A's packaging structure is similar to Figure 14A and Figure 14B The package structure 1000A differs from the 9000A in that, in the package structure 9000A, substrate 300A is replaced by substrate 300C, wherein substrate 300C includes wiring portions 320A and 320B, solder mask layer 330A, and solder mask layer 330B. Details of wiring portions 320A and 320B, solder mask layer 330A, and solder mask layer 330B have been previously described. Figure 12A , Figure 12B and Figure 16A The above has been described in the text; therefore, for the sake of brevity, it will not be repeated in this article.

[0245] In such embodiments, support structure 10 is replaced by support structure 40, wherein support structure 40 includes a first portion 11 and a second portion 12 connected to the first portion 11. Details of the first portion 11 and the second portion 12 of support structure 40 are the same as previously described. Figure 12A , Figure 12B and Figure 16A The first part 11 and the second part 12 of the support structure 10 described herein are the same, and the configuration of the support structure 40 and the ring structure 520 is the same as previously described. Figure 14A and Figure 14B The configurations of the support structure 10 and the ring structure 520 described herein are the same or similar; therefore, for the sake of brevity, they will not be repeated herein. In some embodiments, wiring portion 320A is connected to (e.g., in contact with) wiring portion 320B, solder mask layer 330A is disposed on wiring portion 320A, and solder mask layer 330B is disposed on wiring portion 320B. That is, for example, wiring portion 320A and wiring portion 320B are directly electrically coupled to each other. Furthermore, a cover (e.g., cover 540) may be used for better heat dissipation, and multiple conductive terminals (e.g., conductive terminals 600) may be used for further electrical connection to external components, see [link to relevant documentation]. Figure 33 The package structure 9000B is used. In other alternative embodiments, multiple conductive terminals (e.g., conductive terminals 600) may also be used in the package structure 9000A.

[0246] like Figure 32 and Figure 33As shown, when measured along direction Z, the thickness T3 of the support structure 40 is substantially the same as the thickness (unmarked) of the substrate 300C. However, this disclosure is not limited thereto; alternatively, the thickness T3 of the support structure 40 may be less than the thickness of the substrate 300C.

[0247] In one embodiment, the support structure included in package structure 9000A and / or package structure 9000B may include only the first portion 11 or the second portion 12. In other words, if the support structure included in package structure 9000A and / or package structure 9000B includes only the first portion 11, the support structure may extend from the first outermost surface of substrate 300C into substrate 300C and may not be exposed in an accessible manner by the second outermost surface of substrate 300C. For example, the first outermost surface of substrate 300C is opposite to the second outermost surface of substrate 300C, and a semiconductor device P1 is disposed on the first outermost surface.

[0248] On the other hand, if the support structure included in package structure 9000A and / or package structure 9000B only includes the second part 12, the support structure can extend from the second outermost surface of substrate 300C into substrate 300C and can be exposed in an accessible manner without being exposed by the first outermost surface of substrate 300C. For example, the first outermost surface of substrate 300C is opposite to the second outermost surface of substrate 300C, and the semiconductor device P1 is disposed on the first outermost surface.

[0249] In addition, in some other embodiments, the support structure included in the package structure 9000A and / or package structure 9000B may include a portion of the first portion 11 and a portion of the second portion 12, or a portion of the second portion 12 and the first portion 11, having a thickness less than that of the substrate 300C, and may be exposed in an accessible manner only by the first outermost surface or the second outermost surface of the substrate 300C.

[0250] Figure 34 This is a schematic cross-sectional view illustrating a package structure 10000A according to some embodiments of the present disclosure. Figure 35 This is a schematic cross-sectional view illustrating a package structure 10000B according to some embodiments of the present disclosure. Elements similar to or substantially the same as those described above will use the same reference numerals, and certain details or descriptions of the same elements (e.g., formation and materials) and their relationships (e.g., relative positioning configuration and electrical connections) will not be repeated herein. In some embodiments, Figure 34 The 10000A packaging structure is similar to Figure 14A and Figure 14BThe package structure 1000A differs from the previous one in that, in the package structure 10000A, the substrate 300A is replaced by a substrate 300D, wherein the substrate 300D includes a wiring portion 320A and a solder mask layer 330A disposed thereon. Details of the wiring portion 320A and the solder mask layer 330A have been previously described. Figure 12A , Figure 12B and Figure 16A The above has been described in the text; therefore, for the sake of brevity, it will not be repeated in this article.

[0251] In one embodiment, support structure 10 is replaced by support structure 50, wherein support structure 50 may consist only of a first portion 11. The details of the first portion 11 of support structure 50 are the same as previously described. Figure 12A , Figure 12B and Figure 16A The first part 11 of the support structure 10 described herein is the same, and the configuration of the support structure 50 and the annular structure 520 is the same as previously described herein. Figure 14A and Figure 14B The configuration of the support structure 10 and the annular structure 520 described herein is the same or similar; therefore, for the sake of brevity, it will not be repeated herein. Furthermore, a cover (e.g., cover 540) may be used for better heat dissipation, and multiple conductive terminals (e.g., conductive terminals 600) may be used for further electrical connection to external components, see [link to relevant documentation]. Figure 35 The package structure 10000B is an example. In other alternative embodiments, multiple conductive terminals (e.g., conductive terminals 600) may also be used in the package structure 10000A.

[0252] like Figure 34 and Figure 35As shown, when measured along direction Z, the thickness T3' of the support structure 50 is substantially the same as the thickness (not marked) of the substrate 300D. However, this disclosure is not limited thereto; alternatively, the thickness T3' of the support structure 50 may be less than the thickness of the substrate 300D. In one embodiment, the support structure included in package structure 10000A and / or package structure 10000B has fewer wiring layers included in the first portion 11 than the number of wiring layers included in the wiring portion 320A of the substrate 300D. In other words, if we consider that there are three wiring layers included in the wiring portion 320A of the substrate 300D, then there are more than one and less than three wiring layers included in the first portion 11 of the support structure. For example, the support structure extends from the first outermost surface of the substrate 300D into the substrate 300D and is not exposed in an accessible manner by the second outermost surface of the substrate 300D. For another example, the support structure extends from the second outermost surface of the substrate 300D into the substrate 300D and is not exposed in an accessible manner by the first outermost surface of the substrate 300D. In some embodiments, the first outermost surface of the substrate 300D is opposite to the second outermost surface of the substrate 300D, and the semiconductor device P1 is disposed on the first outermost surface.

[0253] However, this disclosure is not limited thereto; alternatively, package structure 10000A and / or package structure 10000B may include wiring portion 320B and solder mask layer 330B disposed thereon. In such alternative embodiments, the support structure included in package structure 10000A and / or package structure 10000B has fewer wiring layers included in the second portion 12 than the number of wiring layers included in wiring portion 320B of substrate 300D. In other words, if we consider that there are three wiring layers included in wiring portion 320B of substrate 300D, then there are more than one and less than three wiring layers included in the second portion 12 of the support structure. For example, the support structure extends from the first outermost surface of substrate 300D into substrate 300D and is not exposed in an accessible manner by the second outermost surface of substrate 300D; or, the support structure extends from the second outermost surface of substrate 300D into substrate 300D and is not exposed in an accessible manner by the first outermost surface of substrate 300D. In some embodiments, the first outermost surface of the substrate 300D is opposite to the second outermost surface of the substrate 300D, and the first outermost surface is provided with a semiconductor device P1.

[0254] Figure 36 This is a schematic cross-sectional view illustrating a package structure 11000A according to some embodiments of the present disclosure. Figure 37This is a schematic cross-sectional view illustrating a package structure 11000B according to some embodiments of the present disclosure. Elements similar to or substantially the same as those described above will use the same reference numerals, and certain details or descriptions of the same elements (e.g., formation and materials) and their relationships (e.g., relative positioning configuration and electrical connections) will not be repeated herein. In some embodiments, Figure 36 The 11000A's packaging structure is similar to Figure 14A and Figure 14B The package structure 1000A differs from the previous one in that, in the package structure 11000A, the substrate 300A is replaced by a substrate 300E, wherein the substrate 300E includes wiring portions 320A' and a solder mask layer 330A disposed thereon. Details of the solder mask layer 330A have previously been described. Figure 12A , Figure 12B and Figure 16A The wiring portion 320A' is described in [the previous text], and its formation, materials, and configuration are similar to or the same as those previously described in [the previous text]. Figure 12A , Figure 12B and Figure 16A The process, materials, and configuration for forming the wiring section 320A described in the previous section are not repeated here for the sake of brevity. Figure 36 As shown, for example, the wiring portion 320A' includes only one wiring layer, such as the dielectric layer 322a and the conductive layer 324a disposed thereon.

[0255] In one embodiment, support structure 10 is replaced by support structure 50, wherein support structure 50 may consist only of a first portion 11. The details of the first portion 11 of support structure 50 are the same as previously described. Figure 12A , Figure 12B and Figure 16A The first part 11 of the support structure 10 described herein is the same, and the configuration of the support structure 50 and the annular structure 520 is the same as previously described herein. Figure 14A and Figure 14B The configuration of the support structure 10 and the annular structure 520 described herein is the same or similar; therefore, for the sake of brevity, it will not be repeated herein. Furthermore, a cover (e.g., cover 540) may be used for better heat dissipation, and multiple conductive terminals (e.g., conductive terminals 600) may be used for further electrical connection to external components, see [link to relevant documentation]. Figure 37 The package structure 11000B is used. In other alternative embodiments, multiple conductive terminals (e.g., conductive terminals 600) may also be used in the package structure 11000A.

[0256] like Figure 36 and Figure 37As shown, for example, when measured along direction Z, the thickness T3” of the support structure 50 is substantially the same as the thickness (not marked) of the substrate 300E. In some embodiments, the support structure 50 extends from a first outermost surface of the substrate 300E into the substrate 300E and can be exposed in an accessible manner by a second outermost surface of the substrate 300D. For example, the first outermost surface of the substrate 300E is opposite to the second outermost surface of the substrate 300E, and the semiconductor device P1 is disposed on the first outermost surface. That is, the support structure 50 penetrates the substrate 300E.

[0257] However, this disclosure is not limited thereto; as an alternative, package structure 11000A and / or package structure 11000B may include wiring portion 320B' and solder mask layer 330B disposed thereon. For example, wiring portion 320B' includes only one wiring layer, such as dielectric layer 322a and conductive layer 324a disposed thereon.

[0258] It should be understood that, if applicable, package structures 7000, 8000A, 8000B, 9000A, 9000B, 10000A, 10000B, 11000A, and 11000B can also be derived from modifications of package structure 1000A. Because in Figures 16A to 28 The details of the modifications to the 1000A package structure have already been described, so for the sake of brevity, a detailed description has been omitted.

[0259] According to some embodiments, a package structure includes a circuit substrate, a semiconductor device, and a ring structure. The circuit substrate has a first region and a second region connected to the first region, wherein the circuit substrate includes at least one wiring layer. The at least one wiring layer includes a dielectric portion and a conductive portion disposed above the dielectric portion, wherein a first ratio of the total volume of the conductive portion of the at least one wiring layer in the first region to the total volume of the dielectric and conductive portions of the at least one wiring layer in the first region is less than a second ratio of the total volume of the conductive portion of the at least one wiring layer in the second region to the total volume of the dielectric and conductive portions of the at least one wiring layer in the second region. The semiconductor device is disposed above the circuit substrate in the first region, wherein the semiconductor device is electrically coupled to the circuit substrate. The ring structure is disposed above the circuit substrate in the second region.

[0260] According to some embodiments, in the package structure, the first ratio is less than 80%, and the second ratio is greater than or substantially equal to 80%. According to some embodiments, in the package structure, the at least one wiring layer in the second region does not include a dielectric portion. According to some embodiments, in the package structure, the at least one wiring layer comprises a plurality of wiring layers stacked and electrically coupled to each other in the stacking direction of the semiconductor device and the circuit substrate. According to some embodiments, in the package structure, the circuit substrate further includes: a core substrate; a plurality of vias penetrating the core substrate; and at least one additional wiring layer, wherein the at least one wiring layer and the at least one additional wiring layer are located on opposite sides of the core substrate and electrically coupled to each other via the plurality of vias, wherein a third ratio of the total volume of conductive portions in the core substrate in the first region to the total volume of dielectric and conductive portions in the core substrate in the first region is less than a fourth ratio of the total volume of conductive portions in the core substrate in the second region to the total volume of dielectric and conductive portions in the core substrate in the second region. According to some embodiments, in the package structure, wherein: the at least one wiring layer is sandwiched between the semiconductor device and the core substrate, or the at least one additional wiring layer is sandwiched between the semiconductor device and the core substrate. According to some embodiments, in the package structure, a fifth ratio of the total volume of the conductive portion in the at least one additional wiring layer within the first region to the total volume of the dielectric and conductive portions in the at least one additional wiring layer within the first region is less than a sixth ratio of the total volume of the conductive portion in the at least one additional wiring layer within the second region to the total volume of the dielectric and conductive portions in the at least one additional wiring layer within the second region.

[0261] According to some embodiments, a package structure includes a substrate, a semiconductor device, a metal support structure, and a ring structure. The substrate has a first region and a second region surrounding the first region. The semiconductor device is disposed above the substrate in the first region and electrically coupled to the substrate. The metal support structure is located in the substrate in the second region and is electrically isolated from the semiconductor device. The ring structure is disposed above the substrate in the second region, wherein the ring structure overlaps with the metal support structure in its vertical projection onto the substrate along the stacking direction of the ring structure and the substrate.

[0262] According to some embodiments, in the package structure, the substrate includes: a base substrate; a plurality of vias penetrating the base substrate; a first redistribution circuit structure disposed above a first side of the base substrate and electrically connected to the plurality of vias; and a second redistribution circuit structure disposed above a second side of the base substrate and electrically connected to the plurality of vias, wherein the first redistribution circuit structure is electrically coupled to the second redistribution circuit structure via the plurality of vias, and the first side is opposite to the second side along the stacking direction, wherein the semiconductor device and the annular structure are located on the first side of the base substrate, and the metal support structure is embedded in and penetrates the base substrate and the first redistribution circuit structure. According to some embodiments, in the package structure, the metal support structure is not present in the second redistribution circuit structure. According to some embodiments, in the package structure, the metal support structure is further embedded in and penetrates the second redistribution circuit structure. According to some embodiments, in the packaging structure, the substrate includes: a base substrate; a plurality of vias penetrating the base substrate; a first redistributed wiring structure disposed above a first side of the base substrate and electrically connected to the plurality of vias; and a second redistributed wiring structure disposed above a second side of the base substrate and electrically connected to the plurality of vias, wherein the first redistributed wiring structure is electrically coupled to the second redistributed wiring structure via the plurality of vias, and the first side is opposite to the second side along the stacking direction, wherein the semiconductor device and the annular structure are located on the first side of the base substrate, and the metal support structure is embedded in and penetrates the base substrate and the second redistributed wiring structure, wherein the metal support structure is not present in the first redistributed wiring structure. According to some embodiments, in the packaging structure, the substrate includes: a redistributed wiring structure including at least one dielectric layer and at least one conductive layer disposed above the at least one dielectric layer, wherein the semiconductor device and the annular structure are located on one side of the redistributed wiring structure, and the metal support structure is embedded in the redistributed wiring structure, wherein the metal support structure extends from the outermost surface of the redistributed wiring structure into the redistributed wiring structure. According to some embodiments, in the packaging structure, in a cross-section of the packaging structure along the stacking direction, the lateral dimension of the metal support structure is smaller than the lateral dimension of the second region, and the lateral dimension of the metal support structure is greater than, less than, or substantially equal to the lateral dimension of the annular structure. According to some embodiments, in the packaging structure, in a cross-section of the packaging structure along the stacking direction, the lateral dimension of the metal support structure is substantially equal to the lateral dimension of the second region, and the lateral dimension of the metal support structure is greater than or substantially equal to the lateral dimension of the annular structure.According to some embodiments, the packaging structure further includes: a cover disposed above the annular structure and the semiconductor device and thermally coupled to the annular structure and the semiconductor device; and a thermal interface material inserted between the cover and the semiconductor device and thermally coupled to the cover and the semiconductor device.

[0263] According to some embodiments, a method of manufacturing a package structure includes the following steps: providing a circuit substrate having a first region and a second region connected to the first region, the circuit substrate including at least one wiring layer, the at least one wiring layer including a dielectric portion and a conductive portion disposed above the dielectric portion, and a first ratio of the total volume of the conductive portion in the at least one wiring layer included in the first region to the total volume of the dielectric portion and the conductive portion in the at least one wiring layer included in the first region being less than a second ratio of the total volume of the conductive portion in the at least one wiring layer included in the second region to the total volume of the dielectric portion and the conductive portion in the at least one wiring layer included in the second region; providing a semiconductor device above the circuit substrate; mounting the semiconductor device onto the circuit substrate in the first region, the semiconductor device being electrically coupled to the circuit substrate; and providing a ring structure above the circuit substrate in the second region.

[0264] According to some embodiments, in the method of manufacturing the package structure, providing the circuit substrate includes forming the at least one wiring layer, wherein forming the at least one wiring layer includes: forming a dielectric material; patterning the dielectric material to form the dielectric portion in the first region and the second region; and forming a conductive material on the dielectric portion to form the conductive portion in the first region and the second region, wherein the first ratio is less than 80% and the second ratio is greater than or substantially equal to 80%. According to some embodiments, in the method of manufacturing the package structure, providing the circuit substrate further includes: forming a core substrate having a plurality of vias therethrough before forming the at least one wiring layer, wherein a third ratio of the total volume of conductive portions in the core substrate in the first region to the total volume of dielectric and conductive portions in the core substrate in the first region is less than a fourth ratio of the total volume of conductive portions in the core substrate in the second region to the total volume of dielectric and conductive portions in the core substrate in the second region; and forming the at least one additional wiring layer, including: forming an additional dielectric material over the core substrate; patterning the additional dielectric material to form additional dielectric portions in the first and second regions; and forming an additional conductive material over the additional dielectric portions to form additional conductive portions in the first and second regions, wherein the at least one wiring layer and the at least one additional wiring layer are located on opposite sides of the core substrate. According to some embodiments, in the method of manufacturing the package structure, the at least one additional wiring layer is formed such that a fifth ratio of the total volume of the conductive portion in the at least one additional wiring layer included in the first region to the total volume of the dielectric and conductive portions in the at least one additional wiring layer included in the first region is less than a sixth ratio of the total volume of the conductive portion in the at least one additional wiring layer included in the second region to the total volume of the dielectric and conductive portions in the at least one additional wiring layer included in the second region.

[0265] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art will recognize that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made thereto without departing from the spirit and scope of this disclosure.

Claims

1. A packaging structure, comprising: A circuit substrate having a first region and a second region connected to the first region, wherein the circuit substrate includes: At least one wiring layer includes a dielectric portion and a conductive portion disposed above the dielectric portion. Wherein a first ratio of the total volume of the conductive portion of the at least one wiring layer in the first region to the total volume of the dielectric and conductive portions of the at least one wiring layer in the first region is less than a second ratio of the total volume of the conductive portion of the at least one wiring layer in the second region to the total volume of the dielectric and conductive portions of the at least one wiring layer in the second region, wherein the second ratio is greater than or substantially equal to 80%, wherein in the cross-section of the circuit substrate, the second region has an inner sidewall and an outer sidewall opposite to the inner sidewall, the inner sidewall being in direct contact with the sidewall of the first region, and the outer sidewall being the sidewall of the circuit substrate; A semiconductor device is disposed above the circuit substrate within the first region, wherein the semiconductor device is electrically coupled to the circuit substrate; and A ring-shaped structure is disposed above the circuit substrate within the second region.

2. The packaging structure according to claim 1, wherein the first ratio is less than 80%.

3. The packaging structure according to claim 1, wherein the at least one wiring layer in the second region does not include a dielectric portion.

4. The packaging structure according to claim 1, wherein the at least one wiring layer comprises a plurality of wiring layers, the plurality of wiring layers being stacked and electrically coupled to each other in the stacking direction of the semiconductor device and the circuit substrate.

5. The packaging structure according to claim 1, wherein the circuit substrate further comprises: Core substrate; Multiple vias penetrate the core substrate; as well as At least one additional wiring layer, wherein the at least one wiring layer and the at least one additional wiring layer are located on opposite sides of the core substrate and are electrically coupled to each other via the plurality of vias. This includes a third ratio in which the total volume of the conductive portion in the core substrate within the first region is less than the fourth ratio in which the total volume of the conductive portion in the core substrate within the second region is less than the fourth ratio in which the total volume of the conductive portion in the core substrate within the second region is less than the fourth ratio in which the total volume of the conductive portion in the core substrate within the second region is less than the fourth ratio in which the total volume of the conductive portion in the core substrate within the second region is less than the fourth ratio in the fifth ratio in the second region.

6. The packaging structure according to claim 5, wherein: The at least one wiring layer is sandwiched between the semiconductor device and the core substrate, or The at least one additional wiring layer is sandwiched between the semiconductor device and the core substrate.

7. The packaging structure of claim 5, wherein a fifth ratio of the total volume of the conductive portion in the at least one additional wiring layer in the first region to the total volume of the dielectric and conductive portions in the at least one additional wiring layer in the first region is less than a sixth ratio of the total volume of the conductive portion in the at least one additional wiring layer in the second region to the total volume of the dielectric and conductive portions in the at least one additional wiring layer in the second region.

8. A packaging structure, comprising: A substrate having a first region and a second region surrounding the first region, wherein a first ratio of the total volume of conductive portions in the first region to the total volume of dielectric portions and conductive portions in the first region is less than a second ratio of the total volume of conductive portions in the second region to the total volume of dielectric portions and conductive portions in the second region, wherein the second ratio is greater than or substantially equal to 80%, wherein in a cross-section of the substrate, the second region has an inner sidewall and an outer sidewall opposite to the inner sidewall, the inner sidewall being in direct contact with a sidewall of the first region, and the outer sidewall being a sidewall of the substrate; A semiconductor device is disposed above the substrate within the first region and electrically coupled to the substrate; A metal support structure is located in the substrate within the second region and is electrically isolated from the semiconductor device, wherein the conductive portion within the second region includes the metal support structure; as well as A ring structure is disposed above the substrate within the second region, wherein the ring structure overlaps the metal support structure in a vertical projection onto the substrate along the stacking direction of the ring structure and the substrate.

9. The packaging structure according to claim 8, wherein the substrate comprises: Basic substrate; Multiple perforations penetrate the base substrate; A first re-laid circuit structure is disposed above a first side of the base substrate and electrically connected to the plurality of vias; as well as A second redistributed circuit structure is disposed above a second side of the base substrate and electrically connected to the plurality of vias, wherein the first redistributed circuit structure is electrically coupled to the second redistributed circuit structure via the plurality of vias, and the first side is opposite to the second side along the stacking direction. The semiconductor device and the ring structure are located on the first side of the base substrate, and the metal support structure is embedded in and penetrates the base substrate and the first redistribution circuit structure.

10. The packaging structure according to claim 9, wherein the metal support structure is not present in the second redistribution circuit structure.

11. The packaging structure according to claim 9, wherein the metal support structure is further embedded in and penetrates the second redistribution circuit structure.

12. The packaging structure according to claim 8, wherein the substrate comprises: Basic substrate; Multiple perforations penetrate the base substrate; A first re-laid circuit structure is disposed above a first side of the base substrate and electrically connected to the plurality of vias; as well as A second redistributed circuit structure is disposed above a second side of the base substrate and electrically connected to the plurality of vias, wherein the first redistributed circuit structure is electrically coupled to the second redistributed circuit structure via the plurality of vias, and the first side is opposite to the second side along the stacking direction. The semiconductor device and the ring structure are located on the first side of the base substrate, and the metal support structure is embedded in and penetrates the base substrate and the second redistribution circuit structure. The metal support structure is not present in the first redistribution circuit structure.

13. The packaging structure according to claim 8, wherein the substrate comprises: The redistributed circuit structure includes at least one dielectric layer and at least one conductive layer disposed above the at least one dielectric layer. The semiconductor device and the ring structure are located on one side of the redistribution circuit structure, and the metal support structure is embedded in the redistribution circuit structure. The metal support structure extends from the outermost surface of the redistributed circuit structure into the redistributed circuit structure.

14. The packaging structure of claim 8, wherein in the cross-section of the packaging structure along the stacking direction, The lateral dimension of the metal support structure is smaller than the lateral dimension of the second region, and the lateral dimension of the metal support structure is greater than, less than, or substantially equal to the lateral dimension of the annular structure.

15. The packaging structure of claim 8, wherein in the cross-section of the packaging structure along the stacking direction, The lateral dimension of the metal support structure is substantially equal to the lateral dimension of the second region, and the lateral dimension of the metal support structure is greater than or substantially equal to the lateral dimension of the annular structure.

16. The packaging structure according to claim 8, further comprising: A cover is disposed above the annular structure and the semiconductor device and thermally coupled to the annular structure and the semiconductor device; as well as A thermal interface material is inserted between the cover and the semiconductor device and thermally couples the cover and the semiconductor device.

17. A method for manufacturing a package structure, comprising: A circuit substrate is provided having a first region and a second region connected to the first region. The circuit substrate includes at least one wiring layer, the at least one wiring layer including a dielectric portion and a conductive portion disposed above the dielectric portion. A first ratio of the total volume of the conductive portion in the at least one wiring layer included in the first region to the total volume of the dielectric portion and the conductive portion in the at least one wiring layer included in the first region is less than a second ratio of the total volume of the conductive portion in the at least one wiring layer included in the second region to the total volume of the dielectric portion and the conductive portion in the at least one wiring layer included in the second region, wherein the second ratio is greater than or substantially equal to 80%. In a cross-section of the circuit substrate, the second region has an inner sidewall and an outer sidewall opposite to the inner sidewall, the inner sidewall being in direct contact with a sidewall of the first region, and the outer sidewall being a sidewall of the circuit substrate. A semiconductor device is provided above the circuit substrate; The semiconductor device is mounted on the circuit substrate within the first region, and the semiconductor device is electrically coupled to the circuit substrate. as well as A ring structure is provided above the circuit substrate in the second region.

18. The method of claim 17, wherein providing the circuit substrate includes forming the at least one wiring layer. The formation of the at least one wiring layer includes: Forming dielectric materials; The dielectric material is patterned to form the dielectric portion within the first region and the second region; as well as A conductive material is formed on the dielectric portion to form the conductive portion within the first region and the second region. The first ratio is less than 80%.

19. The method of claim 18, wherein providing the circuit substrate further comprises: Before forming the at least one wiring layer, a core substrate having a plurality of vias passing through it is formed, wherein the total volume of the conductive portion in the core substrate in the first region is a third ratio to the total volume of the dielectric and conductive portions in the core substrate in the first region is less than a fourth ratio to the total volume of the conductive portion in the core substrate in the second region. as well as Forming the at least one additional wiring layer includes: An additional dielectric material is formed above the core substrate; Patterning the additional dielectric material to form additional dielectric portions within the first and second regions; and An additional conductive material is formed over the additional dielectric portion to form additional conductive portions within the first and second regions. The at least one wiring layer and the at least one additional wiring layer are located on opposite sides of the core substrate.

20. The method of claim 19, wherein the at least one additional wiring layer is formed such that a fifth ratio of the total volume of the conductive portion in the at least one additional wiring layer included in the first region to the total volume of the dielectric and conductive portions in the at least one additional wiring layer included in the first region is less than a sixth ratio of the total volume of the conductive portion in the at least one additional wiring layer included in the second region to the total volume of the dielectric and conductive portions in the at least one additional wiring layer included in the second region.

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