Semiconductor devices and their manufacturing methods

Abstract

The semiconductor device includes: a semiconductor substrate; a low-k dielectric layer above the semiconductor substrate; an isolation layer above the low-k dielectric layer; and a work function layer above an etch stop layer. The work function layer is an n-type work function layer. The device also includes: a low-dimensional semiconductor layer on the top surface and sidewalls of the work function layer; source / drain contacts contacting opposite ends of the low-dimensional semiconductor layer; and a dielectric-doped layer above and contacting a channel portion of the low-dimensional semiconductor layer. The dielectric-doped layer includes a metal selected from aluminum and hafnium, and the channel portion of the low-dimensional semiconductor layer also includes a metal. Embodiments of this application also relate to methods of manufacturing semiconductor devices.

Description

Technical Field

[0001] Embodiments of this application also relate to semiconductor devices and methods of manufacturing the same. Background Technology

[0002] In recent developments in integrated circuits, two-dimensional (2D) semiconductor electronic devices have been investigated. A 2D transistor may include a 2D channel, which comprises a channel with atomic-level thickness, formed between two insulating layers. Summary of the Invention

[0003] Some embodiments of this application provide a method for manufacturing a semiconductor device, including: forming a first gate electrode and a second gate electrode; forming a gate dielectric layer extending over the first gate electrode and the second gate electrode; forming an n-type transistor, including: forming a first low-dimensional semiconductor layer over the gate dielectric layer, wherein a first portion of the first low-dimensional semiconductor layer is directly located over the first gate electrode; forming a first source / drain contact on an opposite side of the first gate electrode, wherein the first source / drain contact contacts a first opposite portion of the first low-dimensional semiconductor layer; and depositing contacts over the first low-dimensional semiconductor layer. The first low-dimensional semiconductor layer includes a dielectric doped layer of aluminum oxide or hafnium oxide; and forming a p-type transistor includes: forming a second low-dimensional semiconductor layer over the gate dielectric layer, wherein a second portion of the second low-dimensional semiconductor layer is directly located over the second gate electrode; forming a second source / drain contact on the opposite side of the second gate electrode, wherein the second source / drain contact contacts a second opposite portion of the second low-dimensional semiconductor layer; and depositing a dielectric passivation layer over the second low-dimensional semiconductor layer that contacts the second low-dimensional semiconductor layer, wherein the dielectric passivation layer and the dielectric doped layer are formed of different materials.

[0004] Other embodiments of this application provide a semiconductor device, including: an n-type transistor, including: a first gate electrode; a first gate dielectric layer located above the first gate electrode; a first low-dimensional semiconductor layer including a first portion above the first gate dielectric layer; and a dielectric doped layer including aluminum oxide or hafnium oxide located above and in contact with the first low-dimensional semiconductor layer; and a p-type transistor, including: a second gate electrode; a second gate dielectric layer located above the second gate electrode; a second low-dimensional semiconductor layer including a second portion above the second gate dielectric layer; and a dielectric passivation layer located above and in contact with the second low-dimensional semiconductor layer, wherein the dielectric passivation layer and the dielectric doped layer are formed of different materials.

[0005] Further embodiments of this application provide a semiconductor device, comprising: a semiconductor substrate; a dielectric layer located above the semiconductor substrate; an isolation layer located above the dielectric layer; a first work function layer located above the isolation layer, wherein the first work function layer is an n-type work function layer; a first low-dimensional semiconductor layer located on a first top surface and a first sidewall of the first work function layer; a first source / drain contact contacting opposite ends of the first low-dimensional semiconductor layer; and a dielectric doped layer located above and contacting a channel portion of the first low-dimensional semiconductor layer, wherein the dielectric doped layer comprises a metal selected from aluminum and hafnium, and wherein the channel portion of the first low-dimensional semiconductor layer further comprises the metal. Attached Figure Description

[0006] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0007] Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A and Figure 18B Top views and cross-sectional views of an intermediate stage in the formation of a complementary metal-oxide-semiconductor (CMOS) device, according to some embodiments, are shown.

[0008] Figure 19A cross-sectional view of a CMOS device according to some embodiments is shown.

[0009] Figures 20 to 24 The PFET process in forming the dielectric doped layer and passivation layer is illustrated according to some embodiments.

[0010] Figures 25 to 28 A cycle of some atomic layer deposition processes according to some embodiments is shown.

[0011] Figure 29 A process flow for forming a CMOS device according to some embodiments is shown. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0014] According to some embodiments, complementary metal-oxide-semiconductor (CMOS) devices and methods for forming the same are provided. CMOS devices include p-type MOS (PMOS) devices and n-type MOS (PMOS) devices formed based on two-dimensional channels such as carbon nanotubes (CNTs) as channel materials. Appropriate channel doping is performed to improve the NMOS device, achieving NMOS behavior rather than PMOS behavior. The metal of the source / drain contact plugs of the PMOS and NMOS devices is selected to reduce the contact tunneling barrier. The embodiments discussed herein are intended to provide examples enabling the making or use of the subject matter of the invention, and modifications that can be made will be readily understood by those skilled in the art while remaining within the contemplated scope of the different embodiments. Throughout the various views and illustrative embodiments, the same reference numerals are used to indicate the same elements. While method embodiments may be discussed as being implemented in a particular order, other method embodiments may be implemented in any logical order.

[0015] Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A and Figure 18B Top and cross-sectional views of intermediate stages in the formation of a CMOS device according to some embodiments of the present invention are shown. The corresponding processes are also schematically reflected in... Figure 29 In the process flow shown.

[0016] Figure 1A and Figure 1BTop and cross-sectional views of a portion of wafer 10 including substrate 20 are shown. Substrate 20 may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, etc. Substrate 20 may be doped (e.g., using p-type or n-type dopants) or undoped. Semiconductor substrate 20 may be a portion of wafer 10 such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is provided on a substrate that is typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. According to some embodiments, the semiconductor material of semiconductor substrate 20 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including SiGe, carbon-doped silicon, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof. The substrate 20 can also be formed of other materials such as sapphire, indium tin oxide (ITO), etc.

[0017] According to some embodiments, an active device 22, which may include a transistor (such as a planar transistor, a FinFET, etc.), may be formed on the surface of the semiconductor substrate 20. The transistor may have a semiconductor material such as silicon, silicon germanium, etc., as the channel material. According to an alternative embodiment, the active device 22 is not formed. Therefore, the active devices 22 are shown as dashed lines to show whether they may be formed or not.

[0018] An interconnect structure 24 may be present above the substrate 20. This interconnect structure may include a dielectric layer such as an interlayer dielectric (ILD) and may or may not include an intermetallic dielectric (IMD) above the ILD. According to some embodiments, the ILD comprises or is formed of silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), etc. The ILD can be formed using spin coating, flowable chemical vapor deposition (FCVD), etc. According to an alternative embodiment of the invention, the ILD is formed using deposition methods such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), etc. Contact plugs (not shown), such as source / drain contact plugs, gate contact plugs, etc., can be formed in the ILD.

[0019] Interconnect structure 24 may also include an IMD. According to some embodiments of the invention, the IMD is formed of a low-k dielectric material having a dielectric constant (k value) below about 3.0. The IMD may include Black Diamond (a registered trademark of Applied Materials), carbon-containing low-k dielectric materials, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc. According to some embodiments of the invention, forming the IMD includes: depositing a dielectric material containing a pore-forming agent; and then performing a curing process to remove the pore-forming agent, so that the remaining IMD is porous. Metal lines and vias (not shown) may be formed in the IMD. Examples of metal lines and vias are represented by metal line 30 and via 28 in dielectric layer 26B. The dielectric layers located below dielectric layer 26B are collectively shown as 26A.

[0020] According to some embodiments, the subsequently formed CMOS device is located above layers 26A and 26B. Layer 26A may be an ILD having contact plugs (not shown). Layer 26B may be an IMD. According to an alternative embodiment, the CMOS device to be formed is located above the ILD layer 26A, and no IMD is located below the CMOS device. According to yet another alternative embodiment, the CMOS device and the subsequently formed isolation layer 32 are formed directly on the substrate 20, without any ILD or IMD located below the CMOS device and the etch stop layer 32.

[0021] According to some embodiments, the metal line 30 and the underlying via 28 are formed using a damascene process, which includes: etching a dielectric layer 26B to form a via opening and a trench above the via opening that engages with the via opening; filling the via opening and trench with a conductive material; and performing a planarization process, such as chemical mechanical polishing (CMP) or mechanical abrasion, to remove excess conductive material. The metal line 30 and via 28 may include a diffusion barrier layer 29 and a copper-containing material 31 above the diffusion barrier layer 29. The diffusion barrier layer 29 may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The diffusion barrier layer 29 functions to prevent copper in the copper-containing material 31 from diffusing into the dielectric layer 26B. The diffusion barrier layer 29 may also be used as an adhesive layer.

[0022] like Figure 1B As shown, an isolation layer 32 is formed. The isolation layer 32 can be formed over the interconnect structure 24 or in physical contact with the substrate 20, and can also serve as an etch stop layer. According to some embodiments of the invention, the isolation layer 32 comprises or is formed of oxides (such as silicon oxide), nitrides (such as silicon nitride), high-k dielectric materials (such as aluminum oxide, hafnium oxide, zirconium oxide, lanthanum oxide), etc.

[0023] Similarly, Figure 1BAs shown, wafer 10 includes a PMOS region 100P and an NMOS region 100N, where PMOS devices and NMOS devices will be formed respectively, together forming a CMOS device. Additionally, device region 100I is also shown, which will not have PMOS and NMOS devices formed therein. It should be understood that although metal lines 30 and vias 28 are shown in device region 100I, metal lines and vias that can be directly located under the PMOS and NMOS devices to be formed in subsequent processes can also be formed in device regions 100P and 100N. Device region 100I is not shown in some of the following figures. Figure 1A and Figure 1B Begin and with Figure 18A and Figure 18B In subsequent processes, each of the attached figures includes the letter "A" or "B". The letter "A" indicates that the corresponding figure shows a top view. The letter "B" indicates that the corresponding figure shows a reference section "BB" in the corresponding top view.

[0024] Figure 2A and Figure 2B Top and cross-sectional views are shown respectively during the formation of the p-type work function layer 34P and the n-type work function layer 34N. The corresponding processes are shown as follows. Figure 29 Process 202 in the illustrated process flow 200. Forming each of the p-type power function layer 34P and the n-type power function layer 34N may include: depositing a blanket metal layer; and then patterning the blanket metal layer by a photolithography process. According to some embodiments, the p-type power function layer 34P may include or be formed of a metal such as platinum (Pt), palladium (Pd), gold (Au), or alloys thereof. The n-type power function layer 34N may include or be formed of a metal such as Al, Ti, or alloys thereof. The thickness of the power function layers 34P and 34N may be in the range of about 1 nm to about 10 nm. Formation methods may include physical vapor deposition (PVD), chemical vapor deposition (CVD), etc. The power function layers 34P and 34N serve as the gate electrodes of the respective PMOS and NMOS devices and are referred to as gate electrodes 34P and 34N, respectively.

[0025] Figure 3A and Figure 3B Top and cross-sectional views are shown respectively in the formation of the gate dielectric layer 38. The corresponding process is shown as follows. Figure 29Process 204 in the illustrated process flow 200. According to some embodiments, the gate dielectric layer comprises a high-k dielectric material, such as HfO2, Al2O3, ZrO2, etc., but other materials such as silicon oxide may also be used. Deposition methods may include atomic layer deposition (ALD), CVD, etc. The gate dielectric layer 38 is formed as a conformal layer extending on the top surface and sidewalls of the p-type work function layer 34P and the n-type work function layer 34N. For example, the difference between the horizontal thickness T1 of the horizontal portion and the thickness T2 of the vertical portion of the gate dielectric layer 38 may be less than 20% or 10% of the thicknesses T1 and T2. Figure 25 An exemplary ALD cycle for forming HfO2 is shown, which will be discussed in detail in subsequent paragraphs. According to some embodiments, the thickness of the gate dielectric layer 38 is in the range of about 1 nm to about 15 nm.

[0026] Figure 4A and Figure 4B Top and cross-sectional views are shown respectively of the formation of gate contact openings 40P and 40N in the gate dielectric layer 38. The corresponding process is shown as follows. Figure 29 Process 206 in the illustrated process flow 200. According to some embodiments, forming the gate contact openings 40P and 40N includes an etching process to form a patterned photoresist to define the locations of the via openings 40P and 40N. Figure 4A As shown, gate electrodes 34P and 34N are exposed through gate contact openings 40P and 40N, respectively. Etching can be performed using either a wet etching process or a dry etching process. Gate contact openings 40P and 40N are formed to facilitate the formation of... Figure 15A and Figure 15B The gate contact opening shown reduces the number of layers that need to be etched. According to an alternative embodiment of the invention, skipping... Figure 4A and Figure 4B The process shown.

[0027] refer to Figure 5A and Figure 5B Semiconductor layer 42 is formed by deposition. The corresponding process is shown below. Figure 29Process 208 in the illustrated process flow 200. According to some embodiments of the invention, the semiconductor layer 42 is formed of a low-dimensional material, which may include a carbon nanotube network, aligned carbon nanotubes, a two-dimensional (2D) material such as a transition metal dichalcogenide (TMD), etc. The carbon nanotube network and aligned carbon nanotubes can be formed using impregnation, drop casting, or similar methods. The TMD material can be a compound of transition metals and group VIA elements. Transition metals may include W, Mo, Ti, V, Co, Ni, Zr, Tc, Rh, Pd, Hf, Ta, Re, Ir, Pt, etc. Group VIA elements may be sulfur (S), selenium (Se), tellurium (Te), etc. For example, the semiconductor layer 42 may include or be formed from MoS2, MoSe2, WS2, WSe2, etc. Forming the TMD material may include CVD, for example, using MoO3 powder and sulfur (or Se) powder as precursors, and nitrogen (N2) as a carrier gas. According to alternative embodiments of the invention, PECVD or another suitable method may be used to form the TMD material. According to some embodiments of the present invention, the semiconductor layer 42 has a thickness in the range of about 0.7 nm to about 5 nm. The semiconductor layer 42 is also formed as a conformal layer, for example, the thickness variation between the horizontal and vertical portions is less than about 20 percent or 10 percent.

[0028] Figure 6A and Figure 6B Top and cross-sectional views are shown respectively of portions 42P and 42N of the semiconductor layer 42, which are patterned as device regions 100P and 100N, respectively. Portions 42P and 42N of the semiconductor layer 42 will be used as channel material and portions of the source / drain regions for corresponding PMOS and NMOS devices. The corresponding processes are shown as follows. Figure 29 Process 210 in the process flow 200 shown. Patterning can be implemented by forming a photoresist and then performing an etching process to remove some portions of the semiconductor layer 42, such that the remaining portions 42P and 42N are disconnected from each other. Furthermore, portions of the semiconductor layer 42 extending into the via openings 40P and 40N are also etched, thereby exposing the via openings 40P and 40N again, as shown. Figure 6A As shown. An appropriate etchant is selected corresponding to the material of the semiconductor layer 42. For example, when the semiconductor layer 42 is formed of a carbon nanotube network and aligned carbon nanotubes, an oxygen-based etchant gas such as O2, O3, or a combination thereof can be used as the etchant gas.

[0029] refer to Figure 7A and Figure 7B Annealing process 44 (in) Figure 7B (Marked in the middle). The corresponding process is shown as follows: Figure 29Process 212 in the illustrated process flow 200. The corresponding process gas for the annealing process may include a forming gas comprising hydrogen (H2) and nitrogen (N2). According to some embodiments, the annealing process 44 is performed at a temperature ranging from about 250°C to about 400°C. Carrier gases such as Ar, He, and / or Ne may be added. The annealing duration may range from about 30 minutes to about 60 minutes. The flow rate of hydrogen in the forming gas may range from about 13% to about 15% of the flow rate of the carrier gas. The ambient pressure during the annealing process may range from about 100 torr and one atmosphere. The annealing process may cure the semiconductor layer 42 and the gate dielectric layer 38 to improve their quality. For example, after the annealing process 44, the density of the gate dielectric layer 38 may be less porous.

[0030] Figure 8A and Figure 8B Top and cross-sectional views are shown respectively in the formation of the source / drain contact 46P. The corresponding process is shown as follows. Figure 29 Process 214 in the illustrated process flow 200. According to some embodiments, the formation process includes: depositing a conductive material, which may include a metal or alloy thereof such as Pt, Pd, etc.; and then performing an etching process to pattern the conductive material. The deposition method may include PVD, CVD, etc. The thickness of the conductive material may be in the range of about 10 nm to about 50 nm. The patterned conductive material forms source / drain contacts 46P that are in physical contact with the opposite ends of the semiconductor layer 42P. Figure 8A and Figure 8B Each of the source / drain contacts 46P shown includes a portion that overlaps with a portion of the gate electrode 34P, and a portion of the semiconductor layer 42P is exposed through the source / drain contacts 46P to serve as a channel for the PMOS device.

[0031] Figure 9A and Figure 9B Top and cross-sectional views are shown respectively in the formation of the source / drain contact 46N. The corresponding process is shown as follows. Figure 29Process 216 in the illustrated process flow 200. According to some embodiments, the formation process includes: depositing a conductive material, which may include a metal or alloy thereof such as Ti, Al, etc.; and then performing an etching process to pattern the conductive material. The source / drain contact 46N may also include a gold (Au) layer over the Ti or Al layer to improve the contact. The deposition method may include PVD, CVD, etc. The thickness of the underlying conductive material, such as the Ti or Al layer, may be in the range of about 10 nm to about 50 nm, and the thickness of the upper conductive material, such as the Au layer, may be in the range of about 10 nm to about 30 nm. The patterned conductive layer forms the source / drain contact 46N in partial physical contact with some portions of the semiconductor layer 42N. Figure 9A and Figure 9B Each of the source / drain contacts 46N shown includes a portion overlapping the end of the gate electrode 34N, and a portion of the semiconductor layer 42N is exposed through the source / drain contacts 46N to serve as a channel for the NMOS device.

[0032] According to some embodiments of the present invention, the source / drain contact 46P of the PMOS device and the source / drain contact 46N of the NMOS device use different metals. For example, the source / drain contact 46P uses Pt and / or Pd, and the source / drain contact 46N uses Ti and / or Al. This can reduce the contact tunneling barrier for PMOS and NMOS devices, wherein the contact tunneling barrier includes the barrier between the semiconductor layer 42P and the source / drain contact 46P and the barrier between the semiconductor layer 42N and the source / drain contact 46N.

[0033] exist Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A and Figure 13B In the subsequent process shown, a channel-doped capping layer for the NMOS device and a passivation capping layer for the PMOS device are formed. The example shown is an NFET-first process followed by a PFET-later process, wherein the formation of the channel-doped capping layer for the NMOS device is performed before the formation of the passivation capping layer for the PMOS device.

[0034] refer to Figure 10A and Figure 10B A dielectric-doped layer of 48N is formed. The corresponding process is shown below. Figure 29Process 218 in the illustrated process flow 200. According to some embodiments, the dielectric doped layer 48N is or includes aluminum oxide (Al2O3). According to some embodiments, the aluminum oxide layer 48N includes a lower layer 48N1 and an upper layer 48N2 above the lower layer 48N1. Forming the lower layer 48N1 may include: depositing an aluminum layer, for example, using PVD; and then oxidizing the aluminum layer to form the aluminum oxide layer. The deposited aluminum layer may have a very small thickness, for example, in the range of about 1 nm to about 2 nm. In the oxidation process, the deposited aluminum layer may be oxidized in the open air (and thus by natural oxidation) or in an oxygen-containing (O2) environment with a low oxygen partial pressure, for example, an oxygen partial pressure in the range of about 10 torr to about 500 torr. Oxidation may be carried out at room temperature (e.g., between about 20°C and about 25°C) or at moderately elevated temperatures, for example, in the temperature range between about 20°C and about 150°C, or in the temperature range between about 100°C and about 120°C. With natural oxidation, or oxidation at low partial pressure or low temperature, the oxidation rate decreases, resulting in higher quality alumina 48N1.

[0035] By forming an aluminum layer and then oxidizing that aluminum layer to form an aluminum oxide layer 48N1, it is possible to use ALD (such as, respectively, as...) Figure 27 and Figure 28 The plasma-enhanced ALD (PEALD) or thermal ALD shown deposits an aluminum oxide layer 48N2 on an aluminum oxide layer 48N1. The thickness of the aluminum oxide layer 48N2 can be in the range of about 10 nm to about 50 nm. By forming an aluminum oxide layer 48N1 as a substrate on which the aluminum oxide layer 48N2 is deposited, the uniformity of the aluminum oxide layer 48N is improved compared to depositing the aluminum oxide layer 48N2 directly on the semiconductor layer 42. Furthermore, by utilizing the aluminum oxide layer 48N1 formed by deposition and oxidation, water vapor used in the ALD process for forming the aluminum oxide layer 48N2 can be separated from the channel material of the NMOS device, and the threshold voltage of the resulting NMOS is improved to the sensitivity of aluminum doping into the channel layer 42B. In addition, the aluminum oxide layer 48N2 is less porous.

[0036] Figure 27 An example of a PEALD cycle for depositing alumina (Al2O3) according to some embodiments is shown. The PEALD process involves pulsed oxygen (conducted) into a corresponding chamber, with plasma turned on when oxygen is pulsed. The plasma power can be in the range of about 20 watts to about 60 watts, for example, an RF power source operating at a frequency of 13.56 MHz. The oxygen is then purged with a nitrogen pulse. Next, a precursor such as trimethylaluminum (TMA, (CH3)3Al) is pulsed, followed by purging of the precursor with a nitrogen pulse. The PEALD cycle can make approximately Atomized alumina layers are deposited, and multiple PEALD cycles can increase the alumina thickness to the desired thickness.

[0037] Figure 28 An example of a thermal ALD cycle for forming alumina (Al2O3) according to some embodiments is shown. The thermal ALD process includes pulsed water vapor (H2O) into a corresponding chamber. The water vapor is then purged with a nitrogen pulse. Next, a precursor, such as TMA, is pulsed, followed by purging of the precursor with a nitrogen pulse. During thermal ALD, the temperature of wafer 10 can be in the range of about 150°C to about 300°C. The thermal ALD cycle can make approximately Atom-based alumina layer deposition is performed, and multiple thermal ALD cycles can increase the alumina thickness to the desired thickness. It should be understood that, because water vapor can be used, the alumina layer 48N1 prevents water vapor from reaching and degrading the semiconductor layer 42.

[0038] According to an optional embodiment, instead of forming an alumina layer as the dielectric doping layer, a hafnium oxide layer (which may be hafnium-rich) is formed as the dielectric doping layer 48N. The thickness of the hafnium oxide layer or the hafnium-rich hafnium oxide layer 48N can be in the range of about 10 nm and about 50 nm. The hafnium oxide layer 48N can be as follows: Figure 25 The PEALD process shown is used to form the gate dielectric layer 38, which can also be used to form the gate dielectric layer 38. Figure 25 As shown, the PEALD process involves pulsed a precursor, such as tetra(ethylmethylamino)hafnium (also known as Hf(NMeEt)4), into the reaction chamber, followed by purging of the precursor with a nitrogen pulse. Next, oxygen is pulsed into the corresponding chamber, and plasma is turned on when oxygen is pulsed. The plasma power can be in the range of approximately 20 watts to approximately 60 watts, for example, an RF power source operating at a frequency of 13.56 MHz. Next, oxygen is purged with a nitrogen pulse. The PEALD cycle can make approximately Atom hafnium oxide layers were deposited and multiple PEALD cycles were performed.

[0039] Figure 26An example of a thermal ALD cycle for forming hafnium-rich hafnium oxide (HfO2) according to some embodiments is shown. The thermal ALD process includes pulsed water vapor (H2O) into a corresponding chamber. The water vapor is then purged with a nitrogen pulse. Next, a precursor such as Hf(NMeEt)4 is pulsed, followed by purging of Hf(NMeEt)4 with a nitrogen pulse. Next, one or more additional Hf(NMeEt)4 pulses and purging processes are performed to increase the atomic percentage of hafnium. For example, in hafnium-rich hafnium oxide, the atomic percentage of hafnium can be greater than about 30 percent, and can be in the range between about 32 percent and about 35 percent. During the thermal ALD process, the wafer temperature can be in the range between about 150°C and about 300°C. The thermal ALD cycle can make approximately Atom-rich hafnium oxide layer was deposited, and multiple thermal ALD cycles were performed.

[0040] Figure 11A and Figure 11B Top and cross-sectional views of the patterned dielectric doped layer 48N are shown. The process includes removing the dielectric doped layer 48N from device region 100P using photolithography. The corresponding process is shown as follows. Figure 29 Process 220 in the process flow 200 shown.

[0041] Figure 12A and Figure 12B Top and cross-sectional views of the deposited dielectric passivation layer 48P are shown respectively. The corresponding process is illustrated as follows. Figure 29 Process 222 in the illustrated process flow 200. According to some embodiments, the passivation layer 48P comprises or is formed of silicon oxide. The deposition method may include PVD, which may include a thermal evaporation process. The resulting passivation layer 48P may have a thickness in the range of about 10 nm to about 50 nm.

[0042] Figure 13A and Figure 13B Top and cross-sectional views of the patterned passivation layer 48P are shown respectively. The process includes removing the passivation layer 48P from the device region 100N using a photolithography process. The corresponding process is shown as follows. Figure 29 Process 224 in the process flow 200 shown.

[0043] refer to Figure 14A and Figure 14B Annealing process was carried out on 50 ( Figure 14B The corresponding process is shown as follows. Figure 29Process 226 in the illustrated process flow 200. The process gas may include a formation gas comprising hydrogen (H2) and nitrogen (N2). A carrier gas such as Ar, He, etc., may be added. According to some embodiments, the annealing process is performed at a temperature in the range of about 250°C to about 400°C. The annealing duration may be in the range of about 30 minutes to about 60 minutes. The flow rate of hydrogen in the formation gas may be in the range of about 13% to about 15% of the flow rate of the carrier gas. The ambient pressure during the annealing process may be in the range of about 100 torr and one atmosphere. The annealing process may cure the passivation layer 48P and the dielectric doped layer 48N. Furthermore, aluminum or hafnium in the dielectric doped layer 48N may diffuse into the semiconductor layer 42N, thereby causing the resulting MOS device to move from the P-side to the N-side. For example, if aluminum or hafnium is not doped into the semiconductor layer 42N, the resulting NMOS device in device region 100N can exhibit a negative threshold voltage (meaning the device turns on when a negative Vgs voltage is applied). With doping with aluminum or hafnium, the threshold voltage increases to a positive threshold voltage. When using hafnium-rich hafnium oxide, the magnitude of the threshold voltage adjustment can be adjusted by changing the thickness of the dielectric doped layer 48N and / or the atomic percentage of hafnium. According to some embodiments, during the annealing process, the threshold voltage of the NMOS device increases by, for example, an amount in the range of about 0.5 volts to about 1.0 volts. On the other hand, due to the choice of material for the passivation layer 48P, the threshold voltage of the PMOS device remains unchanged during the annealing process.

[0044] Figure 15A and Figure 15B The following are shown respectively when the gate contact opening 40P is reopened ( Figure 15A ) and forming source / drain contact opening 51P ( Figure 15B The top view and cross-sectional view are shown in the figure. The corresponding process is shown as follows. Figure 29 Process 228 in the process flow 200 shown. For example... Figure 4A The gate contact opening 40P shown may have been filled with a dielectric passivation layer 48P, which may include or be formed of silicon oxide. Therefore, an etching process is performed to remove the dielectric passivation layer 48P from the gate contact opening 40P, and the contact opening 40P is exposed again.

[0045] Figure 16A and Figure 16B Top and cross-sectional views are shown, respectively, of the reopening of the gate contact opening 40N and the formation of the source / drain contact opening 51N. The corresponding process is shown as follows. Figure 29 Process 230 in the illustrated process flow 200. For example... Figure 4AThe gate contact opening 40N shown may have been filled with a dielectric doped layer 48N, which may be formed from HfO2, Hf-rich HfO2, Al2O3, etc. Therefore, an etching process is performed to remove the dielectric doped layer 48N from the gate contact opening 40N, and the contact opening 40N is exposed again.

[0046] Figure 17A and Figure 17B Top and cross-sectional views are shown respectively, according to some embodiments, of forming metal interconnects 54 including 54A, 54B, 54C, and 54D. The corresponding processes are shown as follows. Figure 29 Process 232 in the illustrated process flow 200. This forms PMOS device 102P and NMOS device 102N, which together form a CMOS device. According to some embodiments, metal interconnect 54 includes or is formed of copper, aluminum, tungsten, etc. Formation processes may include PVD, CVD, etc. According to some embodiments, metal interconnect 54A interconnects gate electrodes 34P and 34N. Metal interconnect 54B interconnects the drain of NMOS device 102N and the drain of PMOS device 102P. Metal interconnects 54C and 54D connect to the source regions of PMOS device 102P and NMOS device 102N. It should be understood that the exemplary connection scheme shown is for an inverter. If PMOS device 102P and NMOS device 102N are used to form other circuits, different interconnects are employed.

[0047] Figure 18A and Figure 18B Top and cross-sectional views of the formation of dielectric layer 56 are shown respectively. The corresponding process is shown as follows. Figure 29 Process 234 in the illustrated process flow 200. According to some embodiments, dielectric layer 56 is formed of a dielectric material, such as silicon oxide, silicon nitride, etc., which can be formed using PECVD or similar methods. According to an alternative embodiment, dielectric layer 56 is formed of a low-k dielectric material, which can be selected from the same group of candidate materials for forming dielectric layer 26B.

[0048] Figure 18B Further illustration shows the formation of metal wires 58 and through-holes 60, which can be formed using an inlay process. It should be understood that metal wires and through-holes can also be formed to connect to metal interconnects 54, which are not shown.

[0049] Figure 19 A CMOS device including a PMOS device 102P and an NMOS device 102N according to some embodiments is shown. Unless otherwise stated, these embodiments (and) Figures 20 to 23The materials and forming processes of the components in the illustrated embodiments are substantially the same as those of the same components indicated by the same reference numerals in the embodiments shown in the foregoing figures. Therefore, details regarding the processes and materials for forming the components shown in the foregoing figures can be found in the discussion of the foregoing embodiments.

[0050] Figure 19 The CMOS device shown is similar to Figure 18A and Figure 18B In the illustrated embodiment, gate electrodes 34P and 34N are formed in dielectric layer 26B instead of protruding above the underlying planar dielectric layer, and may have a top surface coplanar with the top surface of dielectric layer 26B. Forming gate electrodes 34P and 34N can be implemented via a damascene process comprising: forming trenches in dielectric layer 26B; filling the trenches with a metal layer; and then performing a planarization process to make the top surfaces of gate electrodes 34P and 34N flush with the top surface of dielectric layer 26B. Gate electrodes 34P and 34N can be derived from a reference... Figure 2A and Figure 2B The materials discussed can be formed using different processes, or they can be formed from the same materials (and using the same processes) such as copper or copper alloys. Therefore, the gate dielectric layer 38 according to these embodiments is a planar layer.

[0051] In the foregoing Figure 10A and Figures 10B to 13A and Figure 13B In the illustrated process, a first-stage NFET process is performed, wherein a dielectric doped layer 48N is formed prior to the dielectric passivation layer 48P. According to an alternative embodiment, such as... Figures 20 to 24 As shown, a PFET process is implemented first, in which a dielectric passivation layer 48P is formed before the formation of the dielectric doped layer 48N. It should be understood that... Figures 20 to 24 Only the formation of the passivation layer 48P and the dielectric doped layer 48N is shown. Other details are not shown and can be found in reference to... Figure 18A and Figure 18B and Figure 19 The previous figures and their corresponding forming processes can be found. For example, the formation of gate electrodes 34P and 34N and their shapes can be referenced. Figure 18B or Figure 19 turn up.

[0052] Figure 20 The formation of gate dielectric 38, semiconductor layers 42P and 42N, and source / drain contacts 46P and 46N is shown. Next, refer to... Figure 21 A 48P dielectric passivation layer is formed. (Reference) Figure 22 Annealing process 44. Next step, such as... Figure 23As shown, a dielectric doped layer 48N is formed extending into the PMOS device region 100P and the NMOS device region 100N. Next, as... Figure 24 As shown, a portion of the dielectric doped layer 48N in device region 100P is removed, leaving the dielectric doped layer 48N in device region 100N. Because the dielectric passivation layer 48P is formed before the dielectric doped layer 48N, the corresponding process is called a PFET-first process. According to some embodiments, an annealing process 50 is performed. Subsequent processes can be described by referring to… Figure 14A / Figures 14B to 18A / Figure 18B To achieve this through teaching.

[0053] Embodiments of the present invention have several advantageous features. By forming a dielectric doped layer over the channel of an NMOS device and doping the channel of the NMOS device with a suitable metal (such as Al or Hf), the resulting device exhibits increased threshold voltage and displays appropriate NMOS behavior, rather than the behavior of a PMOS device; that is, current begins to conduct when a positive Vgs is applied. By using different metals for the source / drain contacts of the PMOS and NMOS devices, the tunneling barrier of the source / drain contacts of the PMOS and NMOS devices is reduced. Moreover, by depositing and oxidizing aluminum oxide before depositing aluminum oxide, or by adjusting the percentage of hafnium atoms in hafnium oxide, the dielectric doped layer can be used to adjust the threshold voltage of the NMOS device to a desired value.

[0054] According to some embodiments of the present invention, the method includes: forming a first gate electrode and a second gate electrode; forming a gate dielectric layer extending over the first gate electrode and the second gate electrode; and forming an n-type transistor and a p-type transistor. Forming the n-type transistor includes: forming a first low-dimensional semiconductor layer over the gate dielectric layer, wherein a first portion of the first low-dimensional semiconductor layer is directly located over the first gate electrode; forming a first source / drain contact on an opposite side of the first gate electrode, wherein the first source / drain contact contacts a first opposite portion of the first low-dimensional semiconductor layer; and depositing a dielectric doped layer comprising aluminum oxide or hafnium oxide over the first low-dimensional semiconductor layer in contact with the first low-dimensional semiconductor layer. Forming a p-type transistor includes: forming a second low-dimensional semiconductor layer over a gate dielectric layer, wherein a second portion of the second low-dimensional semiconductor layer is directly above a second gate electrode; forming a second source / drain contact on the opposite side of the second gate electrode, wherein the second source / drain contact contacts a second opposite portion of the second low-dimensional semiconductor layer; and depositing a dielectric passivation layer contacting the second low-dimensional semiconductor layer over the second low-dimensional semiconductor layer, wherein the dielectric passivation layer and the dielectric doped layer are formed of different materials. In an embodiment, the method further includes: after depositing the dielectric doped layer and the dielectric passivation layer, performing an annealing process to drive metal from the dielectric doped layer into the first low-dimensional semiconductor layer. In an embodiment, the dielectric doped layer comprises aluminum oxide, and depositing the dielectric doped layer comprises: depositing an aluminum layer; oxidizing the aluminum layer to form a first aluminum oxide layer; and depositing a second aluminum oxide layer on the first aluminum oxide layer. In an embodiment, depositing the dielectric doped layer comprises multiple atomic layer deposition cycles to form a hafnium-rich oxide, wherein each of the multiple atomic layer deposition cycles comprises a water vapor pulse process and multiple hafnium-containing precursor pulse processes. In an embodiment, the annealing process increases the first threshold voltage of the n-type transistor, while the second threshold voltage of the p-type transistor remains unchanged by the annealing process. In an embodiment, the first source / drain contact comprises aluminum or titanium, and the second source / drain contact comprises palladium. In an embodiment, a first low-dimensional semiconductor layer and a second low-dimensional semiconductor layer are formed simultaneously, and comprise a material selected from the group consisting of a carbon nanotube network and aligned carbon nanotubes. In an embodiment, the method further includes forming a low-k dielectric layer, wherein the first gate electrode and the second gate electrode are located at least a portion above the low-k dielectric layer.

[0055] According to some embodiments of the present invention, the device includes an n-type transistor and a p-type transistor. The n-type transistor includes: a first gate electrode; a first gate dielectric layer located above the first gate electrode; a first low-dimensional semiconductor layer including a first portion above the first gate dielectric layer; and a dielectric doped layer including aluminum oxide or hafnium oxide located above and contacting the first low-dimensional semiconductor layer. The p-type transistor includes: a second gate electrode; a second gate dielectric layer located above the second gate electrode; a second low-dimensional semiconductor layer including a second portion above the second gate dielectric layer; and a dielectric passivation layer located above and contacting the second low-dimensional semiconductor layer, wherein the dielectric passivation layer and the dielectric doped layer are formed of different materials. In one embodiment, the dielectric passivation layer includes silicon oxide, and the dielectric doped layer includes aluminum oxide. In another embodiment, the dielectric passivation layer includes silicon oxide, and the dielectric doped layer includes hafnium oxide. In yet another embodiment, the hafnium oxide is hafnium-rich. In an embodiment, the n-type transistor includes a first source / drain contact on the opposite side of the first gate electrode, wherein the first source / drain contact contacts a first opposite portion of the first low-dimensional semiconductor layer; and the p-type transistor includes a second source / drain contact on the opposite side of the second gate electrode, wherein the second source / drain contact contacts a second opposite portion of the second low-dimensional semiconductor layer, and the first source / drain contact and the second source / drain contact comprise different metals. In an embodiment, the first source / drain contact comprises aluminum or titanium, and the second source / drain contact comprises palladium. In an embodiment, the first low-dimensional semiconductor layer comprises: a top portion located directly above the first gate electrode; and a sidewall portion located on the sidewall of the first gate electrode.

[0056] According to some embodiments of the present invention, the device includes: a semiconductor substrate; a low-k dielectric layer located above the semiconductor substrate; an isolation layer located above the low-k dielectric layer; a first work function layer located above the isolation layer, wherein the first work function layer is an n-type work function layer; a first low-dimensional semiconductor layer located on a first top surface and a first sidewall of the first work function layer; first source / drain contacts contacting opposite ends of the first low-dimensional semiconductor layer; and a dielectric doped layer located above and contacting a channel portion of the first low-dimensional semiconductor layer, wherein the dielectric doped layer comprises a metal selected from aluminum and hafnium, and wherein the channel portion of the first low-dimensional semiconductor layer further comprises a metal. In embodiments, the device further includes: an additional transistor formed on the surface of the semiconductor substrate, wherein the additional transistor comprises silicon or silicon-germanium as a channel material. In an embodiment, the device further includes: a second work function layer located above the isolation layer, wherein the second work function layer is a p-type work function layer; a second low-dimensional semiconductor layer located on a second top surface and a second sidewall of the second work function layer; second source / drain contacts contacting opposite ends of the second low-dimensional semiconductor layer; and a dielectric passivation layer, wherein the dielectric passivation layer and the second low-dimensional semiconductor layer are metal-free. In an embodiment, the first source / drain contacts and the second source / drain contacts comprise different metals. In an embodiment, the metal comprises hafnium.

[0057] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. A method for manufacturing a semiconductor device, comprising: Forming the first gate electrode and the second gate electrode; A gate dielectric layer is formed extending over the first gate electrode and the second gate electrode; Forming an n-type transistor includes: A first low-dimensional semiconductor layer is formed above the gate dielectric layer, wherein a first portion of the first low-dimensional semiconductor layer is located directly above the first gate electrode; A first source / drain contact is formed on the opposite side of the first gate electrode, wherein the first source / drain contact is in contact with a first opposite portion of the first low-dimensional semiconductor layer; A dielectric doped layer, comprising aluminum oxide or hafnium oxide, is deposited above the first low-dimensional semiconductor layer in contact with the first low-dimensional semiconductor layer; and Forming a p-type transistor includes: A second low-dimensional semiconductor layer is formed above the gate dielectric layer, wherein a second portion of the second low-dimensional semiconductor layer is located directly above the second gate electrode; A second source / drain contact is formed on the opposite side of the second gate electrode, wherein the second source / drain contact contacts a second opposite portion of the second low-dimensional semiconductor layer; and A dielectric passivation layer is deposited above the second low-dimensional semiconductor layer to contact the second low-dimensional semiconductor layer, wherein the dielectric passivation layer and the dielectric doping layer are formed of different materials. After depositing the dielectric doping layer and the dielectric passivation layer, an annealing process is performed to drive aluminum or hafnium in the dielectric doping layer into the first low-dimensional semiconductor layer.

2. The method according to claim 1, wherein, The dielectric doped layer includes hafnium oxide.

3. The method according to claim 1, wherein, The dielectric doped layer comprises aluminum oxide, and depositing the dielectric doped layer comprises: Deposited aluminum layer; Oxidize the aluminum layer to form a first aluminum oxide layer; and A second alumina layer is deposited on the first alumina layer.

4. The method according to claim 2, wherein, The deposition of the dielectric doped layer comprises multiple atomic layer deposition cycles to form a hafnium-rich oxide, wherein each of the multiple atomic layer deposition cycles comprises a water vapor pulse process and multiple hafnium-containing precursor pulse processes.

5. The method according to claim 2, wherein, The annealing process increases the first threshold voltage of the n-type transistor, while the second threshold voltage of the p-type transistor remains unchanged.

6. The method according to claim 1, wherein, The first source / drain contact comprises aluminum or titanium, and the second source / drain contact comprises palladium.

7. The method according to claim 1, wherein, The first low-dimensional semiconductor layer and the second low-dimensional semiconductor layer are formed simultaneously, and include a material selected from the group consisting of a carbon nanotube network and aligned carbon nanotubes.

8. The method according to claim 1, further comprising: A low-k dielectric layer is formed, wherein the first gate electrode and the second gate electrode are located above at least a portion of the low-k dielectric layer.

9. A semiconductor device, comprising: n-type transistors include: First gate electrode; A first gate dielectric layer is located above the first gate electrode; The first low-dimensional semiconductor layer includes a first portion above the first gate dielectric layer; A dielectric doped layer comprising aluminum oxide or hafnium oxide located above and in contact with the first low-dimensional semiconductor layer, wherein the first low-dimensional semiconductor layer comprises the same aluminum or hafnium metal as the dielectric doped layer, and the same aluminum or hafnium metal is driven from the dielectric doped layer into the first low-dimensional semiconductor layer by an annealing process; and p-type transistors include: Second gate electrode; The second gate dielectric layer is located above the second gate electrode; The second low-dimensional semiconductor layer includes a second portion above the second gate dielectric layer; and A dielectric passivation layer is located above and in contact with the second low-dimensional semiconductor layer, wherein the dielectric passivation layer and the dielectric doped layer are formed of different materials.

10. The semiconductor device according to claim 9, wherein, The dielectric passivation layer comprises silicon oxide, and the dielectric doping layer comprises aluminum oxide.

11. The semiconductor device according to claim 9, wherein, The dielectric passivation layer comprises silicon oxide, and the dielectric doping layer comprises hafnium oxide.

12. The semiconductor device of claim 11, wherein the hafnium oxide is hafnium-rich.

13. The semiconductor device according to claim 9, wherein: The n-type transistor includes a first source / drain contact on the opposite side of the first gate electrode, wherein the first source / drain contact contacts a first opposite portion of the first low-dimensional semiconductor layer; and The p-type transistor includes a second source / drain contact on the opposite side of the second gate electrode, wherein the second source / drain contact contacts a second opposite portion of the second low-dimensional semiconductor layer, and the first source / drain contact and the second source / drain contact comprise different metals.

14. The semiconductor device according to claim 13, wherein, The first source / drain contact comprises aluminum or titanium, and the second source / drain contact comprises palladium.

15. The semiconductor device according to claim 9, wherein, The first low-dimensional semiconductor layer includes: Top, directly above the first gate electrode; and The sidewall portion is located on the sidewall of the first gate electrode.

16. A semiconductor device, comprising: Semiconductor substrate; A dielectric layer is located above the semiconductor substrate; An isolation layer is located above the dielectric layer; The first power function layer is located above the isolation layer, wherein the first power function layer is an n-type power function layer; The first low-dimensional semiconductor layer is located on the first top surface and the first sidewall of the first work function layer; First source / drain contacts, contacting opposite ends of the first low-dimensional semiconductor layer; and A dielectric doped layer is located above and in contact with the channel portion of the first low-dimensional semiconductor layer, wherein the dielectric doped layer comprises a metal selected from aluminum and hafnium, and wherein the channel portion of the first low-dimensional semiconductor layer further comprises the same metal selected from aluminum and hafnium as the dielectric doped layer, wherein the metal selected from aluminum and hafnium is driven into the first low-dimensional semiconductor layer from the dielectric doped layer by an annealing process.

17. The semiconductor device of claim 16, further comprising: Additional transistors are formed on the surface of the semiconductor substrate, wherein the additional transistors comprise silicon or silicon germanium as the channel material.

18. The semiconductor device of claim 16, further comprising: The second power function layer is located above the isolation layer, wherein the second power function layer is a p-type power function layer; The second low-dimensional semiconductor layer is located on the second top surface and the second sidewall of the second work function layer; The second source / drain contact contacts the opposite ends of the second low-dimensional semiconductor layer; and A dielectric passivation layer, wherein the dielectric passivation layer and the second low-dimensional semiconductor layer do not contain the metal.

19. The semiconductor device according to claim 18, wherein, The first source / drain contact and the second source / drain contact comprise different metals.

20. The semiconductor device according to claim 16, wherein, The metal includes hafnium.

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