Semiconductor structure and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor structure and a method of manufacturing the same. The semiconductor structure includes a first semiconductor structure including a first metal layer, a second semiconductor structure including a second metal layer, and the second semiconductor structure is disposed on the first semiconductor structure, and the first metal layer has a first protrusion embedded into the second metal layer. The semiconductor structure and the method of manufacturing the same, the first metal layer has the first protrusion embedded into the second metal layer to generate the ability to resist lateral stress, and increase the bonding strength and reliability of the bonding.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, specifically to semiconductor structures and their manufacturing methods. Background Technology

[0002] Hybrid bonding technology involves simultaneously bonding planar metal and dielectric layers at the bonding interface between wafers (or chips). During bonding, the surfaces of the metal layers are first ground smooth. Then, the metal layers at the bonding interface are aligned with each other, and the dielectric layers with each other, and bonding is performed under specific temperature conditions. The bonding interface is a relatively continuous plane.

[0003] During reliability testing (such as lateral shear performance testing), delamination of the bonding interfaces between metal layers may occur. Summary of the Invention

[0004] This disclosure provides semiconductor structures and methods for manufacturing them.

[0005] In a first aspect, this disclosure provides a semiconductor structure comprising: a first semiconductor structure including a first metal layer; a second semiconductor structure including a second metal layer; the second semiconductor structure being disposed on the first semiconductor structure, the first metal layer having a first protrusion embedded in the second metal layer.

[0006] In some alternative embodiments, the second metal layer has a second protrusion embedded in the first metal layer.

[0007] In some alternative implementations, the height of the first protrusion and / or the second protrusion is between 2 micrometers and 25 micrometers.

[0008] In some alternative embodiments, the first semiconductor structure further includes a second dielectric layer having a first opening, with a first metal layer disposed within the first opening; and / or the second semiconductor structure further includes a fourth dielectric layer having a second opening, the fourth dielectric layer covering the second metal layer such that the second metal layer is disposed within the second opening.

[0009] In some alternative implementations, the sidewall of the first metal layer contacts the sidewall of the first opening; and / or the sidewall of the second metal layer contacts the sidewall of the second opening.

[0010] In some alternative embodiments, a first space is provided between the corner of the first metal layer and the first opening, and a second space is provided between the first metal layer and the fourth dielectric layer; and / or a third space is provided between the corner of the second metal layer and the second opening, and a fourth space is provided between the second metal layer and the second dielectric layer.

[0011] In some alternative implementations, the sidewalls of the first metal layer and the sidewalls of the second metal layer are not coplanar.

[0012] In some optional embodiments, the first semiconductor structure further includes a first seed layer disposed between the first opening and the first metal layer, wherein the width of the first metal layer is greater than the width of the first seed layer; and / or the second semiconductor structure further includes a second seed layer disposed between the second opening and the second metal layer, wherein the width of the second metal layer is greater than the width of the second seed layer.

[0013] In some alternative implementations, an external electrical connection is provided on the unbonded region of the first semiconductor structure.

[0014] In some alternative implementations, the width of the metal layer in the unbonded region is the same as the width of the seed layer.

[0015] In some alternative implementations, the sidewalls of the metal layer in the non-bonded region do not contact the sidewalls of the openings in the dielectric layer of the non-bonded region.

[0016] In some optional embodiments, the first semiconductor structure further includes a first substrate, a first bonding pad, and a first dielectric layer, and the second semiconductor structure further includes a second substrate, a second bonding pad, and a third dielectric layer. The first dielectric layer is disposed on the first substrate, the first bonding pad is embedded in the first dielectric layer, the second dielectric layer is disposed on the first dielectric layer, and the first bonding pad contacts the first seed layer. The third dielectric layer is disposed on the fourth dielectric layer, the second bonding pad is embedded in the third dielectric layer, the second substrate is disposed on the third dielectric layer, and the second bonding pad contacts the second seed layer.

[0017] In a second aspect, this disclosure provides a method for manufacturing a semiconductor structure, comprising: forming a first opening on a second dielectric layer, forming a first metal layer within the first opening, the height of the first metal layer being greater than the height of the second dielectric layer; forming a second opening on a fourth dielectric layer, forming a second metal layer within the second opening, the height of the second metal layer being greater than the height of the fourth dielectric layer; bonding the second dielectric layer and the fourth dielectric layer; and bonding the first metal layer and the second metal layer, such that a first protrusion formed on the first metal layer is embedded into the second metal layer.

[0018] In some alternative embodiments, the method further includes embedding a second protrusion formed on the second metal layer into the first metal layer.

[0019] In some optional embodiments, forming a first opening on a second dielectric layer and forming a first metal layer within the first opening, the height of the first metal layer being greater than the height of the second dielectric layer, includes: forming a first opening on the second dielectric layer, forming a first metal layer within the first opening, the height of the first metal layer being greater than the height of the second dielectric layer, and having a first predetermined distance between the sidewalls of the first metal layer and the sidewalls of the second dielectric layer; and forming a second opening on a fourth dielectric layer and forming a second metal layer within the second opening, the height of the second metal layer being greater than the height of the fourth dielectric layer, includes: forming a second opening on the fourth dielectric layer, forming a second metal layer within the second opening, the height of the second metal layer being greater than the height of the fourth dielectric layer, and having a second predetermined distance between the sidewalls of the second metal layer and the sidewalls of the fourth dielectric layer; and bonding the second dielectric layer and the fourth dielectric layer, including: bonding the second dielectric layer and the fourth dielectric layer such that the sidewall of the first metal layer contacts the sidewall of the second dielectric layer, and the sidewall of the second metal layer contacts the sidewall of the fourth dielectric layer.

[0020] To address the potential for metal-to-metal bonding interface delamination during reliability testing (e.g., lateral shear performance testing), the semiconductor structure and manufacturing method disclosed herein provide a method for forming a hybrid bonding interface with discontinuous planes. The metal layer has a protrusion embedded into the opposite metal layer to generate resistance to lateral stress, thereby increasing the bonding strength and reliability. Attached Figure Description

[0021] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0022] Figure 1 This is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure;

[0023] Figure 2 This is a schematic diagram of a semiconductor structure according to yet another embodiment of the present disclosure;

[0024] Figure 3 This is a schematic diagram of a semiconductor structure according to another embodiment of the present disclosure;

[0025] Figures 4A to 4H A schematic diagram of the manufacturing process of the semiconductor structure disclosed herein.

[0026] Symbol explanation:

[0027] 1-First semiconductor structure, 11-First substrate, 121-First bonding pad, 122-First dielectric layer, 123-Second dielectric layer, 1231-First opening, 124-First seed layer, 125-First metal layer, 1251-First protrusion, 2-Second semiconductor structure, 21-Second substrate, 221-Second bonding pad, 222-Third dielectric layer, 223-Fourth dielectric layer, 2231-Second opening, 224-Second seed layer, 225-Second metal layer, 2251-Second protrusion, 3-External electrical connector, L1-First preset distance, L2-Second preset distance, 4-Metal layer of non-bonded region, 5-Dielectric layer of non-bonded region, 51-Opening, 6-Barrier layer, 7-Bond layer. Detailed Implementation

[0028] The specific embodiments of this disclosure will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by this disclosure and the resulting technical effects through the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the relevant invention and not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0029] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art in understanding and reading the content described herein, and are not intended to limit the implementation conditions of this disclosure. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this disclosure, should still fall within the scope of the technical content disclosed herein. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this disclosure. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this disclosure's implementation.

[0030] Furthermore, the embodiments and features described herein can be combined with each other, unless otherwise specified. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0031] Figure 1 This is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure. Figure 1As shown, the semiconductor structure may include a first semiconductor structure 1 and a second semiconductor structure 2. The first semiconductor structure 1 may include a first metal layer 125, and the second semiconductor structure 2 may include a second metal layer 225. The second semiconductor structure 2 may be disposed on the first semiconductor structure 1, and the first metal layer 125 may have a first protrusion 1251 embedded in the second metal layer 225.

[0032] The first metal layer 125 and the second metal layer 225 may be made of, for example, copper, aluminum, silver or their alloys.

[0033] The first protrusion 1251 may be formed when the first metal layer 125 and the second metal layer 225 are bonded at the annealing temperature, the first metal layer 125 expands due to heat and extends into the gap of the second metal layer 225 on the opposite side, so as to form a first protrusion 1251 embedded in the second metal layer 225.

[0034] In some alternative embodiments, the second metal layer 225 has a second protrusion 2251 embedded in the first metal layer 125.

[0035] The second protrusion 2251 may be formed when the first metal layer 125 and the second metal layer 225 are bonded at the annealing temperature, and the second metal layer 225 is heated and expands, extending into the gap of the first metal layer 125 on the opposite side, so as to form a second protrusion 2251 embedded in the first metal layer 125.

[0036] In some alternative embodiments, the height of the first protrusion 1251 and / or the second protrusion 2251 can be between 2 micrometers and 25 micrometers.

[0037] In some alternative embodiments, the first semiconductor structure 1 may further include a second dielectric layer 123 having a first opening 1231, and a first metal layer 125 disposed within the first opening 1231; and / or the second semiconductor structure 2 may further include a fourth dielectric layer 223 having a second opening 2231, and a second metal layer 225 disposed within the second opening 2231, wherein, from a top view, the fourth dielectric layer 223 covers the second metal layer 225.

[0038] The second dielectric layer 123 and the fourth dielectric layer 223 may be made of, for example, silicon oxide, polyimide (PI) or other suitable insulating materials.

[0039] In some alternative embodiments, the sidewall of the first metal layer 125 may contact the sidewall of the first opening 1231; and / or the sidewall of the second metal layer 225 may contact the sidewall of the second opening 2231.

[0040] In some alternative embodiments, a first space may be provided between the corner of the first metal layer 125 and the first opening 1231, and a second space may be provided between the first metal layer 125 and the fourth dielectric layer 223; and / or a third space may be provided between the corner of the second metal layer 225 and the second opening 2231, and a fourth space may be provided between the second metal layer 225 and the second dielectric layer 123.

[0041] In some alternative embodiments, the sidewalls of the first metal layer 125 and the sidewalls of the second metal layer 225 may be non-coplanar.

[0042] During the bonding process between the first semiconductor structure 1 and the first semiconductor structure 2, the first metal layer 125, the second metal layer 225, the second dielectric layer 123 and the fourth dielectric layer 223 on the bonding interface undergo different degrees of deformation and stress under a certain temperature, resulting in alignment misalignment. Alternatively, due to the alignment error of the bonding equipment, the sidewalls of the first metal layer 125 and the second metal layer 225 may not be coplanar.

[0043] In some optional embodiments, the first semiconductor structure 1 may further include a first seed layer 124 disposed between the first opening 1231 and the first metal layer 125, wherein the width of the first metal layer 125 is greater than the width of the first seed layer 124; and / or the second semiconductor structure 2 may further include a second seed layer 224 disposed between the second opening 2231 and the second metal layer 225, wherein the width of the second metal layer 225 is greater than the width of the second seed layer 224.

[0044] In the process of manufacturing the first semiconductor structure 1, the height of the first metal layer 125 is designed to be greater than the height of the second dielectric layer 123, and the sidewalls of the first metal layer 125 and the second dielectric layer 123 can have a first preset distance L1. Before forming the first metal layer 125, a first seed layer 124 is formed to provide conductivity to ensure the formation of the first metal layer 125. At this time, the width of the first metal layer 125 is the same as the width of the first seed layer 124.

[0045] Similarly, in the process of manufacturing the second semiconductor structure 2, the height of the second metal layer 225 is designed to be greater than the height of the fourth dielectric layer 223, and the sidewalls of the second metal layer 225 and the sidewalls of the fourth dielectric layer 223 can have a second preset distance L2. Before forming the second metal layer 225, a second seed layer 224 is formed first to provide conductivity to ensure the formation of the second metal layer 225. At this time, the width of the second metal layer 225 is the same as the width of the second seed layer 224.

[0046] Finally, during the bonding process between the first semiconductor structure 1 and the first semiconductor structure 2, since the height of the first metal layer 125 is greater than the height of the second dielectric layer 123, and the height of the second metal layer 225 is greater than the height of the fourth dielectric layer 223, the first metal layer 125 and the second metal layer 225 are compressed. The first metal layer 125 extends into the space between the first metal layer 125 and the second dielectric layer 123 to contact the sidewall of the second dielectric layer 123. The second metal layer 223 extends into the space between the second metal layer 225 and the fourth dielectric layer 223 to contact the sidewall of the fourth dielectric layer 223. At this time, due to the extension of the first metal layer 125, the width of the first metal layer 125 is the same as the width of the first seed layer 124. Due to the extension of the second metal layer 225, the width of the second metal layer 225 is greater than the width of the second seed layer 224.

[0047] The first seed layer 124 and the second seed layer 224 can be, for example, a copper layer, a titanium layer, or a copper-titanium layer (copper layer and titanium layer).

[0048] In some alternative implementations, Figure 2 This is a schematic diagram of a semiconductor structure according to yet another embodiment of the present disclosure, as shown below. Figure 1 and Figure 2 As shown, the first semiconductor structure 1 may further include a first substrate 11, a first bonding pad 121, and a first dielectric layer 122, and the second semiconductor structure 2 may further include a second substrate 21, a second bonding pad 221, and a third dielectric layer 222. The first dielectric layer 122 is disposed on the first substrate 11, the first bonding pad 121 is embedded in the first dielectric layer 122, the second dielectric layer 123 is disposed on the first dielectric layer 122, and the first bonding pad 121 contacts the first seed layer 124. The third dielectric layer 222 is disposed on the fourth dielectric layer 223, the second bonding pad 221 is embedded in the third dielectric layer 222, the second substrate 21 is disposed on the third dielectric layer 222, and the second bonding pad 221 contacts the second seed layer 224.

[0049] The first solder pad 121 and the second solder pad 221 may be made of, for example, gold, copper, aluminum, gold or their alloys.

[0050] The first dielectric layer 122 and the third dielectric layer 222 can be made of, for example, silicon oxide, PI or other suitable insulating materials.

[0051] The first substrate 11 and the second substrate 21 can be, for example, a wafer, a circuit board, an ASIC (Application Specific Integrated Circuit) chip, or an HBM (High Bandwidth Memory) chip.

[0052] The semiconductor structure provided in this disclosure forms a hybrid bonding interface with discontinuous planes. The first metal layer 125 has a first protrusion 1251 embedded in the second metal layer 225 on the opposite side. The second metal layer 225 has a second protrusion 2251 embedded in the first metal layer 125 on the opposite side to generate the ability to resist lateral stress, thereby increasing the bonding strength and reliability.

[0053] Figure 3 This is a schematic diagram of another embodiment of the semiconductor structure according to the present disclosure. Figure 3 As shown, an external electrical connector 3 is provided on the unbonded region of the first semiconductor structure 1.

[0054] External electrical connectors 3 can be, for example, traces, bumps, solder balls, etc.

[0055] Specifically, a barrier layer 6, a solder layer 7, and an external electrical connector 3 can be sequentially provided on the unbonded region. Since direct contact between the metal layer 4 in the unbonded region and the external electrical connector 3 will form an intermetallic compound (IMC), the presence of which can cause cracks in the solder joint, thereby reducing its reliability and affecting electrical performance. Therefore, to prevent the formation of intermetallic compounds, a barrier layer 6 is provided between the metal layer 4 in the unbonded region and the external electrical connector 3 to prevent mutual diffusion contact. Furthermore, a solder layer 7 is provided on the barrier layer 6 to fill the space between the metal layer 4 in the unbonded region and the dielectric layer 5 of the unbonded region, preventing the external electrical connector 3 from flowing into the space during manufacturing and achieving connection with the external electrical connector 3.

[0056] In some alternative embodiments, the barrier layer 6 may be, for example, a titanium-copper alloy or a titanium-nickel-copper alloy.

[0057] In some alternative embodiments, the solder layer 7 may be, for example, gold, silver, copper, nickel, aluminum alloy or alloy thereof.

[0058] In some alternative embodiments, the sidewalls of the metal layer 4 in the non-bonded region do not contact the sidewalls of the opening 51 of the dielectric layer 5 in the non-bonded region.

[0059] In the bonding region of the first semiconductor structure 1, the sidewall of the first metal layer 125 can contact the sidewall of the first opening 1231 of the second dielectric layer 123. Compared with the bonding region of the first semiconductor structure 1, the metal layer 4 in the non-bonded region of the first semiconductor structure 1 does not contact the opening 51 of the dielectric layer 5 in the non-bonded region.

[0060] In some alternative implementations, the width of the metal layer 4 in the unbonded region of the first semiconductor structure 1 is the same as the width of the seed layer.

[0061] In the bonding region between the first semiconductor structure 1 and the second semiconductor structure 2, the width of the first metal layer 125 is greater than the width of the first seed layer 124, and the width of the second metal layer 225 is greater than the width of the second seed layer 224. Compared with the bonding region between the first semiconductor structure 1 and the second semiconductor structure 2, the width of the metal layer 4 in the non-bonded region of the first semiconductor structure 1 is the same as the width of the seed layer.

[0062] In the bonding region between the first semiconductor structure 1 and the second semiconductor structure 2, since the first metal layer 125 may have a first protrusion 1251 embedded in the second metal layer 225, and the second metal layer 225 has a second protrusion 2251 embedded in the first metal layer 125, the bonding interface between the first metal layer 125 and the second metal layer 225 is a discontinuous plane. Therefore, the surface of the first metal layer 125 is not coplanar with the surface of the second dielectric layer 123, and the surface of the second metal layer 225 is not coplanar with the surface of the fourth dielectric layer 223. Compared with the bonding region between the first semiconductor structure 1 and the second semiconductor structure 2, the surface of the metal layer 4 in the non-bonded region of the first semiconductor structure 1 is coplanar with the surface of the dielectric layer.

[0063] The semiconductor structure provided in this disclosure achieves electrical connection between the semiconductor structure and the outside by providing an external electrical connector 3 in the non-bonding region on the first semiconductor structure 1.

[0064] Figures 4A to 4H A schematic diagram of the manufacturing process of the semiconductor structure according to this disclosure. The figures have been simplified for better understanding of various aspects of this disclosure.

[0065] Please refer to Figure 4A In some alternative embodiments, a second pad 221 is provided on the second substrate 21.

[0066] Please refer to Figure 4B In some alternative embodiments, a third dielectric layer 222 is provided on the second substrate 21 so that the second pad 221 is embedded in the third dielectric layer 222.

[0067] Please refer to Figure 4C A fourth dielectric layer 223 is disposed on the third dielectric layer 222, and a second opening 2231 is disposed on the fourth dielectric layer 223.

[0068] Please refer to Figure 4D In some alternative embodiments, a second seed layer 224 is provided within the second opening 2231.

[0069] Please refer to Figure 4EA second metal layer 225 is disposed on the second seed layer 224 within the second opening 2231.

[0070] The height of the second metal layer 225 can be greater than the height of the fourth dielectric layer 223, and there can be a second preset distance L2 between the sidewall of the second metal layer 225 and the sidewall of the fourth dielectric layer 223.

[0071] according to Figures 4A-4E This forms a second semiconductor structure 2.

[0072] Please refer to Figure 4F ,according to Figures 4A-4E This forms the first semiconductor structure 1.

[0073] Specifically, a first bonding pad 121 is disposed on a first substrate 11. A first dielectric layer 122 is disposed on the first substrate 11 so that the first bonding pad 121 is embedded in the first dielectric layer 122. A second dielectric layer 123 is disposed on the first dielectric layer 122, and a first opening 1231 is disposed on the second dielectric layer 123. A first seed layer 124 is disposed within the first opening 1231. A first metal layer 125 is disposed on the first seed layer 124 within the first opening 1231.

[0074] The height of the first metal layer 125 can be greater than the height of the second dielectric layer 123, and there can be a first preset distance L1 between the sidewalls of the first metal layer 125 and the sidewalls of the second dielectric layer 123.

[0075] Please refer to Figure 4G The second dielectric layer 123 and the fourth dielectric layer 223 are bonded together, and the first metal layer 125 and the second metal layer 225 are bonded together, so that the first protrusion 1251 formed on the first metal layer 125 is embedded into the second metal layer 225, and the second protrusion 2251 formed on the second metal layer 225 is embedded into the first metal layer 125.

[0076] Specifically, the second dielectric layer 123 and the fourth dielectric layer 223 can be bonded together. Since the height of the first metal layer 125 is greater than the height of the second dielectric layer 123, and the height of the second metal layer 225 is greater than the height of the fourth dielectric layer 223, the sidewalls of the first metal layer 125 and the second metal layer 225 can contact each other. At the annealing temperature, the first metal layer 125 and the second metal layer 225 can be bonded together. The first metal layer 125 expands due to heat and extends into the gaps of the second metal layer 225 to form a first protrusion 1251 embedded in the second metal layer 225. The second metal layer 225 expands due to heat and extends into the gaps of the first metal layer 125 to form a second protrusion 2251 embedded in the first metal layer 125.

[0077] Please refer to Figure 4H An external electrical connector 3 is disposed on the unbonded region of the first semiconductor structure 1.

[0078] External electrical connector 3 can be used to realize electrical connection between the semiconductor structure and the outside. External electrical connector 3 can be, for example, a wire, a bump, a solder ball, etc.

[0079] The semiconductor structure manufacturing method disclosed herein firstly involves designing a first metal layer 125 with a height greater than the second dielectric layer 123, a second metal layer 225 with a height greater than the fourth dielectric layer 223, a first predetermined distance L1 between the sidewalls of the first metal layer 125 and the second dielectric layer 123, and a second predetermined distance L2 between the sidewalls of the second metal layer 225 and the fourth dielectric layer 223. Then, at room temperature or low temperature, bonding is performed between the second dielectric layer 123 and the fourth dielectric layer 223. Because the heights of the first metal layer 125 and the second dielectric layer 225 are greater than those of the fourth dielectric layer 223, the first metal layer 125 and the second metal layer 225 are compressed. The first metal layer 125 extends into the space between the first metal layer 125 and the second dielectric layer 123 to contact the sidewall of the second dielectric layer 123. The second metal layer 223 extends into the space between the second metal layer 225 and the fourth dielectric layer 223 to contact the sidewall of the fourth dielectric layer 223. Finally, at the annealing temperature, bonding is performed between the first metal layer 125 and the second metal layer 225. The first metal layer 125, due to thermal expansion, extends into the gap between itself and the opposite fourth dielectric layer 223, and the second metal layer 225, due to thermal expansion, extends into the gap between itself and the opposite second dielectric layer 123, thereby forming a discontinuous bonding interface between the first metal layer 125 and the second metal layer 225. Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such description and illustration do not limit this disclosure. Those skilled in the art will clearly understand that various changes can be made, and equivalent elements can be substituted within the embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this disclosure and actual implementation due to variables in the manufacturing process, etc. Other embodiments of this disclosure may exist that are not specifically described. The description and illustrations should be considered illustrative, not restrictive. Modifications may be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications fall within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or rearranged to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit this disclosure.

Claims

1. A semiconductor structure, comprising: A first semiconductor structure, including a first metal layer; The second semiconductor structure includes a second metal layer; The second semiconductor structure is disposed on the first semiconductor structure, the first metal layer and the second metal layer form a discontinuous planar hybrid bonding interface, the first metal layer has a first protrusion embedded in the second metal layer, the second metal layer has a second protrusion embedded in the first metal layer, and the height of the first protrusion and / or the second protrusion is between 2 micrometers and 25 micrometers. The first protrusion is formed as follows: when the first metal layer and the second metal layer are bonded at the annealing temperature, the first metal layer expands due to heat and extends into the gap of the second metal layer on the opposite side to form the first protrusion embedded in the second metal layer; The second protrusion is formed as follows: when the first metal layer and the second metal layer are bonded at the annealing temperature, the second metal layer expands due to heat and extends into the gap of the first metal layer on the opposite side to form the second protrusion embedded in the first metal layer; The first semiconductor structure further includes a second dielectric layer having a first opening, and the first metal layer is disposed within the first opening; and / or The second semiconductor structure further includes a fourth dielectric layer having a second opening, the fourth dielectric layer covering the second metal layer such that the second metal layer is disposed within the second opening; A first space is provided between the corner of the first metal layer and the first opening, and a second space is provided between the first metal layer and the fourth dielectric layer; and / or A third space is provided between the corner of the second metal layer and the second opening, and a fourth space is provided between the second metal layer and the second dielectric layer; The sidewalls of the first metal layer and the sidewalls of the second metal layer are not coplanar.

2. The semiconductor structure according to claim 1, wherein, The sidewall of the first metal layer contacts the sidewall of the first opening; and / or The sidewall of the second metal layer contacts the sidewall of the second opening.

3. The semiconductor structure according to claim 1, wherein, The first semiconductor structure further includes a first seed layer disposed between the first opening and the first metal layer, wherein the width of the first metal layer is greater than the width of the first seed layer; and / or The second semiconductor structure further includes a second seed layer disposed between the second opening and the second metal layer, wherein the width of the second metal layer is greater than the width of the second seed layer.

4. The semiconductor structure according to any one of claims 1-3, wherein, An external electrical connector is provided on the unbonded region of the first semiconductor structure.

5. The semiconductor structure according to claim 4, wherein, The width of the metal layer in the non-bonded region is the same as the width of the seed layer; and / or The sidewall of the metal layer in the non-bonded region does not contact the sidewall of the opening in the dielectric layer of the non-bonded region.

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