Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes a substrate, a package structure, a first heat spreader, and a second heat spreader. The package structure is disposed on the substrate. The first heat spreader is disposed on the substrate. The first heat spreader surrounds the package structure. The second heat spreader is disposed on the package structure. The second heat spreader is connected to the first heat spreader. A material of the first heat spreader is different from a material of the second heat spreader.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing the same. More specifically, this invention relates to a semiconductor device having a first heat sink and a second heat sink, and a method for manufacturing the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. During this growth, the functional density of devices generally increases with the size of device features. This scaling down process typically provides benefits by improving production efficiency, reducing costs, and / or improving performance. This scaling down also increases the complexity of handling and manufacturing ICs. To achieve these advancements, IC fabrication needs to be further developed. Summary of the Invention

[0003] A semiconductor device includes a substrate, a package structure, a first heat sink, and a second heat sink. The package structure is disposed on the substrate. The first heat sink is disposed on the substrate and surrounds the package structure. The second heat sink is disposed on the package structure and connected to the first heat sink. The material of the first heat sink is different from the material of the second heat sink.

[0004] A semiconductor device includes a substrate, a cover structure, and a package structure. The cover structure is disposed on the substrate. The cover structure includes a first heat sink and a second heat sink. The first heat sink is attached to the substrate. The first heat sink includes a first body portion and a recess from the top surface of the first body portion. The second heat sink includes a second body portion and a protrusion from the bottom surface of the second body portion. The protrusion of the second heat sink engages with the recess of the first heat sink. The package structure is located between the substrate and the cover structure.

[0005] A method for manufacturing a semiconductor device includes at least the following steps: providing a substrate; bonding a package structure to the substrate; applying an adhesive layer to the substrate; applying a thermal interface material (TIM) layer to the package structure; engaging a first heat sink and a second heat sink to form a cover structure; and attaching the cover structure to the substrate and the package structure via the adhesive layer and the thermal interface material layer. Attached Figure Description

[0006] The best understanding of all aspects of this disclosure will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be increased or decreased arbitrarily for clarity of explanation.

[0007] Figures 1A to 1H This is a schematic cross-sectional view of a semiconductor die manufacturing process according to some embodiments of the present disclosure.

[0008] Figures 2A to 2C This is a schematic cross-sectional view illustrating the manufacturing process of a packaging structure according to some embodiments of the present disclosure.

[0009] Figures 3A to 3F This is a schematic cross-sectional view of a manufacturing process for a semiconductor device according to some embodiments of the present disclosure.

[0010] Figure 4 yes Figure 3F A schematic perspective view of a semiconductor device.

[0011] Figure 5 yes Figure 4 A schematic cross-sectional view of a semiconductor device.

[0012] Figure 6 This is a schematic cross-sectional view of a semiconductor device according to some alternative embodiments of the present disclosure.

[0013] Figure 7 This is a schematic cross-sectional view of a semiconductor device according to some alternative embodiments of the present disclosure.

[0014] Figure 8 This is a schematic cross-sectional view of a semiconductor device according to some alternative embodiments of the present disclosure.

[0015] Figure 9 This is a schematic cross-sectional view of a semiconductor device according to some alternative embodiments of the present disclosure.

[0016] Figure 10 This is a schematic cross-sectional view of a semiconductor device according to some alternative embodiments of the present disclosure.

[0017] Explanation of icon numbers

[0018] 10, 20, 30, 40, 50, 60: Semiconductor devices

[0019] 100: Semiconductor die

[0020] 110: Semiconductor substrate

[0021] 110': Semiconductor wafer

[0022] 120: Internal Wiring Structure

[0023] 122: Interlayer dielectric

[0024] 124: Patterned conductive layer

[0025] 130, 202: Dielectric layer

[0026] 140: Conductive pad

[0027] 150: Passivation layer

[0028] 160: Post-passivation layer

[0029] 170: Conductive column

[0030] 180, 400, 900: Conductive terminals

[0031] 200: Intermediary layer

[0032] 200a, S1: First surface

[0033] 200b, S2: Second surface

[0034] 204: Conductive Pattern Layer

[0035] 206: Through hole

[0036] 300: Encapsulation

[0037] 500: Thermal interface material (TIM) layer

[0038] 600: Adhesive layer

[0039] 700, 700a, 700b, 700c, 700d, 700e: First radiator

[0040] 702, 802: Body part

[0041] 704, 704a, 806, 806a: Groove

[0042] 706, 706a, 804, 804a: Protrusions

[0043] 800, 800a, 800b, 800c, 800d, 800e: Second heatsink

[0044] C1: First conductive layer

[0045] C2: Second conductive layer

[0046] C3: Third conductive layer

[0047] D1, D2: Distance

[0048] D 704 D 704a D 806 D 806a :depth

[0049] FS: Front Surface

[0050] H 700 H 700a H 700b H 700c H 700d H 700e Minimum height

[0051] H 706 H 706a H 804 H 804a H LS H LS1 H LS2 H LS3 H LS4 H LS5 :high

[0052] H 800 H 800a H 800b H 800c H 800d H 800e Maximum height

[0053] ISW1 700 ISW1 700a ISW1 700b ISW1 700c ISW1 700d ISW1 700e First inner wall

[0054] ISW 800 ISW 800a ISW 800b ISW 800c ISW 800d ISW 800e Inner wall

[0055] ISW2 700 ISW2 700a ISW2 700b ISW2 700c ISW2 700d ISW2 700e Second inner wall

[0056] LS, LS1, LS2, LS3, LS4, LS5: Cover structure

[0057] N: Notch

[0058] OP1, OP2: Contact openings

[0059] OP3: Opening

[0060] OSW 700 OSW700a OSW 700b OSW 700c OSW 700d OSW 700e OSW 800 OSW 800a OSW 800b OSW 800c OSW 800d OSW 800e : Lateral wall

[0061] P 704 P 704a P 706 P 706a P 804 P 804a P 806 P 806a Pitch

[0062] PKG: Packaging Structure

[0063] PR: Patterned photoresist layer

[0064] RP: Wiring pattern

[0065] RS: Rear Surface

[0066] SL: Seed layer

[0067] SUB: Substrate

[0068] T 300 T 700 T 700a T 700b T 700c T 700d T 700e T 800 T 800a T 800b T 800c T 800d T 800e T UF1 Top surface

[0069] UF1, UF2: Bottom filler layer

[0070] W 704 W 704a W 706 W 706a W 804 W 804a W 806 W 806a :width Detailed Implementation

[0071] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout this disclosure. This repetition is for the sake of brevity and clarity and does not in itself imply a relationship between the various embodiments and / or configurations discussed.

[0072] Furthermore, for ease of explanation, spatially relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. In addition to the orientations illustrated in the figures, these spatially relative terms are also intended to encompass different orientations of the device in use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein will be interpreted accordingly.

[0073] Other features and processes may also be included. For example, test structures may be included to aid in the verification testing of three-dimensional (3D) packaged or three-dimensional integrated circuit (3DIC) devices. These test structures may include, for example, test pads formed in redistribution layers or on a substrate to enable testing of 3D packages or 3DICs, the use of probes and / or probe cards, etc. Verification tests can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be combined with test methods including intermediate verification of known good dies to improve yield and reduce costs.

[0074] Figures 1A to 1H This is a schematic cross-sectional view illustrating the manufacturing process of a semiconductor die 100 according to some embodiments of the present disclosure. (Refer to...) Figure 1AA semiconductor wafer 110' is provided. In some embodiments, the semiconductor wafer 110' is made of the following materials: suitable elemental semiconductors, such as crystalline silicon, diamond, or germanium; suitable compound semiconductors, such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide; or suitable alloy semiconductors, such as silicon germanium carbide, gallium arsenide, or gallium indium phosphide. In some embodiments, the semiconductor wafer 110' has active components (e.g., transistors, etc.) and passive components (e.g., resistors, capacitors, inductors, etc.) formed therein.

[0075] In some embodiments, an interconnect structure 120 is formed on a semiconductor wafer 110'. In some embodiments, the interconnect structure 120 includes an inter-dielectric layer 122 and a plurality of patterned conductive layers 124. For simplicity, the inter-dielectric layer 122 is... Figure 1A The dielectric interlayer 122 is shown as a bulk layer, but it should be understood that it may be composed of multiple dielectric layers. Patterned conductive layers 124 and dielectric layers of the dielectric interlayer 122 are stacked alternately. In some embodiments, two adjacent patterned conductive layers 124 in the vertical direction are electrically connected to each other through a via sandwiched between the two patterned conductive layers 124.

[0076] In some embodiments, the dielectric interlayer 122 is made of polyimide, epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzoxazole (PBO), or other suitable polymer-based dielectric materials. The dielectric interlayer 122 can be formed using suitable fabrication techniques (e.g., spin coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), etc.). In some embodiments, the patterned conductive layer 124 is made of aluminum, titanium, copper, nickel, tungsten, and / or alloys thereof. The patterned conductive layer 124 can be formed by electroplating, deposition, and / or photolithography and etching. It should be noted that... Figure 1A The number of patterned conductive layers 124 and the number of dielectric layers in the dielectric interlayer 122 shown are merely exemplary and this disclosure is not limiting. In some alternative embodiments, the number of patterned conductive layers 124 and the number of dielectric layers in the dielectric interlayer 122 may be adjusted according to wiring requirements.

[0077] Reference Figure 1BA dielectric layer 130 is formed on the interconnect structure 120. In some embodiments, the material of the dielectric layer 130 includes polyimide, epoxy resin, acrylic resin, phenolic resin, BCB, PBO, or any other suitable polymer-based dielectric material. The dielectric layer 130 can be formed using suitable fabrication techniques (e.g., spin coating, CVD, PECVD, etc.). In some embodiments, a plurality of openings are formed in the dielectric layer 130 to expose a portion of the topmost patterned conductive layer 124. After forming the openings, a plurality of conductive pads 140 are formed on the dielectric layer 130. For example, conductive pads 140 are formed on the semiconductor wafer 110' and the interconnect structure 120 such that the interconnect structure 120 is located between the semiconductor wafer 110' and the conductive pads 140. In some embodiments, the positions of the conductive pads 140 correspond to the positions of the openings in the dielectric layer 130. For example, conductive pad 140 extends into an opening in dielectric layer 130 to provide an electrical connection between conductive pad 140 and a portion of interconnect structure 120 (i.e., patterned conductive layer 124). In some embodiments, conductive pad 140 is an aluminum pad, copper pad, or other suitable metal pad. The number and shape of conductive pad 140 can be selected based on requirements.

[0078] After the conductive pad 140 is distributed on the dielectric layer 130, a passivation layer 150 and a post-passivation layer 160 are sequentially formed on the dielectric layer 130 and the conductive pad 140. In some embodiments, the passivation layer 150 has a plurality of contact openings OP1, and the plurality of contact openings OP1 partially expose the conductive pad 140. In some embodiments, the passivation layer 150 is a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a dielectric layer formed of other suitable dielectric materials. Figure 1B As shown, the post-passivation layer 160 covers the passivation layer 150 and has a plurality of contact openings OP2. The conductive pad 140 is partially exposed by the contact openings OP2 of the post-passivation layer 160. In some embodiments, the post-passivation layer 160 is a polyimide layer, a PBO layer, or a dielectric layer formed of other suitable polymers. It should be noted that in some embodiments, the post-passivation layer 160 may be optional.

[0079] Reference Figure 1C After the post-passivation layer 160 is formed, a seed layer SL is conformally formed on the post-passivation layer 160. For example, at least a portion of the seed layer SL extends into the contact opening OP2 of the post-passivation layer 160 to make physical contact with the conductive pad 140. The seed layer SL can be formed by sputtering, physical vapor deposition (PVD), or the like. In some embodiments, the seed layer SL consists of two sublayers (not shown). The first sublayer may contain titanium, titanium nitride, tantalum, tantalum nitride, other suitable materials, or combinations thereof. On the other hand, the second sublayer may contain copper, copper alloys, or other suitable material selections.

[0080] Reference Figure 1D A patterned photoresist layer PR is formed on the seed layer SL. In some embodiments, the patterned photoresist layer PR is made of a photosensitive material. In some embodiments, the patterned photoresist layer PR has a plurality of openings OP3, and the plurality of openings OP3 partially expose the seed layer SL above the conductive pad 140. For example, the openings OP3 expose the seed layer SL located directly above the conductive pad 140.

[0081] Reference Figure 1E A first conductive layer C1, a second conductive layer C2, and a third conductive layer C3 are sequentially deposited on the exposed seed layer SL. For example, the first conductive layer C1, the second conductive layer C2, and the third conductive layer C3 are filled into the opening OP3 of the patterned photoresist layer PR. In some embodiments, the first conductive layer C1, the second conductive layer C2, and the third conductive layer C3 are formed using the same technique. However, this disclosure is not limited to this. In some alternative embodiments, the first conductive layer C1, the second conductive layer C2, and the third conductive layer C3 can be formed using different techniques. In some embodiments, the first conductive layer C1, the second conductive layer C2, and the third conductive layer C3 are formed by a plating process. The plating process is, for example, an electroplating process, an electroless plating process, an immersion plating process, etc. In some embodiments, the materials of the first conductive layer C1, the second conductive layer C2, and the third conductive layer C3 are different. For example, the first conductive layer C1 is made of aluminum, titanium, copper, tungsten, and / or alloys thereof. On the other hand, the second conductive layer C2 is made of nickel. Additionally, the third conductive layer C3 is made of solder. In some embodiments, the thickness of the first conductive layer C1 is greater than the thickness of the second conductive layer C2 and the thickness of the third conductive layer C3. On the other hand, the thickness of the third conductive layer C3 is greater than the thickness of the second conductive layer C2.

[0082] Reference Figure 1E and Figure 1F The patterned photoresist layer PR is removed. The patterned photoresist layer PR can be removed by etching, lift-off, ashing, or combinations thereof. Subsequently, the seed layer SL not covered by the first conductive layer C1, second conductive layer C2, and third conductive layer C3 is removed using a first conductive layer C1, second conductive layer C2, and third conductive layer C3 as a hard mask. In some embodiments, a portion of the seed layer SL is removed by etching. After removing a portion of the seed layer SL, the remaining seed layer SL lies directly beneath the first conductive layer C1. That is, the seed layer SL is sandwiched between the conductive pad 140 and the first conductive layer C1. In some embodiments, the remaining seed layer SL, the first conductive layer C1, and the second conductive layer C2 are collectively referred to as conductive pillars 170.

[0083] Reference Figure 1F and Figure 1G A reflow process is performed on the third conductive layer C3 to transform it into a conductive terminal 180. That is, a conductive terminal 180 is formed on the conductive post 170. In some embodiments, the third conductive layer C3 is reshaped during the reflow process to form a hemispherical conductive terminal 180.

[0084] Reference Figure 1G and Figure 1H ,Will Figure 1G The structure shown is monolithized to obtain Figure 1H The diagram shows multiple semiconductor dies 100. In some embodiments, the monomerization process typically involves cutting using a rotating blade and / or a laser beam. In other words, the monomerization process includes laser cutting, mechanical cutting, laser grooving, other suitable processes, or combinations thereof. For example, it can be used for... Figure 1G The structure shown is subjected to a laser grooving process to form trenches (not shown) in the structure. Subsequently, a mechanical cutting process can be performed at the location of the trenches to cut through the structure, thereby dividing the semiconductor wafer 110' into semiconductor substrates 110 and obtaining semiconductor dies 100.

[0085] like Figure 1H As shown, the semiconductor die 100 includes a semiconductor substrate 110, an interconnect structure 120, a dielectric layer 130, a conductive pad 140, a passivation layer 150, a rear passivation layer 160, a conductive pillar 170, and a conductive terminal 180. In some embodiments, the semiconductor substrate 110 has a front surface FS and a rear surface RS opposite to the front surface FS. The interconnect structure 120 is disposed on the front surface FS of the semiconductor substrate 110. The dielectric layer 130, conductive pad 140, passivation layer 150, and rear passivation layer 160 are sequentially disposed on the interconnect structure 120. The conductive pillar 170 is disposed on the rear passivation layer 160 and electrically connected to the conductive pad 140. The conductive terminal 180 is disposed on the conductive pillar 170.

[0086] In some embodiments, the semiconductor die 100 can perform logic functions. For example, the semiconductor die 100 may be a central processing unit (CPU) die, a graphics processing unit (GPU) die, a field-programmable gate array (FPGA), etc. In some embodiments, the semiconductor die 100 may be utilized in a package structure. For example, the semiconductor die 100 may be assembled with other components to form a package structure. The manufacturing process of the package structure utilizing the semiconductor die 100 will be described below.

[0087] Figures 2A to 2C This is a schematic cross-sectional view illustrating the manufacturing process of a packaging structure PKG according to some embodiments of this disclosure. (Refer to...) Figure 2A An interposer layer 200 is provided. In some embodiments, the interposer layer 200 includes a plurality of dielectric layers 202, a plurality of conductive pattern layers 204, and a plurality of vias 206. In some embodiments, the dielectric layers 202 and the conductive pattern layers 204 are stacked alternately. On the other hand, the vias 206 are embedded in the dielectric layers 202. In some embodiments, the conductive pattern layers 204 are interconnected with each other through the vias 206. For example, the vias 206 penetrate through the dielectric layers 202 to connect the conductive pattern layers 204. In some embodiments, each conductive pattern layer 204 includes a plurality of conductive patterns used as redistribution wiring. In some embodiments, Figure 2A The conductive pattern of the outermost conductive pattern layer 204 shown (i.e., the topmost and bottommost conductive pattern layers 204) can be referred to as an under-ball metallurgy (UBM) pattern for ball mounting. In some embodiments, the conductive pattern layer 204 transmits signals in the horizontal direction while the via 206 transmits signals in the vertical direction.

[0088] In some embodiments, the dielectric layer 202 is made of polyimide, epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzoxazole (PBO), or any other suitable polymer-based dielectric material. In some embodiments, the dielectric layer 202 comprises a resin mixed with a filler. The dielectric layer 202 can be formed using suitable fabrication techniques such as film lamination, spin coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), etc. In some embodiments, the conductive pattern layer 204 and the via 206 are made of aluminum, titanium, copper, nickel, tungsten, or alloys thereof. The conductive pattern layer 204 and the via 206 can be formed by electroplating, deposition, and / or photolithography and etching. In some embodiments, the conductive pattern layer 204 and the underlying via 206 are formed simultaneously. It should be noted that... Figure 2A The number of dielectric layers 202, conductive patterned layers 204, and vias 206 shown are for illustrative purposes only and this disclosure is not limited thereto. In some alternative embodiments, fewer or more dielectric layers 202, conductive patterned layers 204, and vias 206 may be formed depending on the circuit design.

[0089] In some embodiments, the interposer 200 has a first surface 200a and a second surface 200b opposite to the first surface 200a. The topmost conductive patterned layer 204 is exposed at the first surface 200a and the bottommost conductive patterned layer 204 is exposed at the second surface 200b. Figure 2A As shown, interposer 200 is a redistribution layer (RDL) interposer. However, this disclosure is not limited thereto. In some alternative embodiments, other types of interposers (e.g., silicon interposers, organic interposers, etc.) may be used as interposer 200.

[0090] like Figure 2A As shown, Figure 1H Multiple semiconductor dies 100 are bonded to a first surface 200a of an interposer 200. In some embodiments, the semiconductor dies 100 are attached to the interposer 200 via conductive terminals 180. For example, the conductive terminals 180 of the semiconductor dies 100 are in physical contact with the topmost conductive pattern layer 204 exposed at the first surface 200a of the interposer 200 to provide an electrical connection between the semiconductor dies 100 and the interposer 200. In some embodiments, after attaching the conductive terminals 180 to the topmost conductive pattern layer 204 of the interposer 200, a reflow process is performed to reshape the conductive terminals 180.

[0091] In some embodiments, the semiconductor die 100 is bonded to the interposer 200 via flip-chip bonding. In other words, the semiconductor die 100 is positioned such that the rear surface RS face of the semiconductor substrate 110 faces upwards. Figure 2A As shown, two semiconductor dies 100 are bonded to an interposer 200. However, it should be noted that... Figure 2A The number of semiconductor dies 100 shown is merely exemplary and this disclosure is not limiting. In some alternative embodiments, the number of semiconductor dies 100 may be adjusted according to the design. For example, a single semiconductor die 100 may be bonded to the interposer 200, or more than two semiconductor dies 100 may be bonded to the interposer 200. Furthermore, as... Figure 2AAs shown, two identical semiconductor dies 100 are bonded to the interposer 200. However, this disclosure is not limited to this. In some alternative embodiments, semiconductor dies with different functions may be bonded to the interposer 200. For example, as described above, semiconductor die 100 is capable of performing logic functions. Therefore, in some alternative embodiments, one of the semiconductor dies 100 may be replaced by another die capable of performing storage functions. For example, one of the semiconductor dies 100 may be replaced by Dynamic Random Access Memory (DRAM), Resistive Random Access Memory (RRAM), Static Random Access Memory (SRAM), etc.

[0092] In some embodiments, a bottom filler layer UF1 is formed on the interposer 200 to partially encapsulate the semiconductor die 100. For example, the bottom filler layer UF1 surrounds the conductive pillars 170 and conductive terminals 180 of the semiconductor die 100. The bottom filler layer UF1 also completely covers the inner sidewall of each semiconductor die 100 and partially covers the outer sidewall of each semiconductor die 100. For example, the portion of the bottom filler layer UF1 located between two adjacent semiconductor dies 100 has a top surface T that is substantially coplanar with the rear surface RS of the semiconductor substrate 110 of the semiconductor die 100. UF1 However, this disclosure is not limited thereto. In some alternative embodiments, the top surface T of the bottom filler layer UF1 UF1 It may be located below or above the rear surface RS of the semiconductor substrate 110. In some embodiments, the material of the bottom filler layer UF1 is an insulating material and includes resin (e.g., epoxy resin), filler material, stress release agent (SRA), adhesion promoter, other materials, or combinations thereof. In some embodiments, the bottom filler layer UF1 is optional.

[0093] Reference Figure 2B An encapsulation body 300 is formed on the interposer layer 200 to encapsulate the semiconductor die 100 and the underfill layer UF1. For example, the encapsulation body 300 laterally encapsulates the semiconductor die 100 and the underfill layer UF1. Figure 2B As shown, the top surface T of the encapsulation body 300 300 The rear surface RS of the semiconductor substrate 110 of the semiconductor die 100 and the top surface T of the bottom filler layer UF1 UF1They are substantially coplanar. That is, the encapsulation 300 exposes the semiconductor substrate 110 of the semiconductor die 100. In some embodiments, the encapsulation 300 is a molding compound, a molding underfill, a resin (e.g., epoxy resin), etc. In some embodiments, the encapsulation 300 includes filler. The filler may be particles made of silicon dioxide, aluminum dioxide, etc. In some embodiments, the encapsulation 300 is formed by molding processes, injection processes, combinations thereof, etc. Molding processes include, for example, transfer molding processes, compression molding processes, etc.

[0094] Reference Figure 2C A plurality of conductive terminals 400 are formed on the second surface 200b of the interposer layer 200. In some embodiments, the conductive terminals 400 are solder balls, ball grid array (BGA) balls, etc. In some embodiments, the conductive terminals 400 are made of a conductive material with low resistivity (e.g., Sn, Pb, Ag, Cu, Ni, Bi, or alloys thereof). In some embodiments, the conductive terminals 400 are in solid contact with the bottommost conductive pattern layer 204 exposed at the second surface 200b of the interposer layer 200.

[0095] After the conductive terminals 400 are formed, a monomerization process is performed on the encapsulation 300 and the interposer 200 to obtain multiple package structures PKG. In some embodiments, the monomerization process typically involves cutting using a rotating blade and / or a laser beam. In other words, the monomerization process includes laser cutting, mechanical cutting, laser grooving, other suitable processes, or combinations thereof. In some embodiments, since the interposer 200 is in wafer form, the package structure PKG is considered to be formed via a chip-on-wafer process.

[0096] In some embodiments, a packaged PKG structure can be used in a semiconductor device. For example, the packaged PKG structure can be assembled with other components to form a semiconductor device. The manufacturing process of a semiconductor device utilizing a packaged PKG structure will be described below.

[0097] Figures 3A to 3F This is a schematic cross-sectional view illustrating the manufacturing process of a semiconductor device 10 according to some embodiments of the present disclosure. (Refer to...) Figure 3A A substrate SUB is provided. In some embodiments, the substrate SUB is a printed circuit board (PCB) or the like. In some embodiments, the substrate SUB is referred to as a circuit substrate. In some embodiments, the substrate SUB includes a plurality of wiring patterns RP embedded in the substrate SUB. In some embodiments, the wiring patterns RP are interconnected with each other. That is, the wiring patterns RP are electrically connected to each other. Figure 3AAs shown, the substrate SUB has a first surface S1 and a second surface S2 opposite to the first surface S1. In some embodiments, some wiring patterns RP are exposed at the first surface S1 and some wiring patterns RP are exposed at the second surface S2.

[0098] like Figure 3A As shown, Figure 2C The package structure PKG is bonded to a first surface S1 of the substrate SUB. In some embodiments, the package structure PKG is attached to the substrate SUB via conductive terminals 400. For example, the conductive terminals 400 of the package structure PKG contact the exposed wiring pattern RP on the first surface S1 of the substrate SUB to provide an electrical connection between the package structure PKG and the substrate SUB. In some embodiments, after the conductive terminals 400 are attached to the wiring pattern RP of the substrate SUB, a reflow process may be performed to reshape the conductive terminals 400.

[0099] In some embodiments, an underfill layer UF2 is formed between the package structure PKG and the first surface S1 of the substrate SUB. For example, the underfill layer UF2 surrounds the bottommost conductive pattern layer 204 and conductive terminals 400 of the package structure PKG. In some embodiments, the underfill layer UF2 is used to protect these components. In some embodiments, the underfill layer UF2 further covers a portion of each sidewall of the package structure PKG. In some embodiments, the material of the underfill layer UF2 is an insulating material and includes resin (e.g., epoxy resin), filler material, stress relief agent (SRA), adhesion promoter, other materials, or combinations thereof. In some embodiments, the underfill layer UF2 is optional.

[0100] Reference Figure 3BA thermal interface material (TIM) layer 500 is formed on the packaging structure PKG. The TIM layer 500 comprises a polymer with good thermal conductivity (Tk), which may be between about 3 W / m·K and about 5 W / m·K. In some embodiments, the TIM layer 500 further comprises a thermally conductive filler dispersed in the polymer. The thermally conductive filler can increase the effective Tk of the TIM layer 500 to between about 10 W / m·K and about 50 W / m·K or higher. Suitable materials for the thermally conductive filler include alumina, boron nitride, aluminum nitride, aluminum, copper, silver, indium, and combinations thereof. In some alternative embodiments, the TIM layer 500 comprises other materials, such as metallic materials containing silver or indium paste, or solder-based materials. The TIM layer 500 may be in liquid form or may be a dry film. When the TIM layer 500 is in liquid form, it is dispensed / applied onto the PKG packaging structure. When the TIM layer 500 is a dry film, it is adhered to the PKG packaging structure.

[0101] like Figure 3B As shown, the TIM layer 500 is in physical contact with the semiconductor die 100, the underfill layer UF1, and the encapsulation 300. It should be noted that although the TIM layer 500 is shown as a continuous layer extending over the underfill layer UF1 and the two semiconductor dies 100, this disclosure is not limited thereto. In some alternative embodiments, the TIM layer 500 may be a discontinuous layer. For example, the discontinuous pattern of the TIM layer 500 may cover the semiconductor dies 100 respectively, and air gaps may exist directly above the underfill layer UF1 located between the semiconductor dies 100. In some embodiments, the air gaps can further reduce lateral thermal interactions between the semiconductor dies 100.

[0102] like Figure 3BAs shown, an adhesive layer 600 is formed on the first surface S1 of the substrate SUB. For example, the adhesive layer 600 is formed along the edge of the first surface S1 of the substrate SUB to surround / enclose the package structure PKG and the underfill layer UF2. In some embodiments, the adhesive layer 600 partially covers the first surface S1 of the substrate SUB. For example, the package structure PKG and the underfill layer UF2 are physically separated from the adhesive layer 600. As described above, the adhesive layer 600 is formed along the edge of the first surface S1 of the substrate SUB, therefore the shape of the adhesive layer 600 depends on the shape of the substrate SUB. For example, when the substrate SUB is in wafer form (i.e., having a circular top view), the adhesive layer 600 presents a circular ring shape in the top view. When the substrate SUB is in panel form (i.e., having a rectangular or square top view), the adhesive layer presents a rectangular ring shape or a square ring shape in the top view. In some embodiments, the adhesive layer 600 is applied to the substrate SUB by dispensing, spin coating, etc.

[0103] In some embodiments, the material of the adhesive layer 600 differs from the material of the TIM layer 500. For example, the adhesive layer 600 has better adhesion and lower thermal conductivity than the TIM layer 500. In some embodiments, the adhesive layer 600 has a thermal conductivity of less than about 0.5 W / m·K. In some embodiments, the adhesive layer 600 comprises an epoxy-based material. However, this disclosure is not limited thereto. In some alternative embodiments, other polymeric materials with adhesive properties may be used as the adhesive layer 600.

[0104] Reference Figure 3C and Figure 3D A cover structure LS is provided. In some embodiments, the cover structure LS includes a first heat sink 700 and a second heat sink 800, with the first heat sink 700 connected to the second heat sink 800. For example, the cover structure LS is formed by assembling the first heat sink 700 and the second heat sink 800. In other words, the first heat sink 700 is engaged to the second heat sink 800 to form the cover structure LS. In some embodiments, the first heat sink 700 is a rim structure in perspective view (in... Figure 4 As shown in the diagram, the second heat sink 800 is a hat structure in the perspective view. Figure 4 (as shown in the image).

[0105] In some embodiments, the material of the first radiator 700 differs from the material of the second radiator 800. For example, the material of the first radiator 700 includes copper-tungsten alloy, alloy 42 (a nickel-iron alloy containing 42% nickel), etc. On the other hand, the material of the second radiator 800 includes copper, silver diamond, copper-molybdenum alloy (50%:50% or 40%:60%), copper-tungsten alloy, etc. It should be noted that although copper-tungsten alloy is a common material for both the first radiator 700 and the second radiator 800, copper-tungsten alloy cannot be used simultaneously for both radiators. In some embodiments, when the material of the first radiator 700 is copper-tungsten alloy, the material of the second radiator 800 is copper. On the other hand, when the material of the first radiator 700 is alloy 42, the material of the second radiator 800 can be selected from silver diamond, copper-molybdenum alloy (50%:50% or 40%:60%), and copper-tungsten alloy.

[0106] In some embodiments, the coefficient of thermal expansion (CTE) and Young's modulus of the first heat sink 700 are different from those of the second heat sink 800. In some embodiments, the CTE of the first heat sink 700 is in the range of about 4.35 ppm / °C to about 10.5 ppm / °C, and the CTE of the second heat sink 800 is in the range of about 7.2 ppm / °C to about 17 ppm / °C. On the other hand, the Young's modulus of the first heat sink 700 is in the range of about 145 GPa to about 330 GPa, and the Young's modulus of the second heat sink 800 is in the range of about 110 GPa to about 330 GPa. In some embodiments, when the material of the first heat sink 700 is a copper-tungsten alloy or Alloy 42, the CTE of the first heat sink 700 is 10.5 ppm / °C or 4.35 ppm / °C, and the Young's modulus of the first heat sink 700 is 330 GPa or 145 GPa, respectively. In some embodiments, when the material of the second heat sink 800 is copper, silver diamond, copper-molybdenum alloy (50%:50%), copper-molybdenum alloy (40%:60%), or copper-tungsten alloy, the CTE of the second heat sink 800 is 17 ppm / ℃, 7.2 ppm / ℃, 12.1 ppm / ℃, 10.5 ppm / ℃, or 10.5 ppm / ℃, respectively, and the Young's modulus of the second heat sink 800 is 110 GPa, 275 GPa, 120 GPa, 170 GPa, or 330 GPa, respectively. In some embodiments, the ratio of the CTE of the second heat sink 800 to the CTE of the first heat sink 700 is in the range of about 1:0.36 to about 1:0.62. In some embodiments, the ratio of the Young's modulus of the second heat sink 800 to the Young's modulus of the first heat sink 700 is in the range of about 1:0.44 to about 1:3.

[0107] In some embodiments, the first heat sink 700 includes a body portion 702 and a plurality of recesses 704 recessed from the top surface of the body portion 702. For example... Figure 3C As shown in the cross-sectional view, the body portion 702 is L-shaped and grooves 704 are formed on the L-shaped base. In some embodiments, each groove 704 presents a ring shape in the top view. In other words, the grooves 704 are concentric rings in the top view. In some embodiments, the grooves 704 are formed by removing a portion of the body portion 702 through etching, cutting, drilling, etc. In some embodiments, the second heat sink 800 includes a body portion 802 and a plurality of protrusions 804 projecting from the bottom surface of the body portion 802. Figure 3CAs shown, the body portion 802 is inverted U-shaped, and a protrusion 804 is formed on the leg of the inverted U-shape. In some embodiments, the protrusion 804 of the second heat sink 800 is integrally formed with the body portion 802. For example, the protrusion 804 can be formed by removing a portion of the body portion 802 through etching, cutting, drilling, etc. In some embodiments, each protrusion 804 presents a ring shape in a bottom view. In other words, the protrusion 804 is a concentric ring in a bottom view. In some embodiments, the first heat sink 700 and the second heat sink 800 are assembled by engaging the protrusion 804 of the second heat sink 800 with the groove 704 of the first heat sink 700, as shown. Figure 3C As shown. The following will combine Figure 3D Describe the dimensions of the cover structure LS.

[0108] Reference Figure 3D The cover structure LS has a height H ranging from approximately 3.45 mm to approximately 4.0 mm. LS In some embodiments, the first heat sink 700 has a minimum height H ranging from about 0.75 mm to about 2.45 mm. 700 Meanwhile, the second heat sink 800 has a maximum height H ranging from approximately 1 mm to approximately 2.7 mm. 800 In some embodiments, the depth D of each groove 704 704 It falls within the range of greater than 0 μm and less than 1500 μm. On the other hand, the width W of each groove 704... 704 Within the range of greater than 0 μm and less than 1000 μm. For example... Figure 3D As shown, each recess 704 of the first heat sink 700 has substantially the same depth D. 704 Additionally, each recess 704 of the first heat sink 700 may have substantially the same width W. 704 In some embodiments, the pitch P between two adjacent grooves 704 704 (That is, the distance between the centers of the two adjacent grooves 704) is in the range of greater than 0 μm and less than 2500 μm. In some embodiments, the height H of each protrusion 804 is... 804 It falls within the range of greater than 0 μm and less than 1500 μm. On the other hand, the width W of each protrusion 804... 804 Within the range of greater than 0 μm and less than 1000 μm. For example... Figure 3D As shown, each protrusion 804 of the second radiator 800 has substantially the same height H. 804 Additionally, each protrusion 804 of the second heat sink 800 may have substantially the same width W. 804In some embodiments, the pitch P between two adjacent protrusions 804 804 (That is, the distance between the centers of the two adjacent protrusions 804) is in the range of greater than 0 μm and less than 2500 μm.

[0109] In some embodiments, the recess 704 of the first heat sink 700 perfectly fits the corresponding protrusion 804 of the second heat sink 800. In other words, the width W of each protrusion 804 of the second heat sink 800 is... 804 The width W of the groove 704 corresponding to the first heat sink 700 704 The two are essentially the same, and the height H of each protrusion 804 of the second radiator 800 is the same. 804 The depth D of the groove 704 corresponding to the first heat sink 700 704 They are substantially the same. That is, the shape of each protrusion 804 of the second radiator 800 is substantially the same as the shape of the corresponding recess 704 of the first radiator 700. In this way, the protrusions 804 of the second radiator 800 are securely embedded in the recesses 704 of the first radiator 700 without any adhesive material. For example, the protrusions 804 of the second radiator 800 are surrounded by and securely fixed by the body portion 702 of the first radiator 700. In other words, the first radiator 700 and the second radiator 800 are in solid contact. Thus, the cover structure LS is considered to have a fool-proof design for assembly.

[0110] It should be noted that in some alternative embodiments, the protrusions 804 of the second heat sink 800 may not perfectly fit with the recesses 704 of the first heat sink 700. For example, in some alternative embodiments, the width W of each protrusion 804 of the second heat sink 800 may be... 804 The width W of the groove 704 corresponding to the first heat sink 700 704 They are essentially the same, but the height H of each protrusion 804 of the second radiator 800 is the same. 804 The depth D of the corresponding groove 704 of the first heatsink 700 is different. 704 Despite the height H of protrusion 804 804 The depth D of the groove 704 is different 704 However, since the width is the same (i.e., the width W of the protrusion 804 is the same), 804 Width W of groove 704 704 (Essentially the same), the protrusion 804 can still be firmly engaged with the groove 704 without any adhesive material.

[0111] As described above, the first radiator 700 is L-shaped in cross-sectional view. Therefore, the first radiator 700 has a first inner sidewall ISW1. 700 and the second inner sidewall ISW2 700 ,like Figure 3D As shown in the diagram. Meanwhile, the first radiator 700 has a connection with the first inner sidewall ISW1. 700 and the second inner sidewall ISW2 700 A relative outer sidewall OSW 700 In some embodiments, the second heat sink 800 has an inner sidewall ISW. 800 and the inner sidewall ISW 800 Relative outer wall OSW 800 .like Figure 3D As shown, the first inner wall ISW1 of the first radiator 700 700 The inner wall of the second radiator 800 is ISW 800 It has an offset. For example, on the first inner wall ISW1 of the first heatsink 700. 700 The inner wall of the second radiator 800 is ISW 800 There is a distance D1 between them of approximately 200 μm to approximately 500 μm. For example... Figure 3D As shown, the outer wall OSW of the second heat sink 800 800 The second inner sidewall ISW2 of the first radiator 700 700 Spacing out. For example, on the outer wall of the second radiator 800, OSW 800 The second inner sidewall ISW2 of the first radiator 700 700 There is a distance D2 between them of approximately 200 μm to approximately 500 μm.

[0112] Reference Figure 3E ,Will Figure 3D The cover structure LS shown is disposed on the substrate SUB and the package structure PKG, such that the package structure PKG is located between the cover structure LS and the substrate SUB. In some embodiments, the cover structure LS is attached to the substrate SUB and the package structure PKG via a TIM layer 500 and an adhesive layer 600. For example, the cover structure LS is placed on the substrate SUB and the package structure PKG and pressed against the TIM layer 500 and the adhesive layer 600, thereby causing the first heat sink 700 to be attached to the substrate SUB via the adhesive layer 600 and causing the second heat sink 800 to be attached to the package structure PKG via the TIM layer 500. Figure 3EAs shown, a first heat sink 700 surrounds the package structure PKG and the bottom filler layer UF2. In some embodiments, the first heat sink 700 is spatially spaced from the package structure PKG and the bottom filler layer UF2. In some embodiments, a second heat sink 800 is disposed on the package structure PKG and spatially spaced from the substrate SUB.

[0113] like Figure 3E As shown, the sidewall of the first heat sink 700 is aligned with the sidewall of the adhesive layer 600. However, this disclosure is not limited thereto. In some alternative embodiments, based on... Figure 3B Depending on the amount of adhesive layer 600 applied in the steps shown, during the bonding process of the cover structure LS, the adhesive layer 600 may overflow the sidewall of the first heat sink 700 or may not flow sufficiently to the sidewall of the first heat sink 700. That is, in some alternative embodiments, the sidewall of the first heat sink 700 is not aligned with the sidewall of the adhesive layer 600. Similarly, as Figure 3E As shown, the sidewalls of the encapsulation structure PKG are aligned with the sidewalls of the TIM layer 500. However, this disclosure is not limited thereto. In some alternative embodiments, based on... Figure 3B Depending on the amount of TIM layer 500 applied in the steps shown, the TIM layer 500 may overflow the sidewalls of the package structure PKG or may not flow sufficiently to the sidewalls of the package structure PKG during the bonding process of the cover structure LS. That is, in some alternative embodiments, the sidewalls of the package structure PKG are not aligned with the sidewalls of the TIM layer 500.

[0114] Reference Figure 3F A plurality of conductive terminals 900 are formed on the second surface S2 of the substrate SUB to obtain a semiconductor device 10. In some embodiments, the conductive terminals 900 are solder balls, ball grid array (BGA) balls, etc. In some embodiments, the conductive terminals 900 are made of a conductive material with low resistivity (e.g., Sn, Pb, Ag, Cu, Ni, Bi, or alloys thereof). In some embodiments, the conductive terminals 900 are in contact with the wiring pattern RP entity exposed at the second surface S2 of the substrate SUB.

[0115] like Figure 3F As shown, the top surface T of the second heat sink 800 800 Located on the top surface T of the first heatsink 700 700 At a height higher than the horizontal level. However, it should be understood that, Figure 3F Only a cross-sectional view of the semiconductor device 10 is shown, and does not represent the shape of the entire first heat sink 700. The following will combine... Figure 3F , Figure 4 and Figure 5 Discuss the shape of the first radiator 700.

[0116] Figure 4 yes Figure 3F A schematic perspective view of the semiconductor device 10 in the diagram. Figure 5 yes Figure 4 A schematic cross-sectional view of the semiconductor device 10. Please note that... Figure 3F The cross-sectional view of the semiconductor device 10 shown is along... Figure 4 The line A-A' in the middle is intercepted, and Figure 5 The cross-sectional view of the semiconductor device 10 shown is along... Figure 4 Cut off line B-B' in the middle. (Refer to...) Figure 3F , Figure 4 and Figure 5 The first heat sink 700 has a plurality of notches N. In some embodiments, the notches N are located at the middle portion of the edge of the semiconductor device 10. In other words, the height of the first heat sink 700 at the four corners of the semiconductor device 10 is greater than the height of the first heat sink 700 at the middle portion of the edge of the semiconductor device 10. For example, such as Figure 3F As shown, at the middle portion of the edge of the semiconductor device 10, the top surface T of the second heat sink 800 800 Located on the top surface T of the first heatsink 700 700 At a higher level. On the other hand, such as Figure 5 As shown, at the corner of the semiconductor device 10, the top surface T of the second heat sink 800 800 With the top surface T of the first heat sink 700 700 They are essentially at the same horizontal level.

[0117] In some embodiments, the cap structure LS provides a heat dissipation function. In other words, heat generated during the operation of the semiconductor die 100 can be dissipated through the path created by the cap structure LS. In some embodiments, during the manufacturing process of the semiconductor device 10, especially during high-temperature thermal processes, delamination may occur between components of the semiconductor device 10 due to CTE mismatch between two different materials. However, as described above, the cap structure LS includes a first heat sink 700 and a second heat sink 800 with different CTEs and different Young's moduli. By employing the first heat sink 700 and the second heat sink 800 with different CTEs and different Young's moduli, the stress applied during thermal processes can be sufficiently reduced or compensated. In this way, delamination between components within the semiconductor device 10 can be effectively eliminated.

[0118] Figure 6 This is a schematic cross-sectional view of a semiconductor device 20 according to some alternative embodiments of the present disclosure. (Refer to...) Figure 6 , Figure 6The semiconductor device 20 in the middle is similar to Figure 3F The semiconductor device 10 in the figure, therefore similar elements are indicated by the same reference numerals and their detailed descriptions are omitted herein. However, Figure 3F The cover structure LS in the middle is Figure 6 The cover structure LS1 is replaced in some embodiments. In some embodiments, the cover structure LS1 includes a first heat sink 700a and a second heat sink 800a. Figure 6 The first radiator 700a and the second radiator 800a are similar to... Figure 3D The first heatsink 700 and the second heatsink 800 are described in detail herein, therefore their detailed descriptions are omitted. However, the first heatsink 700a includes components with different depths D. 704a Multiple recesses 704a. Additionally, the second heat sink 800a includes recesses with different heights H. 804a Multiple protrusions 804a.

[0119] like Figure 6 As shown in the cross-sectional view, the body portion 702 is L-shaped and a groove 704a is formed on the L-shaped base. In some embodiments, each groove 704a presents a ring shape in the top view. In other words, the groove 704a is a concentric ring in the top view. In some embodiments, the groove 704a is formed by removing a portion of the body portion 702 through etching, cutting, drilling, etc. Figure 6 As shown, the body portion 802 is inverted U-shaped, and a protrusion 804a is formed on the leg of the inverted U-shape. In some embodiments, the protrusion 804a of the second heat sink 800 is integrally formed with the body portion 802. For example, the protrusion 804a can be formed by removing a portion of the body portion 802 through etching, cutting, drilling, etc. In some embodiments, each protrusion 804a presents a ring shape in a bottom view. In other words, the protrusion 804a is a concentric ring in a bottom view.

[0120] Reference Figure 6 The cover structure LS1 has a height H ranging from approximately 3.45 mm to approximately 5.0 mm. LS1 In some embodiments, the first heat sink 700a has a minimum height H ranging from about 0.75 mm to about 2.45 mm. 700a Meanwhile, the second heat sink 800a has a maximum height H ranging from approximately 1 mm to approximately 2.7 mm. 800a As mentioned above, the groove 704a has a different depth D. 704a The depth D of these grooves 704a 704a It can be within the range of greater than 0 μm and less than 1500 μm. On the other hand, the width W of each groove 704a 704aWithin the range of greater than 0 μm and less than 1000 μm. For example... Figure 6 As shown, each recess 704a of the first heat sink 700a has a substantially equal width W. 704a In some embodiments, the pitch P between two adjacent grooves 704a 704a (That is, the distance between the centers of the two adjacent grooves 704a) is within the range of greater than 0 μm and less than 2500 μm. As mentioned above, the protrusions 804a have different heights H. 804a The height H of these protrusions 804a 804a It can be within the range of greater than 0 μm and less than 1500 μm. On the other hand, the width W of each protrusion 804a 804a Within the range of greater than 0 μm and less than 1000 μm. For example... Figure 6 As shown, each protrusion 804a of the second radiator 800a has a substantially equal width W. 804a In some embodiments, the pitch P between two adjacent protrusions 804a 804a (That is, the distance between the centers of the two adjacent protrusions 804a) is in the range of greater than 0 μm and less than 2500 μm.

[0121] In some embodiments, the recess 704a of the first heat sink 700a perfectly fits the corresponding protrusion 804a of the second heat sink 800a. In other words, the width W of each protrusion 804a of the second heat sink 800a is... 804a The width W of the groove 704a corresponding to the first heat sink 700a 704a The two are essentially the same, and the height H of each protrusion 804a of the second radiator 800a is the same. 804a The depth D of the groove 704a corresponding to the first heat sink 700a 704a They are substantially the same. That is, the shape of each protrusion 804a of the second radiator 800a is substantially the same as the shape of the corresponding groove 704a of the first radiator 700a. In this way, the protrusions 804a of the second radiator 800a are securely embedded in the grooves 704a of the first radiator 700a without any adhesive material. For example, the protrusions 804a of the second radiator 800a are surrounded by and securely fixed by the body portion 702 of the first radiator 700a. In other words, the first radiator 700a and the second radiator 800a are in solid contact. Thus, the cover structure LS1 is considered to have a foolproof design for assembly.

[0122] It should be noted that in some alternative embodiments, the protrusions 804a of the second heat sink 800a may not perfectly fit with the recesses 704a of the first heat sink 700a. For example, in some alternative embodiments, the width W of each protrusion 804a of the second heat sink 800a may be... 804a The width W of the groove 704a corresponding to the first heat sink 700a 704a They are essentially the same, but the height H of each protrusion 804a of the second radiator 800a is the same. 804a The depth D of the corresponding groove 704a of the first heat sink 700a is different. 704a Despite the height H of protrusion 804a 804a The depth D of groove 704a is different 704a However, since the width is the same (i.e., the width W of the protrusion 804a is the same), 804a Width W of groove 704a 704a (Essentially the same), the protrusion 804a can still be firmly engaged in the groove 704a without any adhesive material.

[0123] As described above, the first radiator 700a is L-shaped in cross-sectional view. Therefore, the first radiator 700a has a first inner sidewall ISW1. 700a and the second inner sidewall ISW2 700a ,like Figure 6 As shown in the diagram. Meanwhile, the first radiator 700a has a connection with the first inner sidewall ISW1. 700a and the second inner sidewall ISW2 700a A relative outer sidewall OSW 700a In some embodiments, the second heat sink 800a has an inner sidewall ISW. 800a and the inner sidewall ISW 800a Relative outer wall OSW 800a .like Figure 6 As shown, the first inner wall ISW1 of the first radiator 700a 700a The inner wall of the second radiator 800a is ISW 800a It has a bias. For example, in the first inner wall ISW1 of the first radiator 700a. 700a The inner wall of the second radiator 800a is ISW 800a There is a distance D1 between them of approximately 200 μm to approximately 500 μm. For example... Figure 6 As shown, the outer wall OSW of the second radiator 800a 800a The second inner sidewall ISW2 of the first radiator 700a 700a Spacing out. For example, on the outer wall of the second radiator 800a, OSW 800a The second inner sidewall ISW2 of the first radiator 700a700a There is a distance D2 between them of approximately 200 μm to approximately 500 μm.

[0124] like Figure 6 As shown, the inner wall of the second radiator 800a is ISW 800a and outer side OSW 800a The height H of the closer protrusion 804a 804a The inner wall ISW is greater than 800a from the second radiator. 800a and outer side OSW 800a The height H of the more distant protrusion 804a 804a In other words, the height H of the protrusion 804a 804a ISW towards the inner wall of the second radiator 800a 800a and outer side OSW 800a Gradually increasing. However, this disclosure is not limited thereto. In some embodiments, the height H of the protrusion 804a is... 804a The inner wall of the second radiator 800a is ISW 800a and outer side OSW 800a Gradually decrease.

[0125] like Figure 6 As shown in the cross-sectional view, in the semiconductor device 20, the top surface T of the second heat sink 800a 800a Located on the top surface T of the first heat sink 700a 700a At a higher horizontal level. However, similar to the cross-sectional view of semiconductor device 10, in some other cross-sectional views of semiconductor device 20, the top surface T of the second heat sink 800a is at a higher horizontal level. 800a The top surface T of the first heat sink 700a 700a They are essentially at the same horizontal level.

[0126] In some embodiments, the cover structure LS1 provides a heat dissipation function. In other words, heat generated during the operation of the semiconductor die 100 can be dissipated through the path created by the cover structure LS1. In some embodiments, during the manufacturing process of the semiconductor device 20, particularly during high-temperature thermal processes, delamination may occur between components of the semiconductor device 20 due to CTE mismatch between two different materials. However, as described above, the cover structure LS1 includes a first heat sink 700a and a second heat sink 800a with different CTEs and different Young's moduli. By employing the first heat sink 700a and the second heat sink 800a with different CTEs and different Young's moduli, the stress applied during thermal processes can be sufficiently reduced or compensated. In this way, delamination between components within the semiconductor device 20 can be effectively eliminated.

[0127] Figure 7This is a schematic cross-sectional view of a semiconductor device 30 according to some alternative embodiments of the present disclosure. (Refer to...) Figure 7 , Figure 7 The semiconductor device 30 in the middle is similar to Figure 3F The semiconductor device 10 in the figure, therefore similar elements are indicated by the same reference numerals and their detailed descriptions are omitted herein. However, Figure 3F The cover structure LS in the middle is Figure 7 The cover structure LS2 is replaced in some embodiments. In some embodiments, the cover structure LS2 includes a first heat sink 700b and a second heat sink 800b. Figure 7 The materials of the first radiator 700b and the second radiator 800b are similar to those of the following: Figure 3C The materials of the first heat sink 700 and the second heat sink 800 are not detailed in this document.

[0128] In some embodiments, the first heat sink 700b includes a body portion 702 and a plurality of protrusions 706 projecting from the top surface of the body portion 702. For example... Figure 7 As shown in the cross-sectional view, the body portion 702 is L-shaped and protrusions 706 are formed on the L-shaped base. In some embodiments, each protrusion 706 presents a ring shape in the top view. In other words, the protrusions 706 are concentric rings in the top view. In some embodiments, the protrusions 706 of the first heat sink 700b are integrally formed with the body portion 702. For example, the protrusions 706 can be formed by removing a portion of the body portion 702 through etching, cutting, drilling, etc. In some embodiments, the second heat sink 800b includes a body portion 802 and a plurality of recesses 806 recessed from the bottom surface of the body portion 802. Figure 7 As shown in the cross-sectional view, the body portion 802 presents an inverted U-shape, and grooves 806 are formed on the legs of the inverted U-shape. In some embodiments, each groove 806 presents a ring shape in the bottom view. In other words, the grooves 806 are concentric rings in the bottom view. In some embodiments, the grooves 806 are formed by removing a portion of the body portion 802 through etching, cutting, drilling, etc. In some embodiments, the first heat sink 700b and the second heat sink 800b are assembled by engaging the protrusion 706 of the first heat sink 700b with the groove 806 of the second heat sink 800b, as shown in the cross-sectional view. Figure 7 As shown in the image.

[0129] In some embodiments, the cover structure LS2 has a height H ranging from about 3.45 mm to about 5.0 mm. LS2 In some embodiments, the first heat sink 700b has a minimum height H ranging from about 0.75 mm to about 2.45 mm. 700bMeanwhile, the second heatsink 800b has a maximum height H ranging from approximately 1 mm to approximately 2.7 mm. 800b In some embodiments, the height H of each protrusion 706 706 It falls within the range of greater than 0 μm and less than 1500 μm. On the other hand, the width W of each protrusion 706... 706 Within the range of greater than 0 μm and less than 1000 μm. For example... Figure 7 As shown, each protrusion 706 of the first radiator 700b has substantially the same height H. 706 Additionally, each protrusion 706 of the first heat sink 700b may have substantially the same width W. 706 In some embodiments, the pitch P between two adjacent protrusions 706 706 (That is, the distance between the centers of the two adjacent protrusions 706) is in the range of greater than 0 μm and less than 2500 μm. In some embodiments, the depth D of each groove 806 is... 806 It falls within the range of greater than 0 μm and less than 1500 μm. On the other hand, the width W of each groove 806... 806 Within the range of greater than 0 μm and less than 1000 μm. For example... Figure 7 As shown, each recess 806 of the second heat sink 800b has substantially the same depth D. 806 Additionally, each recess 806 of the second heat sink 800b may have substantially the same width W. 806 In some embodiments, the pitch P between two adjacent grooves 806 806 (That is, the distance between the centers of the two adjacent grooves 806) is in the range of greater than 0 μm and less than 2500 μm.

[0130] In some embodiments, the protrusions 706 of the first heat sink 700b perfectly fit into the corresponding recesses 806 of the second heat sink 800b. In other words, the width W of each protrusion 706 of the first heat sink 700b is... 706 The width W of the groove 806 corresponding to the second heat sink 800b 806 The components are substantially the same, and the height H of each protrusion 706 of the first radiator 700b is [missing information]. 706 The depth D of the groove 806 corresponding to the second heat sink 800b 806They are substantially the same. That is, the shape of each protrusion 706 of the first heat sink 700b is substantially the same as the shape of the corresponding recess 806 of the second heat sink 800b. In this way, the protrusions 706 of the first heat sink 700b are securely embedded in the recesses 806 of the second heat sink 800b without any adhesive material. For example, the protrusions 706 of the first heat sink 700b are surrounded by and securely fixed by the body portion 802 of the second heat sink 800b. In other words, the first heat sink 700b and the second heat sink 800b are in solid contact. Thus, the cover structure LS2 is considered to have a foolproof design for assembly.

[0131] It should be noted that in some alternative embodiments, the protrusions 706 of the first heat sink 700b and the recesses 806 of the second heat sink 800b may not fit perfectly. For example, in some alternative embodiments, the width W of each protrusion 706 of the first heat sink 700b may be... 706 The width W of the groove 806 corresponding to the second heat sink 800b 806 They are essentially the same, but the height H of each protrusion 706 of the first radiator 700b is the same. 706 The depth D of the corresponding recess 806 of the second heatsink 800b is different. 806 Despite the height H of the protrusion 706 706 Unlike the depth D of groove 806 806 However, since the width is the same (i.e., the width W of the protrusion 706 is the same), 706 Width W of groove 806 806 (Essentially the same), the protrusion 706 can still be firmly engaged with the groove 806 without any adhesive material.

[0132] As described above, the first heat sink 700b is L-shaped in cross-sectional view. Therefore, the first heat sink 700b has a first inner sidewall ISW1. 700b and the second inner sidewall ISW2 700b ,like Figure 7 As shown in the diagram. Meanwhile, the first radiator 700b has a connection with the first inner sidewall ISW1. 700b and the second inner sidewall ISW2 700b A relative outer sidewall OSW 700b In some embodiments, the second heat sink 800b has an inner sidewall ISW. 800b and the inner sidewall ISW 800b Relative outer wall OSW 800b .like Figure 7 As shown, the first inner wall ISW1 of the first radiator 700b 700b With the inner wall of the second heatsink 800b ISW800b It has a bias. For example, on the first inner sidewall ISW1 of the first heatsink 700b. 700b With the inner wall of the second heatsink 800b ISW 800b There is a distance D1 between them of approximately 200 μm to approximately 500 μm. For example... Figure 7 As shown, the outer wall OSW of the second heat sink 800b 800b The second inner sidewall of the first radiator 700b is ISW2 700b Spacing out. For example, on the outer wall of the second heatsink 800b, OSW 800b The second inner sidewall of the first radiator 700b is ISW2 700b There is a distance D2 between them of approximately 200 μm to approximately 500 μm.

[0133] like Figure 7 As shown in the cross-sectional view, in the semiconductor device 30, the top surface T of the second heat sink 800b 800b Located on the top surface T of the first heatsink 700b 700b At a higher horizontal level. However, similar to the cross-sectional view of semiconductor device 10, in some other cross-sectional views of semiconductor device 30, the top surface T of the second heat sink 800b is at a higher horizontal level. 800b With the top surface T of the first heat sink 700b 700b They are essentially at the same horizontal level.

[0134] In some embodiments, the cover structure LS2 provides a heat dissipation function. In other words, heat generated during the operation of the semiconductor die 100 can be dissipated through the path created by the cover structure LS2. In some embodiments, during the manufacturing process of the semiconductor device 30, particularly during high-temperature thermal processes, delamination may occur between components of the semiconductor device 30 due to CTE mismatch between two different materials. However, as described above, the cover structure LS2 includes a first heat sink 700b and a second heat sink 800b with different CTEs and different Young's moduli. By employing the first heat sink 700b and the second heat sink 800b with different CTEs and different Young's moduli, the stress applied during thermal processes can be sufficiently reduced or compensated. In this way, delamination between components within the semiconductor device 30 can be effectively eliminated.

[0135] Figure 8 This is a schematic cross-sectional view of a semiconductor device 40 according to some alternative embodiments of the present disclosure. (Refer to...) Figure 8 , Figure 8 The semiconductor device 40 in the middle is similar to Figure 7 The semiconductor device 30 in the figure is used; therefore, similar elements are indicated by the same reference numerals and their detailed descriptions are omitted herein. However, Figure 7The cover structure LS2 in the middle is Figure 8 The cover structure LS3 is replaced in some embodiments. In some embodiments, the cover structure LS3 includes a first heat sink 700c and a second heat sink 800c. Figure 8 The first radiator 700c and the second radiator 800c are similar to... Figure 7 The first heatsink 700b and the second heatsink 800b are described in detail herein, therefore their detailed descriptions are omitted. However, the first heatsink 700c includes components with different heights H. 706a Multiple protrusions 706a. Additionally, the second heat sink 800c includes components with different depths D. 806a Multiple grooves 806a.

[0136] like Figure 8 As shown in the cross-sectional view, the body portion 702 is L-shaped and a protrusion 706a is formed on the L-shaped base. In some embodiments, each protrusion 706a presents a ring shape in the top view. In other words, the protrusions 706a are concentric rings in the top view. In some embodiments, the protrusions 706a of the first heat sink 700c are integrally formed with the body portion 702. For example, the protrusions 706a can be formed by removing a portion of the body portion 702 through etching, cutting, drilling, etc. Figure 8 As shown in the cross-sectional view, the body portion 802 presents an inverted U-shape, and a groove 806a is formed on the leg of the inverted U-shape. In some embodiments, each groove 806a presents a ring shape in the bottom view. In other words, the groove 806a is a concentric ring in the bottom view. In some embodiments, the groove 806a is formed by removing a portion of the body portion 802 by etching, cutting, drilling, etc.

[0137] Reference Figure 8 The cover structure LS3 has a height H ranging from approximately 3.45 mm to approximately 5.0 mm. LS3 In some embodiments, the first heat sink 700c has a minimum height H ranging from about 0.75 mm to about 2.45 mm. 700c Meanwhile, the second radiator 800c has a maximum height H ranging from approximately 1 mm to approximately 2.7 mm. 800c As described above, the protrusions 706a have different heights H. 706a The height H of these protrusions 706 706a It can be within the range of greater than 0 μm and less than 1500 μm. On the other hand, the width W of each protrusion 706a 706a Within the range of greater than 0 μm and less than 1000 μm. For example... Figure 8 As shown, each protrusion 706a of the first radiator 700c has a substantially equal width W. 706aIn some embodiments, the pitch P between two adjacent protrusions 706a 706a (That is, the distance between the centers of the two adjacent protrusions 706a) is within the range of greater than 0 μm and less than 2500 μm. As described above, the grooves 806a have different depths D. 806a The depth D of these grooves 806a 806a It can be within the range of greater than 0 μm and less than 1500 μm. On the other hand, the width W of each groove 806a 806a Within the range of greater than 0 μm and less than 1000 μm. For example... Figure 8 As shown, each recess 806a of the second heat sink 800c has a substantially identical width W. 806a In some embodiments, the pitch P between two adjacent grooves 806a 806a (That is, the distance between the centers of the two adjacent grooves 806a) is in the range of greater than 0 μm and less than 2500 μm.

[0138] In some embodiments, the protrusions 706a of the first heat sink 700c perfectly fit into the corresponding recesses 806a of the second heat sink 800c. In other words, the width W of each protrusion 706a of the first heat sink 700c is... 706a The width W of the groove 806a corresponding to the second heat sink 800c 806a They are substantially the same, and the height H of each protrusion 706a of the first radiator 700c is... 706a The depth D of the groove 806a corresponding to the second heat sink 800c 806a They are substantially the same. That is, the shape of each protrusion 706a of the first heat sink 700c is substantially the same as the shape of the corresponding groove 806a of the second heat sink 800c. In this way, the protrusions 706a of the first heat sink 700c are firmly embedded into the grooves 806a of the second heat sink 800c without any adhesive material. For example, the protrusions 706a of the first heat sink 700c are surrounded by and firmly fixed by the body portion 802 of the second heat sink 800c. In other words, the first heat sink 700c and the second heat sink 800c are in solid contact. In this way, the cover structure LS3 is considered to have a foolproof design for assembly.

[0139] It should be noted that in some alternative embodiments, the protrusions 706a of the first heat sink 700c and the recesses 806a of the second heat sink 800c may not completely fit together. For example, in some alternative embodiments, the width W of each protrusion 706a of the first heat sink 700c may be... 706a The width W of the groove 806a corresponding to the second heat sink 800c806a They are essentially the same, but the height H of each protrusion 706a of the first radiator 700c is different. 706a The depth D of the corresponding groove 806a of the second heatsink 800c is different. 806a Despite the height H of the protrusion 706a 706a The depth D of groove 806a is different 806a However, since the width is the same (i.e., the width W of the protrusion 706a is the same), 706a Width W of groove 806a 806a (Essentially the same), the protrusion 706a can still be firmly engaged with the groove 806a without any adhesive material.

[0140] As described above, the first radiator 700c is L-shaped in cross-sectional view. Therefore, the first radiator 700c has a first inner sidewall ISW1. 700c and the second inner sidewall ISW2 700c ,like Figure 8 As shown in the diagram. Meanwhile, the first radiator 700c has a connection with the first inner sidewall ISW1. 700c and the second inner sidewall ISW2 700c A relative outer sidewall OSW 700c In some embodiments, the second radiator 800c has an inner sidewall ISW. 800c and the inner sidewall ISW 800c Relative outer wall OSW 800c .like Figure 8 As shown, the first inner wall ISW1 of the first radiator 700c 700c The inner wall of the second radiator 800c is ISW 800c It has a bias. For example, in the first inner wall ISW1 of the first radiator 700c. 700c The inner wall of the second radiator 800c is ISW 800c There is a distance D1 between them of approximately 200 μm to approximately 500 μm. For example... Figure 8 As shown, the outer wall OSW of the second radiator 800c 800c The second inner sidewall of the first radiator 700c is ISW2 700c Spacing out. For example, on the outer wall of the second radiator 800c, OSW 800c The second inner sidewall of the first radiator 700c is ISW2 700c There is a distance D2 between them of approximately 200 μm to approximately 500 μm.

[0141] like Figure 8 As shown, the inner wall of the second radiator is 800c away from the inner wall. 800c and outer side OSW 800cThe height H of the closer protrusion 706a 706a The inner wall ISW is greater than 800 cm from the second radiator. 800c and outer side OSW 800c The height H of the more distant protrusion 706a 706a In other words, the height H of the protrusion 706a 706a ISW towards the inner wall of the second radiator 800c 800c and outer side OSW 800c Gradually increasing. However, this disclosure is not limited thereto. In some embodiments, the height H of the protrusion 706a is... 706a The inner wall of the second radiator 800c is ISW 800c and outer side OSW 800c Gradually decrease.

[0142] like Figure 8 As shown in the cross-sectional view, in the semiconductor device 40, the top surface T of the second heat sink 800c 800c Located on the top surface T of the first heatsink 700c 700c At a higher horizontal level. However, similar to the cross-sectional view of semiconductor device 10, in some other cross-sectional views of semiconductor device 40, the top surface T of the second heat sink 800c is at a higher horizontal level. 800c The top surface T of the first heat sink 700c 700c They are essentially at the same horizontal level.

[0143] In some embodiments, the cover structure LS3 provides a heat dissipation function. In other words, heat generated during the operation of the semiconductor die 100 can be dissipated through the path created by the cover structure LS3. In some embodiments, during the manufacturing process of the semiconductor device 40, particularly during high-temperature thermal processes, delamination may occur between components of the semiconductor device 40 due to CTE mismatch between two different materials. However, as described above, the cover structure LS3 includes a first heat sink 700c and a second heat sink 800c with different CTEs and different Young's moduli. By employing the first heat sink 700c and the second heat sink 800c with different CTEs and different Young's moduli, the stress applied during thermal processes can be sufficiently reduced or compensated. In this way, delamination between components within the semiconductor device 40 can be effectively eliminated.

[0144] Figure 9 This is a schematic cross-sectional view of a semiconductor device 50 according to some alternative embodiments of the present disclosure. (Refer to...) Figure 9 , Figure 9 The semiconductor device 50 in the middle is similar to Figure 7 The semiconductor device 30 in the figure is used; therefore, similar elements are indicated by the same reference numerals and their detailed descriptions are omitted herein. However, Figure 7 The cover structure LS2 in the middle is Figure 9 The cover structure LS4 is replaced in some embodiments. In some embodiments, the cover structure LS4 includes a first heat sink 700d and a second heat sink 800d. Figure 9 The first radiator 700d and the second radiator 800d are similar to... Figure 7 The first heatsink 700b and the second heatsink 800b are used in this document, therefore their detailed descriptions are omitted here. However, as... Figure 9 As shown, the top surface of the body portion 702 and the top surface of the protrusion 706 are substantially coplanar. That is, the top surface of the body portion 702 and the top surface of the protrusion 706 are substantially at the same horizontal height.

[0145] In some embodiments, the cover structure LS4 has a height H ranging from about 3.45 mm to about 5.0 mm. LS4 In some embodiments, the first heat sink 700d has a minimum height H ranging from about 0.75 mm to about 2.45 mm. 700d Meanwhile, the second heatsink 800d has a maximum height H ranging from approximately 1 mm to approximately 2.7 mm. 800d In some embodiments, the first heat sink 700d presents an L-shape in cross-sectional view. Therefore, the first heat sink 700d has a first inner sidewall ISW1. 700d and the second inner sidewall ISW2 700d ,like Figure 9 As shown in the diagram. Meanwhile, the first radiator 700d has a connection with the first inner sidewall ISW1. 700d and the second inner sidewall ISW2 700d A relative outer sidewall OSW 700d In some embodiments, the second heat sink 800d has an inner sidewall ISW. 800d and the inner sidewall ISW 800d Relative outer wall OSW 800d .like Figure 9 As shown, the first inner wall ISW1 of the first radiator 700d 700d The inner sidewall of the second radiator 800d is ISW 800d It has a bias. For example, in the first inner sidewall ISW1 of the first radiator 700d. 700d The inner sidewall of the second radiator 800d is ISW 800d There is a distance D1 between them of approximately 200 μm to approximately 500 μm. For example... Figure 9 As shown, the outer wall OSW of the second radiator 800d 800d The second inner sidewall of the first radiator 700d is ISW2 700dSpacing out. For example, on the outer wall of the second radiator 800d, OSW 800d The second inner sidewall of the first radiator 700d is ISW2 700d There is a distance D2 between them of approximately 200 μm to approximately 500 μm.

[0146] like Figure 9 As shown in the cross-sectional view, in the semiconductor device 50, the top surface T of the second heat sink 800d 800d Located on the top surface T of the first heatsink 700d 700d At a higher horizontal level. However, similar to the cross-sectional view of semiconductor device 10, in some other cross-sectional views of semiconductor device 50, the top surface T of the second heat sink 800d is at a higher horizontal level. 800d The top surface T of the first heatsink 700d 700d They are essentially at the same horizontal level.

[0147] In some embodiments, the cover structure LS4 provides a heat dissipation function. In other words, heat generated during the operation of the semiconductor die 100 can be dissipated through the path created by the cover structure LS4. In some embodiments, during the manufacturing process of the semiconductor device 50, particularly during high-temperature thermal processes, delamination may occur between components of the semiconductor device 50 due to CTE mismatch between two different materials. However, as described above, the cover structure LS4 includes a first heat sink 700d and a second heat sink 800d with different CTEs and different Young's moduli. By employing the first heat sink 700d and the second heat sink 800d with different CTEs and different Young's moduli, the stress applied during thermal processes can be sufficiently reduced or compensated. In this way, delamination between components within the semiconductor device 50 can be effectively eliminated.

[0148] Figure 10 This is a schematic cross-sectional view of a semiconductor device 60 according to some alternative embodiments of the present disclosure. (Refer to...) Figure 10 , Figure 10 The semiconductor device 60 in the middle is similar to Figure 8 The semiconductor device 40 in the figure is therefore represented by the same reference numerals and its detailed description is omitted herein. However, Figure 8 The cover structure LS3 in the middle is Figure 10 The cover structure LS5 is replaced in some embodiments. In some embodiments, the cover structure LS5 includes a first heat sink 700e and a second heat sink 800e. Figure 10 The first radiator 700e and the second radiator 800e are similar to... Figure 8 The first heatsink 700c and the second heatsink 800c are used in this design, therefore their detailed descriptions are omitted in this document. However, as... Figure 10As shown, the top surface of the main body 702 and the top surface of the shortest protrusion 706a are substantially coplanar. That is, the top surface of the main body 702 and the top surface of the shortest protrusion 706a are substantially at the same horizontal height.

[0149] In some embodiments, the cover structure LS5 has a height H ranging from about 3.45 mm to about 5.0 mm. LS5 In some embodiments, the first heat sink 700e has a minimum height H ranging from about 0.75 mm to about 2.45 mm. 700e Meanwhile, the second heatsink 800e has a maximum height H ranging from approximately 1 mm to approximately 2.7 mm. 800e In some embodiments, the first heat sink 700e is L-shaped in cross-sectional view. Therefore, the first heat sink 700e has a first inner sidewall ISW1. 700e and the second inner sidewall ISW2 700e ,like Figure 10 As shown in the diagram. Meanwhile, the first heat sink 700e has a connection with the first inner sidewall ISW1. 700e and the second inner sidewall ISW2 700e A relative outer sidewall OSW 700e In some embodiments, the second heat sink 800e has an inner sidewall ISW. 800e and the inner sidewall ISW 800e Relative outer wall OSW 800e .like Figure 10 As shown, the first inner wall ISW1 of the first radiator 700e 700e With the inner sidewall of the second radiator 800e ISW 800e It has a bias. For example, in the first inner sidewall ISW1 of the first radiator 700e. 700e With the inner sidewall of the second radiator 800e ISW 800e There is a distance D1 between them of approximately 200 μm to approximately 500 μm. For example... Figure 10 As shown, the outer wall OSW of the second heat sink 800e 800e The second inner sidewall of the first radiator 700e, ISW2 700e Spacing out. For example, on the outer wall of the second radiator 800e, OSW 800e The second inner sidewall of the first radiator 700e, ISW2 700e There is a distance D2 between them of approximately 200 μm to approximately 500 μm.

[0150] like Figure 10 As shown, the inner wall of the second radiator is 800e away from the second radiator. 800e and outer side OSW 800eThe height H of the closer protrusion 706a 706a Less than 800e from the inner wall of the second radiator ISW 800e and outer side OSW 800e The height H of the more distant protrusion 706a 706a In other words, the height H of the protrusion 706a 706a ISW towards the inner wall of the second radiator 800e 800e and outer side OSW 800e Gradually decreasing. However, this disclosure is not limited thereto. In some embodiments, the height H of the protrusion 706a is... 706a The inner wall of the second radiator 800e is ISW 800e and outer side OSW 800e Gradually increase.

[0151] like Figure 10 As shown in the cross-sectional view, in the semiconductor device 60, the top surface T of the second heat sink 800e 800e Located on the top surface T of the first heatsink 700e 700e At a higher horizontal level. However, similar to the cross-sectional view of semiconductor device 10, in some other cross-sectional views of semiconductor device 60, the top surface T of the second heat sink 800e is at a higher horizontal level. 800e With the top surface T of the first heatsink 700e 700e They are essentially at the same horizontal level.

[0152] In some embodiments, the cover structure LS5 provides a heat dissipation function. In other words, heat generated during the operation of the semiconductor die 100 can be dissipated through the path created by the cover structure LS5. In some embodiments, during the manufacturing process of the semiconductor device 60, particularly during high-temperature thermal processes, delamination may occur between components of the semiconductor device 60 due to CTE mismatch between two different materials. However, as described above, the cover structure LS5 includes a first heat sink 700e and a second heat sink 800e with different CTEs and different Young's moduli. By employing the first heat sink 700e and the second heat sink 800e with different CTEs and different Young's moduli, the stress applied during thermal processes can be sufficiently reduced or compensated. In this way, delamination between components within the semiconductor device 60 can be effectively eliminated.

[0153] According to some embodiments of this disclosure, a semiconductor device includes a substrate, a package structure, a first heat sink, and a second heat sink. The package structure is disposed on the substrate. The first heat sink is disposed on the substrate and surrounds the package structure. The second heat sink is disposed on the package structure and connected to the first heat sink. The material of the first heat sink is different from the material of the second heat sink.

[0154] According to some embodiments of this disclosure, the coefficient of thermal expansion and Young's modulus of the first heat sink are different from those of the second heat sink.

[0155] According to some embodiments of this disclosure, the first heat sink is in physical contact with the second heat sink.

[0156] According to some embodiments of this disclosure, one of the first radiator and the second radiator includes a protrusion, and the other of the first radiator and the second radiator includes a groove, wherein the protrusion is embedded in the groove.

[0157] According to some embodiments of this disclosure, the first heat sink is attached to the substrate via an adhesive layer.

[0158] According to some embodiments of this disclosure, the second heat sink is attached to the encapsulation structure via a thermal interface material layer.

[0159] According to some embodiments of this disclosure, the packaging structure includes an interposer, at least one semiconductor die, and an encapsulator. The at least one semiconductor die is disposed on the interposer. The encapsulator is disposed on the interposer to encapsulate the at least one semiconductor die.

[0160] According to some alternative embodiments of this disclosure, a semiconductor device includes a substrate, a cover structure, and a package structure. The cover structure is disposed on the substrate. The cover structure includes a first heat sink and a second heat sink. The first heat sink is attached to the substrate. The first heat sink includes a first body portion and a recess from the top surface of the first body portion. The second heat sink includes a second body portion and a protrusion from the bottom surface of the second body portion. The protrusion of the second heat sink engages with the recess of the first heat sink. The package structure is located between the substrate and the cover structure.

[0161] According to some alternative embodiments of this disclosure, each of the protrusions of the second radiator has the same height.

[0162] According to some alternative embodiments of this disclosure, at least two of the protrusions of the second radiator have different heights.

[0163] According to some alternative embodiments of this disclosure, each of the grooves in the first heat sink has the same depth.

[0164] According to some alternative embodiments of this disclosure, at least two of the grooves in the first heat sink have different depths.

[0165] According to some alternative embodiments of this disclosure, the width of each of the protrusions of the second heat sink is the same as the width of the corresponding groove of the first heat sink.

[0166] According to some alternative embodiments of this disclosure, the height of each of the protrusions of the second heat sink is the same as the depth of the corresponding groove of the first heat sink.

[0167] According to some alternative embodiments of this disclosure, the coefficient of thermal expansion and Young's modulus of the first heat sink are different from those of the second heat sink.

[0168] According to some alternative embodiments of this disclosure, the packaging structure includes an interposer, at least one semiconductor die, and an encapsulator. The at least one semiconductor die is disposed on the interposer. The encapsulator is disposed on the interposer to encapsulate the at least one semiconductor die.

[0169] According to some embodiments of this disclosure, a method of manufacturing a semiconductor device includes at least the following steps: providing a substrate; bonding a package structure to the substrate; applying an adhesive layer to the substrate; applying a thermal interface material (TIM) layer to the package structure; engaging a first heat sink and a second heat sink to form a cover structure; and attaching the cover structure to the substrate and the package structure via the adhesive layer and the TIM layer.

[0170] According to some embodiments of this disclosure, the material of the first radiator is different from the material of the second radiator.

[0171] According to some embodiments of this disclosure, one of the first radiator and the second radiator includes a protrusion, the other of the first radiator and the second radiator includes a groove, and engaging the first radiator and the second radiator includes embedding the protrusion into the groove.

[0172] According to some embodiments of this disclosure, the first heat sink is attached to the substrate via the adhesive layer, and the second heat sink is attached to the packaging structure via the thermal interface material layer.

[0173] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications thereto without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: Substrate; An encapsulation structure is disposed on the substrate; A first heat sink is disposed on the substrate, wherein the first heat sink surrounds the package structure; as well as A second heat sink is disposed on the encapsulation structure, wherein the second heat sink is connected to the first heat sink, and the material of the first heat sink is different from that of the second heat sink, and the first heat sink laterally surrounds the outer sidewall of the second heat sink, wherein the second heat sink includes a body portion that presents an inverted U-shape, and the inner sidewall of the first heat sink is located below the legs of the inverted U-shape.

2. The semiconductor device according to claim 1, wherein the coefficient of thermal expansion and Young's modulus of the first heat sink are different from those of the second heat sink.

3. The semiconductor device of claim 1, wherein the first heat sink is in contact with the second heat sink body.

4. The semiconductor device of claim 1, wherein one of the first heat sink and the second heat sink includes a protrusion, the other of the first heat sink and the second heat sink includes a groove, and the protrusion is embedded in the groove.

5. The semiconductor device of claim 1, wherein the first heat sink is attached to the substrate via an adhesive layer.

6. The semiconductor device of claim 1, wherein the second heat sink is attached to the package structure via a thermal interface material layer.

7. The semiconductor device of claim 1, wherein the package structure comprises: Intermediate layer; At least one semiconductor die is disposed on the interposer layer; as well as An encapsulation body is disposed on the interposer layer to encapsulate the at least one semiconductor die.

8. A semiconductor device, characterized in that, include: Substrate; A cover structure is disposed on the substrate, wherein the cover structure includes: A first heat sink is attached to the substrate, wherein the first heat sink includes a first body portion and a groove recessed from the top surface of the first body portion; and A second radiator, wherein the second radiator includes a second body portion and a protrusion extending from the bottom surface of the second body portion, and the protrusion of the second radiator engages with the groove of the first radiator, and the first body portion of the first radiator laterally surrounds the outer sidewall of the second radiator, and the inner sidewall of the first radiator is located below the bottom surface of the second body portion; and The encapsulation structure is located between the substrate and the cover structure.

9. The semiconductor device of claim 8, wherein each of the protrusions of the second heat sink has the same height.

10. The semiconductor device of claim 8, wherein at least two of the protrusions of the second heat sink have different heights.

11. The semiconductor device of claim 8, wherein each of the recesses of the first heat sink has the same depth.

12. The semiconductor device of claim 8, wherein at least two of the recesses in the first heat sink have different depths.

13. The semiconductor device of claim 8, wherein the width of each of the protrusions of the second heat sink is the same as the width of the corresponding groove of the first heat sink.

14. The semiconductor device of claim 13, wherein the height of each of the protrusions of the second heat sink is the same as the depth of the corresponding groove of the first heat sink.

15. The semiconductor device of claim 8, wherein the coefficient of thermal expansion and Young's modulus of the first heat sink are different from those of the second heat sink.

16. The semiconductor device of claim 8, wherein the package structure comprises: Intermediate layer; At least one semiconductor die is disposed on the interposer layer; as well as An encapsulation body is disposed on the interposer layer to encapsulate the at least one semiconductor die.

17. A method for manufacturing a semiconductor device, characterized in that, include: Provide substrate; The packaging structure is bonded to the substrate; An adhesive layer is applied to the substrate; A thermal interface material layer is applied to the encapsulation structure; A first radiator and a second radiator are engaged to form a cover structure, wherein the first radiator laterally surrounds the outer sidewall of the second radiator, wherein the second radiator includes a body portion forming an inverted U-shape, and the inner sidewall of the first radiator is located below the legs of the inverted U-shape; and The cover structure is attached to the substrate and the encapsulation structure through the adhesive layer and the thermal interface material layer.

18. The method of manufacturing a semiconductor device according to claim 17, wherein the material of the first heat sink is different from the material of the second heat sink.

19. The method of manufacturing a semiconductor device according to claim 17, wherein one of the first heat sink and the second heat sink includes a protrusion, the other of the first heat sink and the second heat sink includes a groove, and engaging the first heat sink and the second heat sink includes embedding the protrusion into the groove.

20. The method of manufacturing a semiconductor device according to claim 17, wherein the first heat sink is attached to the substrate via the adhesive layer, and the second heat sink is attached to the package structure via the thermal interface material layer.

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