Three-dimensional semiconductor device including word line structure with protrusions

Abstract

This application relates to three-dimensional semiconductor devices including word line structures having protrusions. Three-dimensional memory devices are provided. The three-dimensional memory devices can include a substrate, a common electrode layer on the substrate, a word line layer stack disposed on the common electrode layer, the word line layer stack having alternately stacked interlayer insulating layers and word line structures, and vertical channel pillars that penetrate the word line layer stack, the vertical channel pillars being electrically connected to the common electrode layer. Each of the word line structures includes a main portion having a first vertical width and an extension portion having a second vertical width that is greater than the first vertical width. The extension portion is contiguous with the vertical channel pillars.

Description

Technical Field

[0001] This disclosure relates to a three-dimensional (3D) semiconductor device including a word line structure with protrusions and a method of manufacturing the 3D semiconductor device. Background Technology

[0002] Highly integrated 3D semiconductor devices have been proposed. These devices can store data by trapping charges based on the electric field between the word line structure and the channel layer. Summary of the Invention

[0003] Embodiments of this disclosure provide a word line structure configured to widen the electric field and a 3D semiconductor device having the word line structure.

[0004] Embodiments of this disclosure provide a word line structure with improved charge trapping capability and a 3D semiconductor device having the word line structure.

[0005] A three-dimensional memory device according to embodiments of the present disclosure may include: a substrate; a common electrode layer located on the substrate; a word line stack disposed on the common electrode layer, the word line stack having alternating layers of interlayer insulating layers and word line structures; and a vertical channel post penetrating the word line stack, the vertical channel post being electrically connected to the common electrode layer. Each of the word line structures includes a body portion having a first vertical width and an extension portion having a second vertical width greater than the first vertical width. The extension portion abuts the vertical channel post.

[0006] A three-dimensional memory device according to embodiments of the present disclosure may include: a substrate; a common electrode layer located on the substrate; a word line stack disposed on the common electrode layer, the word line stack including alternating layers of interlayer insulating layers and word line structures; and a vertical channel post penetrating the word line stack and electrically connected to the common electrode layer. Each of the word line structures includes a body portion located between the interlayer insulating layers and an extension portion contacting the vertical channel post. The extension portion includes an upper protrusion projecting upward from the top surface of the body portion and a lower protrusion projecting downward from the bottom surface of the body portion.

[0007] A semiconductor device according to embodiments of the present disclosure may include: a word line stack disposed above a common electrode layer, the word line stack including alternating layers of interlayer insulating layers and word line structures. Each of the word line structures may include a body portion and an extension portion located at one end of the body portion. The extension portion may contact a vertical channel post. The extension portion may include an upper protrusion extending vertically upward above the top surface of the body portion and a lower protrusion extending vertically downward below the bottom surface of the body portion. Attached Figure Description

[0008] Figure 1This is a schematic longitudinal cross-sectional view of a 3D semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 2A yes Figure 1 A magnified view of region A.

[0010] Figure 2B This is a diagram illustrating the operation of the word line structure in the embodiments of this disclosure.

[0011] Figures 3A to 3D This is a schematic illustration of a word line structure 40 according to an embodiment of the present disclosure.

[0012] Figures 4A to 4L This is a diagram illustrating a method for manufacturing a 3D semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 5 and Figure 6 This is a block diagram illustrating the configuration of a memory system according to an embodiment of the present disclosure.

[0014] Figure 7 and Figure 8 This is a block diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure. Detailed Implementation

[0015] Various examples and embodiments of the disclosed technology are described in detail below with reference to the accompanying drawings. The drawings may not necessarily be drawn to scale, and in some cases, the scale of at least some structures in the drawings may be exaggerated to clearly illustrate some features of the described examples or embodiments. When a particular example is presented in a drawing or description having two or more layers in a multilayer structure, the relative positional relationship of these layers or the order in which these layers are arranged reflects the particular embodiment of the described or illustrated example, and different relative positional relationships or orders in which these layers are arranged are also possible. Furthermore, the example of the described or illustrated multilayer structure may not reflect all layers present in that particular multilayer structure (e.g., one or more additional layers may exist between the two illustrated layers). As a particular example, when the first layer in the described or illustrated multilayer structure is referred to as being "on" or "above" the second layer or "on" or "above" the substrate, the first layer may be formed directly on the second layer or the substrate; however, other embodiments or examples may include multilayer structures in which one or more other intervening layers exist between the first layer and the second layer or the substrate.

[0016] Figure 1 This is a schematic longitudinal cross-sectional view of a 3D semiconductor device 100 according to an embodiment of the present disclosure. (Refer to...) Figure 1According to embodiments of the present disclosure, a 3D semiconductor device 100 may include a logic circuit layer 20 formed on a substrate 10, and a word line stack WS, a vertical channel pillar 50, a contact plug 61, a lower interconnect insulating layer 62, a bit line 63, and an upper interconnect insulating layer 64 formed on the logic circuit layer 20.

[0017] The substrate 10 may include a semiconductor material. For example, the substrate 10 may include a single-crystal silicon wafer, an epitaxially grown silicon layer, silicon-on-insulator (SOI), a compound semiconductor, and other semiconductor layers.

[0018] The logic circuit layer 20 may include transistors 21, logic interconnects 23, a logic insulating layer 25, and a common electrode layer 27. Transistors 21 may include a gate disposed on the substrate 10 and a source / drain formed in the substrate 10. Logic interconnects 23 may include multiple metal layers. The logic insulating layer 25 may surround transistors 21 and logic interconnects 23 to insulate them from each other. The common electrode layer 27 may be disposed at the uppermost portion of the logic circuit layer 20. The common electrode layer 27 may include a polysilicon layer doped with N-type ions, a metal layer (such as, for example, tungsten (W)), a metal compound layer (such as, for example, titanium nitride (TiN)), or a metal silicide layer. The common electrode layer 27 may be plate-shaped.

[0019] The word line stack WS may include alternating layers of interlayer insulating layers 30 and word line structures 40. The interlayer insulating layers 30 may insulate the common electrode layer 27 and the word line structure WS in the vertical direction. The interlayer insulating layers 30 may include silicon oxide (SiO2). Each of the word line structures 40 may include a conductive material.

[0020] The vertical channel post 50 can penetrate vertically through the word line stack WS to electrically connect to the common electrode layer 27. The vertical channel post 50 can protrude downward into the common electrode layer 27.

[0021] The lower interconnect insulating layer 62 can be formed on the word line stack WS and the vertical channel post 50.

[0022] The contact plug 61 can pass through the lower interconnect insulation layer 62 to be electrically connected to the vertical channel post 50. The contact plug 61 can be cylindrical.

[0023] The upper interconnect insulating layer 64 can be formed on the lower interconnect insulating layer 62 and the contact plug 61.

[0024] Bit line 63 can be connected to contact plug 61 and can have a parallel line shape.

[0025] The lower interconnect insulating layer 62 and the upper interconnect insulating layer 64 may comprise silicon oxide (SiO2). The contact plug 61 and the bit line 63 may comprise a metal (such as, for example, tungsten (W)) or a metal nitride (such as, for example, titanium nitride (TiN)).

[0026] Figure 2A yes Figure 1 A magnified view of region A. (Refer to...) Figure 2A The vertical trench post 50 may include an insulating core post 51, a trench layer 52, a tunneling layer 53, a charge trapping layer 54, a barrier insulating layer 55, and a buffer layer 56.

[0027] The core post 51 may be located in the center. The core post 51 may include an insulating material, such as, for example, silicon oxide (SiO2).

[0028] The channel layer 52 may have a cylindrical shape surrounding the side surface of the core pillar 51. The channel layer 52 may include a semiconductor material, such as, for example, silicon.

[0029] The tunneling layer 53 may have a cylindrical shape surrounding the side surface of the channel layer 52. The tunneling layer 53 may include an insulating material, such as, for example, silicon oxide (SiO2).

[0030] The charge trapping layer 54 may have a cylindrical shape surrounding the side surface of the tunneling layer 53. The charge trapping layer 54 may include a high-k material, such as, for example, silicon nitride (SiN).

[0031] The barrier insulating layer 55 may have a cylindrical shape surrounding the side surface of the charge trapping layer 54. The barrier insulating layer 55 may provide a potential barrier. The barrier insulating layer 55 may have a higher work function than the charge trapping layer 54. The barrier insulating layer 55 may include a metallic insulating material, such as, for example, aluminum oxide (Al2O3).

[0032] The buffer layer 56 may have a cylindrical shape surrounding the side surface of the barrier insulating layer 55. The buffer layer 56 may include an insulating material that is softer than the barrier insulating layer 55, such as, for example, silicon oxide (SiO2).

[0033] In an embodiment, the barrier insulating layer 55 may include silicon oxide (SiO2), and the buffer layer 56 may include a metallic insulating material, such as, for example, aluminum oxide (Al2O3).

[0034] Each of the character line structures 40 may include a main body portion B and an extension portion E. The main body portion B may have a flat top surface and a flat bottom surface. For example, the main body portion B may have a uniform vertical thickness. The extension portion E may have a larger vertical thickness than the main body portion B.

[0035] The extension E may have an upper protrusion Pa that protrudes upward above the top surface of the main body B. The extension E may also have a lower protrusion Pb that protrudes downward below the lower surface of the main body. The extension E may be positioned adjacent to the vertical channel post 50. For example, the extension E may protrude laterally into the vertical channel post 50. In embodiments, the upper protrusion Pa and the lower protrusion Pb may have the same shape and may be symmetrical to each other. For example, the upper protrusion Pa and the lower protrusion Pb may have a curved shape. The portion of the extension adjacent to the vertical channel post 50 may be substantially flat, and the upper and lower edges gradually curve toward the upper protrusion Pa and the lower protrusion Pb.

[0036] The main body B may have a first vertical width W1, and the extension E may have a second vertical width W2. The second vertical width W2 may be greater than the first vertical width W1. In an embodiment, the extension E may replace a portion of the interlayer insulation layer 30 and a portion of the buffer layer 56. For example, the vertical interface IF between the word line structure 40 and the vertical channel post 50 may be set to be closer to the core post 51 of the vertical channel post 50 than the vertical interface between the interlayer insulation layer 30 and the vertical channel post 50. The vertical interface IF between the word line structure 40 and the vertical channel post 50 may be located inside the buffer layer 56.

[0037] The word line structure 40 may include a word line electrode 41, a barrier metal layer 42, and an insulating liner 43. The word line electrode 41 may form an electric field with the channel layer 52 of the vertical channel post 50. The word line electrode 41 may include a metal, such as, for example, tungsten (W). The barrier metal layer 42 may surround the surface of the word line electrode 41. The barrier metal layer 42 may prevent the word line electrode 41 from contacting the interlayer insulating layer 30, the barrier insulating layer 55, the buffer layer 56, or the liner 43. The barrier metal layer 42 surrounding the surface of the word line electrode 41 in the main body B of the word line structure 40 may contact the interlayer insulating layer 30.

[0038] The liner 43 may be conformally formed in the extension E. For example, the liner 43 may surround the surface of the barrier metal layer 42 at a protrusion in the extension E. The liner 43 may include a high-k dielectric with a dielectric constant greater than 10, such as, for example, strontium titanate (SrTiO3), zirconium oxide (ZrO2), or hafnium oxide (HfO2). A high-k dielectric is a material with a dielectric constant significantly higher than that of silicon nitride (SiN) or silicon oxide (SiO2).

[0039] The barrier metal layer 42 and the vertical channel post 50 can be in direct contact with each other at the vertical interface IF of the extension E of the word line structure 40. For example, the liner 43 may not be formed at the vertical interface IF of the extension E of the word line structure 40.

[0040] Figure 2BThis is a diagram for explaining the operation of the word line structure 40 according to an embodiment of the present disclosure. Refer to Figure 2B When a positive (+) voltage is applied to the word line structure 40, the charge e− can be captured from the channel layer 52 into the charge trapping layer 54. In the 3D semiconductor device 100 according to an embodiment, the charge e− can be further captured into the charge trapping layer 54 by the extension portion E of the word line structure 40. For example, the electric field between the word line structure 40 and the channel layer 52 can be formed wider by the sum of the third vertical width W3 and the fourth vertical width W4, and the sum of the third vertical width W3 and the fourth vertical width W4 is the same as the difference between the second vertical width W2 of the extension portion E and the first vertical width W1 of the main body portion B. Therefore, the amount of the charge e− captured in the charge trapping layer 54 can be increased, and the data of the 3D semiconductor device 100 can be erased and stored more reliably. The liner layer 43 formed on the protrusion of the extension portion E can relieve the concentration of the electric field at the edge of the word line structure 40.

[0041] Figures 3A to 3D This is a diagram schematically illustrating the word line structure 40 according to an embodiment of the present disclosure. Refer to Figure 3A The extension portion E of the word line structure 40 can replace a part of the interlayer insulating layer 30 and a part of the buffer layer 56. The vertical interface IF between the word line structure 40 and the vertical channel pillar 50 can be adjacent to the blocking insulating layer 55.

[0042] Refer to Figure 3B The extension portion E of the word line structure 40 can replace a part of the interlayer insulating layer 30, a part of the buffer layer 56, and a part of the blocking insulating layer 55. The vertical interface IF between the word line structure 40 and the vertical channel pillar 50 can be located inside the blocking insulating layer 55.

[0043] Refer to Figure 3C The extension portion E of the word line structure 40 can replace a part of the buffer layer 56. The vertical interface IF between the word line structure 40 and the vertical channel pillar 50 can be adjacent to the blocking insulating layer 55. The thickness of the buffer layer 56 and the thickness of the extension portion E can be similar or substantially the same. For example, the extension portion E can be restricted inside the vertical channel pillar 50. In one embodiment, the extension portion E can partially protrude into the blocking insulating layer 55. In one embodiment, the extension portion E can protrude into the interlayer insulating layer 30.

[0044] Refer to Figure 3D The word line structure 40 can include a word line electrode 41 and a blocking metal layer 42. Compared with Figure 2A the liner layer 43 can be omitted. Figure 2A And Figures 3A to 3D The features shown in

[0045] Figures 4A to 4L This is a diagram illustrating a method for manufacturing a 3D semiconductor device according to an embodiment of the present disclosure. (Refer to...) Figure 4A The method of manufacturing a 3D semiconductor device according to an embodiment may include forming a logic circuit layer 20 on a substrate 10. Forming the logic circuit layer 20 may include forming transistors 21, logic interconnects 23, a logic insulating layer 25, and a common electrode layer 27 on the substrate 10. Forming the common electrode layer 27 may include forming one of an N-type ion-doped silicon layer, a metal layer (such as, for example, tungsten (W)), a metal compound layer (such as, for example, titanium nitride (TiN)), or a metal silicide on the logic insulating layer 25.

[0046] Reference Figure 4B The method may further include forming an insulating layer stack DS on the logic circuit layer 20. Forming the insulating layer stack DS may include performing multiple deposition processes to alternately stack multiple interlayer insulating layers 30 and multiple sacrificial insulating layers 35 on the logic circuit layer 20. The stacking direction of the multiple interlayer insulating layers 30 may also be referred to as the vertical direction. The interlayer insulating layers 30 may include high-temperature silicon oxide (SiO2), and the sacrificial insulating layers 35 may include silicon nitride (SiN). (See reference...) Figure 4C The method may further include forming a vertically penetrating insulating layer stack DS to connect to a plurality of vertical channel pillars 50 of the common electrode layer 27. Forming the vertical channel pillars 50 may include forming a vertically penetrating insulating layer stack DS to expose vertical channel holes of the common electrode layer 27 and forming various material layers in the vertical channel holes.

[0047] Figure 4D yes Figure 4C A magnified view of region B. (Refer to...) Figure 4D The vertical channel post 50 may include a centrally located core post 51, a channel layer 52 surrounding the sidewalls of the core post 51, a tunneling layer 53 surrounding the sidewalls of the channel layer 52, a charge trapping layer 54 surrounding the sidewalls of the tunneling layer 53, a barrier insulating layer 55 surrounding the sidewalls of the charge trapping layer 54, and a buffer layer 56 surrounding the sidewalls of the barrier insulating layer 55. The channel layer 52, tunneling layer 53, charge trapping layer 54, barrier insulating layer 55, and buffer layer 56 may have a cylindrical shape.

[0048] Forming the vertical channel pillar 50 may include: performing photolithography and etching processes to form a vertical channel hole that penetrates the insulating layer stack DS vertically; performing a first deposition process to conformally form a buffer layer 56 on the inner wall of the vertical channel hole; performing a second deposition process to conformally form a barrier insulating layer 55 on the inner wall of the buffer layer 56; performing a third deposition process to conformally form a charge trapping layer 54 on the inner wall of the barrier insulating layer 55; performing a fourth deposition process to conformally form a tunneling layer 53 on the inner wall of the charge trapping layer 54; performing a fifth deposition process to conformally form a channel layer 52 on the inner wall of the tunneling layer 53; and performing a gap filling process to form a core pillar 51 that fills the vertical channel hole on the inner wall of the channel layer 52.

[0049] Figure 4F yes Figure 4E A magnified view of region C. (Refer to...) Figure 4E and Figure 4F The method may further include removing the sacrificial insulating layer 35 to form a space S between the interlayer insulating layers 30 that exposes the side surfaces of the vertical trench posts 50. Prior to this process, a process for forming slits for removing the sacrificial insulating layer 35 may be performed.

[0050] Reference Figure 4G The method may further include forming a mask layer 36 on the surface of the interlayer insulating layer 30 through a slit. The thickness of the mask layer 36 may gradually decrease as it approaches the vertical channel pillar 50. For example, the mask layer 36 may have a cantilever shape. The mask layer 36 may have etch selectivity for the buffer layer 56 and the interlayer insulating layer 30. In one embodiment, the mask layer 36 may include at least one of spin-coated glass (SOG), low-temperature silicon oxide (LTO), carbon-doped silicon oxide (SiOC), silicon nitride oxide (SiON), or polycrystalline silicon. The mask layer 36 may form an opening Op that spatially connects the space S to the outside.

[0051] Reference Figure 4H The method may further include partially removing the buffer layer 56 and interlayer insulating layer 30 exposed in the space S through the opening Op to form the recess R. In an embodiment, the mask layer 36 may be removed during this process.

[0052] Reference Figure 4I The method may further include conformally forming a liner 43 within the recess R. Forming the liner 43 may include conformally forming a high-k dielectric film, such as, for example, strontium titanate (SrTiO3), zirconium oxide (ZrO2), or hafnium oxide (HfO2), and performing an etching process to allow the high-k dielectric film to remain in the recess R. In an embodiment, the mask layer 36 may be removed during this process.

[0053] Reference Figure 4JThe method may further include conformally forming a barrier metal layer 42 in the space S and the recess R and filling the word line electrode 41 to form a word line structure 40. The barrier metal layer 42 may include a barrier metal, such as, for example, titanium nitride (TiN) or tantalum nitride (TaN). The word line electrode 41 may include a metal, such as, for example, tungsten (W).

[0054] Figure 4K This shows how to execute a reference Figures 4G to 4J The described word line replacement process is used to form the word line overlay (WS). Figure 4C In contrast, the sacrificial insulating layer 35 can be replaced with the word line structure 40, allowing the formation of a word line stack WS. Therefore, the word line stack WS may include alternating layers of interlayer insulating layer 30 and word line structure 40.

[0055] Reference Figure 4L The method may further include forming a contact plug 61 perpendicularly aligned with the vertical channel post 50 on the word line stack WS, and forming a lower interconnect insulating layer 62 surrounding the side surfaces of the contact plug 61. The top surfaces of the contact plug 61 and the lower interconnect insulating layer 62 may be coplanar. Thereafter, refer to... Figure 1 The method may further include forming a bit line 63 on the contact plug 61 and forming an upper interconnect insulating layer 64 surrounding the side surface of the bit line 63. The top surface of the bit line 63 and the top surface of the upper interconnect insulating layer 64 may be coplanar. The contact plug 61 and the bit line 63 may include metal, and the lower interconnect insulating layer 62 and the upper interconnect insulating layer 64 may include an insulating material, such as, for example, silicon oxide.

[0056] Figure 5 This is a block diagram illustrating the configuration of a memory system according to an embodiment of the present disclosure. (Refer to...) Figure 5The memory system 1000 may include a memory device 1200 and a controller 1100. The memory device 1200 may be used to store data information having various data formats (such as, for example, text, graphics, and software code). The memory device 1200 may be non-volatile memory. Furthermore, the memory device 1200 may include at least one of the 3D memory devices according to embodiments of the present disclosure. The controller 1100 may be coupled to a host and the memory device 1200. The controller 1100 may access the memory device 1200 in response to a request from the host. For example, the controller 1100 may control read operations, write operations, erase operations, and background operations of the memory device 1200. The controller 1100 may include at least one of random access memory (RAM) 1110, a central processing unit (CPU) 1120, a host interface 1130, error correction code (ECC) circuitry 1140, and a memory interface 1150. RAM 1110 can be used as operating memory for CPU 1120, cache memory between memory device 1200 and host, buffer memory between memory device 1200 and host, etc. For reference, RAM 1110 can be replaced with other types of memory, such as static random access memory (SRAM), read-only memory (ROM), etc. CPU 1120 can control the overall operation of controller 1100. For example, CPU 1120 can execute instructions stored in RAM 1110, such as firmware like, for example, flash translation layer (FTL). Host interface 1130 can be connected to host interface. For example, controller 1100 can communicate with the host via at least one of various communication standards or interface protocols, such as: Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI-Fast (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, proprietary protocols, etc. ECC circuitry 1140 can use error correction codes (ECC) to detect and correct errors in data read from memory device 1200. Memory interface 1150 can interface with memory device 1200. For example, memory interface 1150 may include a NAND interface or a NOR interface. For example, controller 1100 may also include a buffer memory for temporary data storage. The buffer memory can be used to temporarily store data to be transferred from host interface 1130 to an external device or data to be transferred from memory interface 1150 to memory device 1200. In addition, the controller 1100 may also include a ROM for storing code data for interfacing with the host.Since the memory system 1000 according to this embodiment may include a memory device 1200 with improved integration and characteristics obtained from the embodiments of this disclosure, the integration and characteristics of the memory system 1000 can also be improved.

[0057] Figure 6 This is a block diagram illustrating the configuration of a memory system according to an embodiment of the present disclosure. In the following text, repeated descriptions will be omitted if deemed redundant. See also... Figure 6 The memory system 1000' according to the embodiments may include a memory device 1200' and a controller 1100. Furthermore, the controller 1100 may include RAM 1110, CPU 1120, host interface 1130, ECC circuitry 1140, memory interface 1150, etc. The memory device 1200' may include non-volatile memory. Furthermore, the memory device 1200' may have at least one of the 3D memory devices according to embodiments of the present disclosure. Additionally, the memory device 1200' may include a multi-chip package having multiple memory chips. The multiple memory devices may be divided into multiple groups. The multiple groups may communicate with the controller 1100 via first channels CH1 to k-th channels CHk (where k is an integer). The memory chips of each group may communicate with the controller 1100 via a common channel. For reference, the memory system 1000' may be modified such that each individual memory chip is coupled to a corresponding individual channel. As described above, since the memory system 1000' according to the embodiments may include the memory device 1200' with improved integration and characteristics obtained by the embodiments of the present disclosure, the integration and characteristics of the memory system 1000' can also be improved. Specifically, the memory device 1200' may include a multi-chip package, thereby enabling an increase in its data storage capacity and operating speed.

[0058] Figure 7 This is a block diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure. In the following text, repeated descriptions will be omitted if deemed redundant. See also... Figure 7The computing system 2000 according to embodiments of the present disclosure may include a memory device 2100, a CPU 2200, a RAM 2300, a user interface 2400, a power supply 2500, a system bus 2600, etc. The memory device 2100 stores data provided via the user interface 2400, data processed by the CPU 2200, etc. Furthermore, the memory device 2100 can be electrically connected to the CPU 2200, RAM 2300, user interface 2400, power supply 2500, etc., via the system bus 2600. For example, the memory device 2100 can be connected to the system bus 2600 via a controller or directly connected to the system bus 2600. When the memory device 2100 is directly connected to the system bus 2600, the functions of the controller can be executed by the CPU 2200, RAM 2300, etc. The memory device 2100 may include non-volatile memory. The memory device 2100 may include at least one of the 3D memory devices according to embodiments of the present disclosure. Furthermore, the memory device 2100 may include components having, as described in reference... Figure 6 A multi-chip package containing multiple memory chips is described. The computing system 2000 may include one of the following: a computer, an ultra-mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a network tablet, a wireless telephone, a mobile phone, a smartphone, an e-book reader, a portable multimedia player (PMP), a portable gaming device, a navigation device, a black box, a digital camera, a 3D television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices constituting a home network, a computer network, a telematics network, or an RFID device. As described above, since the computing system 2000 according to this embodiment includes a memory device 2100 with improved integration and characteristics obtained by embodiments of this disclosure, the characteristics of the computing system 2000 can also be improved.

[0059] Figure 8 This is a block diagram illustrating a computing system according to an embodiment of the present disclosure. (Refer to...) Figure 8The computing system 3000 according to embodiments of this disclosure may include a software layer, which includes, for example, an operating system 3200, applications 3100, a file system 3300, a translation layer 3400, etc. Furthermore, the computing system 3000 may include a hardware layer, such as, for example, a memory device 3500. The operating system 3200 can manage the software and hardware resources of the computing system 3000, and can control the program execution of the CPU. Applications 3100 may be various application programs executed in the computing system 3000 and may be utilities executed by the operating system 3200. The file system 3300 may refer to the logical structure used to control data, files, etc., existing in the computing system 3000, and can organize files or data to be stored in the memory device 3500, etc., according to given rules. The file system 3300 may be determined based on the operating system 3200 used in the computing system 3000. For example, if the operating system 3200 is a Microsoft Windows system, the file system 3300 may be a File Allocation Table (FAT), an NT File System (NTFS), etc. If the operating system 3200 is a Unix / Linux system, then the file system 3300 may be an Extended File System (EXT), a Unix File System (UFS), a Journal File System (JFS), etc. Although the operating system 3200, application 3100, and file system 3300 are represented by separate blocks in the diagram, application 3100 and file system 3300 may be included within the operating system 3200. The translation layer 3400 may translate addresses into a form suitable for the memory device 3500 in response to a request from the file system 3300. For example, the translation layer 3400 may translate logical addresses generated by the file system 3300 into physical addresses of the memory device 3500. The mapping information between logical and physical addresses may be stored in an address translation table. For example, the translation layer 3400 may be a Flash Translation Layer (FTL), a Universal Flash Memory Link Layer (ULL), etc. The memory device 3500 may be non-volatile memory. Furthermore, the memory device 3500 may include at least one of the 3D memory devices according to embodiments of this disclosure. As described above, since the computing system 3000 according to this embodiment may include a memory device 3500 with improved integration and characteristics obtained by the embodiments of this disclosure, the characteristics of the computing system 3000 may also be improved.

[0060] According to embodiments of this disclosure, the charge trapping capability of the charge trapping layer can be improved because the electric field between the word line structure and the channel layer is widened.

[0061] While this disclosure contains numerous details, these details should not be construed as limiting the scope of this disclosure or the scope of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of this disclosure. Specific features described in the context of individual embodiments of this disclosure may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in some combination, or even initially claimed in this manner, in some cases one or more features of the claimed combination may be removed from the combination, and the claimed combination may involve sub-combinations or variations thereof.

[0062] Similarly, although operations are depicted in a specific order in the accompanying drawings, this should not be construed as requiring such operations to be performed in the specific order shown or in sequential order, or to perform all illustrated operations to achieve the desired result. Furthermore, the separation of various system components in the embodiments described in this disclosure should not be construed as requiring such separation in all embodiments. Only a few embodiments and examples have been described. Other embodiments, enhancements, and modifications can be made based on what is described and illustrated in this disclosure.

[0063] Cross-references to related applications

[0064] This application claims priority to Korean Patent Application No. 10-2021-0006066, filed on January 15, 2021, the entire contents of which are incorporated herein by reference.

Claims

1. A three-dimensional semiconductor device, the three-dimensional semiconductor device comprising: substrate; A common electrode layer is located on the substrate; A word line stack disposed on the common electrode layer, the word line stack having alternating layers of interlayer insulating layers and word line structures; and A vertical channel post penetrates the word line stack and is electrically connected to the common electrode layer. Each of the character line structures includes a main body portion having a first vertical width and an extension portion having a second vertical width greater than the first vertical width. The extension is adjacent to the vertical channel post. The extension includes a word core, a barrier metal layer surrounding the top, side, and bottom surfaces of the word core, and a liner partially surrounding the barrier metal layer such that the barrier metal layer is in direct contact with the vertical channel post.

2. The three-dimensional semiconductor device according to claim 1, in, The extension includes an upper protrusion that projects upward from the top surface of the main body and a lower protrusion that projects downward from the bottom surface of the main body.

3. The three-dimensional semiconductor device according to claim 2, wherein, The main body includes the word core and the blocking metal layer, the blocking metal layer surrounding the top surface and the bottom surface of the word core to contact the corresponding interlayer insulation layer in the interlayer insulation layer.

4. The three-dimensional semiconductor device according to claim 3, in, The liner is formed at the upper protrusion and the lower protrusion, and the liner is not formed at the interface between the barrier metal layer and the vertical channel post.

5. The three-dimensional semiconductor device according to claim 3, in, The liner comprises an insulating material having a high dielectric constant greater than 10.

6. The three-dimensional semiconductor device according to claim 3, in, The word core comprises metal, and The barrier metal layer includes at least one of titanium nitride and tantalum nitride.

7. The three-dimensional semiconductor device according to claim 2, in, The vertical trench column includes: Core post; A channel layer that surrounds the side surface of the core post; A tunneling layer that surrounds the side surface of the channel layer; A charge trapping layer surrounds the side surface of the tunneling layer; A barrier insulating layer surrounds the side surface of the charge trapping layer; and A buffer layer surrounds the side surface of the barrier insulating layer. The extension protrudes laterally into the interior of the vertical channel column.

8. The three-dimensional semiconductor device according to claim 7, in, The interface between the extension and the vertical channel post is located inside the buffer layer.

9. The three-dimensional semiconductor device according to claim 7, in, The interface between the extension and the vertical trench post is adjacent to the barrier insulation layer.

10. The three-dimensional semiconductor device according to claim 7, in, The interface between the extension and the vertical channel post is located inside the barrier insulation layer.

11. The three-dimensional semiconductor device according to claim 7, in, The barrier insulating layer comprises a metal oxide, and The buffer layer comprises silicon oxide.

12. The three-dimensional semiconductor device according to claim 1, further comprising: A transistor, logic interconnects, and a logic insulating layer are formed between the substrate and the common electrode layer, the logic insulating layer surrounding the transistor and the logic interconnects. The common electrode layer is formed on the logic insulating layer.

13. A three-dimensional semiconductor device, the three-dimensional semiconductor device comprising: substrate; A common electrode layer is located on the substrate; A word line stack, which is disposed on the common electrode layer, the word line stack comprising alternating layers of interlayer insulating layers and word line structures; as well as A vertical channel post penetrates the word line stack and is electrically connected to the common electrode layer. Each of the word line structures includes a main body located between the interlayer insulating layers and an extension that contacts the vertical channel post. The extension includes an upper protrusion projecting upward from the top surface of the main body and a lower protrusion projecting downward from the bottom surface of the main body. The extension includes a word core, a barrier metal layer surrounding the top, side and bottom surfaces of the word core, and a liner partially surrounding the barrier metal layer so that the barrier metal layer is in direct contact with the vertical channel post.

14. The three-dimensional semiconductor device according to claim 13, in, The main body includes the word core and the barrier metal layer surrounding the top and bottom surfaces of the word core and in contact with the corresponding interlayer insulation layer in the interlayer insulation layer.

15. The three-dimensional semiconductor device according to claim 13, in, The liner is formed at the upper and lower protrusions of the extension, and The liner is not formed at the interface between the extension and the vertical channel post.

16. The three-dimensional semiconductor device according to claim 13, in, The vertical trench column includes: Core post; A channel layer that surrounds the side surface of the core post; A tunneling layer that surrounds the side surface of the channel layer; A charge trapping layer surrounds the side surface of the tunneling layer; A barrier insulating layer surrounds the side surface of the charge trapping layer; and A buffer layer surrounds the side surface of the barrier insulating layer. The extension protrudes laterally into the interior of the vertical channel column.

17. The three-dimensional semiconductor device according to claim 16, in, The interface between the extension and the vertical channel post is closer to the core post than the interface between the interlayer insulation layer and the vertical channel post.

18. The three-dimensional semiconductor device according to claim 16, in, The extension is formed inside the buffer layer.

19. The three-dimensional semiconductor device according to claim 13, in, Each of the word line structures includes a word line core and a blocking metal layer surrounding the word line core. The character line core has a first vertical width in the main body. The letter core has a second vertical width in the extension, and The second vertical width is greater than the first vertical width.

20. A semiconductor device comprising: A word line stack, disposed above a common electrode layer, comprising alternating layers of interlayer insulating layers and word line structures; Each of the word line structures includes a main body and an extension located at one end of the main body, the extension contacting a vertical channel post. The extension includes an upper protrusion extending vertically upward above the top surface of the main body and a lower protrusion extending vertically downward below the bottom surface of the main body. The extension includes a word core, a barrier metal layer surrounding the top, side and bottom surfaces of the word core, and a liner partially surrounding the barrier metal layer so that the barrier metal layer is in direct contact with the vertical channel post.

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