Image sensor and method for forming an image sensor

Abstract

Various embodiments of the present invention relate to image sensors and methods for forming image sensors, wherein an inter-pixel trench isolation structure is defined by a low-transmittance layer. In some embodiments, the image sensor includes an array of pixels and an inter-pixel trench isolation structure. The array of pixels is located on a substrate, and the pixels of the array include individual photodetectors located within the substrate. The inter-pixel trench isolation structure is located within the substrate. Furthermore, the inter-pixel trench isolation structure extends along the boundaries of the pixels and individually surrounds the photodetectors to separate the photodetectors from each other. The inter-pixel trench isolation structure is defined by a low-transmittance layer having low transmittance to incident radiation, such that the inter-pixel trench isolation structure has low transmittance to incident radiation. The low-transmittance layer may be, for example, a metal and / or some other suitable material.

Description

Technical Field

[0001] Embodiments of the present invention relate to image sensors and methods for forming image sensors. Background Technology

[0002] Integrated circuits (ICs) with image sensors are used in a variety of modern electronic devices, such as cameras and mobile phones. In recent years, complementary metal-oxide-semiconductor (CMOS) image sensors have become widely used, largely replacing charge-coupled device (CCD) image sensors. Compared to CCD image sensors, CMOS image sensors are increasingly favored due to their low power consumption, small size, fast data processing speed, direct data output, and low manufacturing cost. Some types of CMOS image sensors include front-side illumination (FSI) image sensors and back-side illumination (BSI) image sensors. Summary of the Invention

[0003] Embodiments of the present invention provide an image sensor, comprising: a substrate; a pixel including a photodetector, wherein the photodetector is located in the substrate; and an external trench isolation structure extending into the substrate, wherein the external trench isolation structure has a pair of external isolation segments located at the boundary of the pixel on opposite sides of the photodetector, wherein the external trench isolation structure includes a low transmittance layer, and wherein the low transmittance layer blocks incident radiation regardless of the incident angle.

[0004] Another embodiment of the present invention provides an image sensor, comprising: a substrate; an array of pixels located in multiple rows and columns on the substrate, wherein each pixel includes a separate photodetector located in the substrate; and an inter-pixel trench isolation structure located in the substrate, wherein the inter-pixel trench isolation structure extends along the boundaries of the pixels and individually surrounds the pixels to separate the pixels from each other, and wherein the inter-pixel trench isolation structure includes a metal layer.

[0005] Another embodiment of the present invention provides a method for forming an image sensor, the method comprising: forming a pixel on a substrate, the pixel including a photodetector located in the substrate; patterning the substrate to form an external trench, wherein the external trench surrounds the photodetector along the boundary of the pixel and has a pair of external isolation segments respectively located on opposite sides of the photodetector; and depositing a low-transmittance layer covering the substrate and filling the external trench, wherein the low-transmittance layer blocks incident radiation regardless of the incident angle. Attached Figure Description

[0006] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1 Cross-sectional views of some embodiments of an image sensor are shown, which includes an inter-pixel trench isolation structure partially defined by a low-transmittance layer.

[0008] Figure 2 It shows Figure 1 Top view layout diagram of some embodiments of the image sensor.

[0009] Figure 3A and Figure 3B It shows Figure 1 Cross-sectional views of some alternative embodiments of the image sensor, wherein the image sensor includes additional components.

[0010] Figure 4A and Figure 4B It shows Figure 1 Cross-sectional views of some alternative embodiments of the image sensor, wherein the configuration of the image sensor varies.

[0011] Figure 5A and Figure 5B It shows Figure 1 Cross-sectional views of some alternative embodiments of the image sensor, wherein the configuration of the image sensor is omitted.

[0012] Figure 6 It shows Figure 1 Cross-sectional views of some embodiments of an image sensor, wherein the image sensor includes multiple pixels.

[0013] Figure 7 It shows Figure 6 Top view layout diagram of some embodiments of the image sensor.

[0014] Figure 8 It shows Figure 1 Cross-sectional views of some alternative embodiments of the image sensor, wherein the low-transmittance layer has a high absorption rate.

[0015] Figure 9 It shows Figure 8 Top view layout diagram of some embodiments of the image sensor.

[0016] Figure 10 It shows Figure 8 Cross-sectional views of some embodiments of an image sensor, wherein the image sensor includes multiple pixels.

[0017] Figure 11 It shows Figure 10 Top view layout diagram of some embodiments of the image sensor.

[0018] Figure 12 It shows Figure 1 A cross-sectional view of some alternative embodiments of the image sensor, wherein the low-transmittance layer has a high absorptivity, and the image sensor also includes an in-pixel trench isolation structure.

[0019] Figures 13A to 13C It shows Figure 12 Top view layout diagram of some embodiments of the image sensor.

[0020] Figure 14A and Figure 14B It shows Figure 12 A cross-sectional view of some alternative embodiments of the image sensor, wherein the image sensor further includes an additional inter-pixel trench isolation structure.

[0021] Figure 15 It shows Figure 12 Cross-sectional views of some embodiments of an image sensor, wherein the image sensor includes multiple pixels.

[0022] Figure 16 It shows Figure 15 Top view layout diagram of some embodiments of the image sensor.

[0023] Figure 17 It shows Figure 1 Cross-sectional views of some embodiments of the image sensor, showing the photodetector in more detail, and the interconnect structure electrically coupled to the photodetector.

[0024] Figure 18 It shows Figure 1 Cross-sectional views of some alternative embodiments of the image sensor, wherein the image sensor is front-side illuminated (FSI).

[0025] Figure 19A and Figure 19B It shows Figure 18 A cross-sectional view of some alternative embodiments of the image sensor, wherein the inter-pixel trench isolation structure extends to the back side of the substrate.

[0026] Figure 20 It shows Figure 18 Cross-sectional views of some embodiments of the image sensor, showing the photodetector in more detail, and the interconnect structure electrically coupled to the photodetector.

[0027] Figures 21 to 26 , Figure 27A , Figure 27B , Figure 28 and Figure 29A series of cross-sectional views are shown of some embodiments of a method for forming an image sensor, which includes an inter-pixel trench isolation structure partially defined by a low-transmittance layer.

[0028] Figure 30 It shows Figures 21 to 26 , Figure 27A , Figure 27B , Figure 28 and Figure 29 Block diagrams of some embodiments of the method.

[0029] Figures 31 to 33 , Figure 34A , Figure 34B , Figure 35 and Figure 36 It shows Figures 21 to 26 , Figure 27A , Figure 27B , Figure 28 and Figure 29 A series of cross-sectional views of some alternative embodiments of the method, wherein the dielectric liner layer and the first back-side dielectric layer are integrated.

[0030] Figure 37 It shows Figures 31 to 33 , Figure 34A , Figure 34B , Figure 35 and Figure 36 Block diagrams of some embodiments of the method.

[0031] Figure 38 , Figure 39 , Figure 40A , Figure 40B , Figure 41 and Figure 42 It shows Figures 21 to 26 , Figure 27A , Figure 27B , Figure 28 and Figure 29 A series of cross-sectional views of some alternative embodiments of the method, wherein a dielectric liner layer covering a first back-side dielectric layer is deposited.

[0032] Figure 43 It shows Figure 38 , Figure 39 , Figure 40A , Figure 40B , Figure 41 and Figure 42 Block diagrams of some embodiments of the method.

[0033] Figures 44 to 47 , Figure 48A , Figure 48B , Figure 49 and Figure 50 It shows Figures 21 to 26 , Figure 27A , Figure 27B , Figure 28 and Figure 29 A series of cross-sectional views of some alternative embodiments of the method, wherein the image sensor further includes an in-pixel trench isolation structure.

[0034] Figure 51 It shows Figures 44 to 47 , Figure 48A , Figure 48B , Figure 49 and Figure 50 Block diagrams of some embodiments of the method.

[0035] Figures 52 to 54 , Figure 55A , Figure 55B and Figures 56 to 58 It shows Figures 21 to 26 , Figure 27A , Figure 27B , Figure 28 and Figure 29 A series of cross-sectional views of some alternative embodiments of the method, wherein the image sensor is an FSI.

[0036] Figure 59 It shows Figures 52 to 54 , Figure 55A , Figure 55B and Figures 56 to 58 Block diagrams of some embodiments of the method. Detailed Implementation

[0037] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0038] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0039] Some image sensors include an array of pixels and inter-pixel trench isolation structures. The array is located on a substrate, and each pixel comprises an individual photodetector located within the substrate. The inter-pixel trench isolation structures extend to the substrate and individually surround the photodetectors along the boundaries of the pixels to separate the photodetectors from each other. Typically, the inter-pixel trench isolation structures are dielectric materials with a refractive index lower than that of the substrate to promote total internal reflection (TIR) ​​at the sidewall interfaces where the inter-pixel trench isolation structures are in direct contact with the substrate. For example, the inter-pixel trench isolation structures can be silicon dioxide, while the substrate can be silicon. However, other suitable materials are also possible.

[0040] The TIR at the sidewall interface reflects the incident radiation, which would otherwise propagate between photodetectors. Therefore, inter-pixel trench isolation structures can reduce crosstalk and improve photodetector performance through TIR. Furthermore, the TIR at the sidewall interface can reflect the incident radiation back to the receiving photodetector. Thus, inter-pixel trench isolation structures can provide additional opportunities for photodetectors to absorb radiation and further improve their performance. However, TIR depends on the radiation incident at the sidewall interface at an angle greater than the so-called critical angle. For example, when the inter-pixel trench isolation structure and the substrate are silicon dioxide and silicon, respectively, the critical angle can be approximately 20 degrees. Therefore, radiation incident at the sidewall interface at an angle less than the critical angle can propagate between photodetectors and increase crosstalk.

[0041] Some photodetectors operate in a reverse-biased state with a high bias voltage, thus exhibiting a strong electric field in the corresponding depletion region. Such photodetectors can include, for example, avalanche photodiodes (APDs), single-photon avalanche diodes (SPADs), and other suitable types of photodetectors. Due to the strong electric field, hot carrier luminescence may occur. Hot carrier luminescence is omnidirectional and emits radiation in any direction. As a result, radiation from hot carrier luminescence may be incident on the sidewall interfaces at angles less than the critical angle, and thus may propagate between photodetectors. This can increase crosstalk and therefore potentially degrade photodetector performance.

[0042] Various embodiments of the present invention relate to image sensors and methods for forming image sensors, wherein the inter-pixel trench isolation structure is wholly or partially defined by a low-transmittance layer. In some embodiments, the image sensor includes an array of pixels and an inter-pixel trench isolation structure. The array of pixels is located on a substrate, and the pixels of the array include individual photodetectors located in the substrate. The inter-pixel trench isolation structure is located in the substrate and, as described above, is wholly or partially defined by a low-transmittance layer. Furthermore, the inter-pixel trench isolation structure extends along the boundaries of the pixels and surrounds the photodetectors respectively to separate the photodetectors from each other. The low-transmittance layer has low transmittance to incident radiation, such that the inter-pixel trench isolation structure has low transmittance to incident radiation. Furthermore, due to the inherent properties of the material constituting the low-transmittance layer, the low-transmittance layer has low transmittance, and the low transmittance is independent of TIR. Therefore, the low-transmittance layer blocks radiation regardless of the angle of incidence. The low-transmittance layer may be, for example, or include metals, conductive ceramics, some other suitable materials, or any combination thereof.

[0043] Because the inter-pixel trench isolation structure surrounds the photodetector individually to separate them from each other, it receives radiation propagating between the photodetectors. Because the inter-pixel trench isolation structure has low transmittance, it blocks radiation propagating between the photodetectors, thus reducing crosstalk. This reduced crosstalk, in turn, increases the signal-to-noise ratio (SNR) and other suitable performance parameters of the photodetector. Because the low-transmittance layer has low transmittance due to the inherent properties of the materials constituting it, and is independent of TIR, it effectively blocks radiation emitted by hot carriers, regardless of the angle of incidence.

[0044] refer to Figure 1 A cross-sectional view 100 of some embodiments of an image sensor is provided, wherein an inter-pixel trench isolation structure 102 is partially defined by a low-transmittance layer 104 and separates a pixel 106 in a substrate 108 from adjacent pixels (not shown). The substrate 108 houses a photodetector 110 unique to the pixel 106 and is semiconductor. The substrate 108 may be, for example, or comprise monocrystalline silicon and / or some other suitable semiconductor material.

[0045] The inter-pixel trench isolation structure 102 extends to the back side 108b of the substrate 108 at the boundary of the pixel 106. Furthermore, the inter-pixel trench isolation structure 102 includes a pair of inter-pixel isolation segments located on opposite sides of the pixel 106. In some embodiments, when viewed from above, the inter-pixel trench isolation structure 102 extends along the boundary of the pixel 106 in a closed path. In some embodiments, the inter-pixel trench isolation structure 102 is also referred to as an external trench isolation structure.

[0046] The low-transmittance layer 104 is separated from the substrate 108 by a dielectric pad layer 112 and, in some embodiments, defines most of the inter-pixel trench isolation structure 102. The dielectric pad layer 112 also defines the inter-pixel trench isolation structure 102 and electrically isolates the low-transmittance layer 104 from the substrate 108. The dielectric pad layer 112 may be, for example, silicon oxide and / or some other suitable dielectric.

[0047] The low-transmittance layer 104 has low transmittance to radiation 114, making the inter-pixel trench isolation structure 102 also have low transmittance to radiation 114. Due to the low transmittance, the inter-pixel trench isolation structure 102 blocks radiation 114 from pixel 106 to adjacent pixels, or vice versa, thus reducing crosstalk between pixel 106 and adjacent pixels. By reducing crosstalk, the SNR and other suitable performance indicators of the photodetector 110 can be enhanced. Because the low-transmittance layer 104 prevents radiation 114 from propagating between pixels, the low-transmittance layer 104 can also be called a light-blocking layer.

[0048] In some embodiments, low transmittance is less than about 1%, 5%, 10%, or some other suitable percentage of radiation 114. In some embodiments, the low transmittance layer 104 is opaque to radiation 114. In some embodiments, low transmittance is low compared to the transmittance of the dielectric liner layer 112 and / or the transmittance of silicon oxide. If the transmittance is too high (e.g., greater than about 10% or some other suitable percentage), crosstalk may be high and the performance of photodetector 110 may be low.

[0049] The low-transmittance layer 104 also has high reflectivity for radiation 114, making the inter-pixel trench isolation structure 102 highly reflective of radiation 114. Due to the high reflectivity, the inter-pixel trench isolation structure 102 can reflect radiation 114 back to the photodetector 110. This provides the photodetector 110 with another opportunity to absorb radiation 114, which improves the quantum efficiency (QE), surface-to-noise ratio (SNR), and other suitable performance metrics of the photodetector 110.

[0050] High reflectivity can be, for example, greater than about 80%, 90%, 95%, or some other suitable percentage of radiation 114. If the reflectivity is too low (e.g., less than about 80% or some other suitable percentage), the QE, SNR, and other suitable performance parameters of photodetector 110 may be lower.

[0051] The low transmittance and high reflectance of the low transmittance layer 104 are due to the inherent properties of the material constituting the low transmittance layer 104 and are independent of TIR. In some embodiments, the low transmittance layer 104 is a metal and / or some other suitable conductive material. The metal may be, for example, copper, aluminum, silver, some other suitable metal, or any combination thereof. In alternative embodiments, the low transmittance layer 104 is a dielectric and / or some other suitable material. In at least some embodiments in which the low transmittance layer 104 is a dielectric, the dielectric pad layer 112 may be omitted.

[0052] In some embodiments, the photodetector 110 operates in a reverse-biased state under a high voltage. For example, the photodetector 110 may be an APD, SPAD, or some other suitable type of photodetector. The high voltage may be, for example, a voltage greater than about 100 volts, 200 volts, 1000 volts, 1500 volts, or some other suitable value. Furthermore, the high voltage may be, for example, a voltage of about 100-200 volts, about 200-1000 volts, about 1000-1500 volts, about 1500-2000 volts, or some other suitable value.

[0053] Because photodetector 110 can operate at high voltage, it may readily generate hot carrier emission 116 (schematically shown in a star shape). Hot carrier emission 116 can emit hot carrier radiation 114hc in any direction, making it difficult to effectively block the hot carrier radiation 114hc by TIR. As mentioned above, TIR depends on the incident angle exceeding the so-called critical angle. In some embodiments, the hot carrier radiation 114hc has a wavelength of about 900-1000 nm, about 900-950 nm, about 950-1000 nm, or some other suitable wavelength.

[0054] Because the inter-pixel trench isolation structure 102 has low transmittance and is independent of the TIR used for low transmittance, it can block hot carrier radiation 114hc regardless of the angle of incidence. As a result, the inter-pixel trench isolation structure 102 can effectively reduce crosstalk from hot carrier emission 116. Furthermore, because the inter-pixel trench isolation structure 102 has high reflectivity and is independent of the TIR used for high reflectivity, it can reflect hot carrier radiation 114hc regardless of the angle of incidence.

[0055] In some embodiments, the dielectric pad layer 112 has high transmittance. High transmittance can be, for example, greater than 90%, 95%, 99%, or some other suitable percentage of the incident radiation. In some embodiments, the dielectric pad layer 112 is transparent to the radiation 114. If the transmittance is too low (e.g., less than about 90% or some other suitable percentage), the dielectric pad layer 112 may prevent too much radiation 114 from impacting the low transmittance layer 104 and being reflected. As a result, the QE and other suitable performance parameters of the photodetector 110 may be lower.

[0056] In some embodiments, the thickness T of the dielectric liner layer 112 dll The dielectric liner layer 112 is relatively small, therefore it has high transmittance. Thickness T dll It can be smaller, for example, when it is less than about 100 nanometers, about 50 nanometers, about 10 nanometers, or some other suitable value. Furthermore, the thickness T... dll It can be smaller, for example, at about 10-100 nanometers, about 10-55 nanometers, about 55-100 nanometers, about 20 nanometers, or some other suitable values. If the thickness T... dll If the dielectric liner layer is too large (e.g., greater than about 100 nanometers or some other suitable value), the dielectric liner layer 112 can prevent too much radiation 114 from impacting the low transmittance layer 104. If the thickness T dll If it is too small (e.g., less than about 10 nanometers or some other suitable value), the dielectric pad layer 112 may not be able to provide electrical isolation between the low transmittance layer 104 and the substrate 108.

[0057] In some embodiments, the dielectric liner layer 112 has a higher refractive index than the substrate 108. This can promote TIR at the sidewall interface where the dielectric liner layer 112 and the substrate 108 are in direct contact. However, since the low-transmittance layer 104 has a high reflectivity, TIR may be redundant.

[0058] In some embodiments, the dielectric liner layer 112 also serves as a diffusion barrier layer for the material of the low-transmittance layer 104 to prevent diffusion into the substrate 108. For example, the low-transmittance layer 104 may be or include copper, and the dielectric liner layer 112 may be or include aluminum oxide (e.g., Al2O3) or some other suitable material. Depending on the material of the low-transmittance layer 104, if diffusion into the substrate 108 is permitted, the material may cause the operating parameters of the photodetector 110 to deviate from specifications.

[0059] Continue to refer to Figure 1A front dielectric structure 118 is located beneath the substrate 108 and covers the front side 108f of the substrate 108. The refractive index of the front dielectric structure 118 is higher than that of the substrate 108 at the front side 108f to promote TIR at the front side 108f. As a result, radiation 114 transmitted through the photodetector 110 can be reflected back to the photodetector 110, thus providing the photodetector 110 with another opportunity to absorb radiation 114. This can further improve the QE and other suitable performance parameters of the photodetector 110. The front dielectric structure 118 may be, for example, silicon oxide and / or some other suitable dielectric.

[0060] As seen below, in some embodiments, the front dielectric structure 118 may accommodate all or part of an interconnect structure (not shown). The interconnect structure includes alternating stacked lines, vias, and contacts, and defines a conductive path extending from the photodetector 110. The conductive path may, for example, electrically couple the photodetector 110 to a readout circuit and / or other suitable imaging circuitry.

[0061] A back-side dielectric structure 120 covers the back side 108b of substrate 108 and, together with substrate 108, defines a diffuser 122. The diffuser 122 is located above photodetector 110 and has a periodic pattern at the back side 108b of substrate 108. The periodic pattern of diffuser 122 is used to scatter external radiation 114ex received at the back side 108b of substrate 108. For example, diffuser 122 may scatter external radiation 114ex to increase the angle of incidence of external radiation 114ex at the front side 108f of substrate 108, thereby increasing the TIR at the front side 108f. This can further improve the QE and other suitable performance parameters of photodetector 110. The back-side dielectric structure 120 may be, for example, silicon oxide and / or some other suitable dielectric.

[0062] In some embodiments, the back-side dielectric structure 120 is made of the same material as and / or integrated with the dielectric pad layer 112. Furthermore, in some embodiments, the back-side dielectric structure 120 has a higher refractive index than the substrate 108 at the back side 108b of the substrate 108 to promote TIR at the back side 108b. As a result, radiation 114 can be reflected back to the photodetector 110 via TIR, thus providing the photodetector 110 with another opportunity to absorb radiation 114. This, in turn, can improve the QE and other suitable performance parameters of the photodetector 110.

[0063] A spacer layer 124 is located on the back-side dielectric structure 120, and a microlens 126 is located on the spacer layer 124. In an alternative embodiment, the spacer layer 124 is replaced by a color filter. The spacer layer 124 spaces the microlens 126 from the photodetector 110 and may be, for example, or comprise silicon oxide and / or some other suitable dielectric. The microlens 126 focuses external radiation 114ex onto the photodetector 110.

[0064] refer to Figure 2 Provided Figure 1 Top view layout diagram 200 of some embodiments of the image sensor. For example, Figure 2 You can follow Figure 1 The line A-A' is intercepted, and / or Figure 1 For example, along Figure 2 The line A-A' in the diagram is cut off. Each of the dielectric pad layer 112 and the low-transmittance layer 104 extends along the boundary of the pixel in a closed path to surround the photodetector 110. The low-transmittance layer 104 has low transmittance to reduce crosstalk. In addition, the low-transmittance layer 104 has high reflectivity to reflect radiation 114 back to the photodetector 110. Reduced crosstalk improves the SNR and other suitable performance indicators of the photodetector 110, while high reflectivity improves the QE and other suitable performance indicators of the photodetector 110.

[0065] refer to Figure 3A Provided Figure 1 A cross-sectional view 300A of some alternative embodiments of the image sensor shows that the inter-pixel trench isolation structure 102 is further defined by a barrier layer 302. The barrier layer 302 is a different material from the dielectric liner layer 112 and acts as a diffusion barrier for the material of the low-transmittance layer 104 to prevent the material from diffusing into the substrate 108. For example, the low-transmittance layer 104 may be or include copper, the barrier layer 302 may be or include aluminum oxide (e.g., Al2O3), and the dielectric liner layer 112 may be or include silicon oxide. However, other suitable materials are also possible. Depending on the material of the low-transmittance layer 104, if diffusion is permitted, the material may cause the operating parameters of the photodetector 110 to deviate from specifications and / or degrade the performance of the photodetector 110.

[0066] In some embodiments, the barrier layer 302 is dielectric, thus providing additional electrical isolation between the low-transmittance layer 104 and the substrate 108. In alternative embodiments, the barrier layer 302 is conductive.

[0067] In some embodiments, the blocking layer 302 has high transmittance. High transmittance can be, for example, greater than 90%, 95%, 99%, or other suitable percentage of radiation 114. In some embodiments, the blocking layer 302 is transparent to radiation 114. If the transmittance is too low (e.g., less than about 90% or other suitable percentage), the blocking layer 302 may prevent too much radiation 114 from impacting the low transmittance layer 104 and being reflected. As a result, the QE and other suitable performance parameters of the photodetector 110 may be lower.

[0068] In some embodiments, the thickness T of the barrier layer 302 bl The thickness T is relatively small, therefore the barrier layer 302 has high transmittance. For example, when it is less than about 100 nanometers, about 50 nanometers, about 10 nanometers, or some other suitable value, the thickness T... bl It can be relatively small. Furthermore, for example, when it is approximately 10-100 nanometers, approximately 10-55 nanometers, approximately 55-100 nanometers, approximately 20 nanometers, or some other suitable value, the thickness T... bl It can be smaller. If the thickness T bl If it is too large (e.g., greater than about 100 nanometers or some other suitable value), then the thickness T bl This may prevent too much radiation 114 from impacting the low-transmittance layer 104 and being reflected by it. If the thickness T... bl If it is too small (e.g., less than about 10 nanometers or some other suitable value), the barrier layer 302 may not be able to serve as a diffusion barrier for the material of the low transmittance layer 104.

[0069] refer to Figure 3B Provided Figure 1 A cross-sectional view 300B of some alternative embodiments of the image sensor shows an additional inter-pixel trench isolation structure 304 separating pixel 106 from adjacent pixels (not shown). The additional inter-pixel trench isolation structure 304 extends to the front side 108f of the substrate 108 at the boundary of pixel 106 and directly contacts the inter-pixel trench isolation structure 102 within the substrate 108. Furthermore, the additional inter-pixel trench isolation structure 304 includes a pair of additional inter-pixel isolation segments located on opposite sides of pixel 106. In some embodiments, when viewed from above, the additional inter-pixel trench isolation structure 304 extends along the boundary of pixel 106 in a closed path.

[0070] The additional inter-pixel trench isolation structure 304 includes a dielectric material with a higher refractive index than the substrate 108 to promote TIR at the sidewall interface where the additional inter-pixel trench isolation structure 304 is in direct contact with the substrate 108. By promoting TIR at the sidewall interface, radiation 114 can be reflected back to the photodetector 110 to reduce crosstalk and improve QE, SNR, and other suitable performance parameters. The additional inter-pixel trench isolation structure 304 may be, for example, or include silicon oxide and / or some other suitable dielectric.

[0071] Because the additional inter-pixel trench isolation structure 304 and the inter-pixel trench isolation structure 102 extend to opposite sides of the substrate 108 and are in direct contact within the substrate 108, the additional inter-pixel trench isolation structure 304 defines a composite structure extending through the substrate 108. When the thickness T of the substrate 108... s When the additional inter-pixel trench isolation structure 304 and inter-pixel trench isolation structure 102 extend too far individually through the substrate 108, the composite structure can provide enhanced inter-pixel isolation and reduce crosstalk.

[0072] refer to Figure 4A and Figure 4B Provided Figure 1 Cross-sectional views 400A, 400B show some alternative embodiments of the image sensor, wherein the configuration of the image sensor varies. Figure 4A In this embodiment, the inter-pixel trench isolation structure 102 extends partially through the substrate 108 from the front side 108f. In an alternative embodiment, the inter-pixel trench isolation structure 102 extends completely through the substrate 108. Figure 4B In the middle, the top surface of the low transmittance layer 104 is approximately flush with the top surface of the substrate 108.

[0073] refer to Figure 5A and Figure 5B Provided Figure 1 Cross-sectional views 500A and 500B show some alternative embodiments of the image sensor, where the configuration of the image sensor is omitted. Figure 5A In this design, diffuser 122 is omitted. Thus, the interface between substrate 108 and back-side dielectric structure 120 is flat from the first side of pixel 106 to the second side of pixel 106 opposite to the first side. Figure 5B In this paper, the dielectric pad layer 112 is omitted. For example, the dielectric pad layer 112 can be omitted at least when the low transmittance layer 104 is a dielectric with low transmittance.

[0074] Although reference Figure 1 Described Figure 2 However, it should be understood that in alternative embodiments, Figure 2 Applicable to Figure 3A , Figure 3B, Figure 4A , Figure 4B , Figure 5A and Figure 5B Any one of them. Therefore, Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A and Figure 5B Any one of them can go along Figure 2 The line A-A' in the middle is intercepted. Furthermore, Figure 2 You can follow Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A and Figure 5B Cut off line A-A' from any of them. Figure 2 Applied to Figure 3A In an alternative embodiment, Figure 2 It also includes a blocking layer 302 that extends in a closed path around the photodetector 110 along the boundary of the pixel 106.

[0075] refer to Figure 6 Provided Figure 1 A cross-sectional view 600 of some embodiments of an image sensor, wherein the image sensor includes a plurality of pixels 106. Each of the pixels 106 is... Figure 1 Their counterparts are shown and described. Furthermore, pixels 106 share the inter-pixel trench isolation structure 102. For clarity, the boundaries 602 between pixels 106 are demarcated by dashed lines.

[0076] In some embodiments, the width W of the low transmittance layer 104 ltl Greater than approximately 100 nanometers, approximately 200 nanometers, approximately 500 nanometers, or some other suitable value. Furthermore, in some embodiments, the width W... lt1 It is approximately 100-200 nanometers, approximately 200-500 nanometers, or some other suitable value. If the width W... lt1 If the width W is too small (e.g., less than about 100 nanometers or some other suitable value), the low-transmittance layer 104 and the inter-pixel trench isolation structure 102 may have high transmittance, and therefore crosstalk may be high. lt1 If the size is too large (e.g., greater than about 500 nanometers or some other suitable value), the size of the photodetector 110 may be small and / or the number of pixels 106 may be large. The former results in a low QE for the photodetector 110, while the latter results in a low pixel density.

[0077] In some embodiments, the width W ltl With thickness T dllThe ratio between them is approximately 5:1 to 20:1, approximately 5:1 to 10:1, approximately 10:1 to 15:1, approximately 15:1 to 20:1, or other suitable values. If the ratio is too high (e.g., greater than approximately 20:1 or some other suitable value), the thickness T... dll Possibly too small and / or the width W lt1 It might be too large. If the thickness T dll If the ratio is too small, the dielectric liner layer 112 may provide poor electrical insulation between the low-transmittance layer 104 and the substrate 108. If the ratio is too low (e.g., less than about 5:1 or some other suitable value), the thickness T... dll It may be too large and / or the width W lt1 It might be too small. If the thickness T dll If it is too small, the dielectric pad layer 112 can prevent too much radiation 114 from impacting the low transmittance layer 104.

[0078] Although Figure 6 An image sensor comprising multiple pixels 106 is shown, each pixel configured as follows: Figure 1 In the 106th pixel, however, in an alternative embodiment, Figure 6 Each of the 106 pixels can be configured as Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A and Figure 5B Pixel 106 in any one of them.

[0079] refer to Figure 7 Provided Figure 6 Top view layout diagram 700 of some embodiments of the image sensor. For example, Figure 7 You can follow Figure 6 The line B-B' in the middle is intercepted, and / or Figure 6 For example, along Figure 7 The line B-B' in the diagram is cut off. The low transmittance layer 104 is continuous and individually surrounds the pixel 106 along the boundary 602 of the pixel 106 to separate the pixels 106 from each other and reduce crosstalk. The dielectric pad layer 112 includes a plurality of annular segments. The annular segments are individual for each pixel 106, and each extends along the boundary of the individual pixel in a closed path. Although not visible in the top view layout diagram 700, the annular segments can be interconnected through portions of the dielectric pad layer 112 located beneath the low transmittance layer 104.

[0080] refer to Figure 8 Provided Figure 1A cross-sectional view 800 of some alternative embodiments of the image sensor shows a low-transmittance layer 104 having a high absorptivity rather than a high reflectivity. As a result, when radiation 114 strikes the low-transmittance layer 104, most of the radiation 114 is absorbed by the low-transmittance layer 104 rather than reflected. The high absorptivity can be, for example, greater than about 80%, 90%, or 95%. However, other suitable percentages are also possible.

[0081] Because the low-transmittance layer 104 has high absorptivity and low transmittance, the low-transmittance layer 104, and therefore the inter-pixel trench isolation structure 102, prevents crosstalk. However, if the low-transmittance layer 104 absorbs most of the radiation incident on the inter-pixel trench isolation structure 102, the QE loss will be high, and therefore the QE will be poor. Therefore, the dielectric pad layer 112 is configured to promote TIR at the sidewall interface where the dielectric pad layer 112 and the substrate 108 are in direct contact. TIR reflects most of the radiation, and the low-transmittance layer 104 absorbs the unreflected radiation, thus resulting in low QE loss and low crosstalk. Note that in the foregoing embodiment, because the low-transmittance layer 104 has high reflectivity, the TIR at the sidewall interface is redundant.

[0082] To promote TIR at the sidewall interface, the dielectric pad layer 112 has a higher refractive index than the substrate 108. For example, the dielectric pad layer 112 may be or include silicon oxide, while the substrate 108 may be or include silicon. However, other suitable materials are also possible. Additionally, the dielectric pad layer 112 has a thickness T... dll To increase TIR and minimize QE loss. Typically, thickness T dll The larger the thickness T, the larger the TIR at the sidewall interface, and therefore the smaller the QE loss. dll It can be, for example, greater than about 100 nanometers, about 200 nanometers, about 500 nanometers, or some other suitable value. Additionally, the thickness T... dll It can be, for example, about 100-200 nanometers, about 200 nanometers, about 200-500 nanometers, or some other suitable value.

[0083] If the thickness T dll If the thickness T is too small (e.g., less than about 100 nanometers or some other suitable value), the TIR at the sidewall interface may be low, and the QE loss may be high. Therefore, the QE and other suitable performance parameters of the photodetector 110 may be low. If the thickness T... dll If the size is too large (e.g., greater than about 500 nanometers or some other suitable value), the size of photodetector 110 may be small, and / or the number of pixels 106 may be large. The former results in a low QE for photodetector 110, while the latter results in a low pixel density.

[0084] The low transmittance and high absorptivity of the low transmittance layer 104 are attributed to the inherent properties of the materials constituting the low transmittance layer 104 and are independent of TIR. In some embodiments, the low transmittance layer 104 is a metal, a conductive ceramic, some other suitable conductive material, or any combination thereof. The metal may be, for example, tungsten and / or some other suitable metals. The conductive ceramic may be, for example, titanium nitride, tantalum nitride, some other suitable conductive ceramics, or any combination thereof. In alternative embodiments, the low transmittance layer 104 is a dielectric and / or some other suitable material. In at least some embodiments where the low transmittance layer 104 is a dielectric, the dielectric pad layer 112 may be omitted.

[0085] refer to Figure 9 Provided Figure 8 Top view layout diagram 900 of some embodiments of the image sensor. For example, Figure 9 You can follow Figure 8 The line C-C' in the middle is cut off, and / or Figure 8 For example, along Figure 9 The line C-C' in the diagram is cut off. Radiation 114 striking the sidewall interface of the dielectric pad layer 112 at an angle smaller than the critical angle for TIR (e.g., α1) propagates through the dielectric pad layer 112 and is absorbed by the low transmittance layer 104. On the other hand, radiation 114 striking the sidewall interface of the dielectric pad layer 112 at an angle larger than the critical angle for TIR (e.g., α2) is reflected by TIR. In at least some embodiments where the substrate 108 is or includes silicon and the dielectric pad layer 112 is or includes silicon oxide, the critical angle is about 20 degrees. However, other suitable materials and / or critical angles are also possible.

[0086] refer to Figure 10 Provided Figure 8 A cross-sectional view 1000 of some embodiments of an image sensor, wherein the image sensor includes a plurality of pixels 106. Each pixel 106 is... Figure 8 Their counterparts are shown and described below. Furthermore, pixels 106 share the inter-pixel trench isolation structure 102. For clarity, the boundaries 602 between pixels 106 are demarcated by dashed lines.

[0087] In some embodiments, the width W of the low transmittance layer 104 ltl With the thickness T of dielectric pad layer 112 dll The ratio between them is approximately 1:1 to 5:1, approximately 1:1 to 2.5:1, approximately 2.5:1 to 5:1, or some other suitable value. If the ratio is too high (e.g., greater than approximately 5:1 or some other suitable value), then the thickness T... dll Possibly too small and / or the width W lt1 It might be too large. If the thickness T dllIf it's too small, the TIR at the sidewall interface may be low, while the QE loss may be high. If the width W... lt1 If the ratio is too large, the photodetector 110 may be too small and / or the pixel 106 may be too large. The former results in a low QE, while the latter results in a low pixel density. If the ratio is too low (e.g., less than about 1:1 or some other suitable value), the thickness T... dll It may be too large and / or the width W lt1 It might be too small. If the thickness T dll If the width W is too large, then, as mentioned above, the photodetector 110 may be too small and / or the pixel 106 may be too large. lt1 If it is too small, the low-transmittance layer 104 may be too thin to absorb radiation 114.

[0088] refer to Figure 11 Provided Figure 10 Top view layout diagram 1100 of some embodiments of the image sensor. For example, Figure 11 You can follow Figure 10 The line D-D' is intercepted, and / or Figure 10 For example, along Figure 11 The line D-D' in the middle is cut off.

[0089] refer to Figure 12 Provided Figure 1 Cross-sectional view 1200 of some alternative embodiments of the image sensor, wherein, as shown in Figure 1200, Figure 8 The low-transmittance layer 104 has high absorptivity but not high reflectivity. Because the low-transmittance layer 104 has both high absorptivity and low transmittance, it prevents crosstalk. However, if the low-transmittance layer 104 absorbs most of the radiation across the pixel boundary, the QE loss will be high, and therefore the QE will be poor. Therefore, the image sensor also includes an in-pixel trench isolation structure 1202.

[0090] The intra-pixel trench isolation structure 1202 is surrounded by the inter-pixel trench isolation structure 102 and extends to the back side 108b of the substrate 108. Furthermore, the intra-pixel trench isolation structure 1202 includes a pair of intra-pixel isolation segments located on opposite sides of the pixel 106 and sandwiching the photodetector 110 between them. In some embodiments, when viewed from above, the intra-pixel trench isolation structure 1202 extends in a closed path around the photodetector 110. In some embodiments, the intra-pixel trench isolation structure 1202 is also referred to as an internal trench isolation structure. The intra-pixel trench isolation structure 1202 is configured to facilitate TIR at the sidewall interface where the intra-pixel trench isolation structure 1202 and the substrate 108 are in direct contact. The TIR reflects most of the radiation in its path to the inter-pixel trench isolation structure 102, and the low-transmittance layer 104 absorbs the radiation not reflected by the TIR, resulting in low QE loss and crosstalk.

[0091] To promote TIR, the in-pixel trench isolation structure 1202 has a higher refractive index than the substrate 108. For example, the in-pixel trench isolation structure 1202 may be or include silicon oxide, while the substrate 108 may be or include silicon. However, other suitable materials are also possible. Additionally, the in-pixel trench isolation structure 1202 has a width W. iti To increase TIR and minimize QE loss. Width W iti It can be, for example, greater than approximately 100 nanometers, approximately 200 nanometers, approximately 500 nanometers, or some other suitable value. Additionally, the width W... iti It can be, for example, about 100-200 nanometers, about 200 nanometers, about 200-500 nanometers, or some other suitable value.

[0092] If the width W iti If the value is too small (e.g., less than about 100 nanometers or other suitable values), the TIR at the sidewall interface may be low, while the QE loss may be high. Therefore, the QE and other suitable performance parameters of the photodetector 110 may be low. If the width W... iti If the size is too large (e.g., greater than about 500 nanometers or some other suitable value), the size of the photodetector 110 may be small and / or the pixels may be large. The former results in a low QE, while the latter results in a low pixel density.

[0093] In some embodiments, the intra-pixel trench isolation structure 1202 is defined by the back-side dielectric structure 120. In alternative embodiments, the intra-pixel trench isolation structure 1202 is independent of the back-side dielectric structure 120. In some embodiments, the intra-pixel trench isolation structure 1202 is spaced apart from the inter-pixel trench isolation structure 102 by a distance S, the distance S being about 10-100 nanometers, about 10-55 nanometers, about 55-100 nanometers, or some other suitable value. The intra-pixel trench isolation structure 1202 may be, for example, silicon oxide and / or some other suitable dielectric.

[0094] refer to Figures 13A to 13C Provided Figure 12 Top view layout diagrams 1300A-1300C show some embodiments of the image sensor. Figures 13A to 13C These are alternative embodiments of each other, and for example, they can be along... Figure 12 The line E-E' in the middle is intercepted. Furthermore, Figure 12 For example, along Figures 13A to 13C Intercept any line E-E' in the given path.

[0095] Each of the dielectric liner layer 112 and the low-transmittance layer 104 extends along a closed path along the boundary of the pixel 106 to surround the photodetector 110. An in-pixel trench isolation structure 1202 is surrounded by the dielectric liner layer 112 and the low-transmittance layer 104. Furthermore, the in-pixel trench isolation structure 1202 extends around the photodetector 110 in a closed path at an angle smaller than the critical angle for TIR (e.g., ...). Figure 13A and Figure 13B Radiation 114, which strikes the intra-pixel trench isolation structure 1202 (α1) in the image, is transmitted through the intra-pixel trench isolation structure 1202 and absorbed by the low-transmittance layer 104. This occurs at an angle greater than the critical angle for TIR (e.g., ...). Figure 13A and Figure 13B The radiation 114 that strikes the in-pixel trench isolation structure 1202 (α2) is reflected by TIR.

[0096] exist Figure 13A In the image, the intra-pixel trench isolation structure 1202 is a square ring with rounded corners. Figure 13B In the image, the intra-pixel trench isolation structure 1202 is a chamfered square ring. Figure 13C In this embodiment, the intra-pixel trench isolation structure 1202 is annular. In alternative embodiments, the intra-pixel trench isolation structure 1202 may have other suitable layouts and / or corners.

[0097] refer to Figure 14A Provided Figure 12 Cross-sectional view 1400A of some alternative embodiments of the image sensor shows an additional inter-pixel trench isolation structure 304 separating pixel 106 from adjacent pixels (not shown). The additional inter-pixel trench isolation structure 304 extends to the front side 108f of the substrate 108 at the boundary of pixel 106 and directly contacts the inter-pixel trench isolation structure 102 and the intra-pixel trench isolation structure 1202 within the substrate 108. The additional inter-pixel trench isolation structure 304 can be, for example, as shown in Figure 1400A. Figure 3B As shown, therefore when the thickness T of substrate 108 is... s When the additional inter-pixel trench isolation structure 304 and inter-pixel trench isolation structure 102 extend too far through the substrate 108, they can provide enhanced inter-pixel isolation and reduce crosstalk.

[0098] refer to Figure 14B Provided Figure 14AA cross-sectional view 1400B of some alternative embodiments of the image sensor shows an additional inter-pixel trench isolation structure 304 spaced apart from an intra-pixel trench isolation structure 1202. Furthermore, the additional intra-pixel trench isolation structure 1402 extends into the front side 108f of the substrate 108, reaching the intra-pixel trench isolation structure 1202, while being surrounded by and spaced apart from the additional inter-pixel trench isolation structure 304.

[0099] The additional in-pixel trench isolation structure 1402 includes a dielectric material with a higher refractive index than the substrate 108 to promote TIR at the sidewall interface where the additional in-pixel trench isolation structure 1402 and the substrate 108 are in direct contact. By promoting TIR at the sidewall interface, radiation 114 can be reflected back to the photodetector 110 to reduce crosstalk and improve QE, SNR, and other suitable performance metrics. The additional in-pixel trench isolation structure 1402 may be, for example, or include silicon oxide and / or some other suitable dielectric.

[0100] Although reference Figure 12 Described Figures 13A to 13C However, it should be understood that in alternative embodiments, Figures 13A to 13C Applicable to Figure 14A and Figure 14B Any one of them. Therefore, Figure 14A and Figure 14B Any one of them can go along Figures 13A to 13C The line E-E' in any one of them is intercepted. Furthermore, Figures 13A to 13C Any one of them can go along Figure 14A and Figure 14B The line E-E' in any one of them is cut off.

[0101] refer to Figure 15 Provided Figure 12 A cross-sectional view 1500 of some alternative embodiments of an image sensor, wherein the image sensor includes a plurality of pixels 106. Each pixel 106 is... Figure 12 Their counterparts are shown and described below. Furthermore, pixels 106 share the inter-pixel trench isolation structure 102 and have separate intra-pixel trench isolation structures 1202. For clarity, the boundaries 602 between pixels 106 are demarcated by dashed lines.

[0102] Although Figure 15 An image sensor comprising multiple pixels 106 is shown, each pixel 106 being configured as follows: Figure 12 In the 106th pixel, however, in an alternative embodiment, Figure 15 Each of the 106 pixels can be configured as Figure 14A and Figure 14B Pixel 106 in any one of them.

[0103] refer to Figure 16 Provided Figure 15 Top view layout diagram 1600 of some embodiments of the image sensor. For example, Figure 16 You can follow Figure 15 The line F-F' in the middle is intercepted, and / or Figure 15 For example, along Figure 16 Cut off the line F-F' in the middle.

[0104] refer to Figure 17 Provided Figure 1 A cross-sectional view 1700 of some embodiments of the image sensor shows a photodetector 110 in more detail, and the photodetector 110 is electrically coupled to an interconnect structure 1702 on the front side 108f of the substrate 108. The photodetector 110 includes a first contact region 1704, a guard ring 1706, and a pair of second contact regions 1708. Furthermore, the photodetector 110 may be, for example, an APD, a SPAD, or some other suitable type of photodetector.

[0105] The first contact region 1704 is located at the center of pixel 106. A guard ring 1706 surrounds the first contact region 1704 and has a pair of guard ring segments. The guard ring segments are located on opposite sides of the first contact region 1704 at the boundary of the first contact region. In some embodiments, when viewed from above, the guard ring 1706 extends along the boundary of the first contact region 1704 in a closed path. The first contact region 1704 and the guard ring 1706 have a common doping type, but the first contact region 1704 has a higher doping concentration. Furthermore, the common doping type is opposite to the doping type of the adjacent region of substrate 108 and / or the majority of substrate 108.

[0106] The second contact regions 1708 are located on opposite sides of the guard ring 1706 at the outer periphery of the pixel 106. In some embodiments, the second contact regions 1708 correspond to different segments of an annular contact region extending in a closed path around the guard ring 1706. The second contact regions 1708 share a common doping type opposite to that of the first contact regions 1704 and the guard ring 1706.

[0107] Interconnect structure 1702 is located in front dielectric structure 118 and includes a plurality of contacts 1710, a plurality of lines 1712, and a plurality of vias 1714. Contacts 1710 extend from a first contact region 1704 and a second contact region 1708, and lines 1712 and vias 1714 are alternately stacked below contacts 1710 to define conductive paths leading out from contacts 1710. Contacts 1710, lines 1712, and vias 1714 may be, for example, metal and / or other suitable conductive materials.

[0108] refer to Figure 18 Provided Figure 1 A cross-sectional view 1800 shows some alternative embodiments of the image sensor, wherein the image sensor is front-side illuminated (FSI) instead of back-side illuminated (BSI). Thus, the spacer layer 124 and microlens 126 are located on the front side 108f of the substrate 108, and the image sensor is configured to receive external radiation 114ex from the front side 108f of the substrate 108. Additionally, the inter-pixel trench isolation structure 102 extends into the front side 108f of the substrate 108 to a depth less than the entire thickness of the substrate 108. In an alternative embodiment, the inter-pixel trench isolation structure 102 extends completely through the substrate 108.

[0109] refer to Figure 19A and Figure 19B Provided Figure 18 Cross-sectional views 1900A, 1900B of some alternative embodiments of the image sensor, wherein the inter-pixel trench isolation structure 102 extends into the back side 108b of the substrate 108 instead of the front side 108f of the substrate 108. Figure 19A In the middle, the low transmittance layer 104 and the dielectric pad layer 112 do not cover the back side 108b of the substrate 108. Figure 19B In this structure, a low-transmittance layer 104 and a dielectric pad layer cover the back side 108b of the substrate 108. Furthermore, the back-side dielectric structure 120 is divided into a first back-side dielectric layer 120a and a second back-side dielectric layer 120b, located below and above the low-transmittance layer 104, respectively. The first back-side dielectric layer 120a and / or the second back-side dielectric layer 120b can be, for example, […]. Figure 18 The back-side dielectric structure 120 is described.

[0110] Because the low-transmittance layer 104 covers the back side 108b of the substrate 108 and has high reflectivity, radiation 114 that passes through the back side 108b of the substrate 108 and reaches the low-transmittance layer 104 can be reflected back to the photodetector 110. This gives the photodetector 110 another opportunity to absorb radiation 114. Therefore, the QE and other suitable performance indicators of the photodetector 110 are enhanced.

[0111] refer to Figure 20 Provided Figure 18 A cross-sectional view 2000 of some embodiments of an image sensor shows a photodetector 110 in more detail, which is electrically coupled to an interconnect structure 1702 on the front side 108f of a substrate 108. Except that the conductive components of the interconnect structure 1702 (e.g., contacts 1710, lines 1712, and vias 1714) are not directly located below the first contact region 1704 to allow radiative transfer through the interconnect structure 1702 to the photodetector 110, the photodetector 110 and the interconnect structure 1702 are as shown in... Figure 17As stated in the document.

[0112] Although Figure 3A The diagram shows a barrier layer 302. Figure 1 An alternative embodiment of the image sensor, but Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14A , Figure 14B , Figure 15 , Figure 17 , Figure 18 , Figure 19A , Figure 19B and Figure 20 Any alternative embodiment of the image sensor in any of them may include, Figure 3A The barrier layer 302 in the middle. Although Figure 3B The diagram shows an additional inter-pixel trench isolation structure 304. Figure 1 An alternative embodiment of the image sensor, but Figure 3A , Figure 4B , Figure 5A , Figure 5B , Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 15 and Figure 17 Any alternative embodiment of the image sensor in any of them may include, Figure 3B The additional inter-pixel trench isolation structure 304 in the middle. Although Figure 4A It shows Figure 1 An alternative embodiment of the image sensor, wherein the inter-pixel trench isolation structure 102 extends to the front side 108f of the substrate 108, but Figure 3A , Figure 3B , Figure 4B , Figure 5A , Figure 5B , Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 15 and Figure 17 Any alternative embodiment of the image sensor may also have, as Figure 4A The inter-pixel trench isolation structure 102 extends to the front side 108f of the substrate 108. Although Figure 4B It shows Figure 1 In an alternative embodiment of the image sensor, the top surface of the low-transmittance layer 104 is approximately flush with the top surface of the substrate 108, but Figure 3A, Figure 3B , Figure 4A , Figure 5A , Figure 5B , Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14A , Figure 14B , Figure 15 , Figure 17 , Figure 18 , Figure 19A , Figure 19B and Figure 20 Any alternative embodiment of the image sensor may also have a top surface of a low-transmittance layer 104 that is approximately flush with the top surface of the substrate 108. Although Figure 5A and Figure 5B It shows Figure 1 An alternative embodiment of the image sensor omits the diffuser 122 and / or the dielectric pad layer 112, but Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14A , Figure 14B , Figure 15 , Figure 17 , Figure 18 , Figure 19A , Figure 19B and Figure 20 In any optional embodiment of the image sensor, the diffuser 122 and / or dielectric pad layer 112 may be omitted. Although Figure 8 It shows Figure 1 An alternative embodiment of the image sensor, wherein the low transmittance layer 104 is absorbent and the dielectric pad layer 112 is configured for TIR, but in Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6 , Figure 12 , Figure 14A , Figure 14B , Figure 15 , Figure 17 , Figure 18 , Figure 19A , Figure 19B and Figure 20 In any alternative embodiment of the image sensor, the low transmittance layer 104 may be as follows: Figure 8 The absorbent and dielectric pad layer 112 in the middle can be as Figure 8It is configured for TIR. Although Figure 12 It shows Figure 1 An alternative embodiment of the image sensor, wherein the low-transmittance layer 104 is absorbent, and the image sensor further includes an in-pixel trench isolation structure 1202, but in Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6 , Figure 8 , Figure 10 , Figure 17 , Figure 18 , Figure 19A , Figure 19B and Figure 20 In any alternative embodiment of the image sensor, the low transmittance layer 104 may be as follows: Figure 12 The image sensor shown is absorbent, and may also include an in-pixel trench isolation structure 1202. Although Figure 17 It shows Figure 1 A more detailed embodiment of the image sensor is shown, wherein the photodetector 110 is shown in more detail and the photodetector 110 is electrically coupled to the interconnect structure 1702, but in an alternative embodiment, Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6 , Figure 12 , Figure 14A , Figure 14B and Figure 15 Any photodetector 110 in the photodetector can be as follows Figure 17 As shown, and electrically coupled to as Figure 17 The interconnect structure in 1702. Although Figure 18 It shows Figure 1 The image sensor is an optional embodiment of the FSI image sensor, but in the optional embodiment, Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6 , Figure 12 , Figure 14A , Figure 14B and Figure 15 Any image sensor in the image sensor can be like Figure 18 It is FSI.

[0113] refer to Figures 21 to 26 , Figure 27A , Figure 27B , Figure 28 and Figure 29 A series of cross-sectional views 2100-2600, 2700A, 2700B, 2800, and 2900 are provided for embodiments of a method for forming an image sensor, wherein the inter-pixel trench isolation structure is partially defined by a low-transmittance layer. For example, this method can be used to form Figure 1 , Figure 2 , Figure 3A , Figure 3B , Figure 4B , Figure 5A , Figure 5B and Figures 6 to 11 Any image sensor in the array, as well as other suitable image sensors.

[0114] like Figure 21 As shown in cross-sectional view 2100, a photodetector 110 is formed in substrate 108 from the front side 108f of substrate 108. The photodetector 110 is individual for each pixel 106 of the formed image sensor and includes a first contact region 1704, a guard ring 1706, and a pair of second contact regions 1708. The first contact region 1704 and the guard ring 1706 share a common doping type opposite to that of adjacent regions of substrate 108. Furthermore, the guard ring 1706 has a lower doping concentration than the first contact region 1704. The second contact regions 1708 have a doping type opposite to that of the first contact region 1704 and the guard ring 1706. The photodetector 110 can be, for example, an APD, SPAD, or other suitable type of photodetector. In alternative embodiments, the photodetector 110 has several other suitable configurations.

[0115] like Figure 22 As shown in cross-sectional view 2200, a front dielectric structure 118 is formed, which covers the photodetector 110 on the front side 108f of the substrate 108. In some embodiments, the front dielectric structure 118 has a higher refractive index than the substrate 108 at the interface between the front dielectric structure 118 and the substrate 108 to promote TIR at that interface. The first back dielectric layer 120a may be, for example, silicon oxide and / or some other suitable dielectric.

[0116] For example Figure 22 As shown in cross-sectional view 2200, interconnect structure 1702 is formed to be electrically coupled to photodetector 110 in front dielectric structure 118. Interconnect structure 1702 includes a plurality of contacts 1710, a plurality of lines 1712, and a plurality of vias 1714. Contacts 1710 extend from a first contact region 1704 and a second contact region 1708, and lines 1712 and vias 1714 are alternately stacked above contacts 1710 to define conductive paths leading out from contacts 1710.

[0117] like Figure 23 As shown in cross-sectional view 2300, substrate 108 is flipped so that the back side 108b of substrate 108 is above the front side 108f of substrate 108. Furthermore, the back side 108b of substrate 108 is patterned to form a periodic pattern 2302 directly above photodetector 110. This periodic pattern may, for example, have a zigzag profile or some other suitable profile. Patterning can be performed, for example, by photolithography / etching processes or some other suitable patterning processes.

[0118] like Figure 24 As shown in cross-sectional view 2400, a first back-side dielectric layer 120a is deposited to cover the back side 108b of the substrate 108 and the periodic pattern 2302 (see, for example, see...). Figure 23 The first back-side dielectric layer 120a has a higher refractive index than the substrate 108 to promote TIR at the interface between the first back-side dielectric layer 120a and the substrate 108. Furthermore, the top surface of the first back-side dielectric layer 120a is roughened at least at the periodic patterns. The first back-side dielectric layer 120a may be, for example, silicon oxide and / or some other suitable dielectric.

[0119] The first back-side dielectric layer 120a and the substrate 108 are together in a periodic pattern 2302 (e.g., see...). Figure 23 A diffuser 122 is defined at the back side 108b of the substrate 108. The diffuser 122 is used to scatter the external radiation 114ex received at the back side 108b of the substrate 108. This can, for example, increase the angle of incidence of the external radiation 114ex at the front side 108f of the substrate 108, thereby increasing the TIR at the front side 108f. By increasing the TIR at the front side 108f of the substrate 108, more external radiation 114ex can be reflected back to the photodetector 110. Therefore, the QE and other suitable performance parameters of the photodetector 110 can be enhanced.

[0120] like Figure 25 As shown in cross-sectional view 2500, the top surface of the first back-side dielectric layer 120a is planarized. Planarization can be performed, for example, by chemical mechanical polishing (CMP) or some other suitable planarization process.

[0121] like Figure 26As shown in cross-sectional view 2600, the first back-side dielectric layer 120a and substrate 108 are patterned to define an inter-pixel isolation trench 2602. For example, the inter-pixel isolation trench 2602 is also referred to as an external isolation trench. The inter-pixel isolation trench 2602 has a pair of segments at the boundary of pixel 106, respectively located on opposite sides of photodetector 110. In some embodiments, when viewed from top to bottom, the inter-pixel isolation trench 2602 extends along the boundary of the pixel in a closed path to surround photodetector 110. Furthermore, in some embodiments, the inter-pixel isolation trench 2602 has a... Figure 2 or Figure 7 The top layout is the same as that of the inter-pixel trench isolation structure 102. Patterning can be performed, for example, by photolithography / etching processes or some other suitable patterning processes.

[0122] As by Figure 27A As shown in cross-sectional view 2700A, a dielectric liner layer 112 and a low-transmittance layer 104 are deposited to fill the inter-pixel isolation trench 2602 (see, for example, see...). Figure 26 The dielectric pad layer 112 is deposited prior to the low transmittance layer 104 and electrically isolates the low transmittance layer 104 from the substrate 108. The dielectric pad layer 112 may be, for example, or include silicon oxide, aluminum oxide, some other suitable dielectric, or any combination thereof.

[0123] In some embodiments, the dielectric pad layer 112 also serves as a diffusion barrier for the low transmittance layer 104. For example, the dielectric pad layer 112 may be or include aluminum oxide, while the low transmittance layer 104 may be or include copper. However, other suitable materials are also possible. In some embodiments, the dielectric pad layer 112 has a higher refractive index than the substrate 108. For example, the dielectric pad layer 112 may be or include silicon oxide, while the substrate 108 may be or include silicon.

[0124] The dielectric pad layer 112 has a low absorptivity to radiation and, in some embodiments, a high transmittance to radiation. The low absorptivity can be, for example, less than about 10%, 5%, 1%, or some other suitable percentage of the incident radiation. The high transmittance can be, for example, greater than 90%, 95%, 99%, or some other suitable percentage of the incident radiation. The low absorptivity minimizes QE losses, while the high transmittance allows radiation to travel unimpeded to the low transmittance layer 104. In some embodiments, the dielectric pad layer 112 is transparent to radiation.

[0125] In some embodiments, to achieve low absorption and high transmittance, the thickness T of the dielectric pad layer 112 is... dll Smaller. For example, when less than about 100 nanometers, about 50 nanometers, about 10 nanometers, or some other suitable value, the thickness T dllIt can be relatively small. Furthermore, for example, when it is approximately 10-100 nanometers, approximately 10-55 nanometers, approximately 55-100 nanometers, approximately 20 nanometers, or some other suitable value, the thickness T... dll It can be smaller. If the thickness T dll If the dielectric liner layer is too small (e.g., less than about 10 nanometers or some other suitable value), the dielectric liner layer 112 may not be able to electrically isolate the low transmittance layer 104 from the substrate 108. If the thickness T... dll If the dielectric liner layer 112 is too large (e.g., greater than about 100 nanometers or some other suitable value), it may absorb or otherwise interfere with the radiation propagating to the low transmittance layer 104.

[0126] The dielectric liner 112 can be deposited, for example, by thermal oxidation, such that the dielectric liner 112 is grown from the substrate 108 but not from the first back-side dielectric layer 120a, or is grown minimally. Alternatively, the dielectric liner 112 can be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), or some other suitable deposition process.

[0127] A low-transmittance layer 104 is located above the dielectric pad layer 112 in the inter-pixel isolation trench 2602 and also covers the first back-side dielectric layer 120a. The low-transmittance layer 104 has low transmittance to radiation, thus blocking most or all of the radiation incident upon it. In some embodiments, the low transmittance is less than about 1%, 5%, 10%, or some other suitable percentage of the radiation. In some embodiments, the low-transmittance layer 104 is opaque to radiation. The low-transmittance layer 104 also has high reflectivity to radiation. High reflectivity can be, for example, greater than about 80%, 90%, 95%, or some other suitable percentage of the radiation.

[0128] The low transmittance and high reflectance of the low transmittance layer 104 are due to the inherent properties of the material constituting the low transmittance layer 104, and are not dependent on TIR. In some embodiments, the low transmittance layer 104 is a metal and / or some other suitable conductive material. The metal may be, for example, copper, aluminum, silver, some other suitable metal, or any combination thereof. In alternative embodiments, the low transmittance layer 104 is a dielectric and / or some other suitable material. In at least some embodiments where the low transmittance layer 104 is a dielectric, the deposition of the dielectric pad layer 112 may be omitted, and the low transmittance layer 104 may be deposited directly on the substrate 108 in the inter-pixel isolation trench 2602.

[0129] The low-transmittance layer 104 and the dielectric pad layer 112 define an inter-pixel trench isolation structure 102 that fills the inter-pixel trench 2602. The top layout of the inter-pixel trench isolation structure 102 can be, for example, Figure 2 , Figure 7 , Figure 9 and Figure 11 The top layout of any of them. Because the low-transmittance layer 104 has low transmittance and high reflectance, the inter-pixel trench isolation structure 102 also has low transmittance and high reflectance. Due to the low transmittance, the inter-pixel trench isolation structure 102 can reduce radiation transmitted from pixel 106 to adjacent pixels (not shown) and vice versa, thus reducing crosstalk. By reducing crosstalk, the SNR and other suitable performance indicators of the photodetector 110 can be enhanced. Due to the high reflectance, the inter-pixel trench isolation structure 102 can reflect radiation incident on it back to the photodetector 110. This provides the photodetector 110 with another opportunity to absorb radiation, which can improve the QE, SNR and other suitable performance indicators of the photodetector 110.

[0130] In some embodiments, photodetector 110 operates in a reverse-biased state at a high voltage. For example, photodetector 110 may be an APD, SPAD, or some other suitable type of photodetector. Because photodetector 110 can operate at a high voltage, it may readily emit hot carrier radiation 116 (schematically shown in a star configuration). Hot carrier radiation 116 can emit hot carrier radiation 114hc in any direction, making it difficult to effectively block hot carrier radiation 114hc by TIR. TIR depends on the angle of incidence exceeding the so-called critical angle.

[0131] Because the inter-pixel trench isolation structure 102 has low transmittance and is independent of the TIR used for low transmittance, it can block hot carrier radiation 114hc regardless of the angle of incidence. As a result, the inter-pixel trench isolation structure 102 can effectively reduce crosstalk from hot carrier emission 116. Furthermore, because the inter-pixel trench isolation structure 102 has high reflectivity and is independent of the TIR used for high reflectivity, it can reflect hot carrier radiation 114hc regardless of the angle of incidence.

[0132] In some embodiments, Figure 26 The patterning and deposition of the dielectric pad layer 112 are coordinated to ensure that the width W of the low transmittance layer 104 in the inter-pixel isolation trench 2602 is consistent. ltl Greater than approximately 100 nanometers, approximately 200 nanometers, approximately 500 nanometers, or other suitable values. Furthermore, in some embodiments, the width W... lt1 It is approximately 100-200 nanometers, approximately 200-500 nanometers, or some other suitable value. If the width W... lt1If the width W is too small (e.g., less than about 100 nanometers or some other suitable value), the low-transmittance layer 104 may have high transmittance, and therefore crosstalk may be high. lt1 If the size is too large (e.g., greater than about 500 nanometers or some other suitable value), the size of photodetector 110 may be small and / or the size of pixel 106 may be large. The former reduces the performance of photodetector 110, while the latter reduces pixel density.

[0133] like Figure 27B As shown in cross-sectional view 2700B, according to an alternative embodiment, a dielectric liner layer 112 and a low-transmittance layer 104 are deposited to fill the inter-pixel isolation trench 2602 (e.g., see...). Figure 26 ).in other words, Figure 27A and Figure 27B They are optional to each other, so each is shown individually from Figure 26 Initial deposition. With Figure 27A on the contrary, Figure 27B The low-transmittance layer 104 has a high absorptivity rather than a high reflectivity. As a result, most of the radiation is absorbed by the low-transmittance layer 104 rather than reflected. The high absorptivity can be, for example, greater than about 80%, 90%, or 95%. However, other suitable percentages are also possible.

[0134] If the inter-pixel trench isolation structure 102 absorbs most of the radiation incident on it, the QE loss will be high, and therefore the QE will be poor. Therefore, the dielectric pad layer 112 is configured to facilitate TIR at the sidewall interface where the dielectric pad layer 112 and the substrate 108 are in direct contact. The TIR at the sidewall interface reflects most of the radiation before it reaches the low-transmittance layer 104, and the low-transmittance layer 104 absorbs any radiation transmitted through the dielectric pad layer 112 without being reflected by the TIR, thus resulting in low QE loss and low crosstalk.

[0135] To promote TIR at the sidewall interface, the dielectric pad layer 112 has a higher refractive index than the substrate 108. Additionally, the dielectric pad layer 112 has a thickness T. dll To increase TIR and minimize QE loss. Typically, thickness T dll The larger the thickness T, the larger the TIR at the sidewall interface, and therefore the smaller the QE loss. dll It can be, for example, greater than about 100 nanometers, about 200 nanometers, about 500 nanometers, or some other suitable value. Additionally, the thickness T... dll It can be, for example, about 100-200 nanometers, about 200 nanometers, about 200-500 nanometers, or some other suitable value.

[0136] If the thickness T dllIf the thickness T is too small (e.g., less than about 100 nanometers or other suitable values), the TIR at the sidewall interface may be low, while the QE loss may be high. Therefore, the QE and other suitable performance parameters of the photodetector 110 may be low. If the thickness T... dll If the size is too large (e.g., greater than about 500 nanometers or some other suitable value), the size of the photodetector 110 may be small and / or the size of the pixel 106 may be large. The former leads to low performance, while the latter leads to low pixel density.

[0137] In some embodiments, the low-transmittance layer 104 is a metal, a conductive ceramic, some other suitable conductive material, or any combination thereof. The metal may be, for example, tungsten and / or some other suitable metals. The conductive ceramic may be, for example, titanium nitride, tantalum nitride, some other suitable conductive ceramics, or any combination thereof.

[0138] like Figure 28 As shown in cross-sectional view 2800, the top surface of the low-transmittance layer 104 is recessed to expose the first back-side dielectric layer 120a. This allows for... Figure 27A and Figure 27B Any of the low-transmittance layers 104 in the process are recessed, but using Figure 27A The low-transmittance layer 104 is shown. As described above, Figure 27A and Figure 27B These are alternative approaches. In some embodiments, the recess continues until the top surface of the low-transmittance layer 104 is approximately flush with the top surface of the first back-side dielectric layer 120a. In other embodiments, the recess continues until the top surface of the low-transmittance layer 104 is approximately flush with the top surface of the substrate 108. In some embodiments, the recess also flattens the top surface of the low-transmittance layer 104. For example, the recess can be performed by etch-back, CMP, some other suitable process, or any combination thereof.

[0139] like Figure 29 As shown in cross-sectional view 2900, a second back-side dielectric layer 120b and a spacer layer 124 are deposited over the inter-pixel trench isolation structure 102 and the first back-side dielectric layer 120a. Furthermore, a microlens 126 is formed over the spacer layer 124. The second back-side dielectric layer 120b and the spacer layer 124 may be, for example, silicon oxide and / or some other suitable dielectric.

[0140] Although various embodiments of the reference method are described Figures 21 to 26 , Figure 27A , Figure 27B , Figure 28 and Figure 29 What will be understood is that Figures 21 to 26 , Figure 27A , Figure 27B , Figure 28 and Figure 29 The structure shown is not limited to this method, but can be used independently of it. Although... Figures 21 to 26 , Figure 27A , Figure 27B , Figure 28 and Figure 29 Described as a series of actions, but it should be understood that the order of the actions may be changed in other embodiments. Although... Figures 21 to 26 , Figure 27A , Figure 27B , Figure 28 and Figure 29 A specific set of actions is shown and described, but some actions shown and / or described may be omitted in other embodiments. Furthermore, actions not shown and / or described may be included in other embodiments.

[0141] refer to Figure 30 Provided Figure 26 , Figure 27A , Figure 27B , Figure 28 and Figure 29 A block diagram 3000 shows some embodiments of the method.

[0142] At position 3002, a photodetector is formed in the substrate from the front side of the substrate. See example. Figure 21 .

[0143] At position 3004, an interconnect structure is formed that covers the photodetector and is electrically coupled to the photodetector on the front side of the substrate. See, for example... Figure 22 .

[0144] At 3006, the back side of the substrate is patterned to form a periodic pattern on the photodetector. See example. Figure 23 .

[0145] At 3008, a first back-side dielectric layer is deposited, which covers the back side of the substrate and the periodic pattern. See example. Figure 24 .

[0146] At 3010, the top surface of the first back-side dielectric layer is flattened. See example. Figure 25 .

[0147] At 3012, the back side of the first back-side dielectric layer and the substrate is patterned to form inter-pixel isolation trenches that surround the photodetector along the boundary of the pixel where the photodetector is located. See example Figure 26 .

[0148] At position 3014, a dielectric liner is deposited, which liner and partially fills the inter-pixel isolation trench. See example. Figure 27A and Figure 27B .

[0149] At position 3016, a low-transmittance layer is deposited, which fills the inter-pixel isolation trench above the dielectric liner layer and covers the first back-side dielectric layer. See, for example... Figure 27A and Figure 27B The low-transmittance layer can be, for example, a metal, a conductive ceramic, some other suitable material, or any combination thereof. Furthermore, the low-transmittance layer can, for example, have high reflectivity or high absorptivity.

[0150] At position 3018, the top surface of the low-transmittance layer is recessed to expose the first back-side dielectric layer. See example. Figure 28 .

[0151] At position 3020, a second back-side dielectric layer and a spacer layer are deposited, which cover the first back-side dielectric layer and the low-transmittance layer. See, for example... Figure 29 .

[0152] At position 3022, a microlens is formed that covers the photodetector above the spacer layer. See, for example... Figure 29 .

[0153] Although in this article Figure 30 The block diagram 3000 illustrates and describes a series of actions or events; however, it will be understood that the order in which such actions or events are shown should not be interpreted in a limiting sense. For example, some actions may occur in a different order and / or simultaneously with other actions or events besides those shown and / or described herein. Furthermore, not all of the actions shown may be required to implement one or more aspects or embodiments described herein, and one or more actions shown herein may be performed in one or more separate actions and / or phases.

[0154] refer to Figures 31 to 33 , Figure 34A , Figure 34B , Figure 35 and Figure 36 Provided Figures 31 to 33 , Figure 34A , Figure 34B , Figure 35 and Figure 36 A series of cross-sectional views 3100-3300, 3400A, 3400B, 3500, 3600 of some alternative embodiments of the method, wherein the dielectric liner layer 112 and the first back-side dielectric layer 120a are integrated together.

[0155] like Figure 31 As shown in the cross-sectional view 3100, the execution Figures 21 to 23 Actions at that location. For example, regarding... Figure 21As described, a photodetector 110 is formed in substrate 108 from the front side 108f of substrate 108. (As per...) Figure 22 As described, a front-side dielectric structure 118 and an interconnect structure 1702 are formed, which cover the photodetector 110 on the front side 108f of the substrate 108. (See also: Regarding...) Figure 23 As described, the back side 108b of the patterned substrate 108 is used to form a periodic pattern 2302 directly above the photodetector 110.

[0156] For example Figure 31 As shown in cross-sectional view 3100, a patterned substrate 108 is used to define an inter-pixel isolation trench 2602. The inter-pixel isolation trench 2602 has a pair of segments located on opposite sides of the photodetector 110. In some embodiments, when viewed from above, the inter-pixel isolation trench 2602 extends along the boundary of the pixel 106 in a closed path to surround the photodetector 110. Furthermore, in some embodiments, the inter-pixel isolation trench 2602 has a... Figure 2 or Figure 7 The inter-pixel isolation trench 2602 has the same top layout as the inter-pixel isolation structure 102. Patterning can be performed, for example, by photolithography / etching or some other suitable patterning process. In some embodiments, the patterning of the inter-pixel isolation trench 2602 is independent of the patterning of the periodic pattern 2302. For example, the inter-pixel isolation trench 2602 and the periodic pattern 2302 can be formed using different photolithography / etching processes with different masks.

[0157] like Figure 32 As shown in cross-sectional view 3200, a first back-side dielectric layer 120a is deposited, which covers the back side 108b of the substrate 108 and liner the inter-pixel isolation trench 2602. The first back-side dielectric layer 120a has a higher refractive index than the substrate 108 to promote TIR at the interface between the first back-side dielectric layer 120a and the substrate 108. Furthermore, the top surface of the first back-side dielectric layer 120a is at least in a periodic pattern (e.g., see...). Figure 31 The area is rough. The first back-side dielectric layer 120a may be, for example, silicon oxide and / or some other suitable dielectric.

[0158] The dielectric liner layer 112 can be deposited, for example, by CVD, PVD, or some other suitable deposition process. In some embodiments, due to the deposition process, the thickness T of the first back-side dielectric layer 120a is... fbd The size is larger at the bottom and top surfaces of the first back-side dielectric layer 120a than at the sidewalls of the first back-side dielectric layer 120a.

[0159] The first back-side dielectric layer 120a and the substrate 108 are together in a periodic pattern 2302 (e.g., see...). Figure 31 A diffuser 122 is defined at the location 108b. The diffuser 122 is used to scatter the external radiation 114ex received at the back side 108b of the substrate 108. Furthermore, a portion of the first back-side dielectric layer 120a located in the inter-pixel isolation trench 2602 defines a dielectric pad layer 112. In addition to being formed as part of the first back-side dielectric layer 120a, the dielectric pad layer 112 may, for example, be as described regarding... Figure 27A and Figure 27B As described.

[0160] like Figure 33 As shown in cross-sectional view 3300, the top surface of the first back-side dielectric layer 120a is made flat. Furthermore, the first back-side dielectric layer 120a is etched back to reduce the thickness T of the first back-side dielectric layer 120a at its top and bottom surfaces. fbd Planarization can be performed, for example, by CMP and / or some other suitable planarization process.

[0161] like Figure 34A and Figure 34B As shown in cross-sectional views 3400A and 3400B, a low-transmittance layer 104 is deposited, which fills the inter-pixel isolation trench 2602 above the dielectric pad layer 112 (see, for example, [link to documentation]). Figure 33 ). Figure 34A and Figure 34B They are optional to each other, so each is shown individually in terms of deposition. Figure 34A from Figure 33 In the beginning, and Figure 34B from Figure 33 The alternative embodiment begins, wherein, with a smaller thickness T dll Dielectric liner 112 is formed by deposition or other means.

[0162] exist Figure 34A In China, such as regarding Figure 27B As described, a low-transmittance layer 104 and a dielectric pad layer 112 define an inter-pixel trench isolation structure 102. The low-transmittance layer 104 has low transmittance and high absorptivity, while the dielectric pad layer 112 is configured for TIR (transmissive infrared) radiation. The dielectric pad layer 112 reflects radiation through TIR, and the low-transmittance layer 104 absorbs radiation that is not reflected through TIR, thereby increasing QE (quantum efficiency) and reducing crosstalk, respectively. Figure 34B In China, such as regarding Figure 27AAs described, a low-transmittance layer 104 and a dielectric pad layer 112 define an inter-pixel trench isolation structure 102. The low-transmittance layer 104 has low transmittance and high reflectivity, while the dielectric pad layer 112 has low absorptivity. In some embodiments, the dielectric pad layer 112 is transparent. The low-transmittance layer 104 reflects radiation to reduce crosstalk and increase QE.

[0163] like Figure 35 The cross-sectional view of 3500 is shown, as per the description of... Figure 28 As described, the top surface of the low-transmittance layer 104 is recessed to expose the first back-side dielectric layer 120a. This can be achieved by... Figure 34A and Figure 34B Any of the low-transmittance layers 104 in the process are recessed, but using Figure 34A The low-transmittance layer 104 is shown. As described above, Figure 34A and Figure 34B These are optional options for each other.

[0164] like Figure 36 As shown in cross-sectional view 3600, a second back-side dielectric layer 120b and a spacer layer 124 are deposited over the inter-pixel trench isolation structure 102 and the first back-side dielectric layer 120a. Furthermore, a microlens 126 is formed over the spacer layer 124. The second back-side dielectric layer 120b and the spacer layer 124 may be, for example, silicon oxide and / or some other suitable dielectric.

[0165] Although various embodiments of the reference method are described Figures 31 to 33 , Figure 34A , Figure 34B , Figure 35 and Figure 36 What will be understood is that Figures 31 to 33 , Figure 34A , Figure 34B , Figure 35 and Figure 36 The structure shown is not limited to this method, but can be used independently of it. Although... Figures 31 to 33 , Figure 34A , Figure 34B , Figure 35 and Figure 36 Described as a series of actions, it will be understood that the order of the actions may be changed in other embodiments. Although... Figures 31 to 33 , Figure 34A , Figure 34B , Figure 35 and Figure 36 A specific set of actions is shown and described, but some actions shown and / or described may be omitted in other embodiments. Furthermore, actions not shown and / or described may be included in other embodiments.

[0166] Referring to Figure 3700, it provides Figures 31 to 33 , Figure 34A , Figure 34B , Figure 35 and Figure 36 A block diagram 3700 shows some embodiments of the method.

[0167] At position 3702, a photodetector is formed in the substrate from the front side of the substrate. See example. Figure 31 and Figure 21 .

[0168] At 3704, an interconnect structure is formed that covers and is electrically coupled to the photodetector on the front side of the substrate. See, for example... Figure 31 and Figure 22 .

[0169] At 3706, the back side of the substrate is patterned to form a periodic pattern on the photodetector. See example. Figure 31 and Figure 23 .

[0170] At 3708, the back side of the substrate is patterned to form inter-pixel isolation trenches that surround the photodetector along the boundary of the pixel where the photodetector is located. See example Figure 31 .

[0171] At 3710, a first back-side dielectric layer is deposited, which covers the back side of the substrate and liner the inter-pixel isolation trench. See, for example... Figure 32 .

[0172] At 3712, the top surface of the first back-side dielectric layer is flattened and the top surface of the first back-side dielectric layer is etched back. See example. Figure 33 .

[0173] At position 3714, a low-transmittance layer is deposited, which fills the inter-pixel isolation trenches and covers the first back-side dielectric layer. See example. Figure 34A and Figure 34B .

[0174] At position 3716, the top surface of the low-transmittance layer is recessed to expose the first back-side dielectric layer. See example. Figure 35 .

[0175] At position 3718, a second back-side dielectric layer and a spacer layer are deposited, which cover the first back-side dielectric layer and the low-transmittance layer. See, for example... Figure 36 .

[0176] At position 3720, a microlens is formed to cover the photodetector. See example. Figure 36 .

[0177] Although this article will Figure 37 Block diagram 3700 illustrates and describes a series of actions or events; however, it will be understood that the order in which such actions or events are shown should not be interpreted in a limiting sense. For example, some actions may occur in a different order and / or simultaneously with other actions or events besides those shown and / or described herein. Furthermore, not all of the actions shown may be required to implement one or more aspects or embodiments described herein, and one or more actions depicted herein may be performed in one or more separate actions and / or phases.

[0178] refer to Figure 38 , Figure 39 , Figure 40A , Figure 40B , Figure 41 and Figure 42 Provided Figures 21 to 26 , Figure 27A , Figure 27B , Figure 28 and Figure 29 A series of cross-sectional views 3800, 3900, 4000A, 4000B, 4100, 4200 of some alternative embodiments of the method, wherein a dielectric liner 112 is deposited, the dielectric liner 112 covering a first back-side dielectric layer 120a.

[0179] like Figure 38 As shown in the cross-sectional view 3800, the execution... Figures 21 to 26 Actions at that location. For example, regarding... Figure 21 As described, a photodetector 110 is formed in substrate 108 from the front side 108f of substrate 108. (As per...) Figure 22 As described, a front-side dielectric structure 118 and an interconnect structure 1702 are formed, which cover the photodetector 110 on the front side 108f of the substrate 108. (See also: Regarding...) Figure 23 As described, the back side 108b of the patterned substrate 108 is used to form a periodic pattern directly above the photodetector 110. (As per...) Figure 24 As described, a first back-side dielectric layer 120a is deposited, which covers the back side 108b of the substrate 108 and a periodic pattern. The first back-side dielectric layer 120a and the substrate 108 together define a diffuser 122 at the periodic pattern. (See also: Regarding...) Figure 25 As described, this makes the top surface of the first back-side dielectric layer 120a flat. (As per...) Figure 26 As described, the first back-side dielectric layer 120a and the substrate 108 are patterned to define inter-pixel isolation trenches 2602.

[0180] For example Figure 38As shown in cross-sectional view 3800, a dielectric liner layer 112 is deposited, which covers the first back-side dielectric layer 120a and liner the inter-pixel isolation trench 2602. The dielectric liner layer 112 can be deposited, for example, by CVD, PVD, or some other suitable deposition process. In some embodiments, the thickness T of the dielectric liner layer 112 is [not specified] due to the deposition process. dll The dielectric pad layer 112 is larger at its top and bottom surfaces than at its sidewalls. The dielectric pad layer 112 can be, for example, a reference. Figure 27A and Figure 27B As described.

[0181] like Figure 39 As shown in cross-sectional view 3900, the dielectric pad layer 112 is etched back to reduce the thickness T of the dielectric pad layer 112 at the top and bottom surfaces. dll .

[0182] like Figure 40A and Figure 40B As shown in cross-sectional views 4000A and 4000B, a low-transmittance layer 104 is deposited, which fills the inter-pixel isolation trench 2602 above the dielectric pad layer 112 (see, for example, [link to relevant documentation]). Figure 39 ). Figure 40A and Figure 40B They are optional to each other, so each is shown individually in terms of deposition. Figure 40A from Figure 39 In the beginning, and Figure 40B from Figure 39 The alternative embodiment begins, wherein, with a smaller thickness T dll Dielectric liner 112 is formed by deposition or other means.

[0183] exist Figure 40A In China, such as regarding Figure 27B As described, a low-transmittance layer 104 and a dielectric pad layer 112 define an inter-pixel trench isolation structure 102. The low-transmittance layer 104 has low transmittance and high absorptivity, while the dielectric pad layer 112 is configured for TIR (transmissive infrared) radiation. The dielectric pad layer 112 reflects radiation through TIR, and the low-transmittance layer 104 absorbs radiation that is not reflected through TIR, thereby increasing QE (quantum efficiency) and reducing crosstalk, respectively. Figure 40B In China, such as regarding Figure 27A As described, a low-transmittance layer 104 and a dielectric pad layer 112 define an inter-pixel trench isolation structure 102. The low-transmittance layer 104 has low transmittance and high reflectivity, while the dielectric pad layer 112 has low absorptivity. In some embodiments, the dielectric pad layer 112 is transparent. The low-transmittance layer 104 reflects radiation to reduce crosstalk and increase QE.

[0184] like Figure 41As shown in the cross-sectional view 4100, as per the description Figure 28 As described, the top surface of the low-transmittance layer 104 is recessed to expose the first back-side dielectric layer 120a. This can be achieved by... Figure 40A and Figure 40B Any of the low-transmittance layers 104 in the process are recessed, but using Figure 40A The low transmittance layer 104 is shown. As described above, Figure 40A and Figure 40B These are optional options for each other.

[0185] like Figure 42 As shown in cross-sectional view 4200, a second back-side dielectric layer 120b and a spacer layer 124 are deposited over the inter-pixel trench isolation structure 102 and the first back-side dielectric layer 120a. Furthermore, a microlens 126 is formed over the spacer layer 124. The second back-side dielectric layer 120b and the spacer layer 124 may be, for example, silicon oxide and / or some other suitable dielectric.

[0186] Although various embodiments of the reference method are described Figure 38 , Figure 39 , Figure 40A , Figure 40B , Figure 41 and Figure 42 What will be understood is that Figure 38 , Figure 39 , Figure 40A , Figure 40B , Figure 41 and Figure 42 The structure shown is not limited to this method, but can be used independently of it. Although... Figure 38 , Figure 39 , Figure 40A , Figure 40B , Figure 41 and Figure 42 Described as a series of actions, it will be understood that the order of the actions may be changed in other embodiments. Although... Figure 38 , Figure 39 , Figure 40A , Figure 40B , Figure 41 and Figure 42 A specific set of actions is shown and described, but some actions shown and / or described may be omitted in other embodiments. Furthermore, actions not shown and / or described may be included in other embodiments.

[0187] Referring to Figure 4300, it provides Figure 38 , Figure 39 , Figure 40A , Figure 40B , Figure 41 and Figure 42 A block diagram 4300 shows some embodiments of the method.

[0188] At position 4302, a photodetector is formed in the substrate from the front side of the substrate. See example. Figure 38 and Figure 21 .

[0189] At 4304, an interconnect structure is formed that covers and is electrically coupled to the photodetector on the front side of the substrate. See, for example... Figure 38 and Figure 22 .

[0190] At 4306, the back side of the substrate is patterned to form a periodic pattern on the photodetector. See, for example... Figure 38 and Figure 23 .

[0191] At 4308, a first back-side dielectric layer is deposited, which covers the back side of the substrate and the periodic pattern. See example. Figure 38 and Figure 24 .

[0192] At 4310, the top surface of the first back-side dielectric layer is made flat. See example. Figure 38 and Figure 25 .

[0193] At 4312, the back side of the first back-side dielectric layer and the substrate is patterned to form inter-pixel isolation trenches that surround the photodetector along the boundary of the pixel where the photodetector is located. See example Figure 38 and Figure 36 .

[0194] At 4314, a dielectric liner is deposited, which liner the inter-pixel isolation trench and covers the first back-side dielectric layer. See, for example... Figure 38 .

[0195] At position 4316, the dielectric liner layer is etched back. See example. Figure 39 .

[0196] At 4318, a low-transmittance layer is deposited, which fills the inter-pixel isolation trench above the dielectric liner layer and covers the first back-side dielectric layer. See, for example... Figure 40A and Figure 40B .

[0197] At 4320, the top surface of the low-transmittance layer is recessed to expose the first back-side dielectric layer. See example. Figure 41 .

[0198] At position 4322, a second back-side dielectric layer and a spacer layer are deposited, which cover the first back-side dielectric layer and the low-transmittance layer. See, for example... Figure 42 .

[0199] At position 4324, a microlens is formed that covers the photodetector above the spacer layer. See, for example... Figure 42 .

[0200] Although this article will Figure 43 Block diagram 4300 illustrates and describes a series of actions or events; however, it will be understood that the order in which such actions or events are shown should not be interpreted in a limiting sense. For example, some actions may occur in a different order and / or simultaneously with other actions or events besides those shown and / or described herein. Furthermore, not all of the actions shown may be required to implement one or more aspects or embodiments described herein, and one or more actions depicted herein may be performed in one or more separate actions and / or phases.

[0201] refer to Figures 44 to 47 , Figure 48A , Figure 48B , Figure 49 and Figure 50 Provided Figures 21 to 26 , Figure 27A , Figure 27B , Figure 28 and Figure 29 A series of cross-sectional views 4400-4700, 4800A, 4800B, 4900, and 5000 show some alternative embodiments of the method, wherein the image sensor further includes an in-pixel trench isolation structure. For example, the method can be used to form... Figure 12 , Figures 13A to 13C , Figure 14A , Figure 14B , Figure 15 and Figure 16 Any image sensor in the image sensor and other suitable image sensors.

[0202] like Figure 44 As shown in the cross-sectional view 4400, the execution... Figures 21 to 23 Actions at that location. For example, regarding... Figure 21 As described, a photodetector 110 is formed in substrate 108 from the front side 108f of substrate 108. (As per...) Figure 22 As described, a front-side dielectric structure 118 and an interconnect structure 1702 are formed, which cover the photodetector 110 on the front side 108f of the substrate 108. (See also: Regarding...) Figure 23 As described, the back side 108b of the patterned substrate 108 is used to form a periodic pattern 2302 directly above the photodetector 110.

[0203] For example Figure 44As shown in cross-sectional view 4400, the substrate 108 is patterned to define an in-pixel isolation trench 4402. The in-pixel isolation trench 4402 may also be referred to as an internal isolation trench, for example. The in-pixel isolation trench 4402 has a pair of segments located on opposite sides of the photodetector 110. Patterning can be performed, for example, by a photolithography / etching process or some other suitable patterning process. In some embodiments, the patterning of the in-pixel isolation trench 4402 is independent of the patterning of the periodic pattern 2302. For example, different photolithography / etching processes with different masks can be used to form the in-pixel isolation trench 4402 and the periodic pattern 2302.

[0204] In some embodiments, when viewed from above, the in-pixel isolation trench 4402 extends in a closed path to surround the photodetector 110. In some embodiments, the in-pixel isolation trench 4402 has a [missing information - likely a specific feature or characteristic] with [missing information - likely a specific feature or characteristic] Figures 13A to 13C and Figure 16 The top layout is the same as any of the intra-pixel trench isolation structures 1202. In some embodiments, the width W of the intra-pixel isolation trench 4402 is... iti Greater than approximately 100 nanometers, approximately 200 nanometers, approximately 500 nanometers, or some other suitable value. Furthermore, in some embodiments, the width W... iti For approximately 100-200 nanometers, approximately 200 nanometers, approximately 200-500 nanometers, or some other suitable value.

[0205] As seen below, an intra-pixel trench isolation structure is formed in the intra-pixel isolation trench 4402 and configured to incident radiation via TIR reflection. If the width W iti If the TIR is too small (e.g., less than about 100 nanometers or some other suitable value), the TIR at the sidewall interface may be low. If the inter-pixel trench isolation structure surrounding the intra-pixel trench isolation structure has high absorption, a low TIR can lead to high QE loss. If the width W... iti If the size is too large (e.g., greater than about 500 nanometers or some other suitable value), the size of photodetector 110 may be small, and / or the size of pixel 106 may be large. The former leads to poor performance of photodetector 110, while the latter leads to low pixel density.

[0206] like Figure 45 As shown in cross-sectional view 4500, a first back-side dielectric layer 120a is deposited, which covers the back side 108b of the substrate 108 and fills the in-pixel isolation trench 4402. The first back-side dielectric layer 120a has a higher refractive index than the substrate 108 to promote TIR at the interface between the first back-side dielectric layer 120a and the substrate 108. Furthermore, the top surface of the first back-side dielectric layer 120a is at least in the periodic pattern 2302 (see, for example, [reference needed]). Figure 44The area is rough. The first back-side dielectric layer 120a may be, for example, silicon oxide and / or some other suitable dielectric.

[0207] The first back-side dielectric layer 120a and the substrate 108 together define a diffuser 122, which is configured in a periodic pattern 2302 (e.g., see...). Figure 44 The scattering of external radiation is 114ex at the location. Furthermore, a portion of the first back-side dielectric layer 120a in the in-pixel isolation trench 4402 defines the in-pixel trench isolation structure 1202. The in-pixel trench isolation structure 1202 may, for example, have the following characteristics: Figures 13A to 13C The top layout shown anywhere, or may have some other suitable top layout.

[0208] like Figure 46 As shown in cross-sectional view 4600, the top surface of the first back-side dielectric layer 120a is made flat. Furthermore, the first back-side dielectric layer 120a is etched back to reduce the thickness T of the first back-side dielectric layer 120a at its top and bottom surfaces. fbd Planarization can be performed, for example, by CMP and / or some other suitable planarization process.

[0209] like Figure 47 , Figure 48A , Figure 48B , Figure 49 and Figure 50 The cross-sectional diagrams 4700, 4800A, 4800B, 4900, and 5000 are shown. Execution... Figure 26 , Figure 27A , Figure 27B , Figure 28 and Figure 29 The action at that location. In Figure 47 Places, such as regarding Figure 26 As described, a first back-side dielectric layer 120a and a substrate 108 are patterned to define an inter-pixel isolation trench 2602. The inter-pixel isolation trench 2602 may, for example, have... Figures 13A to 13C The same top layout as the pixel-to-pixel trench isolation structure 102 or some other suitable top layout. Figure 48A and Figure 48B Places, such as regarding Figure 27A and Figure 27B As described, a dielectric liner layer 112 and a low transmittance layer 104 are deposited, and the dielectric liner layer 112 and the low transmittance layer 104 fill the inter-pixel isolation trench 2602 (see, for example...). Figure 47 The low-transmittance layer 104 and the dielectric pad layer 112 together define the inter-pixel trench isolation structure 102. The inter-pixel trench isolation structure 102 may, for example, have the following characteristics: Figures 13A to 13C Any top layout or some other suitable top layout. Figure 49 Places, such as regarding Figure 28 As described, the top surface of the low-transmittance layer 104 is recessed to expose the first back-side dielectric layer 120a. Figure 50 Places, such as regarding Figure 29 As described, a second back-side dielectric layer 120b, a spacer layer 124, and a microlens 126 are formed.

[0210] Although various embodiments of the reference method are described Figures 44 to 47 , Figure 48A , Figure 48B , Figure 49 and Figure 50 What will be understood is that Figures 44 to 47 , Figure 48A , Figure 48B , Figure 49 and Figure 50 The structure shown is not limited to this method, but can be used independently of it. Although... Figures 44 to 47 , Figure 48A , Figure 48B , Figure 49 and Figure 50 Described as a series of actions, but it will be understood that the order of the actions may change in other embodiments. Although... Figures 44 to 47 , Figure 48A , Figure 48B , Figure 49 and Figure 50 A specific set of actions is shown and described, but some actions shown and / or described may be omitted in other embodiments. Furthermore, actions not shown and / or described may be included in other embodiments. For example, actions may be performed instead of... Figure 47 , Figure 48A , Figure 48B , Figure 49 and Figure 50 The action at the location, execution Figures 31 to 33 , Figure 34A , Figure 34B , Figure 35 and Figure 36 Actions at the location.

[0211] refer to Figure 51 Provided Figures 44 to 47 , Figure 48A , Figure 48B , Figure 49 and Figure 50 A block diagram 5100 shows some embodiments of the method.

[0212] At position 5102, a photodetector is formed in the substrate from the front side of the substrate. See example. Figure 44 and Figure 21 .

[0213] At 5104, an interconnect structure is formed that covers and is electrically coupled to the photodetector on the front side of the substrate. See, for example... Figure 44 and Figure 22 .

[0214] At 5106, the back side of the substrate is patterned to form a periodic pattern on the photodetector. See, for example... Figure 44 and Figure 23 .

[0215] At 5108, the back side of the substrate is patterned to form an in-pixel isolation trench surrounding the photodetector. See, for example... Figure 44 .

[0216] At 5110, a first back-side dielectric layer is deposited, which covers the back side of the substrate and fills the in-pixel isolation trench. See, for example... Figure 45 .

[0217] At point 5112, the top surface of the first back-side dielectric layer is flattened and the top surface of the first back-side dielectric layer is etched back. See example. Figure 46 .

[0218] At 5114, the back side of the first back-side dielectric layer and the substrate are patterned to form inter-pixel isolation trenches that surround the intra-pixel isolation trenches along the boundary of the pixel where the photodetector is located. See, for example... Figure 47 .

[0219] At position 5116, a dielectric liner is deposited, which liner and partially fills the inter-pixel isolation trench. See example. Figure 48A and Figure 48B .

[0220] At 5118, a low-transmittance layer is deposited, which fills the inter-pixel isolation trench above the dielectric liner layer and covers the first back-side dielectric layer. See, for example... Figure 48A and Figure 48B .

[0221] At 5120, the top surface of the low-transmittance layer is recessed to expose the first back-side dielectric layer. See example. Figure 49 .

[0222] At position 5122, a second back-side dielectric layer and a spacer layer are deposited, which cover the first back-side dielectric layer and the low-transmittance layer. See, for example... Figure 50 .

[0223] At position 5124, a microlens is formed that covers the photodetector above the spacer layer. See, for example... Figure 50 .

[0224] Although this article will Figure 51 Block diagram 5100 illustrates and describes a series of actions or events; however, it will be understood that the order in which such actions or events are shown should not be interpreted in a limiting sense. For example, some actions may occur in a different order and / or simultaneously with other actions or events besides those shown and / or described herein. Furthermore, not all of the actions shown may be required to implement one or more aspects or embodiments described herein, and one or more actions described herein may be performed in one or more separate actions and / or phases.

[0225] refer to Figures 52 to 54 , Figure 55A , Figure 55B and Figures 56 to 58 Provided Figures 21 to 26 , Figure 27A , Figure 27B , Figure 28 and Figure 29 A series of cross-sectional views 5200-5400, 5500A, 5500B, and 5600-5800 are provided for some alternative embodiments of the method, wherein the image sensor is an FSI. For example, the method can be used to form Figure 18 and Figure 20 Any image sensor in the image sensor and other suitable image sensors.

[0226] like Figure 52 As shown in the cross-sectional diagram 5200, the execution... Figures 23 to 25 Actions at that location. For example, regarding... Figure 23 As described, the back side 108b of the patterned substrate 108 is used to form a periodic pattern at pixel 106. (As per...) Figure 24 As described, a first back-side dielectric layer 120a is deposited, which covers the back side 108b of the substrate 108 and the periodic pattern. The first back-side dielectric layer 120a and the substrate 108 together define a diffuser 122 at the periodic pattern. (See also: Regarding...) Figure 25 As described, the top surface of the first back-side dielectric layer 120a is flat.

[0227] like Figure 53 As shown in cross-sectional view 5300, substrate 108 is flipped such that the front side 108f of substrate 108 is located above the back side 108b of substrate 108. Furthermore, a mask layer 5302 is deposited, covering the front side 108f of substrate 108. Mask layer 5302 may be, for example, or include silicon oxide, silicon nitride, some other suitable dielectric, or any combination thereof.

[0228] If passed Figure 54 , Figure 55A , Figure 55B and Figure 56The cross-sectional diagrams 5400, 5500A, 5500B, and 5600 are shown below. Execute... Figure 26 , Figure 27A , Figure 27B and Figure 28 The action at that location. In Figure 54 Places, such as regarding Figure 26 As described, a patterned mask layer 5302 and a substrate 108 are used to define inter-pixel isolation trenches 2602. Figure 55A and Figure 55B Places, such as regarding Figure 27A and Figure 27B As described, a dielectric liner layer 112 and a low transmittance layer 104 are deposited, and the dielectric liner layer 112 and the low transmittance layer 104 fill the inter-pixel isolation trench 2602 (see, for example...). Figure 54 The low-transmittance layer 104 and the dielectric pad layer 112 together define the inter-pixel trench isolation structure 102. Figure 56 Places, such as regarding Figure 28 As described, the top surface of the low-transmittance layer 104 is recessed to expose the mask layer 5302. Furthermore, in Figure 56 At this location, the mask layer 5302 is removed. In an alternative embodiment, the mask layer 5302 is... Figure 56 The action continues after the point is taken.

[0229] like Figure 57 As shown in cross-sectional view 5700, a photodetector 110 is formed in a substrate 108 surrounded by an inter-pixel trench isolation structure 102. For example, the photodetector 110 can be as described regarding... Figure 21 It forms as described.

[0230] like Figure 58 As shown in cross-sectional view 5800, a front dielectric structure 118 is formed, which covers the photodetector 110 and the inter-pixel trench isolation structure 102 on the front side 108f of the substrate 108. Furthermore, during the formation of the front dielectric structure 118, an interconnect structure 1702 is formed, which covers the photodetector 110 and is electrically coupled to it. The interconnect structure 1702 includes a plurality of contacts 1710, a plurality of lines 1712, and a plurality of vias 1714 stacked in the front dielectric structure 118.

[0231] For example Figure 58 As shown in cross-sectional view 5800, a spacer layer 124 is deposited over the front dielectric structure 118 and the interconnect structure 1702. Furthermore, a microlens 126 is formed over the spacer layer 124. The spacer layer 124 may be, for example, silicon oxide and / or some other suitable dielectric.

[0232] Although various embodiments of the reference method are described Figures 52 to 54 , Figure 55A , Figure 55B and Figures 56 to 58 However, we will understand. Figures 52 to 54 , Figure 55A , Figure 55B and Figures 56 to 58 The structure shown is not limited to this method, but can be used independently of it. Although... Figures 52 to 54 , Figure 55A , Figure 55B and Figures 56 to 58 Described as a series of actions, but it will be understood that the order of the actions may change in other embodiments. Although... Figures 52 to 54 , Figure 55A , Figure 55B and Figures 56 to 58 A specific set of actions is shown and described, but some actions shown and / or described may be omitted in other embodiments. Furthermore, actions not shown and / or described may be included in other embodiments.

[0233] refer to Figure 59 Provided Figures 52 to 54 , Figure 55A , Figure 55B and Figures 56 to 58 Block diagram 5900 shows some embodiments of the method.

[0234] At 5902, the back side of the substrate is patterned to form a periodic pattern at the pixel. See, for example... Figure 52 and Figure 23 .

[0235] At position 5904, a first back-side dielectric layer is deposited, which covers the back side of the substrate and the periodic pattern. See example. Figure 52 and Figure 24 .

[0236] At position 5906, the top surface of the first back-side dielectric layer is flattened and the top surface of the first back-side dielectric layer is etched back. See example. Figure 52 and Figure 25 .

[0237] At position 5908, a mask layer is deposited, covering the front side of the substrate. See example. Figure 53 .

[0238] At 5910, the mask layer and substrate are patterned to form inter-pixel isolation trenches that surround the pixels along their boundaries. See, for example... Figure 54 .

[0239] At position 5912, a dielectric liner is deposited, which liner and partially fills the inter-pixel isolation trench. See example. Figure 55A and Figure 55B .

[0240] At position 5914, a low-transmittance layer is deposited, which fills the inter-pixel isolation trench above the dielectric pad layer and covers the mask layer. See example. Figure 55A and Figure 55B .

[0241] At position 5916, the top surface of the low-transmittance layer is recessed to expose the mask layer. See example. Figure 56 .

[0242] At position 5918, remove the mask layer. See example. Figure 56 .

[0243] At position 5920, a photodetector is formed in the substrate located at the pixel. See example. Figure 57 .

[0244] At position 5922, an interconnect structure is formed that covers and is electrically coupled to the photodetector on the front side of the substrate. See, for example... Figure 58 .

[0245] At position 5924, a spacer layer covering the interconnect structure is deposited. See, for example... Figure 58 .

[0246] At position 5926, a microlens is formed to cover the photodetector. See example. Figure 58 .

[0247] Although this article will Figure 59 Block diagram 5900 illustrates and describes a series of actions or events; however, it will be understood that the order in which such actions or events are shown should not be interpreted in a limiting sense. For example, some actions may occur in a different order and / or simultaneously with other actions or events besides those shown and / or described herein. Furthermore, not all of the actions shown may be required to implement one or more aspects or embodiments described herein, and one or more actions depicted herein may be performed in one or more separate actions and / or phases.

[0248] In some embodiments, the present invention provides an image sensor comprising: a substrate; a pixel including a photodetector, wherein the photodetector is located within the substrate; and an external trench isolation structure extending into the substrate, wherein the external trench isolation structure has a pair of external isolation segments located at the boundary of the pixel on opposite sides of the photodetector, wherein the external trench isolation structure includes a low-transmittance layer, and wherein the low-transmittance layer blocks incident radiation regardless of the incident angle. In some embodiments, the low-transmittance layer is metallic and reflects incident radiation. In some embodiments, the low-transmittance layer is metallic and absorbs incident radiation. In some embodiments, the external trench isolation structure includes a dielectric pad layer separating the low-transmittance layer from the substrate, wherein the dielectric pad layer has a lower refractive index than the substrate. In some embodiments, the thickness of the dielectric pad layer is greater than about 100 nanometers. In some embodiments, the image sensor further includes an internal trench isolation structure including a pair of internal isolation segments located on opposite sides of the photodetector, wherein the internal trench isolation structure is located between the external isolation segments and includes a dielectric having a lower refractive index than the substrate. In some embodiments, the external trench isolation structure extends along the pixel boundary in a closed path to completely surround the pixel. In some embodiments, the light transmittance of the low transmittance layer is less than about 10%.

[0249] In some embodiments, the present invention provides another image sensor, comprising: a substrate; an array of pixels in multiple rows and columns on the substrate, wherein each pixel includes an individual photodetector located in the substrate; and an inter-pixel trench isolation structure located in the substrate, wherein the inter-pixel trench isolation structure extends along the boundaries of the pixels and individually surrounds the pixels to separate them from each other, and wherein the inter-pixel trench isolation structure includes a metal layer. In some embodiments, the metal layer includes copper and / or aluminum. In some embodiments, the metal layer includes tungsten, titanium nitride, tantalum nitride, or any combination thereof. In some embodiments, the inter-pixel trench isolation structure is configured to reflect radiation incident on the sidewalls of the inter-pixel trench isolation structure at any angle. In some embodiments, the image sensor further includes an intra-pixel trench isolation structure comprising a plurality of annular trench isolation segments, wherein the annular trench isolation segments are individual for each pixel and are surrounded by the inter-pixel trench isolation structure at each individual pixel. In some embodiments, the intra-pixel trench isolation structure is configured to reflect radiation incident on the sidewalls of the intra-pixel trench isolation structure at an angle greater than about 20 degrees but not less than about 20 degrees.

[0250] In some embodiments, the present invention provides a method for forming an image sensor, the method comprising: forming a pixel on a substrate, the pixel including a photodetector located in the substrate; patterning the substrate to form an external trench, wherein the external trench surrounds the photodetector along a boundary of the pixel and has a pair of external isolation segments located on opposite sides of the photodetector; and depositing a low-transmittance layer covering the substrate and filling the external trench, wherein the low-transmittance layer blocks incident radiation regardless of the incident angle. In some embodiments, the method includes recessing a top surface of the low-transmittance layer to position the low-transmittance layer to the external trench. The incident radiation is independent of the incident angle. In some embodiments, the method includes depositing a dielectric pad layer lining the external trench, wherein the low-transmittance layer is deposited over the dielectric pad layer. The incident radiation is independent of the incident angle. In some embodiments, the method includes configuring the dielectric pad layer for TIR at the sidewalls of the dielectric pad layer in the external trench. In some embodiments, the method further includes: patterning a substrate to form an internal trench, wherein the internal trench has a pair of internal isolation segments respectively located on opposite sides of the photodetector, and wherein an external trench surrounds the internal trench; and depositing a dielectric layer filling the internal trench prior to patterning to form the external trench. In some embodiments, the method further includes: patterning a substrate to form a periodic structure on the photodetector; depositing a dielectric layer covering the substrate and having a bottom surface conformal to the periodic structure, wherein the dielectric layer has a higher refractive index than the substrate; and flattening the top surface of the dielectric layer prior to patterning to form the external trench.

[0251] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. An image sensor, comprising: Substrate; A pixel, including a photodetector, wherein the photodetector is located in the substrate; and An external trench isolation structure extends into the substrate, wherein the external trench isolation structure has a pair of external isolation segments located at the boundary of the pixel on opposite sides of the photodetector. An internal trench isolation structure includes a pair of internal isolation segments located on opposite sides of the photodetector, wherein the internal trench isolation structure is situated between the external isolation segments and includes a dielectric material having a lower refractive index than the substrate. The external trench isolation structure includes a low-transmittance layer, wherein the low-transmittance layer blocks incident radiation regardless of the incident angle. The internal trench completely penetrates the substrate, and the external trench and the internal trench have different heights.

2. The image sensor of claim 1, wherein, The low-transmittance layer is metallic and reflects the incident radiation.

3. The image sensor of claim 1, wherein, The low-transmittance layer is metal and absorbs the incident radiation.

4. The image sensor according to claim 1, wherein, The external trench isolation structure includes a dielectric pad layer that separates the low-transmittance layer from the substrate, wherein the dielectric pad layer has a lower refractive index than the substrate.

5. The image sensor according to claim 4, wherein, The thickness of the dielectric liner is greater than 100 nanometers.

6. The image sensor according to claim 1, wherein: The top surface of the low-transmittance layer is higher than the top surface of the substrate.

7. The image sensor according to claim 1, wherein, The external trench isolation structure extends along the boundary of the pixel in a closed path to completely surround the pixel.

8. The image sensor according to claim 1, wherein, The light transmittance of the low transmittance layer is less than 10%.

9. An image sensor, comprising: Substrate; An array of pixels, located in multiple rows and columns on the substrate, wherein each pixel includes an individual photodetector located within the substrate; and An inter-pixel trench isolation structure is located in the substrate, wherein the inter-pixel trench isolation structure extends along the boundary of the pixel and individually surrounds the pixel to separate the pixels from each other. An intra-pixel trench isolation structure includes multiple annular trench isolation segments, wherein each annular trench isolation segment is individual for the pixel and is surrounded by the inter-pixel trench isolation structure at that individual pixel. The inter-pixel trench isolation structure includes a metal layer. The intra-pixel trench isolation structure completely penetrates the substrate, and the inter-pixel trench isolation structure and the intra-pixel trench isolation structure have different heights.

10. The image sensor according to claim 9, wherein, The metal layer includes copper and / or aluminum.

11. The image sensor according to claim 9, wherein, The metal layer includes tungsten, titanium nitride, tantalum nitride, or any combination thereof.

12. The image sensor according to claim 9, wherein, The inter-pixel trench isolation structure is configured to reflect radiation incident on the sidewalls of the inter-pixel trench isolation structure at any angle.

13. The image sensor according to claim 9, wherein: The top surface of the metal layer is higher than the top surface of the substrate.

14. The image sensor according to claim 9, wherein, The in-pixel trench isolation structure is configured to reflect radiation incident on the sidewall of the in-pixel trench isolation structure at an angle greater than 20 degrees.

15. A method for forming an image sensor, the method comprising: A pixel is formed on a substrate, the pixel including a photodetector located in the substrate; The substrate is patterned to form internal trenches, wherein the internal trenches have a pair of internal isolation segments located on opposite sides of the photodetector; and Deposit a dielectric layer to fill the internal trenches; The substrate and the dielectric layer are patterned to form an external trench, wherein the external trench surrounds the photodetector along the boundary of the pixel and has a pair of external isolation segments located on opposite sides of the photodetector, with an internal isolation segment sandwiched between the external isolation segments; and A low-transmittance layer is deposited, which covers the substrate and fills the external trench, wherein the low-transmittance layer blocks incident radiation regardless of the incident angle; The low-transmittance layer is planarized so that its top surface is flush with the top surface of the dielectric layer and higher than the top surface of the substrate. The internal trench completely penetrates the substrate, and the external trench and the internal trench have different heights.

16. The method of claim 15, further comprising: The top surface of the low-transmittance layer is recessed to position the low-transmittance layer in the external trench.

17. The method of claim 15, further comprising: A dielectric liner layer is deposited on the outer trench, wherein the low transmittance layer is deposited on top of the dielectric liner layer.

18. The method according to claim 17, wherein, The dielectric liner is configured for total internal reflection at the sidewalls of the dielectric liner in the external trench.

19. The method of claim 15, wherein: The light transmittance of the low transmittance layer is less than 10%.

20. The method of claim 15, further comprising: The substrate is patterned to form a periodic structure on the photodetector; The dielectric layer is further formed to cover the substrate and have a bottom surface conformal to the periodic structure, wherein the dielectric layer has a higher refractive index than the substrate; and Before patterning to form the external trench, the top surface of the dielectric layer is flattened.

Images